if_rlreg.h revision 217911
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_rlreg.h 217911 2011-01-26 21:14:20Z yongari $ 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 41#define RL_IDR3 0x0003 42#define RL_IDR4 0x0004 43#define RL_IDR5 0x0005 44 /* 0006-0007 reserved */ 45#define RL_MAR0 0x0008 /* Multicast hash table */ 46#define RL_MAR1 0x0009 47#define RL_MAR2 0x000A 48#define RL_MAR3 0x000B 49#define RL_MAR4 0x000C 50#define RL_MAR5 0x000D 51#define RL_MAR6 0x000E 52#define RL_MAR7 0x000F 53 54#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 58 59#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 63 64#define RL_RXADDR 0x0030 /* RX ring start address */ 65#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67#define RL_COMMAND 0x0037 /* command register */ 68#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70#define RL_IMR 0x003C /* interrupt mask register */ 71#define RL_ISR 0x003E /* interrupt status register */ 72#define RL_TXCFG 0x0040 /* transmit config */ 73#define RL_RXCFG 0x0044 /* receive config */ 74#define RL_TIMERCNT 0x0048 /* timer count register */ 75#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76#define RL_EECMD 0x0050 /* EEPROM command register */ 77#define RL_CFG0 0x0051 /* config register #0 */ 78#define RL_CFG1 0x0052 /* config register #1 */ 79#define RL_CFG2 0x0053 /* config register #2 */ 80#define RL_CFG3 0x0054 /* config register #3 */ 81#define RL_CFG4 0x0055 /* config register #4 */ 82#define RL_CFG5 0x0056 /* config register #5 */ 83 /* 0057 reserved */ 84#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 85 /* 0059-005A reserved */ 86#define RL_MII 0x005A /* 8129 chip only */ 87#define RL_HALTCLK 0x005B 88#define RL_MULTIINTR 0x005C /* multiple interrupt */ 89#define RL_PCIREV 0x005E /* PCI revision value */ 90 /* 005F reserved */ 91#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 92 93/* Direct PHY access registers only available on 8139 */ 94#define RL_BMCR 0x0062 /* PHY basic mode control */ 95#define RL_BMSR 0x0064 /* PHY basic mode status */ 96#define RL_ANAR 0x0066 /* PHY autoneg advert */ 97#define RL_LPAR 0x0068 /* PHY link partner ability */ 98#define RL_ANER 0x006A /* PHY autoneg expansion */ 99 100#define RL_DISCCNT 0x006C /* disconnect counter */ 101#define RL_FALSECAR 0x006E /* false carrier counter */ 102#define RL_NWAYTST 0x0070 /* NWAY test register */ 103#define RL_RX_ER 0x0072 /* RX_ER counter */ 104#define RL_CSCFG 0x0074 /* CS configuration register */ 105 106/* 107 * When operating in special C+ mode, some of the registers in an 108 * 8139C+ chip have different definitions. These are also used for 109 * the 8169 gigE chip. 110 */ 111#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 112#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 113#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 114#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 115#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 116#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 117#define RL_CFG2 0x0053 118#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 119#define RL_TXSTART 0x00D9 /* 8 bits */ 120#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 121#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 122#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 123#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 124 125/* 126 * Registers specific to the 8169 gigE chip 127 */ 128#define RL_GTXSTART 0x0038 /* 8 bits */ 129#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 130#define RL_PHYAR 0x0060 131#define RL_TBICSR 0x0064 132#define RL_TBI_ANAR 0x0068 133#define RL_TBI_LPAR 0x006A 134#define RL_GMEDIASTAT 0x006C /* 8 bits */ 135#define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */ 136#define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */ 137#define RL_PMCH 0x006F /* 8 bits */ 138#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 139#define RL_INTRMOD 0x00E2 /* 16 bits */ 140 141/* 142 * TX config register bits 143 */ 144#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 145#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 146#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 147#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 148#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 149#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 150#define RL_TXCFG_HWREV 0x7CC00000 151 152#define RL_LOOPTEST_OFF 0x00000000 153#define RL_LOOPTEST_ON 0x00020000 154#define RL_LOOPTEST_ON_CPLUS 0x00060000 155 156/* Known revision codes. */ 157 158#define RL_HWREV_8169 0x00000000 159#define RL_HWREV_8169S 0x00800000 160#define RL_HWREV_8110S 0x04000000 161#define RL_HWREV_8169_8110SB 0x10000000 162#define RL_HWREV_8169_8110SC 0x18000000 163#define RL_HWREV_8102EL 0x24800000 164#define RL_HWREV_8102EL_SPIN1 0x24C00000 165#define RL_HWREV_8168D 0x28000000 166#define RL_HWREV_8168DP 0x28800000 167#define RL_HWREV_8168E 0x2C000000 168#define RL_HWREV_8168E_VL 0x2C800000 169#define RL_HWREV_8168B_SPIN1 0x30000000 170#define RL_HWREV_8100E 0x30800000 171#define RL_HWREV_8101E 0x34000000 172#define RL_HWREV_8102E 0x34800000 173#define RL_HWREV_8103E 0x34C00000 174#define RL_HWREV_8168B_SPIN2 0x38000000 175#define RL_HWREV_8168B_SPIN3 0x38400000 176#define RL_HWREV_8168C 0x3C000000 177#define RL_HWREV_8168C_SPIN2 0x3C400000 178#define RL_HWREV_8168CP 0x3C800000 179#define RL_HWREV_8105E 0x40800000 180#define RL_HWREV_8139 0x60000000 181#define RL_HWREV_8139A 0x70000000 182#define RL_HWREV_8139AG 0x70800000 183#define RL_HWREV_8139B 0x78000000 184#define RL_HWREV_8130 0x7C000000 185#define RL_HWREV_8139C 0x74000000 186#define RL_HWREV_8139D 0x74400000 187#define RL_HWREV_8139CPLUS 0x74800000 188#define RL_HWREV_8101 0x74C00000 189#define RL_HWREV_8100 0x78800000 190#define RL_HWREV_8169_8110SBL 0x7CC00000 191#define RL_HWREV_8169_8110SCE 0x98000000 192 193#define RL_TXDMA_16BYTES 0x00000000 194#define RL_TXDMA_32BYTES 0x00000100 195#define RL_TXDMA_64BYTES 0x00000200 196#define RL_TXDMA_128BYTES 0x00000300 197#define RL_TXDMA_256BYTES 0x00000400 198#define RL_TXDMA_512BYTES 0x00000500 199#define RL_TXDMA_1024BYTES 0x00000600 200#define RL_TXDMA_2048BYTES 0x00000700 201 202/* 203 * Transmit descriptor status register bits. 204 */ 205#define RL_TXSTAT_LENMASK 0x00001FFF 206#define RL_TXSTAT_OWN 0x00002000 207#define RL_TXSTAT_TX_UNDERRUN 0x00004000 208#define RL_TXSTAT_TX_OK 0x00008000 209#define RL_TXSTAT_EARLY_THRESH 0x003F0000 210#define RL_TXSTAT_COLLCNT 0x0F000000 211#define RL_TXSTAT_CARR_HBEAT 0x10000000 212#define RL_TXSTAT_OUTOFWIN 0x20000000 213#define RL_TXSTAT_TXABRT 0x40000000 214#define RL_TXSTAT_CARRLOSS 0x80000000 215 216/* 217 * Interrupt status register bits. 218 */ 219#define RL_ISR_RX_OK 0x0001 220#define RL_ISR_RX_ERR 0x0002 221#define RL_ISR_TX_OK 0x0004 222#define RL_ISR_TX_ERR 0x0008 223#define RL_ISR_RX_OVERRUN 0x0010 224#define RL_ISR_PKT_UNDERRUN 0x0020 225#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 226#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 227#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 228#define RL_ISR_SWI 0x0100 /* C+ only */ 229#define RL_ISR_CABLE_LEN_CHGD 0x2000 230#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 231#define RL_ISR_TIMEOUT_EXPIRED 0x4000 232#define RL_ISR_SYSTEM_ERR 0x8000 233 234#define RL_INTRS \ 235 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 236 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 237 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 238 239#ifdef RE_TX_MODERATION 240#define RL_INTRS_CPLUS \ 241 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 242 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 243 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 244#else 245#define RL_INTRS_CPLUS \ 246 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 247 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 248 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 249#endif 250 251/* 252 * Media status register. (8139 only) 253 */ 254#define RL_MEDIASTAT_RXPAUSE 0x01 255#define RL_MEDIASTAT_TXPAUSE 0x02 256#define RL_MEDIASTAT_LINK 0x04 257#define RL_MEDIASTAT_SPEED10 0x08 258#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 259#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 260 261/* 262 * Receive config register. 263 */ 264#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 265#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 266#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 267#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 268#define RL_RXCFG_RX_RUNT 0x00000010 269#define RL_RXCFG_RX_ERRPKT 0x00000020 270#define RL_RXCFG_WRAP 0x00000080 271#define RL_RXCFG_MAXDMA 0x00000700 272#define RL_RXCFG_BUFSZ 0x00001800 273#define RL_RXCFG_FIFOTHRESH 0x0000E000 274#define RL_RXCFG_EARLYTHRESH 0x07000000 275 276#define RL_RXDMA_16BYTES 0x00000000 277#define RL_RXDMA_32BYTES 0x00000100 278#define RL_RXDMA_64BYTES 0x00000200 279#define RL_RXDMA_128BYTES 0x00000300 280#define RL_RXDMA_256BYTES 0x00000400 281#define RL_RXDMA_512BYTES 0x00000500 282#define RL_RXDMA_1024BYTES 0x00000600 283#define RL_RXDMA_UNLIMITED 0x00000700 284 285#define RL_RXBUF_8 0x00000000 286#define RL_RXBUF_16 0x00000800 287#define RL_RXBUF_32 0x00001000 288#define RL_RXBUF_64 0x00001800 289 290#define RL_RXFIFO_16BYTES 0x00000000 291#define RL_RXFIFO_32BYTES 0x00002000 292#define RL_RXFIFO_64BYTES 0x00004000 293#define RL_RXFIFO_128BYTES 0x00006000 294#define RL_RXFIFO_256BYTES 0x00008000 295#define RL_RXFIFO_512BYTES 0x0000A000 296#define RL_RXFIFO_1024BYTES 0x0000C000 297#define RL_RXFIFO_NOTHRESH 0x0000E000 298 299/* 300 * Bits in RX status header (included with RX'ed packet 301 * in ring buffer). 302 */ 303#define RL_RXSTAT_RXOK 0x00000001 304#define RL_RXSTAT_ALIGNERR 0x00000002 305#define RL_RXSTAT_CRCERR 0x00000004 306#define RL_RXSTAT_GIANT 0x00000008 307#define RL_RXSTAT_RUNT 0x00000010 308#define RL_RXSTAT_BADSYM 0x00000020 309#define RL_RXSTAT_BROAD 0x00002000 310#define RL_RXSTAT_INDIV 0x00004000 311#define RL_RXSTAT_MULTI 0x00008000 312#define RL_RXSTAT_LENMASK 0xFFFF0000 313 314#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 315/* 316 * Command register. 317 */ 318#define RL_CMD_EMPTY_RXBUF 0x0001 319#define RL_CMD_TX_ENB 0x0004 320#define RL_CMD_RX_ENB 0x0008 321#define RL_CMD_RESET 0x0010 322#define RL_CMD_STOPREQ 0x0080 323 324/* 325 * Twister register values. These are completely undocumented and derived 326 * from public sources. 327 */ 328#define RL_CSCFG_LINK_OK 0x0400 329#define RL_CSCFG_CHANGE 0x0800 330#define RL_CSCFG_STATUS 0xf000 331#define RL_CSCFG_ROW3 0x7000 332#define RL_CSCFG_ROW2 0x3000 333#define RL_CSCFG_ROW1 0x1000 334#define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0 335#define RL_CSCFG_LINK_DOWN_CMD 0xf3c0 336 337#define RL_NWAYTST_RESET 0 338#define RL_NWAYTST_CBL_TEST 0x20 339 340#define RL_PARA78 0x78 341#define RL_PARA78_DEF 0x78fa8388 342#define RL_PARA7C 0x7C 343#define RL_PARA7C_DEF 0xcb38de43 344#define RL_PARA7C_RETUNE 0xfb38de03 345/* 346 * EEPROM control register 347 */ 348#define RL_EE_DATAOUT 0x01 /* Data out */ 349#define RL_EE_DATAIN 0x02 /* Data in */ 350#define RL_EE_CLK 0x04 /* clock */ 351#define RL_EE_SEL 0x08 /* chip select */ 352#define RL_EE_MODE (0x40|0x80) 353 354#define RL_EEMODE_OFF 0x00 355#define RL_EEMODE_AUTOLOAD 0x40 356#define RL_EEMODE_PROGRAM 0x80 357#define RL_EEMODE_WRITECFG (0x80|0x40) 358 359/* 9346 EEPROM commands */ 360#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 361#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 362 363#define RL_9346_WRITE 0x5 364#define RL_9346_READ 0x6 365#define RL_9346_ERASE 0x7 366#define RL_9346_EWEN 0x4 367#define RL_9346_EWEN_ADDR 0x30 368#define RL_9456_EWDS 0x4 369#define RL_9346_EWDS_ADDR 0x00 370 371#define RL_EECMD_WRITE 0x140 372#define RL_EECMD_READ_6BIT 0x180 373#define RL_EECMD_READ_8BIT 0x600 374#define RL_EECMD_ERASE 0x1c0 375 376#define RL_EE_ID 0x00 377#define RL_EE_PCI_VID 0x01 378#define RL_EE_PCI_DID 0x02 379/* Location of station address inside EEPROM */ 380#define RL_EE_EADDR 0x07 381 382/* 383 * MII register (8129 only) 384 */ 385#define RL_MII_CLK 0x01 386#define RL_MII_DATAIN 0x02 387#define RL_MII_DATAOUT 0x04 388#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 389 390/* 391 * Config 0 register 392 */ 393#define RL_CFG0_ROM0 0x01 394#define RL_CFG0_ROM1 0x02 395#define RL_CFG0_ROM2 0x04 396#define RL_CFG0_PL0 0x08 397#define RL_CFG0_PL1 0x10 398#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 399#define RL_CFG0_PCS 0x40 400#define RL_CFG0_SCR 0x80 401 402/* 403 * Config 1 register 404 */ 405#define RL_CFG1_PWRDWN 0x01 406#define RL_CFG1_PME 0x01 407#define RL_CFG1_SLEEP 0x02 408#define RL_CFG1_VPDEN 0x02 409#define RL_CFG1_IOMAP 0x04 410#define RL_CFG1_MEMMAP 0x08 411#define RL_CFG1_RSVD 0x10 412#define RL_CFG1_LWACT 0x10 413#define RL_CFG1_DRVLOAD 0x20 414#define RL_CFG1_LED0 0x40 415#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 416#define RL_CFG1_LED1 0x80 417 418/* 419 * Config 2 register 420 */ 421#define RL_CFG2_PCI33MHZ 0x00 422#define RL_CFG2_PCI66MHZ 0x01 423#define RL_CFG2_PCI64BIT 0x08 424#define RL_CFG2_AUXPWR 0x10 425#define RL_CFG2_MSI 0x20 426 427/* 428 * Config 3 register 429 */ 430#define RL_CFG3_GRANTSEL 0x80 431#define RL_CFG3_WOL_MAGIC 0x20 432#define RL_CFG3_WOL_LINK 0x10 433#define RL_CFG3_JUMBO_EN0 0x04 /* RTL8168C or later. */ 434#define RL_CFG3_FAST_B2B 0x01 435 436/* 437 * Config 4 register 438 */ 439#define RL_CFG4_LWPTN 0x04 440#define RL_CFG4_LWPME 0x10 441#define RL_CFG4_JUMBO_EN1 0x02 /* RTL8168C or later. */ 442 443/* 444 * Config 5 register 445 */ 446#define RL_CFG5_WOL_BCAST 0x40 447#define RL_CFG5_WOL_MCAST 0x20 448#define RL_CFG5_WOL_UCAST 0x10 449#define RL_CFG5_WOL_LANWAKE 0x02 450#define RL_CFG5_PME_STS 0x01 451 452/* 453 * 8139C+ register definitions 454 */ 455 456/* RL_DUMPSTATS_LO register */ 457 458#define RL_DUMPSTATS_START 0x00000008 459 460/* Transmit start register */ 461 462#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 463#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 464#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 465 466/* 467 * Config 2 register, 8139C+/8169/8169S/8110S only 468 */ 469#define RL_CFG2_BUSFREQ 0x07 470#define RL_CFG2_BUSWIDTH 0x08 471#define RL_CFG2_AUXPWRSTS 0x10 472 473#define RL_BUSFREQ_33MHZ 0x00 474#define RL_BUSFREQ_66MHZ 0x01 475 476#define RL_BUSWIDTH_32BITS 0x00 477#define RL_BUSWIDTH_64BITS 0x08 478 479/* C+ mode command register */ 480 481#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 482#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 483#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 484#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 485#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 486#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 487#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 488#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 489#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 490#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 491#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 492#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 493#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 494#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 495#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 496 497/* C+ early transmit threshold */ 498 499#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 500 501/* Timer interrupt register */ 502#define RL_TIMERINT_8169_VAL 0x00001FFF 503#define RL_TIMER_MIN 0 504#define RL_TIMER_MAX 65 /* 65.528us */ 505#define RL_TIMER_DEFAULT RL_TIMER_MAX 506#define RL_TIMER_PCIE_CLK 125 /* 125MHZ */ 507#define RL_USECS(x) ((x) * RL_TIMER_PCIE_CLK) 508 509/* 510 * Gigabit PHY access register (8169 only) 511 */ 512 513#define RL_PHYAR_PHYDATA 0x0000FFFF 514#define RL_PHYAR_PHYREG 0x001F0000 515#define RL_PHYAR_BUSY 0x80000000 516 517/* 518 * Gigabit media status (8169 only) 519 */ 520#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 521#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 522#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 523#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 524#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 525#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 526#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 527#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 528 529/* 530 * The RealTek doesn't use a fragment-based descriptor mechanism. 531 * Instead, there are only four register sets, each or which represents 532 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 533 * packet buffer (32-bit aligned!) and we place the buffer addresses in 534 * the registers so the chip knows where they are. 535 * 536 * We can sort of kludge together the same kind of buffer management 537 * used in previous drivers, but we have to do buffer copies almost all 538 * the time, so it doesn't really buy us much. 539 * 540 * For reception, there's just one large buffer where the chip stores 541 * all received packets. 542 */ 543 544#define RL_RX_BUF_SZ RL_RXBUF_64 545#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 546#define RL_TX_LIST_CNT 4 547#define RL_MIN_FRAMELEN 60 548#define RL_TX_8139_BUF_ALIGN 4 549#define RL_RX_8139_BUF_ALIGN 8 550#define RL_RX_8139_BUF_RESERVE sizeof(int64_t) 551#define RL_RX_8139_BUF_GUARD_SZ \ 552 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE) 553#define RL_TXTHRESH(x) ((x) << 11) 554#define RL_TX_THRESH_INIT 96 555#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 556#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 557#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 558 559#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 560#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 561 562#define RL_ETHER_ALIGN 2 563 564/* 565 * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets. 566 */ 567#define RL_IP4CSUMTX_MINLEN 28 568#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 569 570struct rl_chain_data { 571 uint16_t cur_rx; 572 uint8_t *rl_rx_buf; 573 uint8_t *rl_rx_buf_ptr; 574 575 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 576 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 577 bus_dma_tag_t rl_tx_tag; 578 bus_dma_tag_t rl_rx_tag; 579 bus_dmamap_t rl_rx_dmamap; 580 bus_addr_t rl_rx_buf_paddr; 581 uint8_t last_tx; 582 uint8_t cur_tx; 583}; 584 585#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 586#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 587#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 588#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 589#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 590#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 591#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 592#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 593#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 594 595struct rl_type { 596 uint16_t rl_vid; 597 uint16_t rl_did; 598 int rl_basetype; 599 char *rl_name; 600}; 601 602struct rl_hwrev { 603 uint32_t rl_rev; 604 int rl_type; 605 char *rl_desc; 606 int rl_max_mtu; 607}; 608 609struct rl_mii_frame { 610 uint8_t mii_stdelim; 611 uint8_t mii_opcode; 612 uint8_t mii_phyaddr; 613 uint8_t mii_regaddr; 614 uint8_t mii_turnaround; 615 uint16_t mii_data; 616}; 617 618/* 619 * MII constants 620 */ 621#define RL_MII_STARTDELIM 0x01 622#define RL_MII_READOP 0x02 623#define RL_MII_WRITEOP 0x01 624#define RL_MII_TURNAROUND 0x02 625 626#define RL_8129 1 627#define RL_8139 2 628#define RL_8139CPLUS 3 629#define RL_8169 4 630 631#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 632 (x)->rl_type == RL_8169) 633 634/* 635 * The 8139C+ and 8160 gigE chips support descriptor-based TX 636 * and RX. In fact, they even support TCP large send. Descriptors 637 * must be allocated in contiguous blocks that are aligned on a 638 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 639 */ 640 641/* 642 * RX/TX descriptor definition. When large send mode is enabled, the 643 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 644 * the checksum offload bits are disabled. The structure layout is 645 * the same for RX and TX descriptors 646 */ 647 648struct rl_desc { 649 uint32_t rl_cmdstat; 650 uint32_t rl_vlanctl; 651 uint32_t rl_bufaddr_lo; 652 uint32_t rl_bufaddr_hi; 653}; 654 655#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 656#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 657#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 658#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 659#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 660#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 661#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 662#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 663#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 664#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 665#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 666 667#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 668#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 669/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 670#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 671#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 672#define RL_TDESC_CMD_IPCSUMV2 0x20000000 673#define RL_TDESC_CMD_MSSVALV2 0x1FFC0000 674#define RL_TDESC_CMD_MSSVALV2_SHIFT 18 675 676/* 677 * Error bits are valid only on the last descriptor of a frame 678 * (i.e. RL_TDESC_CMD_EOF == 1) 679 */ 680 681#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 682#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 683#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 684#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 685#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 686#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 687#define RL_TDESC_STAT_OWN 0x80000000 688 689/* 690 * RX descriptor cmd/vlan definitions 691 */ 692 693#define RL_RDESC_CMD_EOR 0x40000000 694#define RL_RDESC_CMD_OWN 0x80000000 695#define RL_RDESC_CMD_BUFLEN 0x00001FFF 696 697#define RL_RDESC_STAT_OWN 0x80000000 698#define RL_RDESC_STAT_EOR 0x40000000 699#define RL_RDESC_STAT_SOF 0x20000000 700#define RL_RDESC_STAT_EOF 0x10000000 701#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 702#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 703#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 704#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 705#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 706#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 707#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 708#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 709#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 710#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 711#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 712#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 713#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 714#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 715#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 716#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 717#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 718#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 719#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 720 RL_RDESC_STAT_CRCERR) 721 722#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 723 (rl_vlandata valid)*/ 724#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 725/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 726#define RL_RDESC_IPV6 0x80000000 727#define RL_RDESC_IPV4 0x40000000 728 729#define RL_PROTOID_NONIP 0x00000000 730#define RL_PROTOID_TCPIP 0x00010000 731#define RL_PROTOID_UDPIP 0x00020000 732#define RL_PROTOID_IP 0x00030000 733#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 734 RL_PROTOID_TCPIP) 735#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 736 RL_PROTOID_UDPIP) 737 738/* 739 * Statistics counter structure (8139C+ and 8169 only) 740 */ 741struct rl_stats { 742 uint64_t rl_tx_pkts; 743 uint64_t rl_rx_pkts; 744 uint64_t rl_tx_errs; 745 uint32_t rl_rx_errs; 746 uint16_t rl_missed_pkts; 747 uint16_t rl_rx_framealign_errs; 748 uint32_t rl_tx_onecoll; 749 uint32_t rl_tx_multicolls; 750 uint64_t rl_rx_ucasts; 751 uint64_t rl_rx_bcasts; 752 uint32_t rl_rx_mcasts; 753 uint16_t rl_tx_aborts; 754 uint16_t rl_rx_underruns; 755}; 756 757/* 758 * Rx/Tx descriptor parameters (8139C+ and 8169 only) 759 * 760 * 8139C+ 761 * Number of descriptors supported : up to 64 762 * Descriptor alignment : 256 bytes 763 * Tx buffer : At least 4 bytes in length. 764 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 765 * 766 * 8169 767 * Number of descriptors supported : up to 1024 768 * Descriptor alignment : 256 bytes 769 * Tx buffer : At least 4 bytes in length. 770 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 771 */ 772#ifndef __NO_STRICT_ALIGNMENT 773#define RE_FIXUP_RX 1 774#endif 775 776#define RL_8169_TX_DESC_CNT 256 777#define RL_8169_RX_DESC_CNT 256 778#define RL_8139_TX_DESC_CNT 64 779#define RL_8139_RX_DESC_CNT 64 780#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT 781#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT 782#define RL_RX_JUMBO_DESC_CNT RL_RX_DESC_CNT 783#define RL_NTXSEGS 32 784 785#define RL_RING_ALIGN 256 786#define RL_DUMP_ALIGN 64 787#define RL_IFQ_MAXLEN 512 788#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 789#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 790#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1)) 791#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 792#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 793#define RL_PKTSZ(x) ((x)/* >> 3*/) 794#ifdef RE_FIXUP_RX 795#define RE_ETHER_ALIGN sizeof(uint64_t) 796#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 797#else 798#define RE_ETHER_ALIGN 0 799#define RE_RX_DESC_BUFLEN MCLBYTES 800#endif 801 802#define RL_MSI_MESSAGES 1 803 804#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 805#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 806 807/* 808 * The number of bits reserved for MSS in RealTek controllers is 809 * 11bits. This limits the maximum interface MTU size in TSO case 810 * as upper stack should not generate TCP segments with MSS greater 811 * than the limit. 812 */ 813#define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN) 814 815/* see comment in dev/re/if_re.c */ 816#define RL_JUMBO_FRAMELEN 7440 817#define RL_JUMBO_MTU \ 818 (RL_JUMBO_FRAMELEN-ETHER_VLAN_ENCAP_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 819#define RL_JUMBO_MTU_6K \ 820 ((6 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 821#define RL_JUMBO_MTU_9K \ 822 ((9 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 823#define RL_MTU \ 824 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 825 826struct rl_txdesc { 827 struct mbuf *tx_m; 828 bus_dmamap_t tx_dmamap; 829}; 830 831struct rl_rxdesc { 832 struct mbuf *rx_m; 833 bus_dmamap_t rx_dmamap; 834 bus_size_t rx_size; 835}; 836 837struct rl_list_data { 838 struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; 839 struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; 840 struct rl_rxdesc rl_jrx_desc[RL_RX_JUMBO_DESC_CNT]; 841 int rl_tx_desc_cnt; 842 int rl_rx_desc_cnt; 843 int rl_tx_prodidx; 844 int rl_rx_prodidx; 845 int rl_tx_considx; 846 int rl_tx_free; 847 bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ 848 bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ 849 bus_dma_tag_t rl_jrx_mtag; /* mbuf RX mapping tag */ 850 bus_dmamap_t rl_rx_sparemap; 851 bus_dmamap_t rl_jrx_sparemap; 852 bus_dma_tag_t rl_stag; /* stats mapping tag */ 853 bus_dmamap_t rl_smap; /* stats map */ 854 struct rl_stats *rl_stats; 855 bus_addr_t rl_stats_addr; 856 bus_dma_tag_t rl_rx_list_tag; 857 bus_dmamap_t rl_rx_list_map; 858 struct rl_desc *rl_rx_list; 859 bus_addr_t rl_rx_list_addr; 860 bus_dma_tag_t rl_tx_list_tag; 861 bus_dmamap_t rl_tx_list_map; 862 struct rl_desc *rl_tx_list; 863 bus_addr_t rl_tx_list_addr; 864}; 865 866enum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE }; 867 868struct rl_softc { 869 struct ifnet *rl_ifp; /* interface info */ 870 bus_space_handle_t rl_bhandle; /* bus space handle */ 871 bus_space_tag_t rl_btag; /* bus space tag */ 872 device_t rl_dev; 873 struct resource *rl_res; 874 int rl_res_id; 875 int rl_res_type; 876 struct resource *rl_res_pba; 877 struct resource *rl_irq[RL_MSI_MESSAGES]; 878 void *rl_intrhand[RL_MSI_MESSAGES]; 879 device_t rl_miibus; 880 bus_dma_tag_t rl_parent_tag; 881 uint8_t rl_type; 882 struct rl_hwrev *rl_hwrev; 883 int rl_eecmd_read; 884 int rl_eewidth; 885 int rl_txthresh; 886 struct rl_chain_data rl_cdata; 887 struct rl_list_data rl_ldata; 888 struct callout rl_stat_callout; 889 int rl_watchdog_timer; 890 struct mtx rl_mtx; 891 struct mbuf *rl_head; 892 struct mbuf *rl_tail; 893 uint32_t rl_rxlenmask; 894 int rl_testmode; 895 int rl_if_flags; 896 int rl_twister_enable; 897 enum rl_twist rl_twister; 898 int rl_twist_row; 899 int rl_twist_col; 900 int suspended; /* 0 = normal 1 = suspended */ 901#ifdef DEVICE_POLLING 902 int rxcycles; 903#endif 904 905 struct task rl_inttask; 906 907 int rl_txstart; 908 int rl_int_rx_act; 909 int rl_int_rx_mod; 910 uint32_t rl_flags; 911#define RL_FLAG_MSI 0x0001 912#define RL_FLAG_AUTOPAD 0x0002 913#define RL_FLAG_PHYWAKE_PM 0x0004 914#define RL_FLAG_PHYWAKE 0x0008 915#define RL_FLAG_JUMBOV2 0x0010 916#define RL_FLAG_PAR 0x0020 917#define RL_FLAG_DESCV2 0x0040 918#define RL_FLAG_MACSTAT 0x0080 919#define RL_FLAG_FASTETHER 0x0100 920#define RL_FLAG_CMDSTOP 0x0200 921#define RL_FLAG_MACRESET 0x0400 922#define RL_FLAG_MSIX 0x0800 923#define RL_FLAG_WOLRXENB 0x1000 924#define RL_FLAG_MACSLEEP 0x2000 925#define RL_FLAG_PCIE 0x4000 926#define RL_FLAG_LINK 0x8000 927}; 928 929#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 930#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 931#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 932 933/* 934 * register space access macros 935 */ 936#define CSR_WRITE_STREAM_4(sc, reg, val) \ 937 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 938#define CSR_WRITE_4(sc, reg, val) \ 939 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 940#define CSR_WRITE_2(sc, reg, val) \ 941 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 942#define CSR_WRITE_1(sc, reg, val) \ 943 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 944 945#define CSR_READ_4(sc, reg) \ 946 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 947#define CSR_READ_2(sc, reg) \ 948 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 949#define CSR_READ_1(sc, reg) \ 950 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 951 952#define CSR_SETBIT_1(sc, offset, val) \ 953 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 954 955#define CSR_CLRBIT_1(sc, offset, val) \ 956 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 957 958#define CSR_SETBIT_2(sc, offset, val) \ 959 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 960 961#define CSR_CLRBIT_2(sc, offset, val) \ 962 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 963 964#define CSR_SETBIT_4(sc, offset, val) \ 965 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 966 967#define CSR_CLRBIT_4(sc, offset, val) \ 968 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 969 970#define RL_TIMEOUT 1000 971#define RL_PHY_TIMEOUT 2000 972 973/* 974 * General constants that are fun to know. 975 * 976 * RealTek PCI vendor ID 977 */ 978#define RT_VENDORID 0x10EC 979 980/* 981 * RealTek chip device IDs. 982 */ 983#define RT_DEVICEID_8139D 0x8039 984#define RT_DEVICEID_8129 0x8129 985#define RT_DEVICEID_8101E 0x8136 986#define RT_DEVICEID_8138 0x8138 987#define RT_DEVICEID_8139 0x8139 988#define RT_DEVICEID_8169SC 0x8167 989#define RT_DEVICEID_8168 0x8168 990#define RT_DEVICEID_8169 0x8169 991#define RT_DEVICEID_8100 0x8100 992 993#define RT_REVID_8139CPLUS 0x20 994 995/* 996 * Accton PCI vendor ID 997 */ 998#define ACCTON_VENDORID 0x1113 999 1000/* 1001 * Accton MPX 5030/5038 device ID. 1002 */ 1003#define ACCTON_DEVICEID_5030 0x1211 1004 1005/* 1006 * Nortel PCI vendor ID 1007 */ 1008#define NORTEL_VENDORID 0x126C 1009 1010/* 1011 * Delta Electronics Vendor ID. 1012 */ 1013#define DELTA_VENDORID 0x1500 1014 1015/* 1016 * Delta device IDs. 1017 */ 1018#define DELTA_DEVICEID_8139 0x1360 1019 1020/* 1021 * Addtron vendor ID. 1022 */ 1023#define ADDTRON_VENDORID 0x4033 1024 1025/* 1026 * Addtron device IDs. 1027 */ 1028#define ADDTRON_DEVICEID_8139 0x1360 1029 1030/* 1031 * D-Link vendor ID. 1032 */ 1033#define DLINK_VENDORID 0x1186 1034 1035/* 1036 * D-Link DFE-530TX+ device ID 1037 */ 1038#define DLINK_DEVICEID_530TXPLUS 0x1300 1039 1040/* 1041 * D-Link DFE-5280T device ID 1042 */ 1043#define DLINK_DEVICEID_528T 0x4300 1044 1045/* 1046 * D-Link DFE-690TXD device ID 1047 */ 1048#define DLINK_DEVICEID_690TXD 0x1340 1049 1050/* 1051 * Corega K.K vendor ID 1052 */ 1053#define COREGA_VENDORID 0x1259 1054 1055/* 1056 * Corega FEther CB-TXD device ID 1057 */ 1058#define COREGA_DEVICEID_FETHERCBTXD 0xa117 1059 1060/* 1061 * Corega FEtherII CB-TXD device ID 1062 */ 1063#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 1064 1065/* 1066 * Corega CG-LAPCIGT device ID 1067 */ 1068#define COREGA_DEVICEID_CGLAPCIGT 0xc107 1069 1070/* 1071 * Linksys vendor ID 1072 */ 1073#define LINKSYS_VENDORID 0x1737 1074 1075/* 1076 * Linksys EG1032 device ID 1077 */ 1078#define LINKSYS_DEVICEID_EG1032 0x1032 1079 1080/* 1081 * Linksys EG1032 rev 3 sub-device ID 1082 */ 1083#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 1084 1085/* 1086 * Peppercon vendor ID 1087 */ 1088#define PEPPERCON_VENDORID 0x1743 1089 1090/* 1091 * Peppercon ROL-F device ID 1092 */ 1093#define PEPPERCON_DEVICEID_ROLF 0x8139 1094 1095/* 1096 * Planex Communications, Inc. vendor ID 1097 */ 1098#define PLANEX_VENDORID 0x14ea 1099 1100/* 1101 * Planex FNW-3603-TX device ID 1102 */ 1103#define PLANEX_DEVICEID_FNW3603TX 0xab06 1104 1105/* 1106 * Planex FNW-3800-TX device ID 1107 */ 1108#define PLANEX_DEVICEID_FNW3800TX 0xab07 1109 1110/* 1111 * LevelOne vendor ID 1112 */ 1113#define LEVEL1_VENDORID 0x018A 1114 1115/* 1116 * LevelOne FPC-0106TX devide ID 1117 */ 1118#define LEVEL1_DEVICEID_FPC0106TX 0x0106 1119 1120/* 1121 * Compaq vendor ID 1122 */ 1123#define CP_VENDORID 0x021B 1124 1125/* 1126 * Edimax vendor ID 1127 */ 1128#define EDIMAX_VENDORID 0x13D1 1129 1130/* 1131 * Edimax EP-4103DL cardbus device ID 1132 */ 1133#define EDIMAX_DEVICEID_EP4103DL 0xAB06 1134 1135/* US Robotics vendor ID */ 1136 1137#define USR_VENDORID 0x16EC 1138 1139/* US Robotics 997902 device ID */ 1140 1141#define USR_DEVICEID_997902 0x0116 1142