if_rlreg.h revision 217498
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_rlreg.h 217498 2011-01-17 02:23:50Z yongari $ 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 41#define RL_IDR3 0x0003 42#define RL_IDR4 0x0004 43#define RL_IDR5 0x0005 44 /* 0006-0007 reserved */ 45#define RL_MAR0 0x0008 /* Multicast hash table */ 46#define RL_MAR1 0x0009 47#define RL_MAR2 0x000A 48#define RL_MAR3 0x000B 49#define RL_MAR4 0x000C 50#define RL_MAR5 0x000D 51#define RL_MAR6 0x000E 52#define RL_MAR7 0x000F 53 54#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 58 59#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 63 64#define RL_RXADDR 0x0030 /* RX ring start address */ 65#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67#define RL_COMMAND 0x0037 /* command register */ 68#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70#define RL_IMR 0x003C /* interrupt mask register */ 71#define RL_ISR 0x003E /* interrupt status register */ 72#define RL_TXCFG 0x0040 /* transmit config */ 73#define RL_RXCFG 0x0044 /* receive config */ 74#define RL_TIMERCNT 0x0048 /* timer count register */ 75#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76#define RL_EECMD 0x0050 /* EEPROM command register */ 77#define RL_CFG0 0x0051 /* config register #0 */ 78#define RL_CFG1 0x0052 /* config register #1 */ 79#define RL_CFG2 0x0053 /* config register #2 */ 80#define RL_CFG3 0x0054 /* config register #3 */ 81#define RL_CFG4 0x0055 /* config register #4 */ 82#define RL_CFG5 0x0056 /* config register #5 */ 83 /* 0057 reserved */ 84#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 85 /* 0059-005A reserved */ 86#define RL_MII 0x005A /* 8129 chip only */ 87#define RL_HALTCLK 0x005B 88#define RL_MULTIINTR 0x005C /* multiple interrupt */ 89#define RL_PCIREV 0x005E /* PCI revision value */ 90 /* 005F reserved */ 91#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 92 93/* Direct PHY access registers only available on 8139 */ 94#define RL_BMCR 0x0062 /* PHY basic mode control */ 95#define RL_BMSR 0x0064 /* PHY basic mode status */ 96#define RL_ANAR 0x0066 /* PHY autoneg advert */ 97#define RL_LPAR 0x0068 /* PHY link partner ability */ 98#define RL_ANER 0x006A /* PHY autoneg expansion */ 99 100#define RL_DISCCNT 0x006C /* disconnect counter */ 101#define RL_FALSECAR 0x006E /* false carrier counter */ 102#define RL_NWAYTST 0x0070 /* NWAY test register */ 103#define RL_RX_ER 0x0072 /* RX_ER counter */ 104#define RL_CSCFG 0x0074 /* CS configuration register */ 105 106/* 107 * When operating in special C+ mode, some of the registers in an 108 * 8139C+ chip have different definitions. These are also used for 109 * the 8169 gigE chip. 110 */ 111#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 112#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 113#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 114#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 115#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 116#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 117#define RL_CFG2 0x0053 118#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 119#define RL_TXSTART 0x00D9 /* 8 bits */ 120#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 121#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 122#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 123#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 124 125/* 126 * Registers specific to the 8169 gigE chip 127 */ 128#define RL_GTXSTART 0x0038 /* 8 bits */ 129#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 130#define RL_PHYAR 0x0060 131#define RL_TBICSR 0x0064 132#define RL_TBI_ANAR 0x0068 133#define RL_TBI_LPAR 0x006A 134#define RL_GMEDIASTAT 0x006C /* 8 bits */ 135#define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */ 136#define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */ 137#define RL_PMCH 0x006F /* 8 bits */ 138#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 139#define RL_INTRMOD 0x00E2 /* 16 bits */ 140 141/* 142 * TX config register bits 143 */ 144#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 145#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 146#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 147#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 148#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 149#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 150#define RL_TXCFG_HWREV 0x7CC00000 151 152#define RL_LOOPTEST_OFF 0x00000000 153#define RL_LOOPTEST_ON 0x00020000 154#define RL_LOOPTEST_ON_CPLUS 0x00060000 155 156/* Known revision codes. */ 157 158#define RL_HWREV_8169 0x00000000 159#define RL_HWREV_8169S 0x00800000 160#define RL_HWREV_8110S 0x04000000 161#define RL_HWREV_8169_8110SB 0x10000000 162#define RL_HWREV_8169_8110SC 0x18000000 163#define RL_HWREV_8102EL 0x24800000 164#define RL_HWREV_8102EL_SPIN1 0x24C00000 165#define RL_HWREV_8168D 0x28000000 166#define RL_HWREV_8168DP 0x28800000 167#define RL_HWREV_8168E 0x2C000000 168#define RL_HWREV_8168E_VL 0x2C800000 169#define RL_HWREV_8168_SPIN1 0x30000000 170#define RL_HWREV_8100E 0x30800000 171#define RL_HWREV_8101E 0x34000000 172#define RL_HWREV_8102E 0x34800000 173#define RL_HWREV_8103E 0x34C00000 174#define RL_HWREV_8168_SPIN2 0x38000000 175#define RL_HWREV_8168_SPIN3 0x38400000 176#define RL_HWREV_8168C 0x3C000000 177#define RL_HWREV_8168C_SPIN2 0x3C400000 178#define RL_HWREV_8168CP 0x3C800000 179#define RL_HWREV_8139 0x60000000 180#define RL_HWREV_8139A 0x70000000 181#define RL_HWREV_8139AG 0x70800000 182#define RL_HWREV_8139B 0x78000000 183#define RL_HWREV_8130 0x7C000000 184#define RL_HWREV_8139C 0x74000000 185#define RL_HWREV_8139D 0x74400000 186#define RL_HWREV_8139CPLUS 0x74800000 187#define RL_HWREV_8101 0x74C00000 188#define RL_HWREV_8100 0x78800000 189#define RL_HWREV_8169_8110SBL 0x7CC00000 190#define RL_HWREV_8169_8110SCE 0x98000000 191 192#define RL_TXDMA_16BYTES 0x00000000 193#define RL_TXDMA_32BYTES 0x00000100 194#define RL_TXDMA_64BYTES 0x00000200 195#define RL_TXDMA_128BYTES 0x00000300 196#define RL_TXDMA_256BYTES 0x00000400 197#define RL_TXDMA_512BYTES 0x00000500 198#define RL_TXDMA_1024BYTES 0x00000600 199#define RL_TXDMA_2048BYTES 0x00000700 200 201/* 202 * Transmit descriptor status register bits. 203 */ 204#define RL_TXSTAT_LENMASK 0x00001FFF 205#define RL_TXSTAT_OWN 0x00002000 206#define RL_TXSTAT_TX_UNDERRUN 0x00004000 207#define RL_TXSTAT_TX_OK 0x00008000 208#define RL_TXSTAT_EARLY_THRESH 0x003F0000 209#define RL_TXSTAT_COLLCNT 0x0F000000 210#define RL_TXSTAT_CARR_HBEAT 0x10000000 211#define RL_TXSTAT_OUTOFWIN 0x20000000 212#define RL_TXSTAT_TXABRT 0x40000000 213#define RL_TXSTAT_CARRLOSS 0x80000000 214 215/* 216 * Interrupt status register bits. 217 */ 218#define RL_ISR_RX_OK 0x0001 219#define RL_ISR_RX_ERR 0x0002 220#define RL_ISR_TX_OK 0x0004 221#define RL_ISR_TX_ERR 0x0008 222#define RL_ISR_RX_OVERRUN 0x0010 223#define RL_ISR_PKT_UNDERRUN 0x0020 224#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 225#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 226#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 227#define RL_ISR_SWI 0x0100 /* C+ only */ 228#define RL_ISR_CABLE_LEN_CHGD 0x2000 229#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 230#define RL_ISR_TIMEOUT_EXPIRED 0x4000 231#define RL_ISR_SYSTEM_ERR 0x8000 232 233#define RL_INTRS \ 234 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 235 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 236 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 237 238#ifdef RE_TX_MODERATION 239#define RL_INTRS_CPLUS \ 240 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 241 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 242 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 243#else 244#define RL_INTRS_CPLUS \ 245 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 246 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 247 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 248#endif 249 250/* 251 * Media status register. (8139 only) 252 */ 253#define RL_MEDIASTAT_RXPAUSE 0x01 254#define RL_MEDIASTAT_TXPAUSE 0x02 255#define RL_MEDIASTAT_LINK 0x04 256#define RL_MEDIASTAT_SPEED10 0x08 257#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 258#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 259 260/* 261 * Receive config register. 262 */ 263#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 264#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 265#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 266#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 267#define RL_RXCFG_RX_RUNT 0x00000010 268#define RL_RXCFG_RX_ERRPKT 0x00000020 269#define RL_RXCFG_WRAP 0x00000080 270#define RL_RXCFG_MAXDMA 0x00000700 271#define RL_RXCFG_BUFSZ 0x00001800 272#define RL_RXCFG_FIFOTHRESH 0x0000E000 273#define RL_RXCFG_EARLYTHRESH 0x07000000 274 275#define RL_RXDMA_16BYTES 0x00000000 276#define RL_RXDMA_32BYTES 0x00000100 277#define RL_RXDMA_64BYTES 0x00000200 278#define RL_RXDMA_128BYTES 0x00000300 279#define RL_RXDMA_256BYTES 0x00000400 280#define RL_RXDMA_512BYTES 0x00000500 281#define RL_RXDMA_1024BYTES 0x00000600 282#define RL_RXDMA_UNLIMITED 0x00000700 283 284#define RL_RXBUF_8 0x00000000 285#define RL_RXBUF_16 0x00000800 286#define RL_RXBUF_32 0x00001000 287#define RL_RXBUF_64 0x00001800 288 289#define RL_RXFIFO_16BYTES 0x00000000 290#define RL_RXFIFO_32BYTES 0x00002000 291#define RL_RXFIFO_64BYTES 0x00004000 292#define RL_RXFIFO_128BYTES 0x00006000 293#define RL_RXFIFO_256BYTES 0x00008000 294#define RL_RXFIFO_512BYTES 0x0000A000 295#define RL_RXFIFO_1024BYTES 0x0000C000 296#define RL_RXFIFO_NOTHRESH 0x0000E000 297 298/* 299 * Bits in RX status header (included with RX'ed packet 300 * in ring buffer). 301 */ 302#define RL_RXSTAT_RXOK 0x00000001 303#define RL_RXSTAT_ALIGNERR 0x00000002 304#define RL_RXSTAT_CRCERR 0x00000004 305#define RL_RXSTAT_GIANT 0x00000008 306#define RL_RXSTAT_RUNT 0x00000010 307#define RL_RXSTAT_BADSYM 0x00000020 308#define RL_RXSTAT_BROAD 0x00002000 309#define RL_RXSTAT_INDIV 0x00004000 310#define RL_RXSTAT_MULTI 0x00008000 311#define RL_RXSTAT_LENMASK 0xFFFF0000 312 313#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 314/* 315 * Command register. 316 */ 317#define RL_CMD_EMPTY_RXBUF 0x0001 318#define RL_CMD_TX_ENB 0x0004 319#define RL_CMD_RX_ENB 0x0008 320#define RL_CMD_RESET 0x0010 321#define RL_CMD_STOPREQ 0x0080 322 323/* 324 * Twister register values. These are completely undocumented and derived 325 * from public sources. 326 */ 327#define RL_CSCFG_LINK_OK 0x0400 328#define RL_CSCFG_CHANGE 0x0800 329#define RL_CSCFG_STATUS 0xf000 330#define RL_CSCFG_ROW3 0x7000 331#define RL_CSCFG_ROW2 0x3000 332#define RL_CSCFG_ROW1 0x1000 333#define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0 334#define RL_CSCFG_LINK_DOWN_CMD 0xf3c0 335 336#define RL_NWAYTST_RESET 0 337#define RL_NWAYTST_CBL_TEST 0x20 338 339#define RL_PARA78 0x78 340#define RL_PARA78_DEF 0x78fa8388 341#define RL_PARA7C 0x7C 342#define RL_PARA7C_DEF 0xcb38de43 343#define RL_PARA7C_RETUNE 0xfb38de03 344/* 345 * EEPROM control register 346 */ 347#define RL_EE_DATAOUT 0x01 /* Data out */ 348#define RL_EE_DATAIN 0x02 /* Data in */ 349#define RL_EE_CLK 0x04 /* clock */ 350#define RL_EE_SEL 0x08 /* chip select */ 351#define RL_EE_MODE (0x40|0x80) 352 353#define RL_EEMODE_OFF 0x00 354#define RL_EEMODE_AUTOLOAD 0x40 355#define RL_EEMODE_PROGRAM 0x80 356#define RL_EEMODE_WRITECFG (0x80|0x40) 357 358/* 9346 EEPROM commands */ 359#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 360#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 361 362#define RL_9346_WRITE 0x5 363#define RL_9346_READ 0x6 364#define RL_9346_ERASE 0x7 365#define RL_9346_EWEN 0x4 366#define RL_9346_EWEN_ADDR 0x30 367#define RL_9456_EWDS 0x4 368#define RL_9346_EWDS_ADDR 0x00 369 370#define RL_EECMD_WRITE 0x140 371#define RL_EECMD_READ_6BIT 0x180 372#define RL_EECMD_READ_8BIT 0x600 373#define RL_EECMD_ERASE 0x1c0 374 375#define RL_EE_ID 0x00 376#define RL_EE_PCI_VID 0x01 377#define RL_EE_PCI_DID 0x02 378/* Location of station address inside EEPROM */ 379#define RL_EE_EADDR 0x07 380 381/* 382 * MII register (8129 only) 383 */ 384#define RL_MII_CLK 0x01 385#define RL_MII_DATAIN 0x02 386#define RL_MII_DATAOUT 0x04 387#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 388 389/* 390 * Config 0 register 391 */ 392#define RL_CFG0_ROM0 0x01 393#define RL_CFG0_ROM1 0x02 394#define RL_CFG0_ROM2 0x04 395#define RL_CFG0_PL0 0x08 396#define RL_CFG0_PL1 0x10 397#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 398#define RL_CFG0_PCS 0x40 399#define RL_CFG0_SCR 0x80 400 401/* 402 * Config 1 register 403 */ 404#define RL_CFG1_PWRDWN 0x01 405#define RL_CFG1_PME 0x01 406#define RL_CFG1_SLEEP 0x02 407#define RL_CFG1_VPDEN 0x02 408#define RL_CFG1_IOMAP 0x04 409#define RL_CFG1_MEMMAP 0x08 410#define RL_CFG1_RSVD 0x10 411#define RL_CFG1_LWACT 0x10 412#define RL_CFG1_DRVLOAD 0x20 413#define RL_CFG1_LED0 0x40 414#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 415#define RL_CFG1_LED1 0x80 416 417/* 418 * Config 2 register 419 */ 420#define RL_CFG2_PCI33MHZ 0x00 421#define RL_CFG2_PCI66MHZ 0x01 422#define RL_CFG2_PCI64BIT 0x08 423#define RL_CFG2_AUXPWR 0x10 424#define RL_CFG2_MSI 0x20 425 426/* 427 * Config 3 register 428 */ 429#define RL_CFG3_GRANTSEL 0x80 430#define RL_CFG3_WOL_MAGIC 0x20 431#define RL_CFG3_WOL_LINK 0x10 432#define RL_CFG3_FAST_B2B 0x01 433 434/* 435 * Config 4 register 436 */ 437#define RL_CFG4_LWPTN 0x04 438#define RL_CFG4_LWPME 0x10 439 440/* 441 * Config 5 register 442 */ 443#define RL_CFG5_WOL_BCAST 0x40 444#define RL_CFG5_WOL_MCAST 0x20 445#define RL_CFG5_WOL_UCAST 0x10 446#define RL_CFG5_WOL_LANWAKE 0x02 447#define RL_CFG5_PME_STS 0x01 448 449/* 450 * 8139C+ register definitions 451 */ 452 453/* RL_DUMPSTATS_LO register */ 454 455#define RL_DUMPSTATS_START 0x00000008 456 457/* Transmit start register */ 458 459#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 460#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 461#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 462 463/* 464 * Config 2 register, 8139C+/8169/8169S/8110S only 465 */ 466#define RL_CFG2_BUSFREQ 0x07 467#define RL_CFG2_BUSWIDTH 0x08 468#define RL_CFG2_AUXPWRSTS 0x10 469 470#define RL_BUSFREQ_33MHZ 0x00 471#define RL_BUSFREQ_66MHZ 0x01 472 473#define RL_BUSWIDTH_32BITS 0x00 474#define RL_BUSWIDTH_64BITS 0x08 475 476/* C+ mode command register */ 477 478#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 479#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 480#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 481#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 482#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 483#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 484#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 485#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 486#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 487#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 488#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 489#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 490#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 491#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 492#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 493 494/* C+ early transmit threshold */ 495 496#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 497 498/* 499 * Gigabit PHY access register (8169 only) 500 */ 501 502#define RL_PHYAR_PHYDATA 0x0000FFFF 503#define RL_PHYAR_PHYREG 0x001F0000 504#define RL_PHYAR_BUSY 0x80000000 505 506/* 507 * Gigabit media status (8169 only) 508 */ 509#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 510#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 511#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 512#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 513#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 514#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 515#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 516#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 517 518/* 519 * The RealTek doesn't use a fragment-based descriptor mechanism. 520 * Instead, there are only four register sets, each or which represents 521 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 522 * packet buffer (32-bit aligned!) and we place the buffer addresses in 523 * the registers so the chip knows where they are. 524 * 525 * We can sort of kludge together the same kind of buffer management 526 * used in previous drivers, but we have to do buffer copies almost all 527 * the time, so it doesn't really buy us much. 528 * 529 * For reception, there's just one large buffer where the chip stores 530 * all received packets. 531 */ 532 533#define RL_RX_BUF_SZ RL_RXBUF_64 534#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 535#define RL_TX_LIST_CNT 4 536#define RL_MIN_FRAMELEN 60 537#define RL_TX_8139_BUF_ALIGN 4 538#define RL_RX_8139_BUF_ALIGN 8 539#define RL_RX_8139_BUF_RESERVE sizeof(int64_t) 540#define RL_RX_8139_BUF_GUARD_SZ \ 541 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE) 542#define RL_TXTHRESH(x) ((x) << 11) 543#define RL_TX_THRESH_INIT 96 544#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 545#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 546#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 547 548#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 549#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 550 551#define RL_ETHER_ALIGN 2 552 553/* 554 * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets. 555 */ 556#define RL_IP4CSUMTX_MINLEN 28 557#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 558 559struct rl_chain_data { 560 uint16_t cur_rx; 561 uint8_t *rl_rx_buf; 562 uint8_t *rl_rx_buf_ptr; 563 564 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 565 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 566 bus_dma_tag_t rl_tx_tag; 567 bus_dma_tag_t rl_rx_tag; 568 bus_dmamap_t rl_rx_dmamap; 569 bus_addr_t rl_rx_buf_paddr; 570 uint8_t last_tx; 571 uint8_t cur_tx; 572}; 573 574#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 575#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 576#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 577#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 578#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 579#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 580#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 581#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 582#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 583 584struct rl_type { 585 uint16_t rl_vid; 586 uint16_t rl_did; 587 int rl_basetype; 588 char *rl_name; 589}; 590 591struct rl_hwrev { 592 uint32_t rl_rev; 593 int rl_type; 594 char *rl_desc; 595}; 596 597struct rl_mii_frame { 598 uint8_t mii_stdelim; 599 uint8_t mii_opcode; 600 uint8_t mii_phyaddr; 601 uint8_t mii_regaddr; 602 uint8_t mii_turnaround; 603 uint16_t mii_data; 604}; 605 606/* 607 * MII constants 608 */ 609#define RL_MII_STARTDELIM 0x01 610#define RL_MII_READOP 0x02 611#define RL_MII_WRITEOP 0x01 612#define RL_MII_TURNAROUND 0x02 613 614#define RL_8129 1 615#define RL_8139 2 616#define RL_8139CPLUS 3 617#define RL_8169 4 618 619#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 620 (x)->rl_type == RL_8169) 621 622/* 623 * The 8139C+ and 8160 gigE chips support descriptor-based TX 624 * and RX. In fact, they even support TCP large send. Descriptors 625 * must be allocated in contiguous blocks that are aligned on a 626 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 627 */ 628 629/* 630 * RX/TX descriptor definition. When large send mode is enabled, the 631 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 632 * the checksum offload bits are disabled. The structure layout is 633 * the same for RX and TX descriptors 634 */ 635 636struct rl_desc { 637 uint32_t rl_cmdstat; 638 uint32_t rl_vlanctl; 639 uint32_t rl_bufaddr_lo; 640 uint32_t rl_bufaddr_hi; 641}; 642 643#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 644#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 645#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 646#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 647#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 648#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 649#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 650#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 651#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 652#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 653#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 654 655#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 656#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 657/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 658#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 659#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 660#define RL_TDESC_CMD_IPCSUMV2 0x20000000 661#define RL_TDESC_CMD_MSSVALV2 0x1FFC0000 662#define RL_TDESC_CMD_MSSVALV2_SHIFT 18 663 664/* 665 * Error bits are valid only on the last descriptor of a frame 666 * (i.e. RL_TDESC_CMD_EOF == 1) 667 */ 668 669#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 670#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 671#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 672#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 673#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 674#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 675#define RL_TDESC_STAT_OWN 0x80000000 676 677/* 678 * RX descriptor cmd/vlan definitions 679 */ 680 681#define RL_RDESC_CMD_EOR 0x40000000 682#define RL_RDESC_CMD_OWN 0x80000000 683#define RL_RDESC_CMD_BUFLEN 0x00001FFF 684 685#define RL_RDESC_STAT_OWN 0x80000000 686#define RL_RDESC_STAT_EOR 0x40000000 687#define RL_RDESC_STAT_SOF 0x20000000 688#define RL_RDESC_STAT_EOF 0x10000000 689#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 690#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 691#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 692#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 693#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 694#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 695#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 696#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 697#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 698#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 699#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 700#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 701#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 702#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 703#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 704#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 705#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 706#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 707#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 708 RL_RDESC_STAT_CRCERR) 709 710#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 711 (rl_vlandata valid)*/ 712#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 713/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 714#define RL_RDESC_IPV6 0x80000000 715#define RL_RDESC_IPV4 0x40000000 716 717#define RL_PROTOID_NONIP 0x00000000 718#define RL_PROTOID_TCPIP 0x00010000 719#define RL_PROTOID_UDPIP 0x00020000 720#define RL_PROTOID_IP 0x00030000 721#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 722 RL_PROTOID_TCPIP) 723#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 724 RL_PROTOID_UDPIP) 725 726/* 727 * Statistics counter structure (8139C+ and 8169 only) 728 */ 729struct rl_stats { 730 uint64_t rl_tx_pkts; 731 uint64_t rl_rx_pkts; 732 uint64_t rl_tx_errs; 733 uint32_t rl_rx_errs; 734 uint16_t rl_missed_pkts; 735 uint16_t rl_rx_framealign_errs; 736 uint32_t rl_tx_onecoll; 737 uint32_t rl_tx_multicolls; 738 uint64_t rl_rx_ucasts; 739 uint64_t rl_rx_bcasts; 740 uint32_t rl_rx_mcasts; 741 uint16_t rl_tx_aborts; 742 uint16_t rl_rx_underruns; 743}; 744 745/* 746 * Rx/Tx descriptor parameters (8139C+ and 8169 only) 747 * 748 * 8139C+ 749 * Number of descriptors supported : up to 64 750 * Descriptor alignment : 256 bytes 751 * Tx buffer : At least 4 bytes in length. 752 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 753 * 754 * 8169 755 * Number of descriptors supported : up to 1024 756 * Descriptor alignment : 256 bytes 757 * Tx buffer : At least 4 bytes in length. 758 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 759 */ 760#ifndef __NO_STRICT_ALIGNMENT 761#define RE_FIXUP_RX 1 762#endif 763 764#define RL_8169_TX_DESC_CNT 256 765#define RL_8169_RX_DESC_CNT 256 766#define RL_8139_TX_DESC_CNT 64 767#define RL_8139_RX_DESC_CNT 64 768#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT 769#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT 770#define RL_NTXSEGS 32 771 772#define RL_RING_ALIGN 256 773#define RL_DUMP_ALIGN 64 774#define RL_IFQ_MAXLEN 512 775#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 776#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 777#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1)) 778#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 779#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 780#define RL_PKTSZ(x) ((x)/* >> 3*/) 781#ifdef RE_FIXUP_RX 782#define RE_ETHER_ALIGN sizeof(uint64_t) 783#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 784#else 785#define RE_ETHER_ALIGN 0 786#define RE_RX_DESC_BUFLEN MCLBYTES 787#endif 788 789#define RL_MSI_MESSAGES 1 790 791#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 792#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 793 794/* 795 * The number of bits reserved for MSS in RealTek controllers is 796 * 11bits. This limits the maximum interface MTU size in TSO case 797 * as upper stack should not generate TCP segments with MSS greater 798 * than the limit. 799 */ 800#define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN) 801 802/* see comment in dev/re/if_re.c */ 803#define RL_JUMBO_FRAMELEN 7440 804#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 805#define RL_MAX_FRAMELEN \ 806 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 807 808struct rl_txdesc { 809 struct mbuf *tx_m; 810 bus_dmamap_t tx_dmamap; 811}; 812 813struct rl_rxdesc { 814 struct mbuf *rx_m; 815 bus_dmamap_t rx_dmamap; 816 bus_size_t rx_size; 817}; 818 819struct rl_list_data { 820 struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; 821 struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; 822 int rl_tx_desc_cnt; 823 int rl_rx_desc_cnt; 824 int rl_tx_prodidx; 825 int rl_rx_prodidx; 826 int rl_tx_considx; 827 int rl_tx_free; 828 bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ 829 bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ 830 bus_dmamap_t rl_rx_sparemap; 831 bus_dma_tag_t rl_stag; /* stats mapping tag */ 832 bus_dmamap_t rl_smap; /* stats map */ 833 struct rl_stats *rl_stats; 834 bus_addr_t rl_stats_addr; 835 bus_dma_tag_t rl_rx_list_tag; 836 bus_dmamap_t rl_rx_list_map; 837 struct rl_desc *rl_rx_list; 838 bus_addr_t rl_rx_list_addr; 839 bus_dma_tag_t rl_tx_list_tag; 840 bus_dmamap_t rl_tx_list_map; 841 struct rl_desc *rl_tx_list; 842 bus_addr_t rl_tx_list_addr; 843}; 844 845enum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE }; 846 847struct rl_softc { 848 struct ifnet *rl_ifp; /* interface info */ 849 bus_space_handle_t rl_bhandle; /* bus space handle */ 850 bus_space_tag_t rl_btag; /* bus space tag */ 851 device_t rl_dev; 852 struct resource *rl_res; 853 int rl_res_id; 854 int rl_res_type; 855 struct resource *rl_irq[RL_MSI_MESSAGES]; 856 void *rl_intrhand[RL_MSI_MESSAGES]; 857 device_t rl_miibus; 858 bus_dma_tag_t rl_parent_tag; 859 uint8_t rl_type; 860 int rl_eecmd_read; 861 int rl_eewidth; 862 uint8_t rl_stats_no_timeout; 863 int rl_txthresh; 864 struct rl_chain_data rl_cdata; 865 struct rl_list_data rl_ldata; 866 struct callout rl_stat_callout; 867 int rl_watchdog_timer; 868 struct mtx rl_mtx; 869 struct mbuf *rl_head; 870 struct mbuf *rl_tail; 871 uint32_t rl_hwrev; 872 uint32_t rl_rxlenmask; 873 int rl_testmode; 874 int rl_if_flags; 875 int rl_twister_enable; 876 enum rl_twist rl_twister; 877 int rl_twist_row; 878 int rl_twist_col; 879 int suspended; /* 0 = normal 1 = suspended */ 880#ifdef DEVICE_POLLING 881 int rxcycles; 882#endif 883 884 struct task rl_txtask; 885 struct task rl_inttask; 886 887 int rl_txstart; 888 uint32_t rl_flags; 889#define RL_FLAG_MSI 0x0001 890#define RL_FLAG_AUTOPAD 0x0002 891#define RL_FLAG_PHYWAKE_PM 0x0004 892#define RL_FLAG_PHYWAKE 0x0008 893#define RL_FLAG_NOJUMBO 0x0010 894#define RL_FLAG_PAR 0x0020 895#define RL_FLAG_DESCV2 0x0040 896#define RL_FLAG_MACSTAT 0x0080 897#define RL_FLAG_FASTETHER 0x0100 898#define RL_FLAG_CMDSTOP 0x0200 899#define RL_FLAG_MACRESET 0x0400 900#define RL_FLAG_WOLRXENB 0x1000 901#define RL_FLAG_MACSLEEP 0x2000 902#define RL_FLAG_PCIE 0x4000 903#define RL_FLAG_LINK 0x8000 904}; 905 906#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 907#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 908#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 909 910/* 911 * register space access macros 912 */ 913#define CSR_WRITE_STREAM_4(sc, reg, val) \ 914 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 915#define CSR_WRITE_4(sc, reg, val) \ 916 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 917#define CSR_WRITE_2(sc, reg, val) \ 918 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 919#define CSR_WRITE_1(sc, reg, val) \ 920 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 921 922#define CSR_READ_4(sc, reg) \ 923 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 924#define CSR_READ_2(sc, reg) \ 925 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 926#define CSR_READ_1(sc, reg) \ 927 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 928 929#define CSR_SETBIT_1(sc, offset, val) \ 930 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 931 932#define CSR_CLRBIT_1(sc, offset, val) \ 933 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 934 935#define CSR_SETBIT_2(sc, offset, val) \ 936 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 937 938#define CSR_CLRBIT_2(sc, offset, val) \ 939 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 940 941#define CSR_SETBIT_4(sc, offset, val) \ 942 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 943 944#define CSR_CLRBIT_4(sc, offset, val) \ 945 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 946 947#define RL_TIMEOUT 1000 948#define RL_PHY_TIMEOUT 2000 949 950/* 951 * General constants that are fun to know. 952 * 953 * RealTek PCI vendor ID 954 */ 955#define RT_VENDORID 0x10EC 956 957/* 958 * RealTek chip device IDs. 959 */ 960#define RT_DEVICEID_8139D 0x8039 961#define RT_DEVICEID_8129 0x8129 962#define RT_DEVICEID_8101E 0x8136 963#define RT_DEVICEID_8138 0x8138 964#define RT_DEVICEID_8139 0x8139 965#define RT_DEVICEID_8169SC 0x8167 966#define RT_DEVICEID_8168 0x8168 967#define RT_DEVICEID_8169 0x8169 968#define RT_DEVICEID_8100 0x8100 969 970#define RT_REVID_8139CPLUS 0x20 971 972/* 973 * Accton PCI vendor ID 974 */ 975#define ACCTON_VENDORID 0x1113 976 977/* 978 * Accton MPX 5030/5038 device ID. 979 */ 980#define ACCTON_DEVICEID_5030 0x1211 981 982/* 983 * Nortel PCI vendor ID 984 */ 985#define NORTEL_VENDORID 0x126C 986 987/* 988 * Delta Electronics Vendor ID. 989 */ 990#define DELTA_VENDORID 0x1500 991 992/* 993 * Delta device IDs. 994 */ 995#define DELTA_DEVICEID_8139 0x1360 996 997/* 998 * Addtron vendor ID. 999 */ 1000#define ADDTRON_VENDORID 0x4033 1001 1002/* 1003 * Addtron device IDs. 1004 */ 1005#define ADDTRON_DEVICEID_8139 0x1360 1006 1007/* 1008 * D-Link vendor ID. 1009 */ 1010#define DLINK_VENDORID 0x1186 1011 1012/* 1013 * D-Link DFE-530TX+ device ID 1014 */ 1015#define DLINK_DEVICEID_530TXPLUS 0x1300 1016 1017/* 1018 * D-Link DFE-5280T device ID 1019 */ 1020#define DLINK_DEVICEID_528T 0x4300 1021 1022/* 1023 * D-Link DFE-690TXD device ID 1024 */ 1025#define DLINK_DEVICEID_690TXD 0x1340 1026 1027/* 1028 * Corega K.K vendor ID 1029 */ 1030#define COREGA_VENDORID 0x1259 1031 1032/* 1033 * Corega FEther CB-TXD device ID 1034 */ 1035#define COREGA_DEVICEID_FETHERCBTXD 0xa117 1036 1037/* 1038 * Corega FEtherII CB-TXD device ID 1039 */ 1040#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 1041 1042/* 1043 * Corega CG-LAPCIGT device ID 1044 */ 1045#define COREGA_DEVICEID_CGLAPCIGT 0xc107 1046 1047/* 1048 * Linksys vendor ID 1049 */ 1050#define LINKSYS_VENDORID 0x1737 1051 1052/* 1053 * Linksys EG1032 device ID 1054 */ 1055#define LINKSYS_DEVICEID_EG1032 0x1032 1056 1057/* 1058 * Linksys EG1032 rev 3 sub-device ID 1059 */ 1060#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 1061 1062/* 1063 * Peppercon vendor ID 1064 */ 1065#define PEPPERCON_VENDORID 0x1743 1066 1067/* 1068 * Peppercon ROL-F device ID 1069 */ 1070#define PEPPERCON_DEVICEID_ROLF 0x8139 1071 1072/* 1073 * Planex Communications, Inc. vendor ID 1074 */ 1075#define PLANEX_VENDORID 0x14ea 1076 1077/* 1078 * Planex FNW-3603-TX device ID 1079 */ 1080#define PLANEX_DEVICEID_FNW3603TX 0xab06 1081 1082/* 1083 * Planex FNW-3800-TX device ID 1084 */ 1085#define PLANEX_DEVICEID_FNW3800TX 0xab07 1086 1087/* 1088 * LevelOne vendor ID 1089 */ 1090#define LEVEL1_VENDORID 0x018A 1091 1092/* 1093 * LevelOne FPC-0106TX devide ID 1094 */ 1095#define LEVEL1_DEVICEID_FPC0106TX 0x0106 1096 1097/* 1098 * Compaq vendor ID 1099 */ 1100#define CP_VENDORID 0x021B 1101 1102/* 1103 * Edimax vendor ID 1104 */ 1105#define EDIMAX_VENDORID 0x13D1 1106 1107/* 1108 * Edimax EP-4103DL cardbus device ID 1109 */ 1110#define EDIMAX_DEVICEID_EP4103DL 0xAB06 1111 1112/* US Robotics vendor ID */ 1113 1114#define USR_VENDORID 0x16EC 1115 1116/* US Robotics 997902 device ID */ 1117 1118#define USR_DEVICEID_997902 0x0116 1119