if_rlreg.h revision 191301
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_rlreg.h 191301 2009-04-20 07:13:04Z yongari $ 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 41#define RL_IDR3 0x0003 42#define RL_IDR4 0x0004 43#define RL_IDR5 0x0005 44 /* 0006-0007 reserved */ 45#define RL_MAR0 0x0008 /* Multicast hash table */ 46#define RL_MAR1 0x0009 47#define RL_MAR2 0x000A 48#define RL_MAR3 0x000B 49#define RL_MAR4 0x000C 50#define RL_MAR5 0x000D 51#define RL_MAR6 0x000E 52#define RL_MAR7 0x000F 53 54#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 58 59#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 63 64#define RL_RXADDR 0x0030 /* RX ring start address */ 65#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67#define RL_COMMAND 0x0037 /* command register */ 68#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70#define RL_IMR 0x003C /* interrupt mask register */ 71#define RL_ISR 0x003E /* interrupt status register */ 72#define RL_TXCFG 0x0040 /* transmit config */ 73#define RL_RXCFG 0x0044 /* receive config */ 74#define RL_TIMERCNT 0x0048 /* timer count register */ 75#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76#define RL_EECMD 0x0050 /* EEPROM command register */ 77#define RL_CFG0 0x0051 /* config register #0 */ 78#define RL_CFG1 0x0052 /* config register #1 */ 79#define RL_CFG2 0x0053 /* config register #2 */ 80#define RL_CFG3 0x0054 /* config register #3 */ 81#define RL_CFG4 0x0055 /* config register #4 */ 82#define RL_CFG5 0x0056 /* config register #5 */ 83 /* 0057 reserved */ 84#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 85 /* 0059-005A reserved */ 86#define RL_MII 0x005A /* 8129 chip only */ 87#define RL_HALTCLK 0x005B 88#define RL_MULTIINTR 0x005C /* multiple interrupt */ 89#define RL_PCIREV 0x005E /* PCI revision value */ 90 /* 005F reserved */ 91#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 92 93/* Direct PHY access registers only available on 8139 */ 94#define RL_BMCR 0x0062 /* PHY basic mode control */ 95#define RL_BMSR 0x0064 /* PHY basic mode status */ 96#define RL_ANAR 0x0066 /* PHY autoneg advert */ 97#define RL_LPAR 0x0068 /* PHY link partner ability */ 98#define RL_ANER 0x006A /* PHY autoneg expansion */ 99 100#define RL_DISCCNT 0x006C /* disconnect counter */ 101#define RL_FALSECAR 0x006E /* false carrier counter */ 102#define RL_NWAYTST 0x0070 /* NWAY test register */ 103#define RL_RX_ER 0x0072 /* RX_ER counter */ 104#define RL_CSCFG 0x0074 /* CS configuration register */ 105 106/* 107 * When operating in special C+ mode, some of the registers in an 108 * 8139C+ chip have different definitions. These are also used for 109 * the 8169 gigE chip. 110 */ 111#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 112#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 113#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 114#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 115#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 116#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 117#define RL_CFG2 0x0053 118#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 119#define RL_TXSTART 0x00D9 /* 8 bits */ 120#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 121#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 122#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 123#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 124 125/* 126 * Registers specific to the 8169 gigE chip 127 */ 128#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 129#define RL_PHYAR 0x0060 130#define RL_TBICSR 0x0064 131#define RL_TBI_ANAR 0x0068 132#define RL_TBI_LPAR 0x006A 133#define RL_GMEDIASTAT 0x006C /* 8 bits */ 134#define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */ 135#define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */ 136#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 137#define RL_GTXSTART 0x0038 /* 8 bits */ 138 139/* 140 * TX config register bits 141 */ 142#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 143#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 144#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 145#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 146#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 147#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 148#define RL_TXCFG_HWREV 0x7CC00000 149 150#define RL_LOOPTEST_OFF 0x00000000 151#define RL_LOOPTEST_ON 0x00020000 152#define RL_LOOPTEST_ON_CPLUS 0x00060000 153 154/* Known revision codes. */ 155 156#define RL_HWREV_8169 0x00000000 157#define RL_HWREV_8169S 0x00800000 158#define RL_HWREV_8110S 0x04000000 159#define RL_HWREV_8169_8110SB 0x10000000 160#define RL_HWREV_8169_8110SC 0x18000000 161#define RL_HWREV_8102EL 0x24800000 162#define RL_HWREV_8168D 0x28000000 163#define RL_HWREV_8168_SPIN1 0x30000000 164#define RL_HWREV_8100E 0x30800000 165#define RL_HWREV_8101E 0x34000000 166#define RL_HWREV_8102E 0x34800000 167#define RL_HWREV_8168_SPIN2 0x38000000 168#define RL_HWREV_8168_SPIN3 0x38400000 169#define RL_HWREV_8168C 0x3C000000 170#define RL_HWREV_8168C_SPIN2 0x3C400000 171#define RL_HWREV_8168CP 0x3C800000 172#define RL_HWREV_8139 0x60000000 173#define RL_HWREV_8139A 0x70000000 174#define RL_HWREV_8139AG 0x70800000 175#define RL_HWREV_8139B 0x78000000 176#define RL_HWREV_8130 0x7C000000 177#define RL_HWREV_8139C 0x74000000 178#define RL_HWREV_8139D 0x74400000 179#define RL_HWREV_8139CPLUS 0x74800000 180#define RL_HWREV_8101 0x74c00000 181#define RL_HWREV_8100 0x78800000 182#define RL_HWREV_8169_8110SBL 0x7CC00000 183#define RL_HWREV_8169_8110SCE 0x98000000 184 185#define RL_TXDMA_16BYTES 0x00000000 186#define RL_TXDMA_32BYTES 0x00000100 187#define RL_TXDMA_64BYTES 0x00000200 188#define RL_TXDMA_128BYTES 0x00000300 189#define RL_TXDMA_256BYTES 0x00000400 190#define RL_TXDMA_512BYTES 0x00000500 191#define RL_TXDMA_1024BYTES 0x00000600 192#define RL_TXDMA_2048BYTES 0x00000700 193 194/* 195 * Transmit descriptor status register bits. 196 */ 197#define RL_TXSTAT_LENMASK 0x00001FFF 198#define RL_TXSTAT_OWN 0x00002000 199#define RL_TXSTAT_TX_UNDERRUN 0x00004000 200#define RL_TXSTAT_TX_OK 0x00008000 201#define RL_TXSTAT_EARLY_THRESH 0x003F0000 202#define RL_TXSTAT_COLLCNT 0x0F000000 203#define RL_TXSTAT_CARR_HBEAT 0x10000000 204#define RL_TXSTAT_OUTOFWIN 0x20000000 205#define RL_TXSTAT_TXABRT 0x40000000 206#define RL_TXSTAT_CARRLOSS 0x80000000 207 208/* 209 * Interrupt status register bits. 210 */ 211#define RL_ISR_RX_OK 0x0001 212#define RL_ISR_RX_ERR 0x0002 213#define RL_ISR_TX_OK 0x0004 214#define RL_ISR_TX_ERR 0x0008 215#define RL_ISR_RX_OVERRUN 0x0010 216#define RL_ISR_PKT_UNDERRUN 0x0020 217#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 218#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 219#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 220#define RL_ISR_SWI 0x0100 /* C+ only */ 221#define RL_ISR_CABLE_LEN_CHGD 0x2000 222#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 223#define RL_ISR_TIMEOUT_EXPIRED 0x4000 224#define RL_ISR_SYSTEM_ERR 0x8000 225 226#define RL_INTRS \ 227 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 228 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 229 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 230 231#ifdef RE_TX_MODERATION 232#define RL_INTRS_CPLUS \ 233 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 234 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 235 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 236#else 237#define RL_INTRS_CPLUS \ 238 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 239 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 240 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 241#endif 242 243/* 244 * Media status register. (8139 only) 245 */ 246#define RL_MEDIASTAT_RXPAUSE 0x01 247#define RL_MEDIASTAT_TXPAUSE 0x02 248#define RL_MEDIASTAT_LINK 0x04 249#define RL_MEDIASTAT_SPEED10 0x08 250#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 251#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 252 253/* 254 * Receive config register. 255 */ 256#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 257#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 258#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 259#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 260#define RL_RXCFG_RX_RUNT 0x00000010 261#define RL_RXCFG_RX_ERRPKT 0x00000020 262#define RL_RXCFG_WRAP 0x00000080 263#define RL_RXCFG_MAXDMA 0x00000700 264#define RL_RXCFG_BUFSZ 0x00001800 265#define RL_RXCFG_FIFOTHRESH 0x0000E000 266#define RL_RXCFG_EARLYTHRESH 0x07000000 267 268#define RL_RXDMA_16BYTES 0x00000000 269#define RL_RXDMA_32BYTES 0x00000100 270#define RL_RXDMA_64BYTES 0x00000200 271#define RL_RXDMA_128BYTES 0x00000300 272#define RL_RXDMA_256BYTES 0x00000400 273#define RL_RXDMA_512BYTES 0x00000500 274#define RL_RXDMA_1024BYTES 0x00000600 275#define RL_RXDMA_UNLIMITED 0x00000700 276 277#define RL_RXBUF_8 0x00000000 278#define RL_RXBUF_16 0x00000800 279#define RL_RXBUF_32 0x00001000 280#define RL_RXBUF_64 0x00001800 281 282#define RL_RXFIFO_16BYTES 0x00000000 283#define RL_RXFIFO_32BYTES 0x00002000 284#define RL_RXFIFO_64BYTES 0x00004000 285#define RL_RXFIFO_128BYTES 0x00006000 286#define RL_RXFIFO_256BYTES 0x00008000 287#define RL_RXFIFO_512BYTES 0x0000A000 288#define RL_RXFIFO_1024BYTES 0x0000C000 289#define RL_RXFIFO_NOTHRESH 0x0000E000 290 291/* 292 * Bits in RX status header (included with RX'ed packet 293 * in ring buffer). 294 */ 295#define RL_RXSTAT_RXOK 0x00000001 296#define RL_RXSTAT_ALIGNERR 0x00000002 297#define RL_RXSTAT_CRCERR 0x00000004 298#define RL_RXSTAT_GIANT 0x00000008 299#define RL_RXSTAT_RUNT 0x00000010 300#define RL_RXSTAT_BADSYM 0x00000020 301#define RL_RXSTAT_BROAD 0x00002000 302#define RL_RXSTAT_INDIV 0x00004000 303#define RL_RXSTAT_MULTI 0x00008000 304#define RL_RXSTAT_LENMASK 0xFFFF0000 305 306#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 307/* 308 * Command register. 309 */ 310#define RL_CMD_EMPTY_RXBUF 0x0001 311#define RL_CMD_TX_ENB 0x0004 312#define RL_CMD_RX_ENB 0x0008 313#define RL_CMD_RESET 0x0010 314#define RL_CMD_STOPREQ 0x0080 315 316/* 317 * Twister register values. These are completely undocumented and derived 318 * from public sources. 319 */ 320#define RL_CSCFG_LINK_OK 0x0400 321#define RL_CSCFG_CHANGE 0x0800 322#define RL_CSCFG_STATUS 0xf000 323#define RL_CSCFG_ROW3 0x7000 324#define RL_CSCFG_ROW2 0x3000 325#define RL_CSCFG_ROW1 0x1000 326#define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0 327#define RL_CSCFG_LINK_DOWN_CMD 0xf3c0 328 329#define RL_NWAYTST_RESET 0 330#define RL_NWAYTST_CBL_TEST 0x20 331 332#define RL_PARA78 0x78 333#define RL_PARA78_DEF 0x78fa8388 334#define RL_PARA7C 0x7C 335#define RL_PARA7C_DEF 0xcb38de43 336#define RL_PARA7C_RETUNE 0xfb38de03 337/* 338 * EEPROM control register 339 */ 340#define RL_EE_DATAOUT 0x01 /* Data out */ 341#define RL_EE_DATAIN 0x02 /* Data in */ 342#define RL_EE_CLK 0x04 /* clock */ 343#define RL_EE_SEL 0x08 /* chip select */ 344#define RL_EE_MODE (0x40|0x80) 345 346#define RL_EEMODE_OFF 0x00 347#define RL_EEMODE_AUTOLOAD 0x40 348#define RL_EEMODE_PROGRAM 0x80 349#define RL_EEMODE_WRITECFG (0x80|0x40) 350 351/* 9346 EEPROM commands */ 352#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 353#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 354 355#define RL_9346_WRITE 0x5 356#define RL_9346_READ 0x6 357#define RL_9346_ERASE 0x7 358#define RL_9346_EWEN 0x4 359#define RL_9346_EWEN_ADDR 0x30 360#define RL_9456_EWDS 0x4 361#define RL_9346_EWDS_ADDR 0x00 362 363#define RL_EECMD_WRITE 0x140 364#define RL_EECMD_READ_6BIT 0x180 365#define RL_EECMD_READ_8BIT 0x600 366#define RL_EECMD_ERASE 0x1c0 367 368#define RL_EE_ID 0x00 369#define RL_EE_PCI_VID 0x01 370#define RL_EE_PCI_DID 0x02 371/* Location of station address inside EEPROM */ 372#define RL_EE_EADDR 0x07 373 374/* 375 * MII register (8129 only) 376 */ 377#define RL_MII_CLK 0x01 378#define RL_MII_DATAIN 0x02 379#define RL_MII_DATAOUT 0x04 380#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 381 382/* 383 * Config 0 register 384 */ 385#define RL_CFG0_ROM0 0x01 386#define RL_CFG0_ROM1 0x02 387#define RL_CFG0_ROM2 0x04 388#define RL_CFG0_PL0 0x08 389#define RL_CFG0_PL1 0x10 390#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 391#define RL_CFG0_PCS 0x40 392#define RL_CFG0_SCR 0x80 393 394/* 395 * Config 1 register 396 */ 397#define RL_CFG1_PWRDWN 0x01 398#define RL_CFG1_PME 0x01 399#define RL_CFG1_SLEEP 0x02 400#define RL_CFG1_VPDEN 0x02 401#define RL_CFG1_IOMAP 0x04 402#define RL_CFG1_MEMMAP 0x08 403#define RL_CFG1_RSVD 0x10 404#define RL_CFG1_LWACT 0x10 405#define RL_CFG1_DRVLOAD 0x20 406#define RL_CFG1_LED0 0x40 407#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 408#define RL_CFG1_LED1 0x80 409 410/* 411 * Config 2 register 412 */ 413#define RL_CFG2_PCI33MHZ 0x00 414#define RL_CFG2_PCI66MHZ 0x01 415#define RL_CFG2_PCI64BIT 0x08 416#define RL_CFG2_AUXPWR 0x10 417#define RL_CFG2_MSI 0x20 418 419/* 420 * Config 3 register 421 */ 422#define RL_CFG3_GRANTSEL 0x80 423#define RL_CFG3_WOL_MAGIC 0x20 424#define RL_CFG3_WOL_LINK 0x10 425#define RL_CFG3_FAST_B2B 0x01 426 427/* 428 * Config 4 register 429 */ 430#define RL_CFG4_LWPTN 0x04 431#define RL_CFG4_LWPME 0x10 432 433/* 434 * Config 5 register 435 */ 436#define RL_CFG5_WOL_BCAST 0x40 437#define RL_CFG5_WOL_MCAST 0x20 438#define RL_CFG5_WOL_UCAST 0x10 439#define RL_CFG5_WOL_LANWAKE 0x02 440#define RL_CFG5_PME_STS 0x01 441 442/* 443 * 8139C+ register definitions 444 */ 445 446/* RL_DUMPSTATS_LO register */ 447 448#define RL_DUMPSTATS_START 0x00000008 449 450/* Transmit start register */ 451 452#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 453#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 454#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 455 456/* 457 * Config 2 register, 8139C+/8169/8169S/8110S only 458 */ 459#define RL_CFG2_BUSFREQ 0x07 460#define RL_CFG2_BUSWIDTH 0x08 461#define RL_CFG2_AUXPWRSTS 0x10 462 463#define RL_BUSFREQ_33MHZ 0x00 464#define RL_BUSFREQ_66MHZ 0x01 465 466#define RL_BUSWIDTH_32BITS 0x00 467#define RL_BUSWIDTH_64BITS 0x08 468 469/* C+ mode command register */ 470 471#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 472#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 473#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 474#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 475#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 476#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 477#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 478#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 479#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 480#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 481#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 482#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 483#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 484#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 485#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 486 487/* C+ early transmit threshold */ 488 489#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 490 491/* 492 * Gigabit PHY access register (8169 only) 493 */ 494 495#define RL_PHYAR_PHYDATA 0x0000FFFF 496#define RL_PHYAR_PHYREG 0x001F0000 497#define RL_PHYAR_BUSY 0x80000000 498 499/* 500 * Gigabit media status (8169 only) 501 */ 502#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 503#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 504#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 505#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 506#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 507#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 508#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 509#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 510 511/* 512 * The RealTek doesn't use a fragment-based descriptor mechanism. 513 * Instead, there are only four register sets, each or which represents 514 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 515 * packet buffer (32-bit aligned!) and we place the buffer addresses in 516 * the registers so the chip knows where they are. 517 * 518 * We can sort of kludge together the same kind of buffer management 519 * used in previous drivers, but we have to do buffer copies almost all 520 * the time, so it doesn't really buy us much. 521 * 522 * For reception, there's just one large buffer where the chip stores 523 * all received packets. 524 */ 525 526#define RL_RX_BUF_SZ RL_RXBUF_64 527#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 528#define RL_TX_LIST_CNT 4 529#define RL_MIN_FRAMELEN 60 530#define RL_TX_8139_BUF_ALIGN 4 531#define RL_RX_8139_BUF_ALIGN 8 532#define RL_RX_8139_BUF_RESERVE sizeof(int64_t) 533#define RL_RX_8139_BUF_GUARD_SZ \ 534 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE) 535#define RL_TXTHRESH(x) ((x) << 11) 536#define RL_TX_THRESH_INIT 96 537#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 538#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 539#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 540 541#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 542#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 543 544#define RL_ETHER_ALIGN 2 545 546/* 547 * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets. 548 */ 549#define RL_IP4CSUMTX_MINLEN 28 550#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 551 552struct rl_chain_data { 553 uint16_t cur_rx; 554 uint8_t *rl_rx_buf; 555 uint8_t *rl_rx_buf_ptr; 556 557 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 558 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 559 bus_dma_tag_t rl_tx_tag; 560 bus_dma_tag_t rl_rx_tag; 561 bus_dmamap_t rl_rx_dmamap; 562 bus_addr_t rl_rx_buf_paddr; 563 uint8_t last_tx; 564 uint8_t cur_tx; 565}; 566 567#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 568#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 569#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 570#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 571#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 572#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 573#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 574#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 575#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 576 577struct rl_type { 578 uint16_t rl_vid; 579 uint16_t rl_did; 580 int rl_basetype; 581 char *rl_name; 582}; 583 584struct rl_hwrev { 585 uint32_t rl_rev; 586 int rl_type; 587 char *rl_desc; 588}; 589 590struct rl_mii_frame { 591 uint8_t mii_stdelim; 592 uint8_t mii_opcode; 593 uint8_t mii_phyaddr; 594 uint8_t mii_regaddr; 595 uint8_t mii_turnaround; 596 uint16_t mii_data; 597}; 598 599/* 600 * MII constants 601 */ 602#define RL_MII_STARTDELIM 0x01 603#define RL_MII_READOP 0x02 604#define RL_MII_WRITEOP 0x01 605#define RL_MII_TURNAROUND 0x02 606 607#define RL_8129 1 608#define RL_8139 2 609#define RL_8139CPLUS 3 610#define RL_8169 4 611 612#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 613 (x)->rl_type == RL_8169) 614 615/* 616 * The 8139C+ and 8160 gigE chips support descriptor-based TX 617 * and RX. In fact, they even support TCP large send. Descriptors 618 * must be allocated in contiguous blocks that are aligned on a 619 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 620 */ 621 622/* 623 * RX/TX descriptor definition. When large send mode is enabled, the 624 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 625 * the checksum offload bits are disabled. The structure layout is 626 * the same for RX and TX descriptors 627 */ 628 629struct rl_desc { 630 uint32_t rl_cmdstat; 631 uint32_t rl_vlanctl; 632 uint32_t rl_bufaddr_lo; 633 uint32_t rl_bufaddr_hi; 634}; 635 636#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 637#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 638#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 639#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 640#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 641#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 642#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 643#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 644#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 645#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 646#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 647 648#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 649#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 650/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 651#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 652#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 653#define RL_TDESC_CMD_IPCSUMV2 0x20000000 654 655/* 656 * Error bits are valid only on the last descriptor of a frame 657 * (i.e. RL_TDESC_CMD_EOF == 1) 658 */ 659 660#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 661#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 662#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 663#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 664#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 665#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 666#define RL_TDESC_STAT_OWN 0x80000000 667 668/* 669 * RX descriptor cmd/vlan definitions 670 */ 671 672#define RL_RDESC_CMD_EOR 0x40000000 673#define RL_RDESC_CMD_OWN 0x80000000 674#define RL_RDESC_CMD_BUFLEN 0x00001FFF 675 676#define RL_RDESC_STAT_OWN 0x80000000 677#define RL_RDESC_STAT_EOR 0x40000000 678#define RL_RDESC_STAT_SOF 0x20000000 679#define RL_RDESC_STAT_EOF 0x10000000 680#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 681#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 682#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 683#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 684#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 685#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 686#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 687#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 688#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 689#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 690#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 691#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 692#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 693#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 694#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 695#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 696#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 697#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 698#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 699 RL_RDESC_STAT_CRCERR) 700 701#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 702 (rl_vlandata valid)*/ 703#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 704/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 705#define RL_RDESC_IPV6 0x80000000 706#define RL_RDESC_IPV4 0x40000000 707 708#define RL_PROTOID_NONIP 0x00000000 709#define RL_PROTOID_TCPIP 0x00010000 710#define RL_PROTOID_UDPIP 0x00020000 711#define RL_PROTOID_IP 0x00030000 712#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 713 RL_PROTOID_TCPIP) 714#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 715 RL_PROTOID_UDPIP) 716 717/* 718 * Statistics counter structure (8139C+ and 8169 only) 719 */ 720struct rl_stats { 721 uint32_t rl_tx_pkts_lo; 722 uint32_t rl_tx_pkts_hi; 723 uint32_t rl_tx_errs_lo; 724 uint32_t rl_tx_errs_hi; 725 uint32_t rl_tx_errs; 726 uint16_t rl_missed_pkts; 727 uint16_t rl_rx_framealign_errs; 728 uint32_t rl_tx_onecoll; 729 uint32_t rl_tx_multicolls; 730 uint32_t rl_rx_ucasts_hi; 731 uint32_t rl_rx_ucasts_lo; 732 uint32_t rl_rx_bcasts_lo; 733 uint32_t rl_rx_bcasts_hi; 734 uint32_t rl_rx_mcasts; 735 uint16_t rl_tx_aborts; 736 uint16_t rl_rx_underruns; 737}; 738 739/* 740 * Rx/Tx descriptor parameters (8139C+ and 8169 only) 741 * 742 * 8139C+ 743 * Number of descriptors supported : up to 64 744 * Descriptor alignment : 256 bytes 745 * Tx buffer : At least 4 bytes in length. 746 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 747 * 748 * 8169 749 * Number of descriptors supported : up to 1024 750 * Descriptor alignment : 256 bytes 751 * Tx buffer : At least 4 bytes in length. 752 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 753 */ 754#ifndef __NO_STRICT_ALIGNMENT 755#define RE_FIXUP_RX 1 756#endif 757 758#define RL_8169_TX_DESC_CNT 256 759#define RL_8169_RX_DESC_CNT 256 760#define RL_8139_TX_DESC_CNT 64 761#define RL_8139_RX_DESC_CNT 64 762#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT 763#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT 764#define RL_NTXSEGS 32 765 766#define RL_RING_ALIGN 256 767#define RL_IFQ_MAXLEN 512 768#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 769#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 770#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1)) 771#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 772#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 773#define RL_PKTSZ(x) ((x)/* >> 3*/) 774#ifdef RE_FIXUP_RX 775#define RE_ETHER_ALIGN sizeof(uint64_t) 776#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 777#else 778#define RE_ETHER_ALIGN 0 779#define RE_RX_DESC_BUFLEN MCLBYTES 780#endif 781 782#define RL_MSI_MESSAGES 1 783 784#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 785#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 786 787/* 788 * The number of bits reserved for MSS in RealTek controllers is 789 * 11bits. This limits the maximum interface MTU size in TSO case 790 * as upper stack should not generate TCP segments with MSS greater 791 * than the limit. 792 */ 793#define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN) 794 795/* see comment in dev/re/if_re.c */ 796#define RL_JUMBO_FRAMELEN 7440 797#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 798#define RL_MAX_FRAMELEN \ 799 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 800 801struct rl_txdesc { 802 struct mbuf *tx_m; 803 bus_dmamap_t tx_dmamap; 804}; 805 806struct rl_rxdesc { 807 struct mbuf *rx_m; 808 bus_dmamap_t rx_dmamap; 809 bus_size_t rx_size; 810}; 811 812struct rl_list_data { 813 struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; 814 struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; 815 int rl_tx_desc_cnt; 816 int rl_rx_desc_cnt; 817 int rl_tx_prodidx; 818 int rl_rx_prodidx; 819 int rl_tx_considx; 820 int rl_tx_free; 821 bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ 822 bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ 823 bus_dmamap_t rl_rx_sparemap; 824 bus_dma_tag_t rl_stag; /* stats mapping tag */ 825 bus_dmamap_t rl_smap; /* stats map */ 826 struct rl_stats *rl_stats; 827 bus_addr_t rl_stats_addr; 828 bus_dma_tag_t rl_rx_list_tag; 829 bus_dmamap_t rl_rx_list_map; 830 struct rl_desc *rl_rx_list; 831 bus_addr_t rl_rx_list_addr; 832 bus_dma_tag_t rl_tx_list_tag; 833 bus_dmamap_t rl_tx_list_map; 834 struct rl_desc *rl_tx_list; 835 bus_addr_t rl_tx_list_addr; 836}; 837 838enum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE }; 839 840struct rl_softc { 841 struct ifnet *rl_ifp; /* interface info */ 842 bus_space_handle_t rl_bhandle; /* bus space handle */ 843 bus_space_tag_t rl_btag; /* bus space tag */ 844 device_t rl_dev; 845 struct resource *rl_res; 846 int rl_res_id; 847 int rl_res_type; 848 struct resource *rl_irq[RL_MSI_MESSAGES]; 849 void *rl_intrhand[RL_MSI_MESSAGES]; 850 device_t rl_miibus; 851 bus_dma_tag_t rl_parent_tag; 852 uint8_t rl_type; 853 int rl_eecmd_read; 854 int rl_eewidth; 855 uint8_t rl_stats_no_timeout; 856 int rl_txthresh; 857 struct rl_chain_data rl_cdata; 858 struct rl_list_data rl_ldata; 859 struct callout rl_stat_callout; 860 int rl_watchdog_timer; 861 struct mtx rl_mtx; 862 struct mbuf *rl_head; 863 struct mbuf *rl_tail; 864 uint32_t rl_hwrev; 865 uint32_t rl_rxlenmask; 866 int rl_testmode; 867 int rl_if_flags; 868 int rl_twister_enable; 869 enum rl_twist rl_twister; 870 int rl_twist_row; 871 int rl_twist_col; 872 int suspended; /* 0 = normal 1 = suspended */ 873#ifdef DEVICE_POLLING 874 int rxcycles; 875#endif 876 877 struct task rl_txtask; 878 struct task rl_inttask; 879 880 int rl_txstart; 881 uint32_t rl_flags; 882#define RL_FLAG_MSI 0x0001 883#define RL_FLAG_AUTOPAD 0x0002 884#define RL_FLAG_PHYWAKE 0x0008 885#define RL_FLAG_NOJUMBO 0x0010 886#define RL_FLAG_PAR 0x0020 887#define RL_FLAG_DESCV2 0x0040 888#define RL_FLAG_MACSTAT 0x0080 889#define RL_FLAG_FASTETHER 0x0100 890#define RL_FLAG_CMDSTOP 0x0200 891#define RL_FLAG_MACRESET 0x0400 892#define RL_FLAG_WOLRXENB 0x1000 893#define RL_FLAG_MACSLEEP 0x2000 894#define RL_FLAG_PCIE 0x4000 895#define RL_FLAG_LINK 0x8000 896}; 897 898#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 899#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 900#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 901 902/* 903 * register space access macros 904 */ 905#define CSR_WRITE_STREAM_4(sc, reg, val) \ 906 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 907#define CSR_WRITE_4(sc, reg, val) \ 908 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 909#define CSR_WRITE_2(sc, reg, val) \ 910 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 911#define CSR_WRITE_1(sc, reg, val) \ 912 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 913 914#define CSR_READ_4(sc, reg) \ 915 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 916#define CSR_READ_2(sc, reg) \ 917 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 918#define CSR_READ_1(sc, reg) \ 919 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 920 921#define CSR_SETBIT_1(sc, offset, val) \ 922 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 923 924#define CSR_CLRBIT_1(sc, offset, val) \ 925 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 926 927#define CSR_SETBIT_2(sc, offset, val) \ 928 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 929 930#define CSR_CLRBIT_2(sc, offset, val) \ 931 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 932 933#define CSR_SETBIT_4(sc, offset, val) \ 934 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 935 936#define CSR_CLRBIT_4(sc, offset, val) \ 937 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 938 939#define RL_TIMEOUT 1000 940#define RL_PHY_TIMEOUT 2000 941 942/* 943 * General constants that are fun to know. 944 * 945 * RealTek PCI vendor ID 946 */ 947#define RT_VENDORID 0x10EC 948 949/* 950 * RealTek chip device IDs. 951 */ 952#define RT_DEVICEID_8139D 0x8039 953#define RT_DEVICEID_8129 0x8129 954#define RT_DEVICEID_8101E 0x8136 955#define RT_DEVICEID_8138 0x8138 956#define RT_DEVICEID_8139 0x8139 957#define RT_DEVICEID_8169SC 0x8167 958#define RT_DEVICEID_8168 0x8168 959#define RT_DEVICEID_8169 0x8169 960#define RT_DEVICEID_8100 0x8100 961 962#define RT_REVID_8139CPLUS 0x20 963 964/* 965 * Accton PCI vendor ID 966 */ 967#define ACCTON_VENDORID 0x1113 968 969/* 970 * Accton MPX 5030/5038 device ID. 971 */ 972#define ACCTON_DEVICEID_5030 0x1211 973 974/* 975 * Nortel PCI vendor ID 976 */ 977#define NORTEL_VENDORID 0x126C 978 979/* 980 * Delta Electronics Vendor ID. 981 */ 982#define DELTA_VENDORID 0x1500 983 984/* 985 * Delta device IDs. 986 */ 987#define DELTA_DEVICEID_8139 0x1360 988 989/* 990 * Addtron vendor ID. 991 */ 992#define ADDTRON_VENDORID 0x4033 993 994/* 995 * Addtron device IDs. 996 */ 997#define ADDTRON_DEVICEID_8139 0x1360 998 999/* 1000 * D-Link vendor ID. 1001 */ 1002#define DLINK_VENDORID 0x1186 1003 1004/* 1005 * D-Link DFE-530TX+ device ID 1006 */ 1007#define DLINK_DEVICEID_530TXPLUS 0x1300 1008 1009/* 1010 * D-Link DFE-5280T device ID 1011 */ 1012#define DLINK_DEVICEID_528T 0x4300 1013 1014/* 1015 * D-Link DFE-690TXD device ID 1016 */ 1017#define DLINK_DEVICEID_690TXD 0x1340 1018 1019/* 1020 * Corega K.K vendor ID 1021 */ 1022#define COREGA_VENDORID 0x1259 1023 1024/* 1025 * Corega FEther CB-TXD device ID 1026 */ 1027#define COREGA_DEVICEID_FETHERCBTXD 0xa117 1028 1029/* 1030 * Corega FEtherII CB-TXD device ID 1031 */ 1032#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 1033 1034/* 1035 * Corega CG-LAPCIGT device ID 1036 */ 1037#define COREGA_DEVICEID_CGLAPCIGT 0xc107 1038 1039/* 1040 * Linksys vendor ID 1041 */ 1042#define LINKSYS_VENDORID 0x1737 1043 1044/* 1045 * Linksys EG1032 device ID 1046 */ 1047#define LINKSYS_DEVICEID_EG1032 0x1032 1048 1049/* 1050 * Linksys EG1032 rev 3 sub-device ID 1051 */ 1052#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 1053 1054/* 1055 * Peppercon vendor ID 1056 */ 1057#define PEPPERCON_VENDORID 0x1743 1058 1059/* 1060 * Peppercon ROL-F device ID 1061 */ 1062#define PEPPERCON_DEVICEID_ROLF 0x8139 1063 1064/* 1065 * Planex Communications, Inc. vendor ID 1066 */ 1067#define PLANEX_VENDORID 0x14ea 1068 1069/* 1070 * Planex FNW-3603-TX device ID 1071 */ 1072#define PLANEX_DEVICEID_FNW3603TX 0xab06 1073 1074/* 1075 * Planex FNW-3800-TX device ID 1076 */ 1077#define PLANEX_DEVICEID_FNW3800TX 0xab07 1078 1079/* 1080 * LevelOne vendor ID 1081 */ 1082#define LEVEL1_VENDORID 0x018A 1083 1084/* 1085 * LevelOne FPC-0106TX devide ID 1086 */ 1087#define LEVEL1_DEVICEID_FPC0106TX 0x0106 1088 1089/* 1090 * Compaq vendor ID 1091 */ 1092#define CP_VENDORID 0x021B 1093 1094/* 1095 * Edimax vendor ID 1096 */ 1097#define EDIMAX_VENDORID 0x13D1 1098 1099/* 1100 * Edimax EP-4103DL cardbus device ID 1101 */ 1102#define EDIMAX_DEVICEID_EP4103DL 0xAB06 1103 1104/* US Robotics vendor ID */ 1105 1106#define USR_VENDORID 0x16EC 1107 1108/* US Robotics 997902 device ID */ 1109 1110#define USR_DEVICEID_997902 0x0116 1111 1112/* 1113 * PCI low memory base and low I/O base register, and 1114 * other PCI registers. 1115 */ 1116 1117#define RL_PCI_VENDOR_ID 0x00 1118#define RL_PCI_DEVICE_ID 0x02 1119#define RL_PCI_COMMAND 0x04 1120#define RL_PCI_STATUS 0x06 1121#define RL_PCI_CLASSCODE 0x09 1122#define RL_PCI_LATENCY_TIMER 0x0D 1123#define RL_PCI_HEADER_TYPE 0x0E 1124#define RL_PCI_LOIO 0x10 1125#define RL_PCI_LOMEM 0x14 1126#define RL_PCI_BIOSROM 0x30 1127#define RL_PCI_INTLINE 0x3C 1128#define RL_PCI_INTPIN 0x3D 1129#define RL_PCI_MINGNT 0x3E 1130#define RL_PCI_MINLAT 0x0F 1131#define RL_PCI_RESETOPT 0x48 1132#define RL_PCI_EEPROM_DATA 0x4C 1133 1134#define RL_PCI_CAPID 0x50 /* 8 bits */ 1135#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 1136#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 1137#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 1138 1139#define RL_PSTATE_MASK 0x0003 1140#define RL_PSTATE_D0 0x0000 1141#define RL_PSTATE_D1 0x0002 1142#define RL_PSTATE_D2 0x0002 1143#define RL_PSTATE_D3 0x0003 1144#define RL_PME_EN 0x0010 1145#define RL_PME_STATUS 0x8000 1146