if_rlreg.h revision 184240
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_rlreg.h 184240 2008-10-25 02:36:08Z yongari $ 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 41#define RL_IDR3 0x0003 42#define RL_IDR4 0x0004 43#define RL_IDR5 0x0005 44 /* 0006-0007 reserved */ 45#define RL_MAR0 0x0008 /* Multicast hash table */ 46#define RL_MAR1 0x0009 47#define RL_MAR2 0x000A 48#define RL_MAR3 0x000B 49#define RL_MAR4 0x000C 50#define RL_MAR5 0x000D 51#define RL_MAR6 0x000E 52#define RL_MAR7 0x000F 53 54#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 58 59#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 63 64#define RL_RXADDR 0x0030 /* RX ring start address */ 65#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67#define RL_COMMAND 0x0037 /* command register */ 68#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70#define RL_IMR 0x003C /* interrupt mask register */ 71#define RL_ISR 0x003E /* interrupt status register */ 72#define RL_TXCFG 0x0040 /* transmit config */ 73#define RL_RXCFG 0x0044 /* receive config */ 74#define RL_TIMERCNT 0x0048 /* timer count register */ 75#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76#define RL_EECMD 0x0050 /* EEPROM command register */ 77#define RL_CFG0 0x0051 /* config register #0 */ 78#define RL_CFG1 0x0052 /* config register #1 */ 79#define RL_CFG2 0x0053 /* config register #2 */ 80#define RL_CFG3 0x0054 /* config register #3 */ 81#define RL_CFG4 0x0055 /* config register #4 */ 82#define RL_CFG5 0x0056 /* config register #5 */ 83 /* 0057 reserved */ 84#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 85 /* 0059-005A reserved */ 86#define RL_MII 0x005A /* 8129 chip only */ 87#define RL_HALTCLK 0x005B 88#define RL_MULTIINTR 0x005C /* multiple interrupt */ 89#define RL_PCIREV 0x005E /* PCI revision value */ 90 /* 005F reserved */ 91#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 92 93/* Direct PHY access registers only available on 8139 */ 94#define RL_BMCR 0x0062 /* PHY basic mode control */ 95#define RL_BMSR 0x0064 /* PHY basic mode status */ 96#define RL_ANAR 0x0066 /* PHY autoneg advert */ 97#define RL_LPAR 0x0068 /* PHY link partner ability */ 98#define RL_ANER 0x006A /* PHY autoneg expansion */ 99 100#define RL_DISCCNT 0x006C /* disconnect counter */ 101#define RL_FALSECAR 0x006E /* false carrier counter */ 102#define RL_NWAYTST 0x0070 /* NWAY test register */ 103#define RL_RX_ER 0x0072 /* RX_ER counter */ 104#define RL_CSCFG 0x0074 /* CS configuration register */ 105 106/* 107 * When operating in special C+ mode, some of the registers in an 108 * 8139C+ chip have different definitions. These are also used for 109 * the 8169 gigE chip. 110 */ 111#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 112#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 113#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 114#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 115#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 116#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 117#define RL_CFG2 0x0053 118#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 119#define RL_TXSTART 0x00D9 /* 8 bits */ 120#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 121#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 122#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 123#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 124 125/* 126 * Registers specific to the 8169 gigE chip 127 */ 128#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 129#define RL_PHYAR 0x0060 130#define RL_TBICSR 0x0064 131#define RL_TBI_ANAR 0x0068 132#define RL_TBI_LPAR 0x006A 133#define RL_GMEDIASTAT 0x006C /* 8 bits */ 134#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 135#define RL_GTXSTART 0x0038 /* 8 bits */ 136 137/* 138 * TX config register bits 139 */ 140#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 141#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 142#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 143#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 144#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 145#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 146#define RL_TXCFG_HWREV 0x7CC00000 147 148#define RL_LOOPTEST_OFF 0x00000000 149#define RL_LOOPTEST_ON 0x00020000 150#define RL_LOOPTEST_ON_CPLUS 0x00060000 151 152/* Known revision codes. */ 153 154#define RL_HWREV_8169 0x00000000 155#define RL_HWREV_8110S 0x00800000 156#define RL_HWREV_8169S 0x04000000 157#define RL_HWREV_8169_8110SB 0x10000000 158#define RL_HWREV_8169_8110SC 0x18000000 159#define RL_HWREV_8102EL 0x24800000 160#define RL_HWREV_8168_SPIN1 0x30000000 161#define RL_HWREV_8100E 0x30800000 162#define RL_HWREV_8101E 0x34000000 163#define RL_HWREV_8102E 0x34800000 164#define RL_HWREV_8168_SPIN2 0x38000000 165#define RL_HWREV_8168_SPIN3 0x38400000 166#define RL_HWREV_8168C 0x3C000000 167#define RL_HWREV_8168C_SPIN2 0x3C400000 168#define RL_HWREV_8168CP 0x3C800000 169#define RL_HWREV_8139 0x60000000 170#define RL_HWREV_8139A 0x70000000 171#define RL_HWREV_8139AG 0x70800000 172#define RL_HWREV_8139B 0x78000000 173#define RL_HWREV_8130 0x7C000000 174#define RL_HWREV_8139C 0x74000000 175#define RL_HWREV_8139D 0x74400000 176#define RL_HWREV_8139CPLUS 0x74800000 177#define RL_HWREV_8101 0x74c00000 178#define RL_HWREV_8100 0x78800000 179#define RL_HWREV_8169_8110SBL 0x7CC00000 180 181#define RL_TXDMA_16BYTES 0x00000000 182#define RL_TXDMA_32BYTES 0x00000100 183#define RL_TXDMA_64BYTES 0x00000200 184#define RL_TXDMA_128BYTES 0x00000300 185#define RL_TXDMA_256BYTES 0x00000400 186#define RL_TXDMA_512BYTES 0x00000500 187#define RL_TXDMA_1024BYTES 0x00000600 188#define RL_TXDMA_2048BYTES 0x00000700 189 190/* 191 * Transmit descriptor status register bits. 192 */ 193#define RL_TXSTAT_LENMASK 0x00001FFF 194#define RL_TXSTAT_OWN 0x00002000 195#define RL_TXSTAT_TX_UNDERRUN 0x00004000 196#define RL_TXSTAT_TX_OK 0x00008000 197#define RL_TXSTAT_EARLY_THRESH 0x003F0000 198#define RL_TXSTAT_COLLCNT 0x0F000000 199#define RL_TXSTAT_CARR_HBEAT 0x10000000 200#define RL_TXSTAT_OUTOFWIN 0x20000000 201#define RL_TXSTAT_TXABRT 0x40000000 202#define RL_TXSTAT_CARRLOSS 0x80000000 203 204/* 205 * Interrupt status register bits. 206 */ 207#define RL_ISR_RX_OK 0x0001 208#define RL_ISR_RX_ERR 0x0002 209#define RL_ISR_TX_OK 0x0004 210#define RL_ISR_TX_ERR 0x0008 211#define RL_ISR_RX_OVERRUN 0x0010 212#define RL_ISR_PKT_UNDERRUN 0x0020 213#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 214#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 215#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 216#define RL_ISR_SWI 0x0100 /* C+ only */ 217#define RL_ISR_CABLE_LEN_CHGD 0x2000 218#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 219#define RL_ISR_TIMEOUT_EXPIRED 0x4000 220#define RL_ISR_SYSTEM_ERR 0x8000 221 222#define RL_INTRS \ 223 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 224 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 225 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 226 227#ifdef RE_TX_MODERATION 228#define RL_INTRS_CPLUS \ 229 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 230 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 231 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 232#else 233#define RL_INTRS_CPLUS \ 234 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 235 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 236 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 237#endif 238 239/* 240 * Media status register. (8139 only) 241 */ 242#define RL_MEDIASTAT_RXPAUSE 0x01 243#define RL_MEDIASTAT_TXPAUSE 0x02 244#define RL_MEDIASTAT_LINK 0x04 245#define RL_MEDIASTAT_SPEED10 0x08 246#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 247#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 248 249/* 250 * Receive config register. 251 */ 252#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 253#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 254#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 255#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 256#define RL_RXCFG_RX_RUNT 0x00000010 257#define RL_RXCFG_RX_ERRPKT 0x00000020 258#define RL_RXCFG_WRAP 0x00000080 259#define RL_RXCFG_MAXDMA 0x00000700 260#define RL_RXCFG_BUFSZ 0x00001800 261#define RL_RXCFG_FIFOTHRESH 0x0000E000 262#define RL_RXCFG_EARLYTHRESH 0x07000000 263 264#define RL_RXDMA_16BYTES 0x00000000 265#define RL_RXDMA_32BYTES 0x00000100 266#define RL_RXDMA_64BYTES 0x00000200 267#define RL_RXDMA_128BYTES 0x00000300 268#define RL_RXDMA_256BYTES 0x00000400 269#define RL_RXDMA_512BYTES 0x00000500 270#define RL_RXDMA_1024BYTES 0x00000600 271#define RL_RXDMA_UNLIMITED 0x00000700 272 273#define RL_RXBUF_8 0x00000000 274#define RL_RXBUF_16 0x00000800 275#define RL_RXBUF_32 0x00001000 276#define RL_RXBUF_64 0x00001800 277 278#define RL_RXFIFO_16BYTES 0x00000000 279#define RL_RXFIFO_32BYTES 0x00002000 280#define RL_RXFIFO_64BYTES 0x00004000 281#define RL_RXFIFO_128BYTES 0x00006000 282#define RL_RXFIFO_256BYTES 0x00008000 283#define RL_RXFIFO_512BYTES 0x0000A000 284#define RL_RXFIFO_1024BYTES 0x0000C000 285#define RL_RXFIFO_NOTHRESH 0x0000E000 286 287/* 288 * Bits in RX status header (included with RX'ed packet 289 * in ring buffer). 290 */ 291#define RL_RXSTAT_RXOK 0x00000001 292#define RL_RXSTAT_ALIGNERR 0x00000002 293#define RL_RXSTAT_CRCERR 0x00000004 294#define RL_RXSTAT_GIANT 0x00000008 295#define RL_RXSTAT_RUNT 0x00000010 296#define RL_RXSTAT_BADSYM 0x00000020 297#define RL_RXSTAT_BROAD 0x00002000 298#define RL_RXSTAT_INDIV 0x00004000 299#define RL_RXSTAT_MULTI 0x00008000 300#define RL_RXSTAT_LENMASK 0xFFFF0000 301 302#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 303/* 304 * Command register. 305 */ 306#define RL_CMD_EMPTY_RXBUF 0x0001 307#define RL_CMD_TX_ENB 0x0004 308#define RL_CMD_RX_ENB 0x0008 309#define RL_CMD_RESET 0x0010 310 311/* 312 * EEPROM control register 313 */ 314#define RL_EE_DATAOUT 0x01 /* Data out */ 315#define RL_EE_DATAIN 0x02 /* Data in */ 316#define RL_EE_CLK 0x04 /* clock */ 317#define RL_EE_SEL 0x08 /* chip select */ 318#define RL_EE_MODE (0x40|0x80) 319 320#define RL_EEMODE_OFF 0x00 321#define RL_EEMODE_AUTOLOAD 0x40 322#define RL_EEMODE_PROGRAM 0x80 323#define RL_EEMODE_WRITECFG (0x80|0x40) 324 325/* 9346 EEPROM commands */ 326#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 327#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 328 329#define RL_9346_WRITE 0x5 330#define RL_9346_READ 0x6 331#define RL_9346_ERASE 0x7 332#define RL_9346_EWEN 0x4 333#define RL_9346_EWEN_ADDR 0x30 334#define RL_9456_EWDS 0x4 335#define RL_9346_EWDS_ADDR 0x00 336 337#define RL_EECMD_WRITE 0x140 338#define RL_EECMD_READ_6BIT 0x180 339#define RL_EECMD_READ_8BIT 0x600 340#define RL_EECMD_ERASE 0x1c0 341 342#define RL_EE_ID 0x00 343#define RL_EE_PCI_VID 0x01 344#define RL_EE_PCI_DID 0x02 345/* Location of station address inside EEPROM */ 346#define RL_EE_EADDR 0x07 347 348/* 349 * MII register (8129 only) 350 */ 351#define RL_MII_CLK 0x01 352#define RL_MII_DATAIN 0x02 353#define RL_MII_DATAOUT 0x04 354#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 355 356/* 357 * Config 0 register 358 */ 359#define RL_CFG0_ROM0 0x01 360#define RL_CFG0_ROM1 0x02 361#define RL_CFG0_ROM2 0x04 362#define RL_CFG0_PL0 0x08 363#define RL_CFG0_PL1 0x10 364#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 365#define RL_CFG0_PCS 0x40 366#define RL_CFG0_SCR 0x80 367 368/* 369 * Config 1 register 370 */ 371#define RL_CFG1_PWRDWN 0x01 372#define RL_CFG1_PME 0x01 373#define RL_CFG1_SLEEP 0x02 374#define RL_CFG1_VPDEN 0x02 375#define RL_CFG1_IOMAP 0x04 376#define RL_CFG1_MEMMAP 0x08 377#define RL_CFG1_RSVD 0x10 378#define RL_CFG1_LWACT 0x10 379#define RL_CFG1_DRVLOAD 0x20 380#define RL_CFG1_LED0 0x40 381#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 382#define RL_CFG1_LED1 0x80 383 384/* 385 * Config 2 register 386 */ 387#define RL_CFG2_PCI33MHZ 0x00 388#define RL_CFG2_PCI66MHZ 0x01 389#define RL_CFG2_PCI64BIT 0x08 390#define RL_CFG2_AUXPWR 0x10 391#define RL_CFG2_MSI 0x20 392 393/* 394 * Config 3 register 395 */ 396#define RL_CFG3_GRANTSEL 0x80 397#define RL_CFG3_WOL_MAGIC 0x20 398#define RL_CFG3_WOL_LINK 0x10 399#define RL_CFG3_FAST_B2B 0x01 400 401/* 402 * Config 4 register 403 */ 404#define RL_CFG4_LWPTN 0x04 405#define RL_CFG4_LWPME 0x10 406 407/* 408 * Config 5 register 409 */ 410#define RL_CFG5_WOL_BCAST 0x40 411#define RL_CFG5_WOL_MCAST 0x20 412#define RL_CFG5_WOL_UCAST 0x10 413#define RL_CFG5_WOL_LANWAKE 0x02 414#define RL_CFG5_PME_STS 0x01 415 416/* 417 * 8139C+ register definitions 418 */ 419 420/* RL_DUMPSTATS_LO register */ 421 422#define RL_DUMPSTATS_START 0x00000008 423 424/* Transmit start register */ 425 426#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 427#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 428#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 429 430/* 431 * Config 2 register, 8139C+/8169/8169S/8110S only 432 */ 433#define RL_CFG2_BUSFREQ 0x07 434#define RL_CFG2_BUSWIDTH 0x08 435#define RL_CFG2_AUXPWRSTS 0x10 436 437#define RL_BUSFREQ_33MHZ 0x00 438#define RL_BUSFREQ_66MHZ 0x01 439 440#define RL_BUSWIDTH_32BITS 0x00 441#define RL_BUSWIDTH_64BITS 0x08 442 443/* C+ mode command register */ 444 445#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 446#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 447#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 448#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 449#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 450#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 451#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 452#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 453#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 454#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 455#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 456#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 457#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 458#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 459#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 460 461/* C+ early transmit threshold */ 462 463#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 464 465/* 466 * Gigabit PHY access register (8169 only) 467 */ 468 469#define RL_PHYAR_PHYDATA 0x0000FFFF 470#define RL_PHYAR_PHYREG 0x001F0000 471#define RL_PHYAR_BUSY 0x80000000 472 473/* 474 * Gigabit media status (8169 only) 475 */ 476#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 477#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 478#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 479#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 480#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 481#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 482#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 483#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 484 485/* 486 * The RealTek doesn't use a fragment-based descriptor mechanism. 487 * Instead, there are only four register sets, each or which represents 488 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 489 * packet buffer (32-bit aligned!) and we place the buffer addresses in 490 * the registers so the chip knows where they are. 491 * 492 * We can sort of kludge together the same kind of buffer management 493 * used in previous drivers, but we have to do buffer copies almost all 494 * the time, so it doesn't really buy us much. 495 * 496 * For reception, there's just one large buffer where the chip stores 497 * all received packets. 498 */ 499 500#define RL_RX_BUF_SZ RL_RXBUF_64 501#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 502#define RL_TX_LIST_CNT 4 503#define RL_MIN_FRAMELEN 60 504#define RL_TX_8139_BUF_ALIGN 4 505#define RL_RX_8139_BUF_ALIGN 8 506#define RL_RX_8139_BUF_RESERVE sizeof(int64_t) 507#define RL_RX_8139_BUF_GUARD_SZ \ 508 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE) 509#define RL_TXTHRESH(x) ((x) << 11) 510#define RL_TX_THRESH_INIT 96 511#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 512#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 513#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 514 515#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 516#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 517 518#define RL_ETHER_ALIGN 2 519 520/* 521 * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets. 522 */ 523#define RL_IP4CSUMTX_MINLEN 28 524#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 525 526struct rl_chain_data { 527 uint16_t cur_rx; 528 uint8_t *rl_rx_buf; 529 uint8_t *rl_rx_buf_ptr; 530 531 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 532 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 533 bus_dma_tag_t rl_tx_tag; 534 bus_dma_tag_t rl_rx_tag; 535 bus_dmamap_t rl_rx_dmamap; 536 bus_addr_t rl_rx_buf_paddr; 537 uint8_t last_tx; 538 uint8_t cur_tx; 539}; 540 541#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 542#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 543#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 544#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 545#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 546#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 547#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 548#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 549#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 550 551struct rl_type { 552 uint16_t rl_vid; 553 uint16_t rl_did; 554 int rl_basetype; 555 char *rl_name; 556}; 557 558struct rl_hwrev { 559 uint32_t rl_rev; 560 int rl_type; 561 char *rl_desc; 562}; 563 564struct rl_mii_frame { 565 uint8_t mii_stdelim; 566 uint8_t mii_opcode; 567 uint8_t mii_phyaddr; 568 uint8_t mii_regaddr; 569 uint8_t mii_turnaround; 570 uint16_t mii_data; 571}; 572 573/* 574 * MII constants 575 */ 576#define RL_MII_STARTDELIM 0x01 577#define RL_MII_READOP 0x02 578#define RL_MII_WRITEOP 0x01 579#define RL_MII_TURNAROUND 0x02 580 581#define RL_8129 1 582#define RL_8139 2 583#define RL_8139CPLUS 3 584#define RL_8169 4 585 586#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 587 (x)->rl_type == RL_8169) 588 589/* 590 * The 8139C+ and 8160 gigE chips support descriptor-based TX 591 * and RX. In fact, they even support TCP large send. Descriptors 592 * must be allocated in contiguous blocks that are aligned on a 593 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 594 */ 595 596/* 597 * RX/TX descriptor definition. When large send mode is enabled, the 598 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 599 * the checksum offload bits are disabled. The structure layout is 600 * the same for RX and TX descriptors 601 */ 602 603struct rl_desc { 604 uint32_t rl_cmdstat; 605 uint32_t rl_vlanctl; 606 uint32_t rl_bufaddr_lo; 607 uint32_t rl_bufaddr_hi; 608}; 609 610#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 611#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 612#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 613#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 614#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 615#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 616#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 617#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 618#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 619#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 620#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 621 622#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 623#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 624/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 625#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 626#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 627#define RL_TDESC_CMD_IPCSUMV2 0x20000000 628 629/* 630 * Error bits are valid only on the last descriptor of a frame 631 * (i.e. RL_TDESC_CMD_EOF == 1) 632 */ 633 634#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 635#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 636#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 637#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 638#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 639#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 640#define RL_TDESC_STAT_OWN 0x80000000 641 642/* 643 * RX descriptor cmd/vlan definitions 644 */ 645 646#define RL_RDESC_CMD_EOR 0x40000000 647#define RL_RDESC_CMD_OWN 0x80000000 648#define RL_RDESC_CMD_BUFLEN 0x00001FFF 649 650#define RL_RDESC_STAT_OWN 0x80000000 651#define RL_RDESC_STAT_EOR 0x40000000 652#define RL_RDESC_STAT_SOF 0x20000000 653#define RL_RDESC_STAT_EOF 0x10000000 654#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 655#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 656#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 657#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 658#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 659#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 660#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 661#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 662#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 663#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 664#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 665#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 666#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 667#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 668#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 669#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 670#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 671#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 672#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 673 RL_RDESC_STAT_CRCERR) 674 675#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 676 (rl_vlandata valid)*/ 677#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 678/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 679#define RL_RDESC_IPV6 0x80000000 680#define RL_RDESC_IPV4 0x40000000 681 682#define RL_PROTOID_NONIP 0x00000000 683#define RL_PROTOID_TCPIP 0x00010000 684#define RL_PROTOID_UDPIP 0x00020000 685#define RL_PROTOID_IP 0x00030000 686#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 687 RL_PROTOID_TCPIP) 688#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 689 RL_PROTOID_UDPIP) 690 691/* 692 * Statistics counter structure (8139C+ and 8169 only) 693 */ 694struct rl_stats { 695 uint32_t rl_tx_pkts_lo; 696 uint32_t rl_tx_pkts_hi; 697 uint32_t rl_tx_errs_lo; 698 uint32_t rl_tx_errs_hi; 699 uint32_t rl_tx_errs; 700 uint16_t rl_missed_pkts; 701 uint16_t rl_rx_framealign_errs; 702 uint32_t rl_tx_onecoll; 703 uint32_t rl_tx_multicolls; 704 uint32_t rl_rx_ucasts_hi; 705 uint32_t rl_rx_ucasts_lo; 706 uint32_t rl_rx_bcasts_lo; 707 uint32_t rl_rx_bcasts_hi; 708 uint32_t rl_rx_mcasts; 709 uint16_t rl_tx_aborts; 710 uint16_t rl_rx_underruns; 711}; 712 713/* 714 * Rx/Tx descriptor parameters (8139C+ and 8169 only) 715 * 716 * 8139C+ 717 * Number of descriptors supported : up to 64 718 * Descriptor alignment : 256 bytes 719 * Tx buffer : At least 4 bytes in length. 720 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 721 * 722 * 8169 723 * Number of descriptors supported : up to 1024 724 * Descriptor alignment : 256 bytes 725 * Tx buffer : At least 4 bytes in length. 726 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 727 */ 728#ifndef __NO_STRICT_ALIGNMENT 729#define RE_FIXUP_RX 1 730#endif 731 732#define RL_8169_TX_DESC_CNT 256 733#define RL_8169_RX_DESC_CNT 256 734#define RL_8139_TX_DESC_CNT 64 735#define RL_8139_RX_DESC_CNT 64 736#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT 737#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT 738#define RL_NTXSEGS 32 739 740#define RL_RING_ALIGN 256 741#define RL_IFQ_MAXLEN 512 742#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 743#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 744#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1)) 745#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 746#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 747#define RL_PKTSZ(x) ((x)/* >> 3*/) 748#ifdef RE_FIXUP_RX 749#define RE_ETHER_ALIGN sizeof(uint64_t) 750#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 751#else 752#define RE_ETHER_ALIGN 0 753#define RE_RX_DESC_BUFLEN MCLBYTES 754#endif 755 756#define RL_MSI_MESSAGES 2 757 758#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 759#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 760 761/* 762 * The number of bits reserved for MSS in RealTek controllers is 763 * 11bits. This limits the maximum interface MTU size in TSO case 764 * as upper stack should not generate TCP segments with MSS greater 765 * than the limit. 766 */ 767#define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN) 768 769/* see comment in dev/re/if_re.c */ 770#define RL_JUMBO_FRAMELEN 7440 771#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 772#define RL_MAX_FRAMELEN \ 773 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 774 775struct rl_txdesc { 776 struct mbuf *tx_m; 777 bus_dmamap_t tx_dmamap; 778}; 779 780struct rl_rxdesc { 781 struct mbuf *rx_m; 782 bus_dmamap_t rx_dmamap; 783 bus_size_t rx_size; 784}; 785 786struct rl_list_data { 787 struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; 788 struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; 789 int rl_tx_desc_cnt; 790 int rl_rx_desc_cnt; 791 int rl_tx_prodidx; 792 int rl_rx_prodidx; 793 int rl_tx_considx; 794 int rl_tx_free; 795 bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ 796 bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ 797 bus_dmamap_t rl_rx_sparemap; 798 bus_dma_tag_t rl_stag; /* stats mapping tag */ 799 bus_dmamap_t rl_smap; /* stats map */ 800 struct rl_stats *rl_stats; 801 bus_addr_t rl_stats_addr; 802 bus_dma_tag_t rl_rx_list_tag; 803 bus_dmamap_t rl_rx_list_map; 804 struct rl_desc *rl_rx_list; 805 bus_addr_t rl_rx_list_addr; 806 bus_dma_tag_t rl_tx_list_tag; 807 bus_dmamap_t rl_tx_list_map; 808 struct rl_desc *rl_tx_list; 809 bus_addr_t rl_tx_list_addr; 810}; 811 812struct rl_softc { 813 struct ifnet *rl_ifp; /* interface info */ 814 bus_space_handle_t rl_bhandle; /* bus space handle */ 815 bus_space_tag_t rl_btag; /* bus space tag */ 816 device_t rl_dev; 817 struct resource *rl_res; 818 int rl_res_id; 819 int rl_res_type; 820 struct resource *rl_irq[RL_MSI_MESSAGES]; 821 void *rl_intrhand[RL_MSI_MESSAGES]; 822 device_t rl_miibus; 823 bus_dma_tag_t rl_parent_tag; 824 uint8_t rl_type; 825 int rl_eecmd_read; 826 int rl_eewidth; 827 uint8_t rl_stats_no_timeout; 828 int rl_txthresh; 829 struct rl_chain_data rl_cdata; 830 struct rl_list_data rl_ldata; 831 struct callout rl_stat_callout; 832 int rl_watchdog_timer; 833 struct mtx rl_mtx; 834 struct mbuf *rl_head; 835 struct mbuf *rl_tail; 836 uint32_t rl_hwrev; 837 uint32_t rl_rxlenmask; 838 int rl_testmode; 839 int rl_if_flags; 840 int suspended; /* 0 = normal 1 = suspended */ 841#ifdef DEVICE_POLLING 842 int rxcycles; 843#endif 844 845 struct task rl_txtask; 846 struct task rl_inttask; 847 848 int rl_txstart; 849 uint32_t rl_flags; 850#define RL_FLAG_MSI 0x0001 851#define RL_FLAG_INVMAR 0x0004 852#define RL_FLAG_PHYWAKE 0x0008 853#define RL_FLAG_NOJUMBO 0x0010 854#define RL_FLAG_PAR 0x0020 855#define RL_FLAG_DESCV2 0x0040 856#define RL_FLAG_MACSTAT 0x0080 857#define RL_FLAG_LINK 0x8000 858}; 859 860#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 861#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 862#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 863 864/* 865 * register space access macros 866 */ 867#define CSR_WRITE_STREAM_4(sc, reg, val) \ 868 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 869#define CSR_WRITE_4(sc, reg, val) \ 870 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 871#define CSR_WRITE_2(sc, reg, val) \ 872 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 873#define CSR_WRITE_1(sc, reg, val) \ 874 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 875 876#define CSR_READ_4(sc, reg) \ 877 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 878#define CSR_READ_2(sc, reg) \ 879 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 880#define CSR_READ_1(sc, reg) \ 881 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 882 883#define CSR_SETBIT_1(sc, offset, val) \ 884 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 885 886#define CSR_CLRBIT_1(sc, offset, val) \ 887 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 888 889#define CSR_SETBIT_2(sc, offset, val) \ 890 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 891 892#define CSR_CLRBIT_2(sc, offset, val) \ 893 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 894 895#define CSR_SETBIT_4(sc, offset, val) \ 896 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 897 898#define CSR_CLRBIT_4(sc, offset, val) \ 899 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 900 901#define RL_TIMEOUT 1000 902 903/* 904 * General constants that are fun to know. 905 * 906 * RealTek PCI vendor ID 907 */ 908#define RT_VENDORID 0x10EC 909 910/* 911 * RealTek chip device IDs. 912 */ 913#define RT_DEVICEID_8139D 0x8039 914#define RT_DEVICEID_8129 0x8129 915#define RT_DEVICEID_8101E 0x8136 916#define RT_DEVICEID_8138 0x8138 917#define RT_DEVICEID_8139 0x8139 918#define RT_DEVICEID_8169SC 0x8167 919#define RT_DEVICEID_8168 0x8168 920#define RT_DEVICEID_8169 0x8169 921#define RT_DEVICEID_8100 0x8100 922 923#define RT_REVID_8139CPLUS 0x20 924 925/* 926 * Accton PCI vendor ID 927 */ 928#define ACCTON_VENDORID 0x1113 929 930/* 931 * Accton MPX 5030/5038 device ID. 932 */ 933#define ACCTON_DEVICEID_5030 0x1211 934 935/* 936 * Nortel PCI vendor ID 937 */ 938#define NORTEL_VENDORID 0x126C 939 940/* 941 * Delta Electronics Vendor ID. 942 */ 943#define DELTA_VENDORID 0x1500 944 945/* 946 * Delta device IDs. 947 */ 948#define DELTA_DEVICEID_8139 0x1360 949 950/* 951 * Addtron vendor ID. 952 */ 953#define ADDTRON_VENDORID 0x4033 954 955/* 956 * Addtron device IDs. 957 */ 958#define ADDTRON_DEVICEID_8139 0x1360 959 960/* 961 * D-Link vendor ID. 962 */ 963#define DLINK_VENDORID 0x1186 964 965/* 966 * D-Link DFE-530TX+ device ID 967 */ 968#define DLINK_DEVICEID_530TXPLUS 0x1300 969 970/* 971 * D-Link DFE-5280T device ID 972 */ 973#define DLINK_DEVICEID_528T 0x4300 974 975/* 976 * D-Link DFE-690TXD device ID 977 */ 978#define DLINK_DEVICEID_690TXD 0x1340 979 980/* 981 * Corega K.K vendor ID 982 */ 983#define COREGA_VENDORID 0x1259 984 985/* 986 * Corega FEther CB-TXD device ID 987 */ 988#define COREGA_DEVICEID_FETHERCBTXD 0xa117 989 990/* 991 * Corega FEtherII CB-TXD device ID 992 */ 993#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 994 995/* 996 * Corega CG-LAPCIGT device ID 997 */ 998#define COREGA_DEVICEID_CGLAPCIGT 0xc107 999 1000/* 1001 * Linksys vendor ID 1002 */ 1003#define LINKSYS_VENDORID 0x1737 1004 1005/* 1006 * Linksys EG1032 device ID 1007 */ 1008#define LINKSYS_DEVICEID_EG1032 0x1032 1009 1010/* 1011 * Linksys EG1032 rev 3 sub-device ID 1012 */ 1013#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 1014 1015/* 1016 * Peppercon vendor ID 1017 */ 1018#define PEPPERCON_VENDORID 0x1743 1019 1020/* 1021 * Peppercon ROL-F device ID 1022 */ 1023#define PEPPERCON_DEVICEID_ROLF 0x8139 1024 1025/* 1026 * Planex Communications, Inc. vendor ID 1027 */ 1028#define PLANEX_VENDORID 0x14ea 1029 1030/* 1031 * Planex FNW-3603-TX device ID 1032 */ 1033#define PLANEX_DEVICEID_FNW3603TX 0xab06 1034 1035/* 1036 * Planex FNW-3800-TX device ID 1037 */ 1038#define PLANEX_DEVICEID_FNW3800TX 0xab07 1039 1040/* 1041 * LevelOne vendor ID 1042 */ 1043#define LEVEL1_VENDORID 0x018A 1044 1045/* 1046 * LevelOne FPC-0106TX devide ID 1047 */ 1048#define LEVEL1_DEVICEID_FPC0106TX 0x0106 1049 1050/* 1051 * Compaq vendor ID 1052 */ 1053#define CP_VENDORID 0x021B 1054 1055/* 1056 * Edimax vendor ID 1057 */ 1058#define EDIMAX_VENDORID 0x13D1 1059 1060/* 1061 * Edimax EP-4103DL cardbus device ID 1062 */ 1063#define EDIMAX_DEVICEID_EP4103DL 0xAB06 1064 1065/* US Robotics vendor ID */ 1066 1067#define USR_VENDORID 0x16EC 1068 1069/* US Robotics 997902 device ID */ 1070 1071#define USR_DEVICEID_997902 0x0116 1072 1073/* 1074 * PCI low memory base and low I/O base register, and 1075 * other PCI registers. 1076 */ 1077 1078#define RL_PCI_VENDOR_ID 0x00 1079#define RL_PCI_DEVICE_ID 0x02 1080#define RL_PCI_COMMAND 0x04 1081#define RL_PCI_STATUS 0x06 1082#define RL_PCI_CLASSCODE 0x09 1083#define RL_PCI_LATENCY_TIMER 0x0D 1084#define RL_PCI_HEADER_TYPE 0x0E 1085#define RL_PCI_LOIO 0x10 1086#define RL_PCI_LOMEM 0x14 1087#define RL_PCI_BIOSROM 0x30 1088#define RL_PCI_INTLINE 0x3C 1089#define RL_PCI_INTPIN 0x3D 1090#define RL_PCI_MINGNT 0x3E 1091#define RL_PCI_MINLAT 0x0F 1092#define RL_PCI_RESETOPT 0x48 1093#define RL_PCI_EEPROM_DATA 0x4C 1094 1095#define RL_PCI_CAPID 0x50 /* 8 bits */ 1096#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 1097#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 1098#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 1099 1100#define RL_PSTATE_MASK 0x0003 1101#define RL_PSTATE_D0 0x0000 1102#define RL_PSTATE_D1 0x0002 1103#define RL_PSTATE_D2 0x0002 1104#define RL_PSTATE_D3 0x0003 1105#define RL_PME_EN 0x0010 1106#define RL_PME_STATUS 0x8000 1107