if_rlreg.h revision 180177
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_rlreg.h 180177 2008-07-02 08:00:14Z yongari $ 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 41#define RL_IDR3 0x0003 42#define RL_IDR4 0x0004 43#define RL_IDR5 0x0005 44 /* 0006-0007 reserved */ 45#define RL_MAR0 0x0008 /* Multicast hash table */ 46#define RL_MAR1 0x0009 47#define RL_MAR2 0x000A 48#define RL_MAR3 0x000B 49#define RL_MAR4 0x000C 50#define RL_MAR5 0x000D 51#define RL_MAR6 0x000E 52#define RL_MAR7 0x000F 53 54#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 58 59#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 63 64#define RL_RXADDR 0x0030 /* RX ring start address */ 65#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67#define RL_COMMAND 0x0037 /* command register */ 68#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70#define RL_IMR 0x003C /* interrupt mask register */ 71#define RL_ISR 0x003E /* interrupt status register */ 72#define RL_TXCFG 0x0040 /* transmit config */ 73#define RL_RXCFG 0x0044 /* receive config */ 74#define RL_TIMERCNT 0x0048 /* timer count register */ 75#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76#define RL_EECMD 0x0050 /* EEPROM command register */ 77#define RL_CFG0 0x0051 /* config register #0 */ 78#define RL_CFG1 0x0052 /* config register #1 */ 79#define RL_CFG2 0x0053 /* config register #2 */ 80#define RL_CFG3 0x0054 /* config register #3 */ 81#define RL_CFG4 0x0055 /* config register #4 */ 82#define RL_CFG5 0x0056 /* config register #5 */ 83 /* 0057 reserved */ 84#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 85 /* 0059-005A reserved */ 86#define RL_MII 0x005A /* 8129 chip only */ 87#define RL_HALTCLK 0x005B 88#define RL_MULTIINTR 0x005C /* multiple interrupt */ 89#define RL_PCIREV 0x005E /* PCI revision value */ 90 /* 005F reserved */ 91#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 92 93/* Direct PHY access registers only available on 8139 */ 94#define RL_BMCR 0x0062 /* PHY basic mode control */ 95#define RL_BMSR 0x0064 /* PHY basic mode status */ 96#define RL_ANAR 0x0066 /* PHY autoneg advert */ 97#define RL_LPAR 0x0068 /* PHY link partner ability */ 98#define RL_ANER 0x006A /* PHY autoneg expansion */ 99 100#define RL_DISCCNT 0x006C /* disconnect counter */ 101#define RL_FALSECAR 0x006E /* false carrier counter */ 102#define RL_NWAYTST 0x0070 /* NWAY test register */ 103#define RL_RX_ER 0x0072 /* RX_ER counter */ 104#define RL_CSCFG 0x0074 /* CS configuration register */ 105 106/* 107 * When operating in special C+ mode, some of the registers in an 108 * 8139C+ chip have different definitions. These are also used for 109 * the 8169 gigE chip. 110 */ 111#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 112#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 113#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 114#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 115#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 116#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 117#define RL_CFG2 0x0053 118#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 119#define RL_TXSTART 0x00D9 /* 8 bits */ 120#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 121#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 122#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 123#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 124 125/* 126 * Registers specific to the 8169 gigE chip 127 */ 128#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 129#define RL_PHYAR 0x0060 130#define RL_TBICSR 0x0064 131#define RL_TBI_ANAR 0x0068 132#define RL_TBI_LPAR 0x006A 133#define RL_GMEDIASTAT 0x006C /* 8 bits */ 134#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 135#define RL_GTXSTART 0x0038 /* 8 bits */ 136 137/* 138 * TX config register bits 139 */ 140#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 141#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 142#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 143#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 144#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 145#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 146#define RL_TXCFG_HWREV 0x7CC00000 147 148#define RL_LOOPTEST_OFF 0x00000000 149#define RL_LOOPTEST_ON 0x00020000 150#define RL_LOOPTEST_ON_CPLUS 0x00060000 151 152/* Known revision codes. */ 153 154#define RL_HWREV_8169 0x00000000 155#define RL_HWREV_8110S 0x00800000 156#define RL_HWREV_8169S 0x04000000 157#define RL_HWREV_8169_8110SB 0x10000000 158#define RL_HWREV_8169_8110SC 0x18000000 159#define RL_HWREV_8168_SPIN1 0x30000000 160#define RL_HWREV_8100E 0x30800000 161#define RL_HWREV_8101E 0x34000000 162#define RL_HWREV_8168_SPIN2 0x38000000 163#define RL_HWREV_8168_SPIN3 0x38400000 164#define RL_HWREV_8168C 0x3C000000 165#define RL_HWREV_8168C_SPIN2 0x3C400000 166#define RL_HWREV_8168CP 0x3C800000 167#define RL_HWREV_8139 0x60000000 168#define RL_HWREV_8139A 0x70000000 169#define RL_HWREV_8139AG 0x70800000 170#define RL_HWREV_8139B 0x78000000 171#define RL_HWREV_8130 0x7C000000 172#define RL_HWREV_8139C 0x74000000 173#define RL_HWREV_8139D 0x74400000 174#define RL_HWREV_8139CPLUS 0x74800000 175#define RL_HWREV_8101 0x74c00000 176#define RL_HWREV_8100 0x78800000 177#define RL_HWREV_8169_8110SBL 0x7CC00000 178 179#define RL_TXDMA_16BYTES 0x00000000 180#define RL_TXDMA_32BYTES 0x00000100 181#define RL_TXDMA_64BYTES 0x00000200 182#define RL_TXDMA_128BYTES 0x00000300 183#define RL_TXDMA_256BYTES 0x00000400 184#define RL_TXDMA_512BYTES 0x00000500 185#define RL_TXDMA_1024BYTES 0x00000600 186#define RL_TXDMA_2048BYTES 0x00000700 187 188/* 189 * Transmit descriptor status register bits. 190 */ 191#define RL_TXSTAT_LENMASK 0x00001FFF 192#define RL_TXSTAT_OWN 0x00002000 193#define RL_TXSTAT_TX_UNDERRUN 0x00004000 194#define RL_TXSTAT_TX_OK 0x00008000 195#define RL_TXSTAT_EARLY_THRESH 0x003F0000 196#define RL_TXSTAT_COLLCNT 0x0F000000 197#define RL_TXSTAT_CARR_HBEAT 0x10000000 198#define RL_TXSTAT_OUTOFWIN 0x20000000 199#define RL_TXSTAT_TXABRT 0x40000000 200#define RL_TXSTAT_CARRLOSS 0x80000000 201 202/* 203 * Interrupt status register bits. 204 */ 205#define RL_ISR_RX_OK 0x0001 206#define RL_ISR_RX_ERR 0x0002 207#define RL_ISR_TX_OK 0x0004 208#define RL_ISR_TX_ERR 0x0008 209#define RL_ISR_RX_OVERRUN 0x0010 210#define RL_ISR_PKT_UNDERRUN 0x0020 211#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 212#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 213#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 214#define RL_ISR_SWI 0x0100 /* C+ only */ 215#define RL_ISR_CABLE_LEN_CHGD 0x2000 216#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 217#define RL_ISR_TIMEOUT_EXPIRED 0x4000 218#define RL_ISR_SYSTEM_ERR 0x8000 219 220#define RL_INTRS \ 221 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 222 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 223 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 224 225#ifdef RE_TX_MODERATION 226#define RL_INTRS_CPLUS \ 227 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 228 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 229 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 230#else 231#define RL_INTRS_CPLUS \ 232 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 233 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 234 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 235#endif 236 237/* 238 * Media status register. (8139 only) 239 */ 240#define RL_MEDIASTAT_RXPAUSE 0x01 241#define RL_MEDIASTAT_TXPAUSE 0x02 242#define RL_MEDIASTAT_LINK 0x04 243#define RL_MEDIASTAT_SPEED10 0x08 244#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 245#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 246 247/* 248 * Receive config register. 249 */ 250#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 251#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 252#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 253#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 254#define RL_RXCFG_RX_RUNT 0x00000010 255#define RL_RXCFG_RX_ERRPKT 0x00000020 256#define RL_RXCFG_WRAP 0x00000080 257#define RL_RXCFG_MAXDMA 0x00000700 258#define RL_RXCFG_BUFSZ 0x00001800 259#define RL_RXCFG_FIFOTHRESH 0x0000E000 260#define RL_RXCFG_EARLYTHRESH 0x07000000 261 262#define RL_RXDMA_16BYTES 0x00000000 263#define RL_RXDMA_32BYTES 0x00000100 264#define RL_RXDMA_64BYTES 0x00000200 265#define RL_RXDMA_128BYTES 0x00000300 266#define RL_RXDMA_256BYTES 0x00000400 267#define RL_RXDMA_512BYTES 0x00000500 268#define RL_RXDMA_1024BYTES 0x00000600 269#define RL_RXDMA_UNLIMITED 0x00000700 270 271#define RL_RXBUF_8 0x00000000 272#define RL_RXBUF_16 0x00000800 273#define RL_RXBUF_32 0x00001000 274#define RL_RXBUF_64 0x00001800 275 276#define RL_RXFIFO_16BYTES 0x00000000 277#define RL_RXFIFO_32BYTES 0x00002000 278#define RL_RXFIFO_64BYTES 0x00004000 279#define RL_RXFIFO_128BYTES 0x00006000 280#define RL_RXFIFO_256BYTES 0x00008000 281#define RL_RXFIFO_512BYTES 0x0000A000 282#define RL_RXFIFO_1024BYTES 0x0000C000 283#define RL_RXFIFO_NOTHRESH 0x0000E000 284 285/* 286 * Bits in RX status header (included with RX'ed packet 287 * in ring buffer). 288 */ 289#define RL_RXSTAT_RXOK 0x00000001 290#define RL_RXSTAT_ALIGNERR 0x00000002 291#define RL_RXSTAT_CRCERR 0x00000004 292#define RL_RXSTAT_GIANT 0x00000008 293#define RL_RXSTAT_RUNT 0x00000010 294#define RL_RXSTAT_BADSYM 0x00000020 295#define RL_RXSTAT_BROAD 0x00002000 296#define RL_RXSTAT_INDIV 0x00004000 297#define RL_RXSTAT_MULTI 0x00008000 298#define RL_RXSTAT_LENMASK 0xFFFF0000 299 300#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 301/* 302 * Command register. 303 */ 304#define RL_CMD_EMPTY_RXBUF 0x0001 305#define RL_CMD_TX_ENB 0x0004 306#define RL_CMD_RX_ENB 0x0008 307#define RL_CMD_RESET 0x0010 308 309/* 310 * EEPROM control register 311 */ 312#define RL_EE_DATAOUT 0x01 /* Data out */ 313#define RL_EE_DATAIN 0x02 /* Data in */ 314#define RL_EE_CLK 0x04 /* clock */ 315#define RL_EE_SEL 0x08 /* chip select */ 316#define RL_EE_MODE (0x40|0x80) 317 318#define RL_EEMODE_OFF 0x00 319#define RL_EEMODE_AUTOLOAD 0x40 320#define RL_EEMODE_PROGRAM 0x80 321#define RL_EEMODE_WRITECFG (0x80|0x40) 322 323/* 9346 EEPROM commands */ 324#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 325#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 326 327#define RL_9346_WRITE 0x5 328#define RL_9346_READ 0x6 329#define RL_9346_ERASE 0x7 330#define RL_9346_EWEN 0x4 331#define RL_9346_EWEN_ADDR 0x30 332#define RL_9456_EWDS 0x4 333#define RL_9346_EWDS_ADDR 0x00 334 335#define RL_EECMD_WRITE 0x140 336#define RL_EECMD_READ_6BIT 0x180 337#define RL_EECMD_READ_8BIT 0x600 338#define RL_EECMD_ERASE 0x1c0 339 340#define RL_EE_ID 0x00 341#define RL_EE_PCI_VID 0x01 342#define RL_EE_PCI_DID 0x02 343/* Location of station address inside EEPROM */ 344#define RL_EE_EADDR 0x07 345 346/* 347 * MII register (8129 only) 348 */ 349#define RL_MII_CLK 0x01 350#define RL_MII_DATAIN 0x02 351#define RL_MII_DATAOUT 0x04 352#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 353 354/* 355 * Config 0 register 356 */ 357#define RL_CFG0_ROM0 0x01 358#define RL_CFG0_ROM1 0x02 359#define RL_CFG0_ROM2 0x04 360#define RL_CFG0_PL0 0x08 361#define RL_CFG0_PL1 0x10 362#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 363#define RL_CFG0_PCS 0x40 364#define RL_CFG0_SCR 0x80 365 366/* 367 * Config 1 register 368 */ 369#define RL_CFG1_PWRDWN 0x01 370#define RL_CFG1_PME 0x01 371#define RL_CFG1_SLEEP 0x02 372#define RL_CFG1_VPDEN 0x02 373#define RL_CFG1_IOMAP 0x04 374#define RL_CFG1_MEMMAP 0x08 375#define RL_CFG1_RSVD 0x10 376#define RL_CFG1_LWACT 0x10 377#define RL_CFG1_DRVLOAD 0x20 378#define RL_CFG1_LED0 0x40 379#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 380#define RL_CFG1_LED1 0x80 381 382/* 383 * Config 2 register 384 */ 385#define RL_CFG2_PCI33MHZ 0x00 386#define RL_CFG2_PCI66MHZ 0x01 387#define RL_CFG2_PCI64BIT 0x08 388#define RL_CFG2_AUXPWR 0x10 389#define RL_CFG2_MSI 0x20 390 391/* 392 * Config 3 register 393 */ 394#define RL_CFG3_GRANTSEL 0x80 395#define RL_CFG3_WOL_MAGIC 0x20 396#define RL_CFG3_WOL_LINK 0x10 397#define RL_CFG3_FAST_B2B 0x01 398 399/* 400 * Config 4 register 401 */ 402#define RL_CFG4_LWPTN 0x04 403#define RL_CFG4_LWPME 0x10 404 405/* 406 * Config 5 register 407 */ 408#define RL_CFG5_WOL_BCAST 0x40 409#define RL_CFG5_WOL_MCAST 0x20 410#define RL_CFG5_WOL_UCAST 0x10 411#define RL_CFG5_WOL_LANWAKE 0x02 412#define RL_CFG5_PME_STS 0x01 413 414/* 415 * 8139C+ register definitions 416 */ 417 418/* RL_DUMPSTATS_LO register */ 419 420#define RL_DUMPSTATS_START 0x00000008 421 422/* Transmit start register */ 423 424#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 425#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 426#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 427 428/* 429 * Config 2 register, 8139C+/8169/8169S/8110S only 430 */ 431#define RL_CFG2_BUSFREQ 0x07 432#define RL_CFG2_BUSWIDTH 0x08 433#define RL_CFG2_AUXPWRSTS 0x10 434 435#define RL_BUSFREQ_33MHZ 0x00 436#define RL_BUSFREQ_66MHZ 0x01 437 438#define RL_BUSWIDTH_32BITS 0x00 439#define RL_BUSWIDTH_64BITS 0x08 440 441/* C+ mode command register */ 442 443#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 444#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 445#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 446#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 447#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 448#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 449#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 450#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 451#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 452#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 453#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 454#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 455#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 456#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 457#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 458 459/* C+ early transmit threshold */ 460 461#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 462 463/* 464 * Gigabit PHY access register (8169 only) 465 */ 466 467#define RL_PHYAR_PHYDATA 0x0000FFFF 468#define RL_PHYAR_PHYREG 0x001F0000 469#define RL_PHYAR_BUSY 0x80000000 470 471/* 472 * Gigabit media status (8169 only) 473 */ 474#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 475#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 476#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 477#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 478#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 479#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 480#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 481#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 482 483/* 484 * The RealTek doesn't use a fragment-based descriptor mechanism. 485 * Instead, there are only four register sets, each or which represents 486 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 487 * packet buffer (32-bit aligned!) and we place the buffer addresses in 488 * the registers so the chip knows where they are. 489 * 490 * We can sort of kludge together the same kind of buffer management 491 * used in previous drivers, but we have to do buffer copies almost all 492 * the time, so it doesn't really buy us much. 493 * 494 * For reception, there's just one large buffer where the chip stores 495 * all received packets. 496 */ 497 498#define RL_RX_BUF_SZ RL_RXBUF_64 499#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 500#define RL_TX_LIST_CNT 4 501#define RL_MIN_FRAMELEN 60 502#define RL_TXTHRESH(x) ((x) << 11) 503#define RL_TX_THRESH_INIT 96 504#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 505#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 506#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 507 508#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 509#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 510 511#define RL_ETHER_ALIGN 2 512 513/* 514 * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets. 515 */ 516#define RL_IP4CSUMTX_MINLEN 28 517#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 518 519struct rl_chain_data { 520 uint16_t cur_rx; 521 uint8_t *rl_rx_buf; 522 uint8_t *rl_rx_buf_ptr; 523 bus_dmamap_t rl_rx_dmamap; 524 525 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 526 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 527 uint8_t last_tx; 528 uint8_t cur_tx; 529}; 530 531#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 532#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 533#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 534#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 535#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 536#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 537#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 538#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 539#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 540 541struct rl_type { 542 uint16_t rl_vid; 543 uint16_t rl_did; 544 int rl_basetype; 545 char *rl_name; 546}; 547 548struct rl_hwrev { 549 uint32_t rl_rev; 550 int rl_type; 551 char *rl_desc; 552}; 553 554struct rl_mii_frame { 555 uint8_t mii_stdelim; 556 uint8_t mii_opcode; 557 uint8_t mii_phyaddr; 558 uint8_t mii_regaddr; 559 uint8_t mii_turnaround; 560 uint16_t mii_data; 561}; 562 563/* 564 * MII constants 565 */ 566#define RL_MII_STARTDELIM 0x01 567#define RL_MII_READOP 0x02 568#define RL_MII_WRITEOP 0x01 569#define RL_MII_TURNAROUND 0x02 570 571#define RL_8129 1 572#define RL_8139 2 573#define RL_8139CPLUS 3 574#define RL_8169 4 575 576#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 577 (x)->rl_type == RL_8169) 578 579/* 580 * The 8139C+ and 8160 gigE chips support descriptor-based TX 581 * and RX. In fact, they even support TCP large send. Descriptors 582 * must be allocated in contiguous blocks that are aligned on a 583 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 584 */ 585 586/* 587 * RX/TX descriptor definition. When large send mode is enabled, the 588 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 589 * the checksum offload bits are disabled. The structure layout is 590 * the same for RX and TX descriptors 591 */ 592 593struct rl_desc { 594 uint32_t rl_cmdstat; 595 uint32_t rl_vlanctl; 596 uint32_t rl_bufaddr_lo; 597 uint32_t rl_bufaddr_hi; 598}; 599 600#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 601#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 602#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 603#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 604#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 605#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 606#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 607#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 608#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 609#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 610#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 611 612#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 613#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 614/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 615#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 616#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 617#define RL_TDESC_CMD_IPCSUMV2 0x20000000 618 619/* 620 * Error bits are valid only on the last descriptor of a frame 621 * (i.e. RL_TDESC_CMD_EOF == 1) 622 */ 623 624#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 625#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 626#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 627#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 628#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 629#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 630#define RL_TDESC_STAT_OWN 0x80000000 631 632/* 633 * RX descriptor cmd/vlan definitions 634 */ 635 636#define RL_RDESC_CMD_EOR 0x40000000 637#define RL_RDESC_CMD_OWN 0x80000000 638#define RL_RDESC_CMD_BUFLEN 0x00001FFF 639 640#define RL_RDESC_STAT_OWN 0x80000000 641#define RL_RDESC_STAT_EOR 0x40000000 642#define RL_RDESC_STAT_SOF 0x20000000 643#define RL_RDESC_STAT_EOF 0x10000000 644#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 645#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 646#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 647#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 648#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 649#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 650#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 651#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 652#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 653#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 654#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 655#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 656#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 657#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 658#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 659#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 660#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 661#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 662#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 663 RL_RDESC_STAT_CRCERR) 664 665#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 666 (rl_vlandata valid)*/ 667#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 668/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 669#define RL_RDESC_IPV6 0x80000000 670#define RL_RDESC_IPV4 0x40000000 671 672#define RL_PROTOID_NONIP 0x00000000 673#define RL_PROTOID_TCPIP 0x00010000 674#define RL_PROTOID_UDPIP 0x00020000 675#define RL_PROTOID_IP 0x00030000 676#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 677 RL_PROTOID_TCPIP) 678#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 679 RL_PROTOID_UDPIP) 680 681/* 682 * Statistics counter structure (8139C+ and 8169 only) 683 */ 684struct rl_stats { 685 uint32_t rl_tx_pkts_lo; 686 uint32_t rl_tx_pkts_hi; 687 uint32_t rl_tx_errs_lo; 688 uint32_t rl_tx_errs_hi; 689 uint32_t rl_tx_errs; 690 uint16_t rl_missed_pkts; 691 uint16_t rl_rx_framealign_errs; 692 uint32_t rl_tx_onecoll; 693 uint32_t rl_tx_multicolls; 694 uint32_t rl_rx_ucasts_hi; 695 uint32_t rl_rx_ucasts_lo; 696 uint32_t rl_rx_bcasts_lo; 697 uint32_t rl_rx_bcasts_hi; 698 uint32_t rl_rx_mcasts; 699 uint16_t rl_tx_aborts; 700 uint16_t rl_rx_underruns; 701}; 702 703/* 704 * Rx/Tx descriptor parameters (8139C+ and 8169 only) 705 * 706 * 8139C+ 707 * Number of descriptors supported : up to 64 708 * Descriptor alignment : 256 bytes 709 * Tx buffer : At least 4 bytes in length. 710 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 711 * 712 * 8169 713 * Number of descriptors supported : up to 1024 714 * Descriptor alignment : 256 bytes 715 * Tx buffer : At least 4 bytes in length. 716 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 717 */ 718#ifndef __NO_STRICT_ALIGNMENT 719#define RE_FIXUP_RX 1 720#endif 721 722#define RL_8169_TX_DESC_CNT 256 723#define RL_8169_RX_DESC_CNT 256 724#define RL_8139_TX_DESC_CNT 64 725#define RL_8139_RX_DESC_CNT 64 726#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT 727#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT 728#define RL_NTXSEGS 32 729 730#define RL_RING_ALIGN 256 731#define RL_IFQ_MAXLEN 512 732#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 733#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 734#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1)) 735#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 736#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 737#define RL_PKTSZ(x) ((x)/* >> 3*/) 738#ifdef RE_FIXUP_RX 739#define RE_ETHER_ALIGN sizeof(uint64_t) 740#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 741#else 742#define RE_ETHER_ALIGN 0 743#define RE_RX_DESC_BUFLEN MCLBYTES 744#endif 745 746#define RL_MSI_MESSAGES 2 747 748#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 749#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 750 751/* see comment in dev/re/if_re.c */ 752#define RL_JUMBO_FRAMELEN 7440 753#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 754#define RL_MAX_FRAMELEN \ 755 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 756 757struct rl_txdesc { 758 struct mbuf *tx_m; 759 bus_dmamap_t tx_dmamap; 760}; 761 762struct rl_rxdesc { 763 struct mbuf *rx_m; 764 bus_dmamap_t rx_dmamap; 765 bus_size_t rx_size; 766}; 767 768struct rl_list_data { 769 struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; 770 struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; 771 int rl_tx_desc_cnt; 772 int rl_rx_desc_cnt; 773 int rl_tx_prodidx; 774 int rl_rx_prodidx; 775 int rl_tx_considx; 776 int rl_tx_free; 777 bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ 778 bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ 779 bus_dmamap_t rl_rx_sparemap; 780 bus_dma_tag_t rl_stag; /* stats mapping tag */ 781 bus_dmamap_t rl_smap; /* stats map */ 782 struct rl_stats *rl_stats; 783 bus_addr_t rl_stats_addr; 784 bus_dma_tag_t rl_rx_list_tag; 785 bus_dmamap_t rl_rx_list_map; 786 struct rl_desc *rl_rx_list; 787 bus_addr_t rl_rx_list_addr; 788 bus_dma_tag_t rl_tx_list_tag; 789 bus_dmamap_t rl_tx_list_map; 790 struct rl_desc *rl_tx_list; 791 bus_addr_t rl_tx_list_addr; 792}; 793 794struct rl_softc { 795 struct ifnet *rl_ifp; /* interface info */ 796 bus_space_handle_t rl_bhandle; /* bus space handle */ 797 bus_space_tag_t rl_btag; /* bus space tag */ 798 device_t rl_dev; 799 struct resource *rl_res; 800 int rl_res_id; 801 int rl_res_type; 802 struct resource *rl_irq[RL_MSI_MESSAGES]; 803 void *rl_intrhand[RL_MSI_MESSAGES]; 804 device_t rl_miibus; 805 bus_dma_tag_t rl_parent_tag; 806 bus_dma_tag_t rl_tag; 807 uint8_t rl_type; 808 int rl_eecmd_read; 809 int rl_eewidth; 810 uint8_t rl_stats_no_timeout; 811 int rl_txthresh; 812 struct rl_chain_data rl_cdata; 813 struct rl_list_data rl_ldata; 814 struct callout rl_stat_callout; 815 int rl_watchdog_timer; 816 struct mtx rl_mtx; 817 struct mbuf *rl_head; 818 struct mbuf *rl_tail; 819 uint32_t rl_hwrev; 820 uint32_t rl_rxlenmask; 821 int rl_testmode; 822 int rl_if_flags; 823 int suspended; /* 0 = normal 1 = suspended */ 824#ifdef DEVICE_POLLING 825 int rxcycles; 826#endif 827 828 struct task rl_txtask; 829 struct task rl_inttask; 830 831 int rl_txstart; 832 uint32_t rl_flags; 833#define RL_FLAG_MSI 0x0001 834#define RL_FLAG_INVMAR 0x0004 835#define RL_FLAG_PHYWAKE 0x0008 836#define RL_FLAG_NOJUMBO 0x0010 837#define RL_FLAG_PAR 0x0020 838#define RL_FLAG_DESCV2 0x0040 839#define RL_FLAG_MACSTAT 0x0080 840#define RL_FLAG_LINK 0x8000 841}; 842 843#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 844#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 845#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 846 847/* 848 * register space access macros 849 */ 850#define CSR_WRITE_STREAM_4(sc, reg, val) \ 851 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 852#define CSR_WRITE_4(sc, reg, val) \ 853 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 854#define CSR_WRITE_2(sc, reg, val) \ 855 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 856#define CSR_WRITE_1(sc, reg, val) \ 857 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 858 859#define CSR_READ_4(sc, reg) \ 860 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 861#define CSR_READ_2(sc, reg) \ 862 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 863#define CSR_READ_1(sc, reg) \ 864 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 865 866#define CSR_SETBIT_1(sc, offset, val) \ 867 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 868 869#define CSR_CLRBIT_1(sc, offset, val) \ 870 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 871 872#define CSR_SETBIT_2(sc, offset, val) \ 873 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 874 875#define CSR_CLRBIT_2(sc, offset, val) \ 876 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 877 878#define CSR_SETBIT_4(sc, offset, val) \ 879 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 880 881#define CSR_CLRBIT_4(sc, offset, val) \ 882 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 883 884#define RL_TIMEOUT 1000 885 886/* 887 * General constants that are fun to know. 888 * 889 * RealTek PCI vendor ID 890 */ 891#define RT_VENDORID 0x10EC 892 893/* 894 * RealTek chip device IDs. 895 */ 896#define RT_DEVICEID_8139D 0x8039 897#define RT_DEVICEID_8129 0x8129 898#define RT_DEVICEID_8101E 0x8136 899#define RT_DEVICEID_8138 0x8138 900#define RT_DEVICEID_8139 0x8139 901#define RT_DEVICEID_8169SC 0x8167 902#define RT_DEVICEID_8168 0x8168 903#define RT_DEVICEID_8169 0x8169 904#define RT_DEVICEID_8100 0x8100 905 906#define RT_REVID_8139CPLUS 0x20 907 908/* 909 * Accton PCI vendor ID 910 */ 911#define ACCTON_VENDORID 0x1113 912 913/* 914 * Accton MPX 5030/5038 device ID. 915 */ 916#define ACCTON_DEVICEID_5030 0x1211 917 918/* 919 * Nortel PCI vendor ID 920 */ 921#define NORTEL_VENDORID 0x126C 922 923/* 924 * Delta Electronics Vendor ID. 925 */ 926#define DELTA_VENDORID 0x1500 927 928/* 929 * Delta device IDs. 930 */ 931#define DELTA_DEVICEID_8139 0x1360 932 933/* 934 * Addtron vendor ID. 935 */ 936#define ADDTRON_VENDORID 0x4033 937 938/* 939 * Addtron device IDs. 940 */ 941#define ADDTRON_DEVICEID_8139 0x1360 942 943/* 944 * D-Link vendor ID. 945 */ 946#define DLINK_VENDORID 0x1186 947 948/* 949 * D-Link DFE-530TX+ device ID 950 */ 951#define DLINK_DEVICEID_530TXPLUS 0x1300 952 953/* 954 * D-Link DFE-5280T device ID 955 */ 956#define DLINK_DEVICEID_528T 0x4300 957 958/* 959 * D-Link DFE-690TXD device ID 960 */ 961#define DLINK_DEVICEID_690TXD 0x1340 962 963/* 964 * Corega K.K vendor ID 965 */ 966#define COREGA_VENDORID 0x1259 967 968/* 969 * Corega FEther CB-TXD device ID 970 */ 971#define COREGA_DEVICEID_FETHERCBTXD 0xa117 972 973/* 974 * Corega FEtherII CB-TXD device ID 975 */ 976#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 977 978/* 979 * Corega CG-LAPCIGT device ID 980 */ 981#define COREGA_DEVICEID_CGLAPCIGT 0xc107 982 983/* 984 * Linksys vendor ID 985 */ 986#define LINKSYS_VENDORID 0x1737 987 988/* 989 * Linksys EG1032 device ID 990 */ 991#define LINKSYS_DEVICEID_EG1032 0x1032 992 993/* 994 * Linksys EG1032 rev 3 sub-device ID 995 */ 996#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 997 998/* 999 * Peppercon vendor ID 1000 */ 1001#define PEPPERCON_VENDORID 0x1743 1002 1003/* 1004 * Peppercon ROL-F device ID 1005 */ 1006#define PEPPERCON_DEVICEID_ROLF 0x8139 1007 1008/* 1009 * Planex Communications, Inc. vendor ID 1010 */ 1011#define PLANEX_VENDORID 0x14ea 1012 1013/* 1014 * Planex FNW-3603-TX device ID 1015 */ 1016#define PLANEX_DEVICEID_FNW3603TX 0xab06 1017 1018/* 1019 * Planex FNW-3800-TX device ID 1020 */ 1021#define PLANEX_DEVICEID_FNW3800TX 0xab07 1022 1023/* 1024 * LevelOne vendor ID 1025 */ 1026#define LEVEL1_VENDORID 0x018A 1027 1028/* 1029 * LevelOne FPC-0106TX devide ID 1030 */ 1031#define LEVEL1_DEVICEID_FPC0106TX 0x0106 1032 1033/* 1034 * Compaq vendor ID 1035 */ 1036#define CP_VENDORID 0x021B 1037 1038/* 1039 * Edimax vendor ID 1040 */ 1041#define EDIMAX_VENDORID 0x13D1 1042 1043/* 1044 * Edimax EP-4103DL cardbus device ID 1045 */ 1046#define EDIMAX_DEVICEID_EP4103DL 0xAB06 1047 1048/* US Robotics vendor ID */ 1049 1050#define USR_VENDORID 0x16EC 1051 1052/* US Robotics 997902 device ID */ 1053 1054#define USR_DEVICEID_997902 0x0116 1055 1056/* 1057 * PCI low memory base and low I/O base register, and 1058 * other PCI registers. 1059 */ 1060 1061#define RL_PCI_VENDOR_ID 0x00 1062#define RL_PCI_DEVICE_ID 0x02 1063#define RL_PCI_COMMAND 0x04 1064#define RL_PCI_STATUS 0x06 1065#define RL_PCI_CLASSCODE 0x09 1066#define RL_PCI_LATENCY_TIMER 0x0D 1067#define RL_PCI_HEADER_TYPE 0x0E 1068#define RL_PCI_LOIO 0x10 1069#define RL_PCI_LOMEM 0x14 1070#define RL_PCI_BIOSROM 0x30 1071#define RL_PCI_INTLINE 0x3C 1072#define RL_PCI_INTPIN 0x3D 1073#define RL_PCI_MINGNT 0x3E 1074#define RL_PCI_MINLAT 0x0F 1075#define RL_PCI_RESETOPT 0x48 1076#define RL_PCI_EEPROM_DATA 0x4C 1077 1078#define RL_PCI_CAPID 0x50 /* 8 bits */ 1079#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 1080#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 1081#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 1082 1083#define RL_PSTATE_MASK 0x0003 1084#define RL_PSTATE_D0 0x0000 1085#define RL_PSTATE_D1 0x0002 1086#define RL_PSTATE_D2 0x0002 1087#define RL_PSTATE_D3 0x0003 1088#define RL_PME_EN 0x0010 1089#define RL_PME_STATUS 0x8000 1090