if_rlreg.h revision 176756
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_rlreg.h 176756 2008-03-03 03:41:06Z yongari $ 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 41#define RL_IDR3 0x0003 42#define RL_IDR4 0x0004 43#define RL_IDR5 0x0005 44 /* 0006-0007 reserved */ 45#define RL_MAR0 0x0008 /* Multicast hash table */ 46#define RL_MAR1 0x0009 47#define RL_MAR2 0x000A 48#define RL_MAR3 0x000B 49#define RL_MAR4 0x000C 50#define RL_MAR5 0x000D 51#define RL_MAR6 0x000E 52#define RL_MAR7 0x000F 53 54#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 58 59#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 63 64#define RL_RXADDR 0x0030 /* RX ring start address */ 65#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67#define RL_COMMAND 0x0037 /* command register */ 68#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70#define RL_IMR 0x003C /* interrupt mask register */ 71#define RL_ISR 0x003E /* interrupt status register */ 72#define RL_TXCFG 0x0040 /* transmit config */ 73#define RL_RXCFG 0x0044 /* receive config */ 74#define RL_TIMERCNT 0x0048 /* timer count register */ 75#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76#define RL_EECMD 0x0050 /* EEPROM command register */ 77#define RL_CFG0 0x0051 /* config register #0 */ 78#define RL_CFG1 0x0052 /* config register #1 */ 79#define RL_CFG2 0x0053 /* config register #2 */ 80#define RL_CFG3 0x0054 /* config register #3 */ 81#define RL_CFG4 0x0055 /* config register #4 */ 82#define RL_CFG5 0x0056 /* config register #5 */ 83 /* 0057 reserved */ 84#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 85 /* 0059-005A reserved */ 86#define RL_MII 0x005A /* 8129 chip only */ 87#define RL_HALTCLK 0x005B 88#define RL_MULTIINTR 0x005C /* multiple interrupt */ 89#define RL_PCIREV 0x005E /* PCI revision value */ 90 /* 005F reserved */ 91#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 92 93/* Direct PHY access registers only available on 8139 */ 94#define RL_BMCR 0x0062 /* PHY basic mode control */ 95#define RL_BMSR 0x0064 /* PHY basic mode status */ 96#define RL_ANAR 0x0066 /* PHY autoneg advert */ 97#define RL_LPAR 0x0068 /* PHY link partner ability */ 98#define RL_ANER 0x006A /* PHY autoneg expansion */ 99 100#define RL_DISCCNT 0x006C /* disconnect counter */ 101#define RL_FALSECAR 0x006E /* false carrier counter */ 102#define RL_NWAYTST 0x0070 /* NWAY test register */ 103#define RL_RX_ER 0x0072 /* RX_ER counter */ 104#define RL_CSCFG 0x0074 /* CS configuration register */ 105 106/* 107 * When operating in special C+ mode, some of the registers in an 108 * 8139C+ chip have different definitions. These are also used for 109 * the 8169 gigE chip. 110 */ 111#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 112#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 113#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 114#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 115#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 116#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 117#define RL_CFG2 0x0053 118#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 119#define RL_TXSTART 0x00D9 /* 8 bits */ 120#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 121#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 122#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 123#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 124 125/* 126 * Registers specific to the 8169 gigE chip 127 */ 128#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 129#define RL_PHYAR 0x0060 130#define RL_TBICSR 0x0064 131#define RL_TBI_ANAR 0x0068 132#define RL_TBI_LPAR 0x006A 133#define RL_GMEDIASTAT 0x006C /* 8 bits */ 134#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 135#define RL_GTXSTART 0x0038 /* 8 bits */ 136 137/* 138 * TX config register bits 139 */ 140#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 141#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 142#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 143#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 144#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 145#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 146#define RL_TXCFG_HWREV 0x7CC00000 147 148#define RL_LOOPTEST_OFF 0x00000000 149#define RL_LOOPTEST_ON 0x00020000 150#define RL_LOOPTEST_ON_CPLUS 0x00060000 151 152/* Known revision codes. */ 153 154#define RL_HWREV_8169 0x00000000 155#define RL_HWREV_8110S 0x00800000 156#define RL_HWREV_8169S 0x04000000 157#define RL_HWREV_8169_8110SB 0x10000000 158#define RL_HWREV_8169_8110SC 0x18000000 159#define RL_HWREV_8168_SPIN1 0x30000000 160#define RL_HWREV_8100E 0x30800000 161#define RL_HWREV_8101E 0x34000000 162#define RL_HWREV_8168_SPIN2 0x38000000 163#define RL_HWREV_8168_SPIN3 0x38400000 164#define RL_HWREV_8139 0x60000000 165#define RL_HWREV_8139A 0x70000000 166#define RL_HWREV_8139AG 0x70800000 167#define RL_HWREV_8139B 0x78000000 168#define RL_HWREV_8130 0x7C000000 169#define RL_HWREV_8139C 0x74000000 170#define RL_HWREV_8139D 0x74400000 171#define RL_HWREV_8139CPLUS 0x74800000 172#define RL_HWREV_8101 0x74c00000 173#define RL_HWREV_8100 0x78800000 174 175#define RL_TXDMA_16BYTES 0x00000000 176#define RL_TXDMA_32BYTES 0x00000100 177#define RL_TXDMA_64BYTES 0x00000200 178#define RL_TXDMA_128BYTES 0x00000300 179#define RL_TXDMA_256BYTES 0x00000400 180#define RL_TXDMA_512BYTES 0x00000500 181#define RL_TXDMA_1024BYTES 0x00000600 182#define RL_TXDMA_2048BYTES 0x00000700 183 184/* 185 * Transmit descriptor status register bits. 186 */ 187#define RL_TXSTAT_LENMASK 0x00001FFF 188#define RL_TXSTAT_OWN 0x00002000 189#define RL_TXSTAT_TX_UNDERRUN 0x00004000 190#define RL_TXSTAT_TX_OK 0x00008000 191#define RL_TXSTAT_EARLY_THRESH 0x003F0000 192#define RL_TXSTAT_COLLCNT 0x0F000000 193#define RL_TXSTAT_CARR_HBEAT 0x10000000 194#define RL_TXSTAT_OUTOFWIN 0x20000000 195#define RL_TXSTAT_TXABRT 0x40000000 196#define RL_TXSTAT_CARRLOSS 0x80000000 197 198/* 199 * Interrupt status register bits. 200 */ 201#define RL_ISR_RX_OK 0x0001 202#define RL_ISR_RX_ERR 0x0002 203#define RL_ISR_TX_OK 0x0004 204#define RL_ISR_TX_ERR 0x0008 205#define RL_ISR_RX_OVERRUN 0x0010 206#define RL_ISR_PKT_UNDERRUN 0x0020 207#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 208#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 209#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 210#define RL_ISR_SWI 0x0100 /* C+ only */ 211#define RL_ISR_CABLE_LEN_CHGD 0x2000 212#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 213#define RL_ISR_TIMEOUT_EXPIRED 0x4000 214#define RL_ISR_SYSTEM_ERR 0x8000 215 216#define RL_INTRS \ 217 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 218 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 219 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 220 221#ifdef RE_TX_MODERATION 222#define RL_INTRS_CPLUS \ 223 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 224 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 225 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 226#else 227#define RL_INTRS_CPLUS \ 228 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 229 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 230 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 231#endif 232 233/* 234 * Media status register. (8139 only) 235 */ 236#define RL_MEDIASTAT_RXPAUSE 0x01 237#define RL_MEDIASTAT_TXPAUSE 0x02 238#define RL_MEDIASTAT_LINK 0x04 239#define RL_MEDIASTAT_SPEED10 0x08 240#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 241#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 242 243/* 244 * Receive config register. 245 */ 246#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 247#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 248#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 249#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 250#define RL_RXCFG_RX_RUNT 0x00000010 251#define RL_RXCFG_RX_ERRPKT 0x00000020 252#define RL_RXCFG_WRAP 0x00000080 253#define RL_RXCFG_MAXDMA 0x00000700 254#define RL_RXCFG_BUFSZ 0x00001800 255#define RL_RXCFG_FIFOTHRESH 0x0000E000 256#define RL_RXCFG_EARLYTHRESH 0x07000000 257 258#define RL_RXDMA_16BYTES 0x00000000 259#define RL_RXDMA_32BYTES 0x00000100 260#define RL_RXDMA_64BYTES 0x00000200 261#define RL_RXDMA_128BYTES 0x00000300 262#define RL_RXDMA_256BYTES 0x00000400 263#define RL_RXDMA_512BYTES 0x00000500 264#define RL_RXDMA_1024BYTES 0x00000600 265#define RL_RXDMA_UNLIMITED 0x00000700 266 267#define RL_RXBUF_8 0x00000000 268#define RL_RXBUF_16 0x00000800 269#define RL_RXBUF_32 0x00001000 270#define RL_RXBUF_64 0x00001800 271 272#define RL_RXFIFO_16BYTES 0x00000000 273#define RL_RXFIFO_32BYTES 0x00002000 274#define RL_RXFIFO_64BYTES 0x00004000 275#define RL_RXFIFO_128BYTES 0x00006000 276#define RL_RXFIFO_256BYTES 0x00008000 277#define RL_RXFIFO_512BYTES 0x0000A000 278#define RL_RXFIFO_1024BYTES 0x0000C000 279#define RL_RXFIFO_NOTHRESH 0x0000E000 280 281/* 282 * Bits in RX status header (included with RX'ed packet 283 * in ring buffer). 284 */ 285#define RL_RXSTAT_RXOK 0x00000001 286#define RL_RXSTAT_ALIGNERR 0x00000002 287#define RL_RXSTAT_CRCERR 0x00000004 288#define RL_RXSTAT_GIANT 0x00000008 289#define RL_RXSTAT_RUNT 0x00000010 290#define RL_RXSTAT_BADSYM 0x00000020 291#define RL_RXSTAT_BROAD 0x00002000 292#define RL_RXSTAT_INDIV 0x00004000 293#define RL_RXSTAT_MULTI 0x00008000 294#define RL_RXSTAT_LENMASK 0xFFFF0000 295 296#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 297/* 298 * Command register. 299 */ 300#define RL_CMD_EMPTY_RXBUF 0x0001 301#define RL_CMD_TX_ENB 0x0004 302#define RL_CMD_RX_ENB 0x0008 303#define RL_CMD_RESET 0x0010 304 305/* 306 * EEPROM control register 307 */ 308#define RL_EE_DATAOUT 0x01 /* Data out */ 309#define RL_EE_DATAIN 0x02 /* Data in */ 310#define RL_EE_CLK 0x04 /* clock */ 311#define RL_EE_SEL 0x08 /* chip select */ 312#define RL_EE_MODE (0x40|0x80) 313 314#define RL_EEMODE_OFF 0x00 315#define RL_EEMODE_AUTOLOAD 0x40 316#define RL_EEMODE_PROGRAM 0x80 317#define RL_EEMODE_WRITECFG (0x80|0x40) 318 319/* 9346 EEPROM commands */ 320#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 321#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 322 323#define RL_9346_WRITE 0x5 324#define RL_9346_READ 0x6 325#define RL_9346_ERASE 0x7 326#define RL_9346_EWEN 0x4 327#define RL_9346_EWEN_ADDR 0x30 328#define RL_9456_EWDS 0x4 329#define RL_9346_EWDS_ADDR 0x00 330 331#define RL_EECMD_WRITE 0x140 332#define RL_EECMD_READ_6BIT 0x180 333#define RL_EECMD_READ_8BIT 0x600 334#define RL_EECMD_ERASE 0x1c0 335 336#define RL_EE_ID 0x00 337#define RL_EE_PCI_VID 0x01 338#define RL_EE_PCI_DID 0x02 339/* Location of station address inside EEPROM */ 340#define RL_EE_EADDR 0x07 341 342/* 343 * MII register (8129 only) 344 */ 345#define RL_MII_CLK 0x01 346#define RL_MII_DATAIN 0x02 347#define RL_MII_DATAOUT 0x04 348#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 349 350/* 351 * Config 0 register 352 */ 353#define RL_CFG0_ROM0 0x01 354#define RL_CFG0_ROM1 0x02 355#define RL_CFG0_ROM2 0x04 356#define RL_CFG0_PL0 0x08 357#define RL_CFG0_PL1 0x10 358#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 359#define RL_CFG0_PCS 0x40 360#define RL_CFG0_SCR 0x80 361 362/* 363 * Config 1 register 364 */ 365#define RL_CFG1_PWRDWN 0x01 366#define RL_CFG1_PME 0x01 367#define RL_CFG1_SLEEP 0x02 368#define RL_CFG1_VPDEN 0x02 369#define RL_CFG1_IOMAP 0x04 370#define RL_CFG1_MEMMAP 0x08 371#define RL_CFG1_RSVD 0x10 372#define RL_CFG1_LWACT 0x10 373#define RL_CFG1_DRVLOAD 0x20 374#define RL_CFG1_LED0 0x40 375#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 376#define RL_CFG1_LED1 0x80 377 378/* 379 * Config 2 register 380 */ 381#define RL_CFG2_PCI33MHZ 0x00 382#define RL_CFG2_PCI66MHZ 0x01 383#define RL_CFG2_PCI64BIT 0x08 384#define RL_CFG2_AUXPWR 0x10 385 386/* 387 * Config 3 register 388 */ 389#define RL_CFG3_GRANTSEL 0x80 390#define RL_CFG3_WOL_MAGIC 0x20 391#define RL_CFG3_WOL_LINK 0x10 392#define RL_CFG3_FAST_B2B 0x01 393 394/* 395 * Config 4 register 396 */ 397#define RL_CFG4_LWPTN 0x04 398#define RL_CFG4_LWPME 0x10 399 400/* 401 * Config 5 register 402 */ 403#define RL_CFG5_WOL_BCAST 0x40 404#define RL_CFG5_WOL_MCAST 0x20 405#define RL_CFG5_WOL_UCAST 0x10 406#define RL_CFG5_WOL_LANWAKE 0x02 407#define RL_CFG5_PME_STS 0x01 408 409/* 410 * 8139C+ register definitions 411 */ 412 413/* RL_DUMPSTATS_LO register */ 414 415#define RL_DUMPSTATS_START 0x00000008 416 417/* Transmit start register */ 418 419#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 420#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 421#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 422 423/* 424 * Config 2 register, 8139C+/8169/8169S/8110S only 425 */ 426#define RL_CFG2_BUSFREQ 0x07 427#define RL_CFG2_BUSWIDTH 0x08 428#define RL_CFG2_AUXPWRSTS 0x10 429 430#define RL_BUSFREQ_33MHZ 0x00 431#define RL_BUSFREQ_66MHZ 0x01 432 433#define RL_BUSWIDTH_32BITS 0x00 434#define RL_BUSWIDTH_64BITS 0x08 435 436/* C+ mode command register */ 437 438#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 439#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 440#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 441#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 442#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 443#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 444 445/* C+ early transmit threshold */ 446 447#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 448 449/* 450 * Gigabit PHY access register (8169 only) 451 */ 452 453#define RL_PHYAR_PHYDATA 0x0000FFFF 454#define RL_PHYAR_PHYREG 0x001F0000 455#define RL_PHYAR_BUSY 0x80000000 456 457/* 458 * Gigabit media status (8169 only) 459 */ 460#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 461#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 462#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 463#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 464#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 465#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 466#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 467#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 468 469/* 470 * The RealTek doesn't use a fragment-based descriptor mechanism. 471 * Instead, there are only four register sets, each or which represents 472 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 473 * packet buffer (32-bit aligned!) and we place the buffer addresses in 474 * the registers so the chip knows where they are. 475 * 476 * We can sort of kludge together the same kind of buffer management 477 * used in previous drivers, but we have to do buffer copies almost all 478 * the time, so it doesn't really buy us much. 479 * 480 * For reception, there's just one large buffer where the chip stores 481 * all received packets. 482 */ 483 484#define RL_RX_BUF_SZ RL_RXBUF_64 485#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 486#define RL_TX_LIST_CNT 4 487#define RL_MIN_FRAMELEN 60 488#define RL_TXTHRESH(x) ((x) << 11) 489#define RL_TX_THRESH_INIT 96 490#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 491#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 492#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 493 494#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 495#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 496 497#define RL_ETHER_ALIGN 2 498 499struct rl_chain_data { 500 uint16_t cur_rx; 501 uint8_t *rl_rx_buf; 502 uint8_t *rl_rx_buf_ptr; 503 bus_dmamap_t rl_rx_dmamap; 504 505 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 506 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 507 uint8_t last_tx; 508 uint8_t cur_tx; 509}; 510 511#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 512#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 513#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 514#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 515#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 516#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 517#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 518#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 519#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 520 521struct rl_type { 522 uint16_t rl_vid; 523 uint16_t rl_did; 524 int rl_basetype; 525 char *rl_name; 526}; 527 528struct rl_hwrev { 529 uint32_t rl_rev; 530 int rl_type; 531 char *rl_desc; 532}; 533 534struct rl_mii_frame { 535 uint8_t mii_stdelim; 536 uint8_t mii_opcode; 537 uint8_t mii_phyaddr; 538 uint8_t mii_regaddr; 539 uint8_t mii_turnaround; 540 uint16_t mii_data; 541}; 542 543/* 544 * MII constants 545 */ 546#define RL_MII_STARTDELIM 0x01 547#define RL_MII_READOP 0x02 548#define RL_MII_WRITEOP 0x01 549#define RL_MII_TURNAROUND 0x02 550 551#define RL_8129 1 552#define RL_8139 2 553#define RL_8139CPLUS 3 554#define RL_8169 4 555 556#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 557 (x)->rl_type == RL_8169) 558 559/* 560 * The 8139C+ and 8160 gigE chips support descriptor-based TX 561 * and RX. In fact, they even support TCP large send. Descriptors 562 * must be allocated in contiguous blocks that are aligned on a 563 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 564 */ 565 566/* 567 * RX/TX descriptor definition. When large send mode is enabled, the 568 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 569 * the checksum offload bits are disabled. The structure layout is 570 * the same for RX and TX descriptors 571 */ 572 573struct rl_desc { 574 uint32_t rl_cmdstat; 575 uint32_t rl_vlanctl; 576 uint32_t rl_bufaddr_lo; 577 uint32_t rl_bufaddr_hi; 578}; 579 580#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 581#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 582#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 583#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 584#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 585#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 586#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 587#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 588#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 589#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 590#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 591 592#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 593#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 594 595/* 596 * Error bits are valid only on the last descriptor of a frame 597 * (i.e. RL_TDESC_CMD_EOF == 1) 598 */ 599 600#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 601#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 602#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 603#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 604#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 605#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 606#define RL_TDESC_STAT_OWN 0x80000000 607 608/* 609 * RX descriptor cmd/vlan definitions 610 */ 611 612#define RL_RDESC_CMD_EOR 0x40000000 613#define RL_RDESC_CMD_OWN 0x80000000 614#define RL_RDESC_CMD_BUFLEN 0x00001FFF 615 616#define RL_RDESC_STAT_OWN 0x80000000 617#define RL_RDESC_STAT_EOR 0x40000000 618#define RL_RDESC_STAT_SOF 0x20000000 619#define RL_RDESC_STAT_EOF 0x10000000 620#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 621#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 622#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 623#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 624#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 625#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 626#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 627#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 628#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 629#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 630#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 631#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 632#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 633#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 634#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 635#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 636#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 637 RL_RDESC_STAT_CRCERR) 638 639#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 640 (rl_vlandata valid)*/ 641#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 642 643#define RL_PROTOID_NONIP 0x00000000 644#define RL_PROTOID_TCPIP 0x00010000 645#define RL_PROTOID_UDPIP 0x00020000 646#define RL_PROTOID_IP 0x00030000 647#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 648 RL_PROTOID_TCPIP) 649#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 650 RL_PROTOID_UDPIP) 651 652/* 653 * Statistics counter structure (8139C+ and 8169 only) 654 */ 655struct rl_stats { 656 uint32_t rl_tx_pkts_lo; 657 uint32_t rl_tx_pkts_hi; 658 uint32_t rl_tx_errs_lo; 659 uint32_t rl_tx_errs_hi; 660 uint32_t rl_tx_errs; 661 uint16_t rl_missed_pkts; 662 uint16_t rl_rx_framealign_errs; 663 uint32_t rl_tx_onecoll; 664 uint32_t rl_tx_multicolls; 665 uint32_t rl_rx_ucasts_hi; 666 uint32_t rl_rx_ucasts_lo; 667 uint32_t rl_rx_bcasts_lo; 668 uint32_t rl_rx_bcasts_hi; 669 uint32_t rl_rx_mcasts; 670 uint16_t rl_tx_aborts; 671 uint16_t rl_rx_underruns; 672}; 673 674/* 675 * Rx/Tx descriptor parameters (8139C+ and 8169 only) 676 * 677 * 8139C+ 678 * Number of descriptors supported : up to 64 679 * Descriptor alignment : 256 bytes 680 * Tx buffer : At least 4 bytes in length. 681 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 682 * 683 * 8169 684 * Number of descriptors supported : up to 1024 685 * Descriptor alignment : 256 bytes 686 * Tx buffer : At least 4 bytes in length. 687 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 688 */ 689#ifndef __NO_STRICT_ALIGNMENT 690#define RE_FIXUP_RX 1 691#endif 692 693#define RL_8169_TX_DESC_CNT 256 694#define RL_8169_RX_DESC_CNT 256 695#define RL_8139_TX_DESC_CNT 64 696#define RL_8139_RX_DESC_CNT 64 697#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT 698#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT 699#define RL_NTXSEGS 32 700 701#define RL_RING_ALIGN 256 702#define RL_IFQ_MAXLEN 512 703#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 704#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 705#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1)) 706#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 707#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 708#define RL_PKTSZ(x) ((x)/* >> 3*/) 709#ifdef RE_FIXUP_RX 710#define RE_ETHER_ALIGN sizeof(uint64_t) 711#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 712#else 713#define RE_ETHER_ALIGN 0 714#define RE_RX_DESC_BUFLEN MCLBYTES 715#endif 716 717#define RL_MSI_MESSAGES 2 718 719#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 720#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 721 722/* see comment in dev/re/if_re.c */ 723#define RL_JUMBO_FRAMELEN 7440 724#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 725#define RL_MAX_FRAMELEN \ 726 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 727 728struct rl_txdesc { 729 struct mbuf *tx_m; 730 bus_dmamap_t tx_dmamap; 731}; 732 733struct rl_rxdesc { 734 struct mbuf *rx_m; 735 bus_dmamap_t rx_dmamap; 736 bus_size_t rx_size; 737}; 738 739struct rl_list_data { 740 struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; 741 struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; 742 int rl_tx_desc_cnt; 743 int rl_rx_desc_cnt; 744 int rl_tx_prodidx; 745 int rl_rx_prodidx; 746 int rl_tx_considx; 747 int rl_tx_free; 748 bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ 749 bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ 750 bus_dmamap_t rl_rx_sparemap; 751 bus_dma_tag_t rl_stag; /* stats mapping tag */ 752 bus_dmamap_t rl_smap; /* stats map */ 753 struct rl_stats *rl_stats; 754 bus_addr_t rl_stats_addr; 755 bus_dma_tag_t rl_rx_list_tag; 756 bus_dmamap_t rl_rx_list_map; 757 struct rl_desc *rl_rx_list; 758 bus_addr_t rl_rx_list_addr; 759 bus_dma_tag_t rl_tx_list_tag; 760 bus_dmamap_t rl_tx_list_map; 761 struct rl_desc *rl_tx_list; 762 bus_addr_t rl_tx_list_addr; 763}; 764 765struct rl_softc { 766 struct ifnet *rl_ifp; /* interface info */ 767 bus_space_handle_t rl_bhandle; /* bus space handle */ 768 bus_space_tag_t rl_btag; /* bus space tag */ 769 device_t rl_dev; 770 struct resource *rl_res; 771 struct resource *rl_irq[RL_MSI_MESSAGES]; 772 void *rl_intrhand[RL_MSI_MESSAGES]; 773 device_t rl_miibus; 774 bus_dma_tag_t rl_parent_tag; 775 bus_dma_tag_t rl_tag; 776 uint8_t rl_type; 777 int rl_eecmd_read; 778 int rl_eewidth; 779 uint8_t rl_stats_no_timeout; 780 int rl_txthresh; 781 struct rl_chain_data rl_cdata; 782 struct rl_list_data rl_ldata; 783 struct callout rl_stat_callout; 784 int rl_watchdog_timer; 785 struct mtx rl_mtx; 786 struct mbuf *rl_head; 787 struct mbuf *rl_tail; 788 uint32_t rl_hwrev; 789 uint32_t rl_rxlenmask; 790 int rl_testmode; 791 int rl_if_flags; 792 int suspended; /* 0 = normal 1 = suspended */ 793#ifdef DEVICE_POLLING 794 int rxcycles; 795#endif 796 797 struct task rl_txtask; 798 struct task rl_inttask; 799 800 int rl_txstart; 801 int rl_link; 802 int rl_msi; 803}; 804 805#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 806#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 807#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 808 809/* 810 * register space access macros 811 */ 812#define CSR_WRITE_STREAM_4(sc, reg, val) \ 813 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 814#define CSR_WRITE_4(sc, reg, val) \ 815 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 816#define CSR_WRITE_2(sc, reg, val) \ 817 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 818#define CSR_WRITE_1(sc, reg, val) \ 819 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 820 821#define CSR_READ_4(sc, reg) \ 822 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 823#define CSR_READ_2(sc, reg) \ 824 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 825#define CSR_READ_1(sc, reg) \ 826 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 827 828#define CSR_SETBIT_1(sc, offset, val) \ 829 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 830 831#define CSR_CLRBIT_1(sc, offset, val) \ 832 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 833 834#define CSR_SETBIT_2(sc, offset, val) \ 835 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 836 837#define CSR_CLRBIT_2(sc, offset, val) \ 838 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 839 840#define CSR_SETBIT_4(sc, offset, val) \ 841 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 842 843#define CSR_CLRBIT_4(sc, offset, val) \ 844 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 845 846#define RL_TIMEOUT 1000 847 848/* 849 * General constants that are fun to know. 850 * 851 * RealTek PCI vendor ID 852 */ 853#define RT_VENDORID 0x10EC 854 855/* 856 * RealTek chip device IDs. 857 */ 858#define RT_DEVICEID_8129 0x8129 859#define RT_DEVICEID_8101E 0x8136 860#define RT_DEVICEID_8138 0x8138 861#define RT_DEVICEID_8139 0x8139 862#define RT_DEVICEID_8169SC 0x8167 863#define RT_DEVICEID_8168 0x8168 864#define RT_DEVICEID_8169 0x8169 865#define RT_DEVICEID_8100 0x8100 866 867#define RT_REVID_8139CPLUS 0x20 868 869/* 870 * Accton PCI vendor ID 871 */ 872#define ACCTON_VENDORID 0x1113 873 874/* 875 * Accton MPX 5030/5038 device ID. 876 */ 877#define ACCTON_DEVICEID_5030 0x1211 878 879/* 880 * Nortel PCI vendor ID 881 */ 882#define NORTEL_VENDORID 0x126C 883 884/* 885 * Delta Electronics Vendor ID. 886 */ 887#define DELTA_VENDORID 0x1500 888 889/* 890 * Delta device IDs. 891 */ 892#define DELTA_DEVICEID_8139 0x1360 893 894/* 895 * Addtron vendor ID. 896 */ 897#define ADDTRON_VENDORID 0x4033 898 899/* 900 * Addtron device IDs. 901 */ 902#define ADDTRON_DEVICEID_8139 0x1360 903 904/* 905 * D-Link vendor ID. 906 */ 907#define DLINK_VENDORID 0x1186 908 909/* 910 * D-Link DFE-530TX+ device ID 911 */ 912#define DLINK_DEVICEID_530TXPLUS 0x1300 913 914/* 915 * D-Link DFE-5280T device ID 916 */ 917#define DLINK_DEVICEID_528T 0x4300 918 919/* 920 * D-Link DFE-690TXD device ID 921 */ 922#define DLINK_DEVICEID_690TXD 0x1340 923 924/* 925 * Corega K.K vendor ID 926 */ 927#define COREGA_VENDORID 0x1259 928 929/* 930 * Corega FEther CB-TXD device ID 931 */ 932#define COREGA_DEVICEID_FETHERCBTXD 0xa117 933 934/* 935 * Corega FEtherII CB-TXD device ID 936 */ 937#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 938 939/* 940 * Corega CG-LAPCIGT device ID 941 */ 942#define COREGA_DEVICEID_CGLAPCIGT 0xc107 943 944/* 945 * Linksys vendor ID 946 */ 947#define LINKSYS_VENDORID 0x1737 948 949/* 950 * Linksys EG1032 device ID 951 */ 952#define LINKSYS_DEVICEID_EG1032 0x1032 953 954/* 955 * Linksys EG1032 rev 3 sub-device ID 956 */ 957#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 958 959/* 960 * Peppercon vendor ID 961 */ 962#define PEPPERCON_VENDORID 0x1743 963 964/* 965 * Peppercon ROL-F device ID 966 */ 967#define PEPPERCON_DEVICEID_ROLF 0x8139 968 969/* 970 * Planex Communications, Inc. vendor ID 971 */ 972#define PLANEX_VENDORID 0x14ea 973 974/* 975 * Planex FNW-3603-TX device ID 976 */ 977#define PLANEX_DEVICEID_FNW3603TX 0xab06 978 979/* 980 * Planex FNW-3800-TX device ID 981 */ 982#define PLANEX_DEVICEID_FNW3800TX 0xab07 983 984/* 985 * LevelOne vendor ID 986 */ 987#define LEVEL1_VENDORID 0x018A 988 989/* 990 * LevelOne FPC-0106TX devide ID 991 */ 992#define LEVEL1_DEVICEID_FPC0106TX 0x0106 993 994/* 995 * Compaq vendor ID 996 */ 997#define CP_VENDORID 0x021B 998 999/* 1000 * Edimax vendor ID 1001 */ 1002#define EDIMAX_VENDORID 0x13D1 1003 1004/* 1005 * Edimax EP-4103DL cardbus device ID 1006 */ 1007#define EDIMAX_DEVICEID_EP4103DL 0xAB06 1008 1009/* US Robotics vendor ID */ 1010 1011#define USR_VENDORID 0x16EC 1012 1013/* US Robotics 997902 device ID */ 1014 1015#define USR_DEVICEID_997902 0x0116 1016 1017/* 1018 * PCI low memory base and low I/O base register, and 1019 * other PCI registers. 1020 */ 1021 1022#define RL_PCI_VENDOR_ID 0x00 1023#define RL_PCI_DEVICE_ID 0x02 1024#define RL_PCI_COMMAND 0x04 1025#define RL_PCI_STATUS 0x06 1026#define RL_PCI_CLASSCODE 0x09 1027#define RL_PCI_LATENCY_TIMER 0x0D 1028#define RL_PCI_HEADER_TYPE 0x0E 1029#define RL_PCI_LOIO 0x10 1030#define RL_PCI_LOMEM 0x14 1031#define RL_PCI_BIOSROM 0x30 1032#define RL_PCI_INTLINE 0x3C 1033#define RL_PCI_INTPIN 0x3D 1034#define RL_PCI_MINGNT 0x3E 1035#define RL_PCI_MINLAT 0x0F 1036#define RL_PCI_RESETOPT 0x48 1037#define RL_PCI_EEPROM_DATA 0x4C 1038 1039#define RL_PCI_CAPID 0x50 /* 8 bits */ 1040#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 1041#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 1042#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 1043 1044#define RL_PSTATE_MASK 0x0003 1045#define RL_PSTATE_D0 0x0000 1046#define RL_PSTATE_D1 0x0002 1047#define RL_PSTATE_D2 0x0002 1048#define RL_PSTATE_D3 0x0003 1049#define RL_PME_EN 0x0010 1050#define RL_PME_STATUS 0x8000 1051