if_rlreg.h revision 171263
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_rlreg.h 171263 2007-07-06 00:05:12Z yongari $ 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 41#define RL_IDR3 0x0003 42#define RL_IDR4 0x0004 43#define RL_IDR5 0x0005 44 /* 0006-0007 reserved */ 45#define RL_MAR0 0x0008 /* Multicast hash table */ 46#define RL_MAR1 0x0009 47#define RL_MAR2 0x000A 48#define RL_MAR3 0x000B 49#define RL_MAR4 0x000C 50#define RL_MAR5 0x000D 51#define RL_MAR6 0x000E 52#define RL_MAR7 0x000F 53 54#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 58 59#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 63 64#define RL_RXADDR 0x0030 /* RX ring start address */ 65#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67#define RL_COMMAND 0x0037 /* command register */ 68#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70#define RL_IMR 0x003C /* interrupt mask register */ 71#define RL_ISR 0x003E /* interrupt status register */ 72#define RL_TXCFG 0x0040 /* transmit config */ 73#define RL_RXCFG 0x0044 /* receive config */ 74#define RL_TIMERCNT 0x0048 /* timer count register */ 75#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76#define RL_EECMD 0x0050 /* EEPROM command register */ 77#define RL_CFG0 0x0051 /* config register #0 */ 78#define RL_CFG1 0x0052 /* config register #1 */ 79 /* 0053-0057 reserved */ 80#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 81 /* 0059-005A reserved */ 82#define RL_MII 0x005A /* 8129 chip only */ 83#define RL_HALTCLK 0x005B 84#define RL_MULTIINTR 0x005C /* multiple interrupt */ 85#define RL_PCIREV 0x005E /* PCI revision value */ 86 /* 005F reserved */ 87#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 88 89/* Direct PHY access registers only available on 8139 */ 90#define RL_BMCR 0x0062 /* PHY basic mode control */ 91#define RL_BMSR 0x0064 /* PHY basic mode status */ 92#define RL_ANAR 0x0066 /* PHY autoneg advert */ 93#define RL_LPAR 0x0068 /* PHY link partner ability */ 94#define RL_ANER 0x006A /* PHY autoneg expansion */ 95 96#define RL_DISCCNT 0x006C /* disconnect counter */ 97#define RL_FALSECAR 0x006E /* false carrier counter */ 98#define RL_NWAYTST 0x0070 /* NWAY test register */ 99#define RL_RX_ER 0x0072 /* RX_ER counter */ 100#define RL_CSCFG 0x0074 /* CS configuration register */ 101 102/* 103 * When operating in special C+ mode, some of the registers in an 104 * 8139C+ chip have different definitions. These are also used for 105 * the 8169 gigE chip. 106 */ 107#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 108#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 109#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 110#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 111#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 112#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 113#define RL_CFG2 0x0053 114#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 115#define RL_TXSTART 0x00D9 /* 8 bits */ 116#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 117#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 118#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 119#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 120 121/* 122 * Registers specific to the 8169 gigE chip 123 */ 124#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 125#define RL_PHYAR 0x0060 126#define RL_TBICSR 0x0064 127#define RL_TBI_ANAR 0x0068 128#define RL_TBI_LPAR 0x006A 129#define RL_GMEDIASTAT 0x006C /* 8 bits */ 130#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 131#define RL_GTXSTART 0x0038 /* 16 bits */ 132 133/* 134 * TX config register bits 135 */ 136#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 137#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 138#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 139#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 140#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 141#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 142#define RL_TXCFG_HWREV 0x7CC00000 143 144#define RL_LOOPTEST_OFF 0x00000000 145#define RL_LOOPTEST_ON 0x00020000 146#define RL_LOOPTEST_ON_CPLUS 0x00060000 147 148/* Known revision codes. */ 149 150#define RL_HWREV_8169 0x00000000 151#define RL_HWREV_8110S 0x00800000 152#define RL_HWREV_8169S 0x04000000 153#define RL_HWREV_8169_8110SB 0x10000000 154#define RL_HWREV_8169_8110SC 0x18000000 155#define RL_HWREV_8168_SPIN1 0x30000000 156#define RL_HWREV_8100E 0x30800000 157#define RL_HWREV_8101E 0x34000000 158#define RL_HWREV_8168_SPIN2 0x38000000 159#define RL_HWREV_8139 0x60000000 160#define RL_HWREV_8139A 0x70000000 161#define RL_HWREV_8139AG 0x70800000 162#define RL_HWREV_8139B 0x78000000 163#define RL_HWREV_8130 0x7C000000 164#define RL_HWREV_8139C 0x74000000 165#define RL_HWREV_8139D 0x74400000 166#define RL_HWREV_8139CPLUS 0x74800000 167#define RL_HWREV_8101 0x74c00000 168#define RL_HWREV_8100 0x78800000 169 170#define RL_TXDMA_16BYTES 0x00000000 171#define RL_TXDMA_32BYTES 0x00000100 172#define RL_TXDMA_64BYTES 0x00000200 173#define RL_TXDMA_128BYTES 0x00000300 174#define RL_TXDMA_256BYTES 0x00000400 175#define RL_TXDMA_512BYTES 0x00000500 176#define RL_TXDMA_1024BYTES 0x00000600 177#define RL_TXDMA_2048BYTES 0x00000700 178 179/* 180 * Transmit descriptor status register bits. 181 */ 182#define RL_TXSTAT_LENMASK 0x00001FFF 183#define RL_TXSTAT_OWN 0x00002000 184#define RL_TXSTAT_TX_UNDERRUN 0x00004000 185#define RL_TXSTAT_TX_OK 0x00008000 186#define RL_TXSTAT_EARLY_THRESH 0x003F0000 187#define RL_TXSTAT_COLLCNT 0x0F000000 188#define RL_TXSTAT_CARR_HBEAT 0x10000000 189#define RL_TXSTAT_OUTOFWIN 0x20000000 190#define RL_TXSTAT_TXABRT 0x40000000 191#define RL_TXSTAT_CARRLOSS 0x80000000 192 193/* 194 * Interrupt status register bits. 195 */ 196#define RL_ISR_RX_OK 0x0001 197#define RL_ISR_RX_ERR 0x0002 198#define RL_ISR_TX_OK 0x0004 199#define RL_ISR_TX_ERR 0x0008 200#define RL_ISR_RX_OVERRUN 0x0010 201#define RL_ISR_PKT_UNDERRUN 0x0020 202#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 203#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 204#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 205#define RL_ISR_SWI 0x0100 /* C+ only */ 206#define RL_ISR_CABLE_LEN_CHGD 0x2000 207#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 208#define RL_ISR_TIMEOUT_EXPIRED 0x4000 209#define RL_ISR_SYSTEM_ERR 0x8000 210 211#define RL_INTRS \ 212 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 213 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 214 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 215 216#ifdef RE_TX_MODERATION 217#define RL_INTRS_CPLUS \ 218 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 219 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 220 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 221#else 222#define RL_INTRS_CPLUS \ 223 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 224 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 225 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 226#endif 227 228/* 229 * Media status register. (8139 only) 230 */ 231#define RL_MEDIASTAT_RXPAUSE 0x01 232#define RL_MEDIASTAT_TXPAUSE 0x02 233#define RL_MEDIASTAT_LINK 0x04 234#define RL_MEDIASTAT_SPEED10 0x08 235#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 236#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 237 238/* 239 * Receive config register. 240 */ 241#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 242#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 243#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 244#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 245#define RL_RXCFG_RX_RUNT 0x00000010 246#define RL_RXCFG_RX_ERRPKT 0x00000020 247#define RL_RXCFG_WRAP 0x00000080 248#define RL_RXCFG_MAXDMA 0x00000700 249#define RL_RXCFG_BUFSZ 0x00001800 250#define RL_RXCFG_FIFOTHRESH 0x0000E000 251#define RL_RXCFG_EARLYTHRESH 0x07000000 252 253#define RL_RXDMA_16BYTES 0x00000000 254#define RL_RXDMA_32BYTES 0x00000100 255#define RL_RXDMA_64BYTES 0x00000200 256#define RL_RXDMA_128BYTES 0x00000300 257#define RL_RXDMA_256BYTES 0x00000400 258#define RL_RXDMA_512BYTES 0x00000500 259#define RL_RXDMA_1024BYTES 0x00000600 260#define RL_RXDMA_UNLIMITED 0x00000700 261 262#define RL_RXBUF_8 0x00000000 263#define RL_RXBUF_16 0x00000800 264#define RL_RXBUF_32 0x00001000 265#define RL_RXBUF_64 0x00001800 266 267#define RL_RXFIFO_16BYTES 0x00000000 268#define RL_RXFIFO_32BYTES 0x00002000 269#define RL_RXFIFO_64BYTES 0x00004000 270#define RL_RXFIFO_128BYTES 0x00006000 271#define RL_RXFIFO_256BYTES 0x00008000 272#define RL_RXFIFO_512BYTES 0x0000A000 273#define RL_RXFIFO_1024BYTES 0x0000C000 274#define RL_RXFIFO_NOTHRESH 0x0000E000 275 276/* 277 * Bits in RX status header (included with RX'ed packet 278 * in ring buffer). 279 */ 280#define RL_RXSTAT_RXOK 0x00000001 281#define RL_RXSTAT_ALIGNERR 0x00000002 282#define RL_RXSTAT_CRCERR 0x00000004 283#define RL_RXSTAT_GIANT 0x00000008 284#define RL_RXSTAT_RUNT 0x00000010 285#define RL_RXSTAT_BADSYM 0x00000020 286#define RL_RXSTAT_BROAD 0x00002000 287#define RL_RXSTAT_INDIV 0x00004000 288#define RL_RXSTAT_MULTI 0x00008000 289#define RL_RXSTAT_LENMASK 0xFFFF0000 290 291#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 292/* 293 * Command register. 294 */ 295#define RL_CMD_EMPTY_RXBUF 0x0001 296#define RL_CMD_TX_ENB 0x0004 297#define RL_CMD_RX_ENB 0x0008 298#define RL_CMD_RESET 0x0010 299 300/* 301 * EEPROM control register 302 */ 303#define RL_EE_DATAOUT 0x01 /* Data out */ 304#define RL_EE_DATAIN 0x02 /* Data in */ 305#define RL_EE_CLK 0x04 /* clock */ 306#define RL_EE_SEL 0x08 /* chip select */ 307#define RL_EE_MODE (0x40|0x80) 308 309#define RL_EEMODE_OFF 0x00 310#define RL_EEMODE_AUTOLOAD 0x40 311#define RL_EEMODE_PROGRAM 0x80 312#define RL_EEMODE_WRITECFG (0x80|0x40) 313 314/* 9346 EEPROM commands */ 315#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 316#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 317 318#define RL_9346_WRITE 0x5 319#define RL_9346_READ 0x6 320#define RL_9346_ERASE 0x7 321#define RL_9346_EWEN 0x4 322#define RL_9346_EWEN_ADDR 0x30 323#define RL_9456_EWDS 0x4 324#define RL_9346_EWDS_ADDR 0x00 325 326#define RL_EECMD_WRITE 0x140 327#define RL_EECMD_READ_6BIT 0x180 328#define RL_EECMD_READ_8BIT 0x600 329#define RL_EECMD_ERASE 0x1c0 330 331#define RL_EE_ID 0x00 332#define RL_EE_PCI_VID 0x01 333#define RL_EE_PCI_DID 0x02 334/* Location of station address inside EEPROM */ 335#define RL_EE_EADDR 0x07 336 337/* 338 * MII register (8129 only) 339 */ 340#define RL_MII_CLK 0x01 341#define RL_MII_DATAIN 0x02 342#define RL_MII_DATAOUT 0x04 343#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 344 345/* 346 * Config 0 register 347 */ 348#define RL_CFG0_ROM0 0x01 349#define RL_CFG0_ROM1 0x02 350#define RL_CFG0_ROM2 0x04 351#define RL_CFG0_PL0 0x08 352#define RL_CFG0_PL1 0x10 353#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 354#define RL_CFG0_PCS 0x40 355#define RL_CFG0_SCR 0x80 356 357/* 358 * Config 1 register 359 */ 360#define RL_CFG1_PWRDWN 0x01 361#define RL_CFG1_SLEEP 0x02 362#define RL_CFG1_IOMAP 0x04 363#define RL_CFG1_MEMMAP 0x08 364#define RL_CFG1_RSVD 0x10 365#define RL_CFG1_DRVLOAD 0x20 366#define RL_CFG1_LED0 0x40 367#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 368#define RL_CFG1_LED1 0x80 369 370/* 371 * 8139C+ register definitions 372 */ 373 374/* RL_DUMPSTATS_LO register */ 375 376#define RL_DUMPSTATS_START 0x00000008 377 378/* Transmit start register */ 379 380#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 381#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 382#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 383 384/* 385 * Config 2 register, 8139C+/8169/8169S/8110S only 386 */ 387#define RL_CFG2_BUSFREQ 0x07 388#define RL_CFG2_BUSWIDTH 0x08 389#define RL_CFG2_AUXPWRSTS 0x10 390 391#define RL_BUSFREQ_33MHZ 0x00 392#define RL_BUSFREQ_66MHZ 0x01 393 394#define RL_BUSWIDTH_32BITS 0x00 395#define RL_BUSWIDTH_64BITS 0x08 396 397/* C+ mode command register */ 398 399#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 400#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 401#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 402#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 403#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 404#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 405 406/* C+ early transmit threshold */ 407 408#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 409 410/* 411 * Gigabit PHY access register (8169 only) 412 */ 413 414#define RL_PHYAR_PHYDATA 0x0000FFFF 415#define RL_PHYAR_PHYREG 0x001F0000 416#define RL_PHYAR_BUSY 0x80000000 417 418/* 419 * Gigabit media status (8169 only) 420 */ 421#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 422#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 423#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 424#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 425#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 426#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 427#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 428#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 429 430/* 431 * The RealTek doesn't use a fragment-based descriptor mechanism. 432 * Instead, there are only four register sets, each or which represents 433 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 434 * packet buffer (32-bit aligned!) and we place the buffer addresses in 435 * the registers so the chip knows where they are. 436 * 437 * We can sort of kludge together the same kind of buffer management 438 * used in previous drivers, but we have to do buffer copies almost all 439 * the time, so it doesn't really buy us much. 440 * 441 * For reception, there's just one large buffer where the chip stores 442 * all received packets. 443 */ 444 445#define RL_RX_BUF_SZ RL_RXBUF_64 446#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 447#define RL_TX_LIST_CNT 4 448#define RL_MIN_FRAMELEN 60 449#define RL_TXTHRESH(x) ((x) << 11) 450#define RL_TX_THRESH_INIT 96 451#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 452#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 453#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 454 455#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 456#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 457 458#define RL_ETHER_ALIGN 2 459 460struct rl_chain_data { 461 uint16_t cur_rx; 462 uint8_t *rl_rx_buf; 463 uint8_t *rl_rx_buf_ptr; 464 bus_dmamap_t rl_rx_dmamap; 465 466 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 467 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 468 uint8_t last_tx; 469 uint8_t cur_tx; 470}; 471 472#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 473#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 474#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 475#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 476#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 477#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 478#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 479#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 480#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 481 482struct rl_type { 483 uint16_t rl_vid; 484 uint16_t rl_did; 485 int rl_basetype; 486 char *rl_name; 487}; 488 489struct rl_hwrev { 490 uint32_t rl_rev; 491 int rl_type; 492 char *rl_desc; 493}; 494 495struct rl_mii_frame { 496 uint8_t mii_stdelim; 497 uint8_t mii_opcode; 498 uint8_t mii_phyaddr; 499 uint8_t mii_regaddr; 500 uint8_t mii_turnaround; 501 uint16_t mii_data; 502}; 503 504/* 505 * MII constants 506 */ 507#define RL_MII_STARTDELIM 0x01 508#define RL_MII_READOP 0x02 509#define RL_MII_WRITEOP 0x01 510#define RL_MII_TURNAROUND 0x02 511 512#define RL_8129 1 513#define RL_8139 2 514#define RL_8139CPLUS 3 515#define RL_8169 4 516 517#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 518 (x)->rl_type == RL_8169) 519 520/* 521 * The 8139C+ and 8160 gigE chips support descriptor-based TX 522 * and RX. In fact, they even support TCP large send. Descriptors 523 * must be allocated in contiguous blocks that are aligned on a 524 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 525 */ 526 527/* 528 * RX/TX descriptor definition. When large send mode is enabled, the 529 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 530 * the checksum offload bits are disabled. The structure layout is 531 * the same for RX and TX descriptors 532 */ 533 534struct rl_desc { 535 uint32_t rl_cmdstat; 536 uint32_t rl_vlanctl; 537 uint32_t rl_bufaddr_lo; 538 uint32_t rl_bufaddr_hi; 539}; 540 541#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 542#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 543#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 544#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 545#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 546#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 547#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 548#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 549#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 550#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 551#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 552 553#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 554#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 555 556/* 557 * Error bits are valid only on the last descriptor of a frame 558 * (i.e. RL_TDESC_CMD_EOF == 1) 559 */ 560 561#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 562#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 563#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 564#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 565#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 566#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 567#define RL_TDESC_STAT_OWN 0x80000000 568 569/* 570 * RX descriptor cmd/vlan definitions 571 */ 572 573#define RL_RDESC_CMD_EOR 0x40000000 574#define RL_RDESC_CMD_OWN 0x80000000 575#define RL_RDESC_CMD_BUFLEN 0x00001FFF 576 577#define RL_RDESC_STAT_OWN 0x80000000 578#define RL_RDESC_STAT_EOR 0x40000000 579#define RL_RDESC_STAT_SOF 0x20000000 580#define RL_RDESC_STAT_EOF 0x10000000 581#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 582#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 583#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 584#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 585#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 586#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 587#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 588#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 589#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 590#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 591#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 592#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 593#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 594#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 595#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 596#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 597#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 598 RL_RDESC_STAT_CRCERR) 599 600#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 601 (rl_vlandata valid)*/ 602#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 603 604#define RL_PROTOID_NONIP 0x00000000 605#define RL_PROTOID_TCPIP 0x00010000 606#define RL_PROTOID_UDPIP 0x00020000 607#define RL_PROTOID_IP 0x00030000 608#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 609 RL_PROTOID_TCPIP) 610#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 611 RL_PROTOID_UDPIP) 612 613/* 614 * Statistics counter structure (8139C+ and 8169 only) 615 */ 616struct rl_stats { 617 uint32_t rl_tx_pkts_lo; 618 uint32_t rl_tx_pkts_hi; 619 uint32_t rl_tx_errs_lo; 620 uint32_t rl_tx_errs_hi; 621 uint32_t rl_tx_errs; 622 uint16_t rl_missed_pkts; 623 uint16_t rl_rx_framealign_errs; 624 uint32_t rl_tx_onecoll; 625 uint32_t rl_tx_multicolls; 626 uint32_t rl_rx_ucasts_hi; 627 uint32_t rl_rx_ucasts_lo; 628 uint32_t rl_rx_bcasts_lo; 629 uint32_t rl_rx_bcasts_hi; 630 uint32_t rl_rx_mcasts; 631 uint16_t rl_tx_aborts; 632 uint16_t rl_rx_underruns; 633}; 634 635/* 636 * Rx/Tx descriptor parameters (8139C+ and 8169 only) 637 * 638 * Tx/Rx count must be equal. Shared code like re_dma_map_desc assumes this. 639 * Buffers must be a multiple of 8 bytes. Currently limit to 64 descriptors 640 * due to the 8139C+. We need to put the number of descriptors in the ring 641 * structure and use that value instead. 642 */ 643#ifndef __NO_STRICT_ALIGNMENT 644#define RE_FIXUP_RX 1 645#endif 646 647#define RL_TX_DESC_CNT 64 648#define RL_TX_DESC_THLD 4 649#define RL_RX_DESC_CNT RL_TX_DESC_CNT 650 651#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) 652#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc)) 653#define RL_RING_ALIGN 256 654#define RL_IFQ_MAXLEN 512 655#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT) 656#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 657#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 658#define RL_PKTSZ(x) ((x)/* >> 3*/) 659#ifdef RE_FIXUP_RX 660#define RE_ETHER_ALIGN sizeof(uint64_t) 661#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 662#else 663#define RE_ETHER_ALIGN 0 664#define RE_RX_DESC_BUFLEN MCLBYTES 665#endif 666 667#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 668#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 669 670/* see comment in dev/re/if_re.c */ 671#define RL_JUMBO_FRAMELEN 7440 672#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 673 674struct rl_softc; 675 676struct rl_dmaload_arg { 677 int rl_idx; 678 int rl_maxsegs; 679 uint32_t rl_flags; 680 struct rl_desc *rl_ring; 681}; 682 683struct rl_list_data { 684 struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT]; 685 struct mbuf *rl_rx_mbuf[RL_RX_DESC_CNT]; 686 int rl_tx_prodidx; 687 int rl_rx_prodidx; 688 int rl_tx_considx; 689 int rl_tx_free; 690 bus_dmamap_t rl_tx_dmamap[RL_TX_DESC_CNT]; 691 bus_dmamap_t rl_rx_dmamap[RL_RX_DESC_CNT]; 692 bus_dma_tag_t rl_mtag; /* mbuf mapping tag */ 693 bus_dma_tag_t rl_stag; /* stats mapping tag */ 694 bus_dmamap_t rl_smap; /* stats map */ 695 struct rl_stats *rl_stats; 696 bus_addr_t rl_stats_addr; 697 bus_dma_tag_t rl_rx_list_tag; 698 bus_dmamap_t rl_rx_list_map; 699 struct rl_desc *rl_rx_list; 700 bus_addr_t rl_rx_list_addr; 701 bus_dma_tag_t rl_tx_list_tag; 702 bus_dmamap_t rl_tx_list_map; 703 struct rl_desc *rl_tx_list; 704 bus_addr_t rl_tx_list_addr; 705}; 706 707struct rl_softc { 708 struct ifnet *rl_ifp; /* interface info */ 709 bus_space_handle_t rl_bhandle; /* bus space handle */ 710 bus_space_tag_t rl_btag; /* bus space tag */ 711 device_t rl_dev; 712 struct resource *rl_res; 713 struct resource *rl_irq; 714 void *rl_intrhand; 715 device_t rl_miibus; 716 bus_dma_tag_t rl_parent_tag; 717 bus_dma_tag_t rl_tag; 718 uint8_t rl_type; 719 int rl_eecmd_read; 720 int rl_eewidth; 721 uint8_t rl_stats_no_timeout; 722 int rl_txthresh; 723 struct rl_chain_data rl_cdata; 724 struct rl_list_data rl_ldata; 725 struct callout rl_stat_callout; 726 int rl_watchdog_timer; 727 struct mtx rl_mtx; 728 struct mbuf *rl_head; 729 struct mbuf *rl_tail; 730 uint32_t rl_hwrev; 731 uint32_t rl_rxlenmask; 732 int rl_testmode; 733 int rl_if_flags; 734 int suspended; /* 0 = normal 1 = suspended */ 735#ifdef DEVICE_POLLING 736 int rxcycles; 737#endif 738 739 struct task rl_txtask; 740 struct task rl_inttask; 741 742 struct mtx rl_intlock; 743 int rl_txstart; 744 int rl_link; 745}; 746 747#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 748#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 749#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 750 751/* 752 * register space access macros 753 */ 754#define CSR_WRITE_STREAM_4(sc, reg, val) \ 755 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 756#define CSR_WRITE_4(sc, reg, val) \ 757 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 758#define CSR_WRITE_2(sc, reg, val) \ 759 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 760#define CSR_WRITE_1(sc, reg, val) \ 761 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 762 763#define CSR_READ_4(sc, reg) \ 764 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 765#define CSR_READ_2(sc, reg) \ 766 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 767#define CSR_READ_1(sc, reg) \ 768 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 769 770#define CSR_SETBIT_1(sc, offset, val) \ 771 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 772 773#define CSR_CLRBIT_1(sc, offset, val) \ 774 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 775 776#define CSR_SETBIT_2(sc, offset, val) \ 777 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 778 779#define CSR_CLRBIT_2(sc, offset, val) \ 780 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 781 782#define CSR_SETBIT_4(sc, offset, val) \ 783 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 784 785#define CSR_CLRBIT_4(sc, offset, val) \ 786 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 787 788#define RL_TIMEOUT 1000 789 790/* 791 * General constants that are fun to know. 792 * 793 * RealTek PCI vendor ID 794 */ 795#define RT_VENDORID 0x10EC 796 797/* 798 * RealTek chip device IDs. 799 */ 800#define RT_DEVICEID_8129 0x8129 801#define RT_DEVICEID_8101E 0x8136 802#define RT_DEVICEID_8138 0x8138 803#define RT_DEVICEID_8139 0x8139 804#define RT_DEVICEID_8169SC 0x8167 805#define RT_DEVICEID_8168 0x8168 806#define RT_DEVICEID_8169 0x8169 807#define RT_DEVICEID_8100 0x8100 808 809#define RT_REVID_8139CPLUS 0x20 810 811/* 812 * Accton PCI vendor ID 813 */ 814#define ACCTON_VENDORID 0x1113 815 816/* 817 * Accton MPX 5030/5038 device ID. 818 */ 819#define ACCTON_DEVICEID_5030 0x1211 820 821/* 822 * Nortel PCI vendor ID 823 */ 824#define NORTEL_VENDORID 0x126C 825 826/* 827 * Delta Electronics Vendor ID. 828 */ 829#define DELTA_VENDORID 0x1500 830 831/* 832 * Delta device IDs. 833 */ 834#define DELTA_DEVICEID_8139 0x1360 835 836/* 837 * Addtron vendor ID. 838 */ 839#define ADDTRON_VENDORID 0x4033 840 841/* 842 * Addtron device IDs. 843 */ 844#define ADDTRON_DEVICEID_8139 0x1360 845 846/* 847 * D-Link vendor ID. 848 */ 849#define DLINK_VENDORID 0x1186 850 851/* 852 * D-Link DFE-530TX+ device ID 853 */ 854#define DLINK_DEVICEID_530TXPLUS 0x1300 855 856/* 857 * D-Link DFE-5280T device ID 858 */ 859#define DLINK_DEVICEID_528T 0x4300 860 861/* 862 * D-Link DFE-690TXD device ID 863 */ 864#define DLINK_DEVICEID_690TXD 0x1340 865 866/* 867 * Corega K.K vendor ID 868 */ 869#define COREGA_VENDORID 0x1259 870 871/* 872 * Corega FEther CB-TXD device ID 873 */ 874#define COREGA_DEVICEID_FETHERCBTXD 0xa117 875 876/* 877 * Corega FEtherII CB-TXD device ID 878 */ 879#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 880 881/* 882 * Corega CG-LAPCIGT device ID 883 */ 884#define COREGA_DEVICEID_CGLAPCIGT 0xc107 885 886/* 887 * Linksys vendor ID 888 */ 889#define LINKSYS_VENDORID 0x1737 890 891/* 892 * Linksys EG1032 device ID 893 */ 894#define LINKSYS_DEVICEID_EG1032 0x1032 895 896/* 897 * Linksys EG1032 rev 3 sub-device ID 898 */ 899#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 900 901/* 902 * Peppercon vendor ID 903 */ 904#define PEPPERCON_VENDORID 0x1743 905 906/* 907 * Peppercon ROL-F device ID 908 */ 909#define PEPPERCON_DEVICEID_ROLF 0x8139 910 911/* 912 * Planex Communications, Inc. vendor ID 913 */ 914#define PLANEX_VENDORID 0x14ea 915 916/* 917 * Planex FNW-3800-TX device ID 918 */ 919#define PLANEX_DEVICEID_FNW3800TX 0xab07 920 921/* 922 * LevelOne vendor ID 923 */ 924#define LEVEL1_VENDORID 0x018A 925 926/* 927 * LevelOne FPC-0106TX devide ID 928 */ 929#define LEVEL1_DEVICEID_FPC0106TX 0x0106 930 931/* 932 * Compaq vendor ID 933 */ 934#define CP_VENDORID 0x021B 935 936/* 937 * Edimax vendor ID 938 */ 939#define EDIMAX_VENDORID 0x13D1 940 941/* 942 * Edimax EP-4103DL cardbus device ID 943 */ 944#define EDIMAX_DEVICEID_EP4103DL 0xAB06 945 946/* US Robotics vendor ID */ 947 948#define USR_VENDORID 0x16EC 949 950/* US Robotics 997902 device ID */ 951 952#define USR_DEVICEID_997902 0x0116 953 954/* 955 * PCI low memory base and low I/O base register, and 956 * other PCI registers. 957 */ 958 959#define RL_PCI_VENDOR_ID 0x00 960#define RL_PCI_DEVICE_ID 0x02 961#define RL_PCI_COMMAND 0x04 962#define RL_PCI_STATUS 0x06 963#define RL_PCI_CLASSCODE 0x09 964#define RL_PCI_LATENCY_TIMER 0x0D 965#define RL_PCI_HEADER_TYPE 0x0E 966#define RL_PCI_LOIO 0x10 967#define RL_PCI_LOMEM 0x14 968#define RL_PCI_BIOSROM 0x30 969#define RL_PCI_INTLINE 0x3C 970#define RL_PCI_INTPIN 0x3D 971#define RL_PCI_MINGNT 0x3E 972#define RL_PCI_MINLAT 0x0F 973#define RL_PCI_RESETOPT 0x48 974#define RL_PCI_EEPROM_DATA 0x4C 975 976#define RL_PCI_CAPID 0x50 /* 8 bits */ 977#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 978#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 979#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 980 981#define RL_PSTATE_MASK 0x0003 982#define RL_PSTATE_D0 0x0000 983#define RL_PSTATE_D1 0x0002 984#define RL_PSTATE_D2 0x0002 985#define RL_PSTATE_D3 0x0003 986#define RL_PME_EN 0x0010 987#define RL_PME_STATUS 0x8000 988