if_rlreg.h revision 168828
1250199Sgrehan/*- 2250199Sgrehan * Copyright (c) 1997, 1998-2003 3250199Sgrehan * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4250199Sgrehan * 5250199Sgrehan * Redistribution and use in source and binary forms, with or without 6250199Sgrehan * modification, are permitted provided that the following conditions 7250199Sgrehan * are met: 8250199Sgrehan * 1. Redistributions of source code must retain the above copyright 9250199Sgrehan * notice, this list of conditions and the following disclaimer. 10250199Sgrehan * 2. Redistributions in binary form must reproduce the above copyright 11250199Sgrehan * notice, this list of conditions and the following disclaimer in the 12250199Sgrehan * documentation and/or other materials provided with the distribution. 13250199Sgrehan * 3. All advertising materials mentioning features or use of this software 14250199Sgrehan * must display the following acknowledgement: 15250199Sgrehan * This product includes software developed by Bill Paul. 16250199Sgrehan * 4. Neither the name of the author nor the names of any co-contributors 17250199Sgrehan * may be used to endorse or promote products derived from this software 18250199Sgrehan * without specific prior written permission. 19250199Sgrehan * 20250199Sgrehan * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21250199Sgrehan * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22250199Sgrehan * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23250199Sgrehan * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24250199Sgrehan * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25250199Sgrehan * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26250199Sgrehan * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27250199Sgrehan * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28250199Sgrehan * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29250199Sgrehan * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30250199Sgrehan * THE POSSIBILITY OF SUCH DAMAGE. 31250199Sgrehan * 32250199Sgrehan * $FreeBSD: head/sys/pci/if_rlreg.h 168828 2007-04-18 00:40:43Z yongari $ 33250199Sgrehan */ 34250199Sgrehan 35250199Sgrehan/* 36250199Sgrehan * RealTek 8129/8139 register offsets 37250199Sgrehan */ 38250199Sgrehan#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39250199Sgrehan#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40250199Sgrehan#define RL_IDR2 0x0002 41250199Sgrehan#define RL_IDR3 0x0003 42250199Sgrehan#define RL_IDR4 0x0004 43250199Sgrehan#define RL_IDR5 0x0005 44250199Sgrehan /* 0006-0007 reserved */ 45250199Sgrehan#define RL_MAR0 0x0008 /* Multicast hash table */ 46250199Sgrehan#define RL_MAR1 0x0009 47250199Sgrehan#define RL_MAR2 0x000A 48282212Swhu#define RL_MAR3 0x000B 49282212Swhu#define RL_MAR4 0x000C 50282212Swhu#define RL_MAR5 0x000D 51282212Swhu#define RL_MAR6 0x000E 52282212Swhu#define RL_MAR7 0x000F 53282212Swhu 54282212Swhu#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55282212Swhu#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56282212Swhu#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57282212Swhu#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 58282212Swhu 59282212Swhu#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60282212Swhu#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61282212Swhu#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62282212Swhu#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 63282212Swhu 64282212Swhu#define RL_RXADDR 0x0030 /* RX ring start address */ 65282212Swhu#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66282212Swhu#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67282212Swhu#define RL_COMMAND 0x0037 /* command register */ 68282212Swhu#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69250199Sgrehan#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70282212Swhu#define RL_IMR 0x003C /* interrupt mask register */ 71282212Swhu#define RL_ISR 0x003E /* interrupt status register */ 72282212Swhu#define RL_TXCFG 0x0040 /* transmit config */ 73282212Swhu#define RL_RXCFG 0x0044 /* receive config */ 74282212Swhu#define RL_TIMERCNT 0x0048 /* timer count register */ 75282212Swhu#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76282212Swhu#define RL_EECMD 0x0050 /* EEPROM command register */ 77282212Swhu#define RL_CFG0 0x0051 /* config register #0 */ 78282212Swhu#define RL_CFG1 0x0052 /* config register #1 */ 79282212Swhu /* 0053-0057 reserved */ 80282212Swhu#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 81282212Swhu /* 0059-005A reserved */ 82282212Swhu#define RL_MII 0x005A /* 8129 chip only */ 83282212Swhu#define RL_HALTCLK 0x005B 84282212Swhu#define RL_MULTIINTR 0x005C /* multiple interrupt */ 85282212Swhu#define RL_PCIREV 0x005E /* PCI revision value */ 86282212Swhu /* 005F reserved */ 87282212Swhu#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 88282212Swhu 89282212Swhu/* Direct PHY access registers only available on 8139 */ 90282212Swhu#define RL_BMCR 0x0062 /* PHY basic mode control */ 91282212Swhu#define RL_BMSR 0x0064 /* PHY basic mode status */ 92282212Swhu#define RL_ANAR 0x0066 /* PHY autoneg advert */ 93282212Swhu#define RL_LPAR 0x0068 /* PHY link partner ability */ 94282212Swhu#define RL_ANER 0x006A /* PHY autoneg expansion */ 95282212Swhu 96282212Swhu#define RL_DISCCNT 0x006C /* disconnect counter */ 97282212Swhu#define RL_FALSECAR 0x006E /* false carrier counter */ 98282212Swhu#define RL_NWAYTST 0x0070 /* NWAY test register */ 99282212Swhu#define RL_RX_ER 0x0072 /* RX_ER counter */ 100282212Swhu#define RL_CSCFG 0x0074 /* CS configuration register */ 101282212Swhu 102282212Swhu/* 103282212Swhu * When operating in special C+ mode, some of the registers in an 104282212Swhu * 8139C+ chip have different definitions. These are also used for 105282212Swhu * the 8169 gigE chip. 106282212Swhu */ 107282212Swhu#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 108282212Swhu#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 109282212Swhu#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 110282212Swhu#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 111282212Swhu#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 112282212Swhu#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 113282212Swhu#define RL_CFG2 0x0053 114282212Swhu#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 115282212Swhu#define RL_TXSTART 0x00D9 /* 8 bits */ 116282212Swhu#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 117282212Swhu#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 118282212Swhu#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 119282212Swhu#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 120282212Swhu 121282212Swhu/* 122282212Swhu * Registers specific to the 8169 gigE chip 123282212Swhu */ 124282212Swhu#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 125282212Swhu#define RL_PHYAR 0x0060 126282212Swhu#define RL_TBICSR 0x0064 127282212Swhu#define RL_TBI_ANAR 0x0068 128282212Swhu#define RL_TBI_LPAR 0x006A 129282212Swhu#define RL_GMEDIASTAT 0x006C /* 8 bits */ 130282212Swhu#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 131282212Swhu#define RL_GTXSTART 0x0038 /* 16 bits */ 132282212Swhu 133282212Swhu/* 134282212Swhu * TX config register bits 135282212Swhu */ 136282212Swhu#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 137282212Swhu#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 138282212Swhu#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 139282212Swhu#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 140282212Swhu#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 141282212Swhu#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 142282212Swhu#define RL_TXCFG_HWREV 0x7CC00000 143282212Swhu 144282212Swhu#define RL_LOOPTEST_OFF 0x00000000 145282212Swhu#define RL_LOOPTEST_ON 0x00020000 146282212Swhu#define RL_LOOPTEST_ON_CPLUS 0x00060000 147282212Swhu 148250199Sgrehan/* Known revision codes. */ 149250199Sgrehan 150250199Sgrehan#define RL_HWREV_8169 0x00000000 151250199Sgrehan#define RL_HWREV_8110S 0x00800000 152250199Sgrehan#define RL_HWREV_8169S 0x04000000 153282212Swhu#define RL_HWREV_8169_8110SB 0x10000000 154250199Sgrehan#define RL_HWREV_8169_8110SC 0x18000000 155250199Sgrehan#define RL_HWREV_8168_SPIN1 0x30000000 156250199Sgrehan#define RL_HWREV_8100E 0x30800000 157250199Sgrehan#define RL_HWREV_8101E 0x34000000 158250199Sgrehan#define RL_HWREV_8168_SPIN2 0x38000000 159250199Sgrehan#define RL_HWREV_8139 0x60000000 160250199Sgrehan#define RL_HWREV_8139A 0x70000000 161250199Sgrehan#define RL_HWREV_8139AG 0x70800000 162250199Sgrehan#define RL_HWREV_8139B 0x78000000 163250199Sgrehan#define RL_HWREV_8130 0x7C000000 164250199Sgrehan#define RL_HWREV_8139C 0x74000000 165250199Sgrehan#define RL_HWREV_8139D 0x74400000 166250199Sgrehan#define RL_HWREV_8139CPLUS 0x74800000 167250199Sgrehan#define RL_HWREV_8101 0x74c00000 168250199Sgrehan#define RL_HWREV_8100 0x78800000 169250199Sgrehan 170250199Sgrehan#define RL_TXDMA_16BYTES 0x00000000 171250199Sgrehan#define RL_TXDMA_32BYTES 0x00000100 172250199Sgrehan#define RL_TXDMA_64BYTES 0x00000200 173250199Sgrehan#define RL_TXDMA_128BYTES 0x00000300 174250199Sgrehan#define RL_TXDMA_256BYTES 0x00000400 175250199Sgrehan#define RL_TXDMA_512BYTES 0x00000500 176282212Swhu#define RL_TXDMA_1024BYTES 0x00000600 177250199Sgrehan#define RL_TXDMA_2048BYTES 0x00000700 178250199Sgrehan 179250199Sgrehan/* 180250199Sgrehan * Transmit descriptor status register bits. 181250199Sgrehan */ 182250199Sgrehan#define RL_TXSTAT_LENMASK 0x00001FFF 183250199Sgrehan#define RL_TXSTAT_OWN 0x00002000 184250199Sgrehan#define RL_TXSTAT_TX_UNDERRUN 0x00004000 185250199Sgrehan#define RL_TXSTAT_TX_OK 0x00008000 186250199Sgrehan#define RL_TXSTAT_EARLY_THRESH 0x003F0000 187250199Sgrehan#define RL_TXSTAT_COLLCNT 0x0F000000 188250199Sgrehan#define RL_TXSTAT_CARR_HBEAT 0x10000000 189250199Sgrehan#define RL_TXSTAT_OUTOFWIN 0x20000000 190250199Sgrehan#define RL_TXSTAT_TXABRT 0x40000000 191250199Sgrehan#define RL_TXSTAT_CARRLOSS 0x80000000 192250199Sgrehan 193250199Sgrehan/* 194250199Sgrehan * Interrupt status register bits. 195250199Sgrehan */ 196250199Sgrehan#define RL_ISR_RX_OK 0x0001 197250199Sgrehan#define RL_ISR_RX_ERR 0x0002 198250199Sgrehan#define RL_ISR_TX_OK 0x0004 199250199Sgrehan#define RL_ISR_TX_ERR 0x0008 200250199Sgrehan#define RL_ISR_RX_OVERRUN 0x0010 201250199Sgrehan#define RL_ISR_PKT_UNDERRUN 0x0020 202250199Sgrehan#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 203250199Sgrehan#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 204250199Sgrehan#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 205250199Sgrehan#define RL_ISR_SWI 0x0100 /* C+ only */ 206250199Sgrehan#define RL_ISR_CABLE_LEN_CHGD 0x2000 207250199Sgrehan#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 208250199Sgrehan#define RL_ISR_TIMEOUT_EXPIRED 0x4000 209250199Sgrehan#define RL_ISR_SYSTEM_ERR 0x8000 210250199Sgrehan 211250199Sgrehan#define RL_INTRS \ 212250199Sgrehan (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 213250199Sgrehan RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 214250199Sgrehan RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 215250199Sgrehan 216250199Sgrehan#ifdef RE_TX_MODERATION 217250199Sgrehan#define RL_INTRS_CPLUS \ 218250199Sgrehan (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 219250199Sgrehan RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 220250199Sgrehan RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 221250199Sgrehan#else 222250199Sgrehan#define RL_INTRS_CPLUS \ 223250199Sgrehan (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 224250199Sgrehan RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 225250199Sgrehan RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 226250199Sgrehan#endif 227250199Sgrehan 228250199Sgrehan/* 229250199Sgrehan * Media status register. (8139 only) 230250199Sgrehan */ 231250199Sgrehan#define RL_MEDIASTAT_RXPAUSE 0x01 232294553Ssephe#define RL_MEDIASTAT_TXPAUSE 0x02 233294553Ssephe#define RL_MEDIASTAT_LINK 0x04 234294553Ssephe#define RL_MEDIASTAT_SPEED10 0x08 235282212Swhu#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 236282212Swhu#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 237250199Sgrehan 238282212Swhu/* 239250199Sgrehan * Receive config register. 240282212Swhu */ 241282212Swhu#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 242282212Swhu#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 243282212Swhu#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 244282212Swhu#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 245282212Swhu#define RL_RXCFG_RX_RUNT 0x00000010 246282212Swhu#define RL_RXCFG_RX_ERRPKT 0x00000020 247282212Swhu#define RL_RXCFG_WRAP 0x00000080 248250199Sgrehan#define RL_RXCFG_MAXDMA 0x00000700 249282212Swhu#define RL_RXCFG_BUFSZ 0x00001800 250282212Swhu#define RL_RXCFG_FIFOTHRESH 0x0000E000 251250199Sgrehan#define RL_RXCFG_EARLYTHRESH 0x07000000 252282212Swhu 253282212Swhu#define RL_RXDMA_16BYTES 0x00000000 254250199Sgrehan#define RL_RXDMA_32BYTES 0x00000100 255282212Swhu#define RL_RXDMA_64BYTES 0x00000200 256282212Swhu#define RL_RXDMA_128BYTES 0x00000300 257293870Ssephe#define RL_RXDMA_256BYTES 0x00000400 258282212Swhu#define RL_RXDMA_512BYTES 0x00000500 259250199Sgrehan#define RL_RXDMA_1024BYTES 0x00000600 260250199Sgrehan#define RL_RXDMA_UNLIMITED 0x00000700 261250199Sgrehan 262250199Sgrehan#define RL_RXBUF_8 0x00000000 263250199Sgrehan#define RL_RXBUF_16 0x00000800 264250199Sgrehan#define RL_RXBUF_32 0x00001000 265250199Sgrehan#define RL_RXBUF_64 0x00001800 266250199Sgrehan 267250199Sgrehan#define RL_RXFIFO_16BYTES 0x00000000 268250199Sgrehan#define RL_RXFIFO_32BYTES 0x00002000 269250199Sgrehan#define RL_RXFIFO_64BYTES 0x00004000 270250199Sgrehan#define RL_RXFIFO_128BYTES 0x00006000 271250199Sgrehan#define RL_RXFIFO_256BYTES 0x00008000 272250199Sgrehan#define RL_RXFIFO_512BYTES 0x0000A000 273250199Sgrehan#define RL_RXFIFO_1024BYTES 0x0000C000 274250199Sgrehan#define RL_RXFIFO_NOTHRESH 0x0000E000 275250199Sgrehan 276250199Sgrehan/* 277250199Sgrehan * Bits in RX status header (included with RX'ed packet 278250199Sgrehan * in ring buffer). 279250199Sgrehan */ 280250199Sgrehan#define RL_RXSTAT_RXOK 0x00000001 281250199Sgrehan#define RL_RXSTAT_ALIGNERR 0x00000002 282250199Sgrehan#define RL_RXSTAT_CRCERR 0x00000004 283250199Sgrehan#define RL_RXSTAT_GIANT 0x00000008 284250199Sgrehan#define RL_RXSTAT_RUNT 0x00000010 285250199Sgrehan#define RL_RXSTAT_BADSYM 0x00000020 286250199Sgrehan#define RL_RXSTAT_BROAD 0x00002000 287250199Sgrehan#define RL_RXSTAT_INDIV 0x00004000 288250199Sgrehan#define RL_RXSTAT_MULTI 0x00008000 289250199Sgrehan#define RL_RXSTAT_LENMASK 0xFFFF0000 290250199Sgrehan 291250199Sgrehan#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 292250199Sgrehan/* 293250199Sgrehan * Command register. 294250199Sgrehan */ 295250199Sgrehan#define RL_CMD_EMPTY_RXBUF 0x0001 296250199Sgrehan#define RL_CMD_TX_ENB 0x0004 297250199Sgrehan#define RL_CMD_RX_ENB 0x0008 298294553Ssephe#define RL_CMD_RESET 0x0010 299250199Sgrehan 300250199Sgrehan/* 301250199Sgrehan * EEPROM control register 302250199Sgrehan */ 303250199Sgrehan#define RL_EE_DATAOUT 0x01 /* Data out */ 304250199Sgrehan#define RL_EE_DATAIN 0x02 /* Data in */ 305250199Sgrehan#define RL_EE_CLK 0x04 /* clock */ 306250199Sgrehan#define RL_EE_SEL 0x08 /* chip select */ 307250199Sgrehan#define RL_EE_MODE (0x40|0x80) 308250199Sgrehan 309250199Sgrehan#define RL_EEMODE_OFF 0x00 310250199Sgrehan#define RL_EEMODE_AUTOLOAD 0x40 311250199Sgrehan#define RL_EEMODE_PROGRAM 0x80 312250199Sgrehan#define RL_EEMODE_WRITECFG (0x80|0x40) 313250199Sgrehan 314250199Sgrehan/* 9346 EEPROM commands */ 315250199Sgrehan 316250199Sgrehan#define RL_9346_WRITE 0x5 317250199Sgrehan#define RL_9346_READ 0x6 318250199Sgrehan#define RL_9346_ERASE 0x7 319250199Sgrehan#define RL_9346_EWEN 0x4 320250199Sgrehan#define RL_9346_EWEN_ADDR 0x30 321250199Sgrehan#define RL_9456_EWDS 0x4 322250199Sgrehan#define RL_9346_EWDS_ADDR 0x00 323250199Sgrehan 324250199Sgrehan#define RL_EECMD_WRITE 0x140 325250199Sgrehan#define RL_EECMD_READ_6BIT 0x180 326250199Sgrehan#define RL_EECMD_READ_8BIT 0x600 327250199Sgrehan#define RL_EECMD_ERASE 0x1c0 328250199Sgrehan 329294553Ssephe#define RL_EE_ID 0x00 330250199Sgrehan#define RL_EE_PCI_VID 0x01 331250199Sgrehan#define RL_EE_PCI_DID 0x02 332250199Sgrehan/* Location of station address inside EEPROM */ 333250199Sgrehan#define RL_EE_EADDR 0x07 334250199Sgrehan 335250199Sgrehan/* 336250199Sgrehan * MII register (8129 only) 337250199Sgrehan */ 338250199Sgrehan#define RL_MII_CLK 0x01 339250199Sgrehan#define RL_MII_DATAIN 0x02 340250199Sgrehan#define RL_MII_DATAOUT 0x04 341294886Ssephe#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 342250199Sgrehan 343282212Swhu/* 344250199Sgrehan * Config 0 register 345282212Swhu */ 346282212Swhu#define RL_CFG0_ROM0 0x01 347250199Sgrehan#define RL_CFG0_ROM1 0x02 348282212Swhu#define RL_CFG0_ROM2 0x04 349282212Swhu#define RL_CFG0_PL0 0x08 350250199Sgrehan#define RL_CFG0_PL1 0x10 351250199Sgrehan#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 352282212Swhu#define RL_CFG0_PCS 0x40 353282212Swhu#define RL_CFG0_SCR 0x80 354250199Sgrehan 355282212Swhu/* 356282212Swhu * Config 1 register 357282212Swhu */ 358282212Swhu#define RL_CFG1_PWRDWN 0x01 359282212Swhu#define RL_CFG1_SLEEP 0x02 360282212Swhu#define RL_CFG1_IOMAP 0x04 361282212Swhu#define RL_CFG1_MEMMAP 0x08 362282212Swhu#define RL_CFG1_RSVD 0x10 363282212Swhu#define RL_CFG1_DRVLOAD 0x20 364282212Swhu#define RL_CFG1_LED0 0x40 365282212Swhu#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 366282212Swhu#define RL_CFG1_LED1 0x80 367282212Swhu 368282212Swhu/* 369282212Swhu * 8139C+ register definitions 370282212Swhu */ 371282212Swhu 372282212Swhu/* RL_DUMPSTATS_LO register */ 373282212Swhu 374282212Swhu#define RL_DUMPSTATS_START 0x00000008 375282212Swhu 376250199Sgrehan/* Transmit start register */ 377250199Sgrehan 378250199Sgrehan#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 379250199Sgrehan#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 380250199Sgrehan#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 381250199Sgrehan 382294553Ssephe/* 383250199Sgrehan * Config 2 register, 8139C+/8169/8169S/8110S only 384250199Sgrehan */ 385250199Sgrehan#define RL_CFG2_BUSFREQ 0x07 386250199Sgrehan#define RL_CFG2_BUSWIDTH 0x08 387250199Sgrehan#define RL_CFG2_AUXPWRSTS 0x10 388250199Sgrehan 389250199Sgrehan#define RL_BUSFREQ_33MHZ 0x00 390250199Sgrehan#define RL_BUSFREQ_66MHZ 0x01 391250199Sgrehan 392250199Sgrehan#define RL_BUSWIDTH_32BITS 0x00 393294886Ssephe#define RL_BUSWIDTH_64BITS 0x08 394294886Ssephe 395294886Ssephe/* C+ mode command register */ 396294886Ssephe 397250199Sgrehan#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 398294886Ssephe#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 399294886Ssephe#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 400294886Ssephe#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 401250199Sgrehan#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 402250199Sgrehan#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 403250199Sgrehan 404250199Sgrehan/* C+ early transmit threshold */ 405250199Sgrehan 406250199Sgrehan#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 407250199Sgrehan 408250199Sgrehan/* 409250199Sgrehan * Gigabit PHY access register (8169 only) 410250199Sgrehan */ 411250199Sgrehan 412250199Sgrehan#define RL_PHYAR_PHYDATA 0x0000FFFF 413250199Sgrehan#define RL_PHYAR_PHYREG 0x001F0000 414250199Sgrehan#define RL_PHYAR_BUSY 0x80000000 415250199Sgrehan 416250199Sgrehan/* 417250199Sgrehan * Gigabit media status (8169 only) 418250199Sgrehan */ 419250199Sgrehan#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 420250199Sgrehan#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 421250199Sgrehan#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 422250199Sgrehan#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 423250199Sgrehan#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 424250199Sgrehan#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 425250199Sgrehan#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 426250199Sgrehan#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 427250199Sgrehan 428250199Sgrehan/* 429250199Sgrehan * The RealTek doesn't use a fragment-based descriptor mechanism. 430250199Sgrehan * Instead, there are only four register sets, each or which represents 431250199Sgrehan * one 'descriptor.' Basically, each TX descriptor is just a contiguous 432250199Sgrehan * packet buffer (32-bit aligned!) and we place the buffer addresses in 433250199Sgrehan * the registers so the chip knows where they are. 434250199Sgrehan * 435250199Sgrehan * We can sort of kludge together the same kind of buffer management 436250199Sgrehan * used in previous drivers, but we have to do buffer copies almost all 437250199Sgrehan * the time, so it doesn't really buy us much. 438250199Sgrehan * 439250199Sgrehan * For reception, there's just one large buffer where the chip stores 440250199Sgrehan * all received packets. 441250199Sgrehan */ 442250199Sgrehan 443250199Sgrehan#define RL_RX_BUF_SZ RL_RXBUF_64 444250199Sgrehan#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 445282212Swhu#define RL_TX_LIST_CNT 4 446250199Sgrehan#define RL_MIN_FRAMELEN 60 447282212Swhu#define RL_TXTHRESH(x) ((x) << 11) 448250199Sgrehan#define RL_TX_THRESH_INIT 96 449250199Sgrehan#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 450250199Sgrehan#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 451250199Sgrehan#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 452250199Sgrehan 453250199Sgrehan#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 454282212Swhu#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 455250199Sgrehan 456250199Sgrehan#define RL_ETHER_ALIGN 2 457250199Sgrehan 458struct rl_chain_data { 459 uint16_t cur_rx; 460 uint8_t *rl_rx_buf; 461 uint8_t *rl_rx_buf_ptr; 462 bus_dmamap_t rl_rx_dmamap; 463 464 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 465 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 466 uint8_t last_tx; 467 uint8_t cur_tx; 468}; 469 470#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 471#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 472#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 473#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 474#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 475#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 476#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 477#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 478#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 479 480struct rl_type { 481 uint16_t rl_vid; 482 uint16_t rl_did; 483 int rl_basetype; 484 char *rl_name; 485}; 486 487struct rl_hwrev { 488 uint32_t rl_rev; 489 int rl_type; 490 char *rl_desc; 491}; 492 493struct rl_mii_frame { 494 uint8_t mii_stdelim; 495 uint8_t mii_opcode; 496 uint8_t mii_phyaddr; 497 uint8_t mii_regaddr; 498 uint8_t mii_turnaround; 499 uint16_t mii_data; 500}; 501 502/* 503 * MII constants 504 */ 505#define RL_MII_STARTDELIM 0x01 506#define RL_MII_READOP 0x02 507#define RL_MII_WRITEOP 0x01 508#define RL_MII_TURNAROUND 0x02 509 510#define RL_8129 1 511#define RL_8139 2 512#define RL_8139CPLUS 3 513#define RL_8169 4 514 515#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 516 (x)->rl_type == RL_8169) 517 518/* 519 * The 8139C+ and 8160 gigE chips support descriptor-based TX 520 * and RX. In fact, they even support TCP large send. Descriptors 521 * must be allocated in contiguous blocks that are aligned on a 522 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 523 */ 524 525/* 526 * RX/TX descriptor definition. When large send mode is enabled, the 527 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 528 * the checksum offload bits are disabled. The structure layout is 529 * the same for RX and TX descriptors 530 */ 531 532struct rl_desc { 533 uint32_t rl_cmdstat; 534 uint32_t rl_vlanctl; 535 uint32_t rl_bufaddr_lo; 536 uint32_t rl_bufaddr_hi; 537}; 538 539#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 540#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 541#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 542#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 543#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 544#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 545#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 546#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 547#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 548#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 549#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 550 551#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 552#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 553 554/* 555 * Error bits are valid only on the last descriptor of a frame 556 * (i.e. RL_TDESC_CMD_EOF == 1) 557 */ 558 559#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 560#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 561#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 562#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 563#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 564#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 565#define RL_TDESC_STAT_OWN 0x80000000 566 567/* 568 * RX descriptor cmd/vlan definitions 569 */ 570 571#define RL_RDESC_CMD_EOR 0x40000000 572#define RL_RDESC_CMD_OWN 0x80000000 573#define RL_RDESC_CMD_BUFLEN 0x00001FFF 574 575#define RL_RDESC_STAT_OWN 0x80000000 576#define RL_RDESC_STAT_EOR 0x40000000 577#define RL_RDESC_STAT_SOF 0x20000000 578#define RL_RDESC_STAT_EOF 0x10000000 579#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 580#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 581#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 582#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 583#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 584#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 585#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 586#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 587#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 588#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 589#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 590#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 591#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 592#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 593#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 594#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 595#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 596 RL_RDESC_STAT_CRCERR) 597 598#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 599 (rl_vlandata valid)*/ 600#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 601 602#define RL_PROTOID_NONIP 0x00000000 603#define RL_PROTOID_TCPIP 0x00010000 604#define RL_PROTOID_UDPIP 0x00020000 605#define RL_PROTOID_IP 0x00030000 606#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 607 RL_PROTOID_TCPIP) 608#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 609 RL_PROTOID_UDPIP) 610 611/* 612 * Statistics counter structure (8139C+ and 8169 only) 613 */ 614struct rl_stats { 615 uint32_t rl_tx_pkts_lo; 616 uint32_t rl_tx_pkts_hi; 617 uint32_t rl_tx_errs_lo; 618 uint32_t rl_tx_errs_hi; 619 uint32_t rl_tx_errs; 620 uint16_t rl_missed_pkts; 621 uint16_t rl_rx_framealign_errs; 622 uint32_t rl_tx_onecoll; 623 uint32_t rl_tx_multicolls; 624 uint32_t rl_rx_ucasts_hi; 625 uint32_t rl_rx_ucasts_lo; 626 uint32_t rl_rx_bcasts_lo; 627 uint32_t rl_rx_bcasts_hi; 628 uint32_t rl_rx_mcasts; 629 uint16_t rl_tx_aborts; 630 uint16_t rl_rx_underruns; 631}; 632 633/* 634 * Rx/Tx descriptor parameters (8139C+ and 8169 only) 635 * 636 * Tx/Rx count must be equal. Shared code like re_dma_map_desc assumes this. 637 * Buffers must be a multiple of 8 bytes. Currently limit to 64 descriptors 638 * due to the 8139C+. We need to put the number of descriptors in the ring 639 * structure and use that value instead. 640 */ 641#ifndef __NO_STRICT_ALIGNMENT 642#define RE_FIXUP_RX 1 643#endif 644 645#define RL_TX_DESC_CNT 64 646#define RL_TX_DESC_THLD 4 647#define RL_RX_DESC_CNT RL_TX_DESC_CNT 648 649#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) 650#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc)) 651#define RL_RING_ALIGN 256 652#define RL_IFQ_MAXLEN 512 653#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT) 654#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 655#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 656#define RL_PKTSZ(x) ((x)/* >> 3*/) 657#ifdef RE_FIXUP_RX 658#define RE_ETHER_ALIGN sizeof(uint64_t) 659#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 660#else 661#define RE_ETHER_ALIGN 0 662#define RE_RX_DESC_BUFLEN MCLBYTES 663#endif 664 665#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 666#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 667 668/* see comment in dev/re/if_re.c */ 669#define RL_JUMBO_FRAMELEN 7440 670#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 671 672struct rl_softc; 673 674struct rl_dmaload_arg { 675 int rl_idx; 676 int rl_maxsegs; 677 uint32_t rl_flags; 678 struct rl_desc *rl_ring; 679}; 680 681struct rl_list_data { 682 struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT]; 683 struct mbuf *rl_rx_mbuf[RL_RX_DESC_CNT]; 684 int rl_tx_prodidx; 685 int rl_rx_prodidx; 686 int rl_tx_considx; 687 int rl_tx_free; 688 bus_dmamap_t rl_tx_dmamap[RL_TX_DESC_CNT]; 689 bus_dmamap_t rl_rx_dmamap[RL_RX_DESC_CNT]; 690 bus_dma_tag_t rl_mtag; /* mbuf mapping tag */ 691 bus_dma_tag_t rl_stag; /* stats mapping tag */ 692 bus_dmamap_t rl_smap; /* stats map */ 693 struct rl_stats *rl_stats; 694 bus_addr_t rl_stats_addr; 695 bus_dma_tag_t rl_rx_list_tag; 696 bus_dmamap_t rl_rx_list_map; 697 struct rl_desc *rl_rx_list; 698 bus_addr_t rl_rx_list_addr; 699 bus_dma_tag_t rl_tx_list_tag; 700 bus_dmamap_t rl_tx_list_map; 701 struct rl_desc *rl_tx_list; 702 bus_addr_t rl_tx_list_addr; 703}; 704 705struct rl_softc { 706 struct ifnet *rl_ifp; /* interface info */ 707 bus_space_handle_t rl_bhandle; /* bus space handle */ 708 bus_space_tag_t rl_btag; /* bus space tag */ 709 device_t rl_dev; 710 struct resource *rl_res; 711 struct resource *rl_irq; 712 void *rl_intrhand; 713 device_t rl_miibus; 714 bus_dma_tag_t rl_parent_tag; 715 bus_dma_tag_t rl_tag; 716 uint8_t rl_type; 717 int rl_eecmd_read; 718 int rl_eewidth; 719 uint8_t rl_stats_no_timeout; 720 int rl_txthresh; 721 struct rl_chain_data rl_cdata; 722 struct rl_list_data rl_ldata; 723 struct callout rl_stat_callout; 724 int rl_watchdog_timer; 725 struct mtx rl_mtx; 726 struct mbuf *rl_head; 727 struct mbuf *rl_tail; 728 uint32_t rl_hwrev; 729 uint32_t rl_rxlenmask; 730 int rl_testmode; 731 int rl_if_flags; 732 int suspended; /* 0 = normal 1 = suspended */ 733#ifdef DEVICE_POLLING 734 int rxcycles; 735#endif 736 737 struct task rl_txtask; 738 struct task rl_inttask; 739 740 struct mtx rl_intlock; 741 int rl_txstart; 742 int rl_link; 743}; 744 745#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 746#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 747#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 748 749/* 750 * register space access macros 751 */ 752#define CSR_WRITE_STREAM_4(sc, reg, val) \ 753 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 754#define CSR_WRITE_4(sc, reg, val) \ 755 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 756#define CSR_WRITE_2(sc, reg, val) \ 757 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 758#define CSR_WRITE_1(sc, reg, val) \ 759 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 760 761#define CSR_READ_4(sc, reg) \ 762 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 763#define CSR_READ_2(sc, reg) \ 764 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 765#define CSR_READ_1(sc, reg) \ 766 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 767 768#define CSR_SETBIT_1(sc, offset, val) \ 769 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 770 771#define CSR_CLRBIT_1(sc, offset, val) \ 772 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 773 774#define CSR_SETBIT_2(sc, offset, val) \ 775 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 776 777#define CSR_CLRBIT_2(sc, offset, val) \ 778 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 779 780#define CSR_SETBIT_4(sc, offset, val) \ 781 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 782 783#define CSR_CLRBIT_4(sc, offset, val) \ 784 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 785 786#define RL_TIMEOUT 1000 787 788/* 789 * General constants that are fun to know. 790 * 791 * RealTek PCI vendor ID 792 */ 793#define RT_VENDORID 0x10EC 794 795/* 796 * RealTek chip device IDs. 797 */ 798#define RT_DEVICEID_8129 0x8129 799#define RT_DEVICEID_8101E 0x8136 800#define RT_DEVICEID_8138 0x8138 801#define RT_DEVICEID_8139 0x8139 802#define RT_DEVICEID_8169SC 0x8167 803#define RT_DEVICEID_8168 0x8168 804#define RT_DEVICEID_8169 0x8169 805#define RT_DEVICEID_8100 0x8100 806 807#define RT_REVID_8139CPLUS 0x20 808 809/* 810 * Accton PCI vendor ID 811 */ 812#define ACCTON_VENDORID 0x1113 813 814/* 815 * Accton MPX 5030/5038 device ID. 816 */ 817#define ACCTON_DEVICEID_5030 0x1211 818 819/* 820 * Nortel PCI vendor ID 821 */ 822#define NORTEL_VENDORID 0x126C 823 824/* 825 * Delta Electronics Vendor ID. 826 */ 827#define DELTA_VENDORID 0x1500 828 829/* 830 * Delta device IDs. 831 */ 832#define DELTA_DEVICEID_8139 0x1360 833 834/* 835 * Addtron vendor ID. 836 */ 837#define ADDTRON_VENDORID 0x4033 838 839/* 840 * Addtron device IDs. 841 */ 842#define ADDTRON_DEVICEID_8139 0x1360 843 844/* 845 * D-Link vendor ID. 846 */ 847#define DLINK_VENDORID 0x1186 848 849/* 850 * D-Link DFE-530TX+ device ID 851 */ 852#define DLINK_DEVICEID_530TXPLUS 0x1300 853 854/* 855 * D-Link DFE-5280T device ID 856 */ 857#define DLINK_DEVICEID_528T 0x4300 858 859/* 860 * D-Link DFE-690TXD device ID 861 */ 862#define DLINK_DEVICEID_690TXD 0x1340 863 864/* 865 * Corega K.K vendor ID 866 */ 867#define COREGA_VENDORID 0x1259 868 869/* 870 * Corega FEther CB-TXD device ID 871 */ 872#define COREGA_DEVICEID_FETHERCBTXD 0xa117 873 874/* 875 * Corega FEtherII CB-TXD device ID 876 */ 877#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 878 879/* 880 * Corega CG-LAPCIGT device ID 881 */ 882#define COREGA_DEVICEID_CGLAPCIGT 0xc107 883 884/* 885 * Linksys vendor ID 886 */ 887#define LINKSYS_VENDORID 0x1737 888 889/* 890 * Linksys EG1032 device ID 891 */ 892#define LINKSYS_DEVICEID_EG1032 0x1032 893 894/* 895 * Linksys EG1032 rev 3 sub-device ID 896 */ 897#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 898 899/* 900 * Peppercon vendor ID 901 */ 902#define PEPPERCON_VENDORID 0x1743 903 904/* 905 * Peppercon ROL-F device ID 906 */ 907#define PEPPERCON_DEVICEID_ROLF 0x8139 908 909/* 910 * Planex Communications, Inc. vendor ID 911 */ 912#define PLANEX_VENDORID 0x14ea 913 914/* 915 * Planex FNW-3800-TX device ID 916 */ 917#define PLANEX_DEVICEID_FNW3800TX 0xab07 918 919/* 920 * LevelOne vendor ID 921 */ 922#define LEVEL1_VENDORID 0x018A 923 924/* 925 * LevelOne FPC-0106TX devide ID 926 */ 927#define LEVEL1_DEVICEID_FPC0106TX 0x0106 928 929/* 930 * Compaq vendor ID 931 */ 932#define CP_VENDORID 0x021B 933 934/* 935 * Edimax vendor ID 936 */ 937#define EDIMAX_VENDORID 0x13D1 938 939/* 940 * Edimax EP-4103DL cardbus device ID 941 */ 942#define EDIMAX_DEVICEID_EP4103DL 0xAB06 943 944/* US Robotics vendor ID */ 945 946#define USR_VENDORID 0x16EC 947 948/* US Robotics 997902 device ID */ 949 950#define USR_DEVICEID_997902 0x0116 951 952/* 953 * PCI low memory base and low I/O base register, and 954 * other PCI registers. 955 */ 956 957#define RL_PCI_VENDOR_ID 0x00 958#define RL_PCI_DEVICE_ID 0x02 959#define RL_PCI_COMMAND 0x04 960#define RL_PCI_STATUS 0x06 961#define RL_PCI_CLASSCODE 0x09 962#define RL_PCI_LATENCY_TIMER 0x0D 963#define RL_PCI_HEADER_TYPE 0x0E 964#define RL_PCI_LOIO 0x10 965#define RL_PCI_LOMEM 0x14 966#define RL_PCI_BIOSROM 0x30 967#define RL_PCI_INTLINE 0x3C 968#define RL_PCI_INTPIN 0x3D 969#define RL_PCI_MINGNT 0x3E 970#define RL_PCI_MINLAT 0x0F 971#define RL_PCI_RESETOPT 0x48 972#define RL_PCI_EEPROM_DATA 0x4C 973 974#define RL_PCI_CAPID 0x50 /* 8 bits */ 975#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 976#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 977#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 978 979#define RL_PSTATE_MASK 0x0003 980#define RL_PSTATE_D0 0x0000 981#define RL_PSTATE_D1 0x0002 982#define RL_PSTATE_D2 0x0002 983#define RL_PSTATE_D3 0x0003 984#define RL_PME_EN 0x0010 985#define RL_PME_STATUS 0x8000 986