if_rlreg.h revision 164460
146116Sphk/*- 22729Sdfr * Copyright (c) 1997, 1998-2003 32729Sdfr * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 42729Sdfr * 52729Sdfr * Redistribution and use in source and binary forms, with or without 62729Sdfr * modification, are permitted provided that the following conditions 72729Sdfr * are met: 82729Sdfr * 1. Redistributions of source code must retain the above copyright 92729Sdfr * notice, this list of conditions and the following disclaimer. 102729Sdfr * 2. Redistributions in binary form must reproduce the above copyright 112729Sdfr * notice, this list of conditions and the following disclaimer in the 122729Sdfr * documentation and/or other materials provided with the distribution. 132729Sdfr * 3. All advertising materials mentioning features or use of this software 142729Sdfr * must display the following acknowledgement: 152729Sdfr * This product includes software developed by Bill Paul. 162729Sdfr * 4. Neither the name of the author nor the names of any co-contributors 172729Sdfr * may be used to endorse or promote products derived from this software 182729Sdfr * without specific prior written permission. 192729Sdfr * 202729Sdfr * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 212729Sdfr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 222729Sdfr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 232729Sdfr * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2411626Sbde * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 252729Sdfr * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 262729Sdfr * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 272729Sdfr * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2811626Sbde * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 292729Sdfr * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3010653Sdg * THE POSSIBILITY OF SUCH DAMAGE. 3110358Sjulian * 3210358Sjulian * $FreeBSD: head/sys/pci/if_rlreg.h 164460 2006-11-21 04:11:31Z yongari $ 332729Sdfr */ 342729Sdfr 352729Sdfr/* 3612866Speter * RealTek 8129/8139 register offsets 3711626Sbde */ 3830994Sphk#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 3911626Sbde#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 4030994Sphk#define RL_IDR2 0x0002 4111626Sbde#define RL_IDR3 0x0003 4230994Sphk#define RL_IDR4 0x0004 4311626Sbde#define RL_IDR5 0x0005 4430994Sphk /* 0006-0007 reserved */ 4512866Speter#define RL_MAR0 0x0008 /* Multicast hash table */ 4611626Sbde#define RL_MAR1 0x0009 472729Sdfr#define RL_MAR2 0x000A 4811626Sbde#define RL_MAR3 0x000B 4912819Sphk#define RL_MAR4 0x000C 5011626Sbde#define RL_MAR5 0x000D 5111626Sbde#define RL_MAR6 0x000E 5211626Sbde#define RL_MAR7 0x000F 532729Sdfr 5412819Sphk#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 5512819Sphk#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 5612819Sphk#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 579759Sbde#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 589759Sbde 599759Sbde#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 609759Sbde#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 612729Sdfr#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 622836Sdg#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6311626Sbde 6411626Sbde#define RL_RXADDR 0x0030 /* RX ring start address */ 652729Sdfr#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 662729Sdfr#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 672729Sdfr#define RL_COMMAND 0x0037 /* command register */ 682729Sdfr#define RL_CURRXADDR 0x0038 /* current address of packet read */ 692729Sdfr#define RL_CURRXBUF 0x003A /* current RX buffer address */ 702729Sdfr#define RL_IMR 0x003C /* interrupt mask register */ 712729Sdfr#define RL_ISR 0x003E /* interrupt status register */ 722729Sdfr#define RL_TXCFG 0x0040 /* transmit config */ 732729Sdfr#define RL_RXCFG 0x0044 /* receive config */ 742729Sdfr#define RL_TIMERCNT 0x0048 /* timer count register */ 752729Sdfr#define RL_MISSEDPKT 0x004C /* missed packet counter */ 762729Sdfr#define RL_EECMD 0x0050 /* EEPROM command register */ 772729Sdfr#define RL_CFG0 0x0051 /* config register #0 */ 782729Sdfr#define RL_CFG1 0x0052 /* config register #1 */ 792729Sdfr /* 0053-0057 reserved */ 802729Sdfr#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 812729Sdfr /* 0059-005A reserved */ 822729Sdfr#define RL_MII 0x005A /* 8129 chip only */ 832729Sdfr#define RL_HALTCLK 0x005B 842729Sdfr#define RL_MULTIINTR 0x005C /* multiple interrupt */ 852729Sdfr#define RL_PCIREV 0x005E /* PCI revision value */ 862729Sdfr /* 005F reserved */ 872729Sdfr#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 882729Sdfr 892729Sdfr/* Direct PHY access registers only available on 8139 */ 902729Sdfr#define RL_BMCR 0x0062 /* PHY basic mode control */ 912729Sdfr#define RL_BMSR 0x0064 /* PHY basic mode status */ 922729Sdfr#define RL_ANAR 0x0066 /* PHY autoneg advert */ 932729Sdfr#define RL_LPAR 0x0068 /* PHY link partner ability */ 942729Sdfr#define RL_ANER 0x006A /* PHY autoneg expansion */ 952729Sdfr 962729Sdfr#define RL_DISCCNT 0x006C /* disconnect counter */ 972729Sdfr#define RL_FALSECAR 0x006E /* false carrier counter */ 982729Sdfr#define RL_NWAYTST 0x0070 /* NWAY test register */ 992729Sdfr#define RL_RX_ER 0x0072 /* RX_ER counter */ 1002729Sdfr#define RL_CSCFG 0x0074 /* CS configuration register */ 1012729Sdfr 1022729Sdfr/* 1032729Sdfr * When operating in special C+ mode, some of the registers in an 1042729Sdfr * 8139C+ chip have different definitions. These are also used for 1052729Sdfr * the 8169 gigE chip. 1062729Sdfr */ 1072729Sdfr#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 1082729Sdfr#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 1092729Sdfr#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 1102729Sdfr#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 1112729Sdfr#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 1122729Sdfr#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 1132729Sdfr#define RL_CFG2 0x0053 1142729Sdfr#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 1152729Sdfr#define RL_TXSTART 0x00D9 /* 8 bits */ 1162729Sdfr#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 1172729Sdfr#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 1182729Sdfr#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 1192729Sdfr#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 1202729Sdfr 1212729Sdfr/* 1222729Sdfr * Registers specific to the 8169 gigE chip 12330994Sphk */ 12411626Sbde#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 12511626Sbde#define RL_PHYAR 0x0060 12611626Sbde#define RL_TBICSR 0x0064 12711626Sbde#define RL_TBI_ANAR 0x0068 12811626Sbde#define RL_TBI_LPAR 0x006A 12911626Sbde#define RL_GMEDIASTAT 0x006C /* 8 bits */ 13011626Sbde#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 13111626Sbde#define RL_GTXSTART 0x0038 /* 16 bits */ 13211626Sbde 13311626Sbde/* 1342729Sdfr * TX config register bits 1352729Sdfr */ 1362729Sdfr#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 1372729Sdfr#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 13830994Sphk#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 1392729Sdfr#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 1402729Sdfr#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 1412729Sdfr#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 1422729Sdfr#define RL_TXCFG_HWREV 0x7CC00000 1432729Sdfr 1442729Sdfr#define RL_LOOPTEST_OFF 0x00000000 1452729Sdfr#define RL_LOOPTEST_ON 0x00020000 1462729Sdfr#define RL_LOOPTEST_ON_CPLUS 0x00060000 1472729Sdfr 1482729Sdfr/* Known revision codes. */ 1492729Sdfr 1502729Sdfr#define RL_HWREV_8169 0x00000000 1512729Sdfr#define RL_HWREV_8110S 0x00800000 1522729Sdfr#define RL_HWREV_8169S 0x04000000 1532729Sdfr#define RL_HWREV_8169_8110SB 0x10000000 1542729Sdfr#define RL_HWREV_8169_8110SC 0x18000000 1552729Sdfr#define RL_HWREV_8168_SPIN1 0x30000000 1562729Sdfr#define RL_HWREV_8100E 0x30800000 1572729Sdfr#define RL_HWREV_8101E 0x34000000 1582729Sdfr#define RL_HWREV_8168_SPIN2 0x38000000 1592729Sdfr#define RL_HWREV_8139 0x60000000 1602729Sdfr#define RL_HWREV_8139A 0x70000000 1612729Sdfr#define RL_HWREV_8139AG 0x70800000 1622729Sdfr#define RL_HWREV_8139B 0x78000000 1632729Sdfr#define RL_HWREV_8130 0x7C000000 1642729Sdfr#define RL_HWREV_8139C 0x74000000 16512866Speter#define RL_HWREV_8139D 0x74400000 1662729Sdfr#define RL_HWREV_8139CPLUS 0x74800000 1672729Sdfr#define RL_HWREV_8101 0x74c00000 1682729Sdfr#define RL_HWREV_8100 0x78800000 16912866Speter 1702729Sdfr#define RL_TXDMA_16BYTES 0x00000000 17112866Speter#define RL_TXDMA_32BYTES 0x00000100 1722729Sdfr#define RL_TXDMA_64BYTES 0x00000200 17312866Speter#define RL_TXDMA_128BYTES 0x00000300 17430994Sphk#define RL_TXDMA_256BYTES 0x00000400 1752729Sdfr#define RL_TXDMA_512BYTES 0x00000500 1762729Sdfr#define RL_TXDMA_1024BYTES 0x00000600 1772729Sdfr#define RL_TXDMA_2048BYTES 0x00000700 1782729Sdfr 1792729Sdfr/* 18012866Speter * Transmit descriptor status register bits. 1813308Sphk */ 1822729Sdfr#define RL_TXSTAT_LENMASK 0x00001FFF 1832729Sdfr#define RL_TXSTAT_OWN 0x00002000 1842729Sdfr#define RL_TXSTAT_TX_UNDERRUN 0x00004000 1852729Sdfr#define RL_TXSTAT_TX_OK 0x00008000 1862729Sdfr#define RL_TXSTAT_EARLY_THRESH 0x003F0000 1872729Sdfr#define RL_TXSTAT_COLLCNT 0x0F000000 1882729Sdfr#define RL_TXSTAT_CARR_HBEAT 0x10000000 1892729Sdfr#define RL_TXSTAT_OUTOFWIN 0x20000000 1902729Sdfr#define RL_TXSTAT_TXABRT 0x40000000 1912729Sdfr#define RL_TXSTAT_CARRLOSS 0x80000000 1922729Sdfr 1932729Sdfr/* 1942729Sdfr * Interrupt status register bits. 1952729Sdfr */ 1962729Sdfr#define RL_ISR_RX_OK 0x0001 1972729Sdfr#define RL_ISR_RX_ERR 0x0002 1982729Sdfr#define RL_ISR_TX_OK 0x0004 1992729Sdfr#define RL_ISR_TX_ERR 0x0008 2002729Sdfr#define RL_ISR_RX_OVERRUN 0x0010 2012729Sdfr#define RL_ISR_PKT_UNDERRUN 0x0020 2022729Sdfr#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 2032729Sdfr#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 2042729Sdfr#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 2052729Sdfr#define RL_ISR_SWI 0x0100 /* C+ only */ 2062729Sdfr#define RL_ISR_CABLE_LEN_CHGD 0x2000 2072729Sdfr#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 2082729Sdfr#define RL_ISR_TIMEOUT_EXPIRED 0x4000 2092729Sdfr#define RL_ISR_SYSTEM_ERR 0x8000 2102729Sdfr 2112729Sdfr#define RL_INTRS \ 2122729Sdfr (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 2132729Sdfr RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 2142729Sdfr RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 2152729Sdfr 2162729Sdfr#ifdef RE_TX_MODERATION 2172729Sdfr#define RL_INTRS_CPLUS \ 2182729Sdfr (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 2192729Sdfr RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 2202729Sdfr RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 2212729Sdfr#else 22246116Sphk#define RL_INTRS_CPLUS \ 2232729Sdfr (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 2242729Sdfr RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 2252729Sdfr RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 2262729Sdfr#endif 2272729Sdfr 2282729Sdfr/* 2292729Sdfr * Media status register. (8139 only) 2302729Sdfr */ 2312729Sdfr#define RL_MEDIASTAT_RXPAUSE 0x01 2322729Sdfr#define RL_MEDIASTAT_TXPAUSE 0x02 2332729Sdfr#define RL_MEDIASTAT_LINK 0x04 2342729Sdfr#define RL_MEDIASTAT_SPEED10 0x08 2352729Sdfr#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 2362729Sdfr#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 2372729Sdfr 2382729Sdfr/* 2392729Sdfr * Receive config register. 2402729Sdfr */ 2412729Sdfr#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 2422729Sdfr#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 2432729Sdfr#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 2442729Sdfr#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 2452729Sdfr#define RL_RXCFG_RX_RUNT 0x00000010 2462729Sdfr#define RL_RXCFG_RX_ERRPKT 0x00000020 2472729Sdfr#define RL_RXCFG_WRAP 0x00000080 2482729Sdfr#define RL_RXCFG_MAXDMA 0x00000700 2492729Sdfr#define RL_RXCFG_BUFSZ 0x00001800 25046116Sphk#define RL_RXCFG_FIFOTHRESH 0x0000E000 2512729Sdfr#define RL_RXCFG_EARLYTHRESH 0x07000000 2522729Sdfr 2532729Sdfr#define RL_RXDMA_16BYTES 0x00000000 25443426Sphk#define RL_RXDMA_32BYTES 0x00000100 25546116Sphk#define RL_RXDMA_64BYTES 0x00000200 25643426Sphk#define RL_RXDMA_128BYTES 0x00000300 25743426Sphk#define RL_RXDMA_256BYTES 0x00000400 25843426Sphk#define RL_RXDMA_512BYTES 0x00000500 2592729Sdfr#define RL_RXDMA_1024BYTES 0x00000600 2602729Sdfr#define RL_RXDMA_UNLIMITED 0x00000700 2612729Sdfr 2622729Sdfr#define RL_RXBUF_8 0x00000000 2632729Sdfr#define RL_RXBUF_16 0x00000800 2642729Sdfr#define RL_RXBUF_32 0x00001000 2652729Sdfr#define RL_RXBUF_64 0x00001800 2662729Sdfr 2672729Sdfr#define RL_RXFIFO_16BYTES 0x00000000 2682729Sdfr#define RL_RXFIFO_32BYTES 0x00002000 2692729Sdfr#define RL_RXFIFO_64BYTES 0x00004000 2702729Sdfr#define RL_RXFIFO_128BYTES 0x00006000 2712729Sdfr#define RL_RXFIFO_256BYTES 0x00008000 2722729Sdfr#define RL_RXFIFO_512BYTES 0x0000A000 2732729Sdfr#define RL_RXFIFO_1024BYTES 0x0000C000 2742729Sdfr#define RL_RXFIFO_NOTHRESH 0x0000E000 2752729Sdfr 2762729Sdfr/* 27734961Sphk * Bits in RX status header (included with RX'ed packet 2782729Sdfr * in ring buffer). 2792729Sdfr */ 2802729Sdfr#define RL_RXSTAT_RXOK 0x00000001 28146116Sphk#define RL_RXSTAT_ALIGNERR 0x00000002 2822729Sdfr#define RL_RXSTAT_CRCERR 0x00000004 2832729Sdfr#define RL_RXSTAT_GIANT 0x00000008 2842729Sdfr#define RL_RXSTAT_RUNT 0x00000010 2852729Sdfr#define RL_RXSTAT_BADSYM 0x00000020 2862729Sdfr#define RL_RXSTAT_BROAD 0x00002000 2872729Sdfr#define RL_RXSTAT_INDIV 0x00004000 2882729Sdfr#define RL_RXSTAT_MULTI 0x00008000 2892729Sdfr#define RL_RXSTAT_LENMASK 0xFFFF0000 2902729Sdfr 2912729Sdfr#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 2922729Sdfr/* 2932729Sdfr * Command register. 2942729Sdfr */ 2952729Sdfr#define RL_CMD_EMPTY_RXBUF 0x0001 2962729Sdfr#define RL_CMD_TX_ENB 0x0004 2972729Sdfr#define RL_CMD_RX_ENB 0x0008 2982729Sdfr#define RL_CMD_RESET 0x0010 29930994Sphk 3002729Sdfr/* 3012729Sdfr * EEPROM control register 3022729Sdfr */ 30312866Speter#define RL_EE_DATAOUT 0x01 /* Data out */ 3042729Sdfr#define RL_EE_DATAIN 0x02 /* Data in */ 3052729Sdfr#define RL_EE_CLK 0x04 /* clock */ 3062729Sdfr#define RL_EE_SEL 0x08 /* chip select */ 3072729Sdfr#define RL_EE_MODE (0x40|0x80) 30812866Speter 3092729Sdfr#define RL_EEMODE_OFF 0x00 31012866Speter#define RL_EEMODE_AUTOLOAD 0x40 31130994Sphk#define RL_EEMODE_PROGRAM 0x80 3122729Sdfr#define RL_EEMODE_WRITECFG (0x80|0x40) 3132729Sdfr 3142729Sdfr/* 9346 EEPROM commands */ 3152729Sdfr 3162729Sdfr#define RL_9346_WRITE 0x5 3172729Sdfr#define RL_9346_READ 0x6 3182729Sdfr#define RL_9346_ERASE 0x7 3192836Sdg#define RL_9346_EWEN 0x4 3202729Sdfr#define RL_9346_EWEN_ADDR 0x30 3212729Sdfr#define RL_9456_EWDS 0x4 3222729Sdfr#define RL_9346_EWDS_ADDR 0x00 3232729Sdfr 3242729Sdfr#define RL_EECMD_WRITE 0x140 3252729Sdfr#define RL_EECMD_READ_6BIT 0x180 3262729Sdfr#define RL_EECMD_READ_8BIT 0x600 3272729Sdfr#define RL_EECMD_ERASE 0x1c0 3282729Sdfr 3292729Sdfr#define RL_EE_ID 0x00 3302729Sdfr#define RL_EE_PCI_VID 0x01 3312729Sdfr#define RL_EE_PCI_DID 0x02 3322729Sdfr/* Location of station address inside EEPROM */ 3332729Sdfr#define RL_EE_EADDR 0x07 3342729Sdfr 3352729Sdfr/* 3362729Sdfr * MII register (8129 only) 3372729Sdfr */ 3382729Sdfr#define RL_MII_CLK 0x01 3392729Sdfr#define RL_MII_DATAIN 0x02 3402729Sdfr#define RL_MII_DATAOUT 0x04 3412729Sdfr#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 34246116Sphk 3432729Sdfr/* 3442729Sdfr * Config 0 register 3452729Sdfr */ 3462729Sdfr#define RL_CFG0_ROM0 0x01 3472729Sdfr#define RL_CFG0_ROM1 0x02 3482729Sdfr#define RL_CFG0_ROM2 0x04 3492729Sdfr#define RL_CFG0_PL0 0x08 3502729Sdfr#define RL_CFG0_PL1 0x10 3512729Sdfr#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 3522729Sdfr#define RL_CFG0_PCS 0x40 3532729Sdfr#define RL_CFG0_SCR 0x80 3542729Sdfr 3552729Sdfr/* 3562729Sdfr * Config 1 register 3572729Sdfr */ 3582729Sdfr#define RL_CFG1_PWRDWN 0x01 3592729Sdfr#define RL_CFG1_SLEEP 0x02 3602729Sdfr#define RL_CFG1_IOMAP 0x04 3612729Sdfr#define RL_CFG1_MEMMAP 0x08 3622729Sdfr#define RL_CFG1_RSVD 0x10 3632729Sdfr#define RL_CFG1_DRVLOAD 0x20 3642729Sdfr#define RL_CFG1_LED0 0x40 3652729Sdfr#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 3662729Sdfr#define RL_CFG1_LED1 0x80 3672729Sdfr 3682729Sdfr/* 3692729Sdfr * 8139C+ register definitions 3702729Sdfr */ 3712729Sdfr 3722729Sdfr/* RL_DUMPSTATS_LO register */ 3738876Srgrimes 3742729Sdfr#define RL_DUMPSTATS_START 0x00000008 3752729Sdfr 3762729Sdfr/* Transmit start register */ 3772729Sdfr 3782729Sdfr#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 3792729Sdfr#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 3802729Sdfr#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 3812729Sdfr 3822729Sdfr/* 3832729Sdfr * Config 2 register, 8139C+/8169/8169S/8110S only 3842729Sdfr */ 3852729Sdfr#define RL_CFG2_BUSFREQ 0x07 3862729Sdfr#define RL_CFG2_BUSWIDTH 0x08 3872729Sdfr#define RL_CFG2_AUXPWRSTS 0x10 3882729Sdfr 3892729Sdfr#define RL_BUSFREQ_33MHZ 0x00 3902729Sdfr#define RL_BUSFREQ_66MHZ 0x01 3912729Sdfr 3922729Sdfr#define RL_BUSWIDTH_32BITS 0x00 3932729Sdfr#define RL_BUSWIDTH_64BITS 0x08 3942729Sdfr 39534961Sphk/* C+ mode command register */ 3962729Sdfr 3972729Sdfr#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 3982729Sdfr#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 3992729Sdfr#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 4002729Sdfr#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 4012729Sdfr#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 4022729Sdfr#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 4032729Sdfr 4042729Sdfr/* C+ early transmit threshold */ 40530994Sphk 4062729Sdfr#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 4072729Sdfr 4082729Sdfr/* 40912866Speter * Gigabit PHY access register (8169 only) 4102729Sdfr */ 4112729Sdfr 41212866Speter#define RL_PHYAR_PHYDATA 0x0000FFFF 4132729Sdfr#define RL_PHYAR_PHYREG 0x001F0000 4142729Sdfr#define RL_PHYAR_BUSY 0x80000000 4152729Sdfr 41612866Speter/* 4172729Sdfr * Gigabit media status (8169 only) 41812866Speter */ 41930994Sphk#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 4202729Sdfr#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 4212729Sdfr#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 4222729Sdfr#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 4232729Sdfr#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 42412866Speter#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 4252729Sdfr#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 4262729Sdfr#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 4272729Sdfr 4282729Sdfr/* 4292729Sdfr * The RealTek doesn't use a fragment-based descriptor mechanism. 4302729Sdfr * Instead, there are only four register sets, each or which represents 4312729Sdfr * one 'descriptor.' Basically, each TX descriptor is just a contiguous 4322729Sdfr * packet buffer (32-bit aligned!) and we place the buffer addresses in 4332729Sdfr * the registers so the chip knows where they are. 4342729Sdfr * 4352729Sdfr * We can sort of kludge together the same kind of buffer management 4362729Sdfr * used in previous drivers, but we have to do buffer copies almost all 4372729Sdfr * the time, so it doesn't really buy us much. 4382729Sdfr * 4392729Sdfr * For reception, there's just one large buffer where the chip stores 4402729Sdfr * all received packets. 4412729Sdfr */ 4422729Sdfr 4432729Sdfr#define RL_RX_BUF_SZ RL_RXBUF_64 4442729Sdfr#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 4452729Sdfr#define RL_TX_LIST_CNT 4 4462729Sdfr#define RL_MIN_FRAMELEN 60 4472729Sdfr#define RL_TXTHRESH(x) ((x) << 11) 4482729Sdfr#define RL_TX_THRESH_INIT 96 4492729Sdfr#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 4502729Sdfr#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 4512729Sdfr#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 4522729Sdfr 4532729Sdfr#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 4542729Sdfr#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 4552729Sdfr 4562729Sdfr#define RL_ETHER_ALIGN 2 4572729Sdfr 4582729Sdfrstruct rl_chain_data { 4592729Sdfr uint16_t cur_rx; 4602729Sdfr uint8_t *rl_rx_buf; 46146116Sphk uint8_t *rl_rx_buf_ptr; 4622729Sdfr bus_dmamap_t rl_rx_dmamap; 4632729Sdfr 4642729Sdfr struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 4652729Sdfr bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 4662729Sdfr uint8_t last_tx; 4672729Sdfr uint8_t cur_tx; 4682729Sdfr}; 4692729Sdfr 4702729Sdfr#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 4712729Sdfr#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 4722729Sdfr#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 4732729Sdfr#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 4742729Sdfr#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 4752729Sdfr#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 4762729Sdfr#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 4772729Sdfr#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 4782729Sdfr#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 4792729Sdfr 4802729Sdfrstruct rl_type { 4812836Sdg uint16_t rl_vid; 4822729Sdfr uint16_t rl_did; 4832729Sdfr int rl_basetype; 4842729Sdfr char *rl_name; 4852729Sdfr}; 4862729Sdfr 4872729Sdfrstruct rl_hwrev { 4882729Sdfr uint32_t rl_rev; 4892729Sdfr int rl_type; 4902729Sdfr char *rl_desc; 4912729Sdfr}; 4922729Sdfr 4932729Sdfrstruct rl_mii_frame { 4942729Sdfr uint8_t mii_stdelim; 4952729Sdfr uint8_t mii_opcode; 4962729Sdfr uint8_t mii_phyaddr; 4972729Sdfr uint8_t mii_regaddr; 4982729Sdfr uint8_t mii_turnaround; 4992729Sdfr uint16_t mii_data; 5002729Sdfr}; 5012729Sdfr 5022729Sdfr/* 5032729Sdfr * MII constants 5042729Sdfr */ 5052729Sdfr#define RL_MII_STARTDELIM 0x01 5062729Sdfr#define RL_MII_READOP 0x02 5072729Sdfr#define RL_MII_WRITEOP 0x01 5082729Sdfr#define RL_MII_TURNAROUND 0x02 5092729Sdfr 5102729Sdfr#define RL_8129 1 5112729Sdfr#define RL_8139 2 5122729Sdfr#define RL_8139CPLUS 3 5132729Sdfr#define RL_8169 4 5142729Sdfr 5152729Sdfr#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 5162729Sdfr (x)->rl_type == RL_8169) 5172729Sdfr 5182729Sdfr/* 5192729Sdfr * The 8139C+ and 8160 gigE chips support descriptor-based TX 5202729Sdfr * and RX. In fact, they even support TCP large send. Descriptors 5212729Sdfr * must be allocated in contiguous blocks that are aligned on a 5222729Sdfr * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 5232729Sdfr */ 5242729Sdfr 5252729Sdfr/* 5262729Sdfr * RX/TX descriptor definition. When large send mode is enabled, the 5272729Sdfr * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 5282729Sdfr * the checksum offload bits are disabled. The structure layout is 5292729Sdfr * the same for RX and TX descriptors 5302729Sdfr */ 5312729Sdfr 5322729Sdfrstruct rl_desc { 5332729Sdfr uint32_t rl_cmdstat; 5342729Sdfr uint32_t rl_vlanctl; 5352729Sdfr uint32_t rl_bufaddr_lo; 5362729Sdfr uint32_t rl_bufaddr_hi; 5372729Sdfr}; 5382729Sdfr 5392729Sdfr#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 5402729Sdfr#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 5412729Sdfr#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 5422729Sdfr#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 5432729Sdfr#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 5442729Sdfr#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 5452729Sdfr#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 5462729Sdfr#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 5472729Sdfr#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 5482729Sdfr#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 5492729Sdfr 5502729Sdfr#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 5512729Sdfr#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 5522729Sdfr 5532729Sdfr/* 5542729Sdfr * Error bits are valid only on the last descriptor of a frame 5552729Sdfr * (i.e. RL_TDESC_CMD_EOF == 1) 5562729Sdfr */ 5572729Sdfr 5582729Sdfr#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 5592729Sdfr#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 5602729Sdfr#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 5612729Sdfr#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 5622729Sdfr#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 5632729Sdfr#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 5642729Sdfr#define RL_TDESC_STAT_OWN 0x80000000 5652729Sdfr 5662729Sdfr/* 5672729Sdfr * RX descriptor cmd/vlan definitions 5682729Sdfr */ 5692729Sdfr 5702729Sdfr#define RL_RDESC_CMD_EOR 0x40000000 5712729Sdfr#define RL_RDESC_CMD_OWN 0x80000000 5722729Sdfr#define RL_RDESC_CMD_BUFLEN 0x00001FFF 5732729Sdfr 5742729Sdfr#define RL_RDESC_STAT_OWN 0x80000000 5752729Sdfr#define RL_RDESC_STAT_EOR 0x40000000 5762729Sdfr#define RL_RDESC_STAT_SOF 0x20000000 5772729Sdfr#define RL_RDESC_STAT_EOF 0x10000000 5782729Sdfr#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 5792729Sdfr#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 5802729Sdfr#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 5812729Sdfr#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 5822729Sdfr#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 5832729Sdfr#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 5842729Sdfr#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 5852729Sdfr#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 5862729Sdfr#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 5872729Sdfr#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 5882729Sdfr#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 5892729Sdfr#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 5902729Sdfr#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 5912729Sdfr#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 5922729Sdfr#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 5932729Sdfr#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 5942729Sdfr#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 5952729Sdfr RL_RDESC_STAT_CRCERR) 5962729Sdfr 5972729Sdfr#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 5982729Sdfr (rl_vlandata valid)*/ 5992729Sdfr#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 6002729Sdfr 6012729Sdfr#define RL_PROTOID_NONIP 0x00000000 6022729Sdfr#define RL_PROTOID_TCPIP 0x00010000 6032729Sdfr#define RL_PROTOID_UDPIP 0x00020000 6042729Sdfr#define RL_PROTOID_IP 0x00030000 6052729Sdfr#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 6062729Sdfr RL_PROTOID_TCPIP) 6072729Sdfr#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 6082729Sdfr RL_PROTOID_UDPIP) 6092729Sdfr 6102729Sdfr/* 6112729Sdfr * Statistics counter structure (8139C+ and 8169 only) 6122729Sdfr */ 6132729Sdfrstruct rl_stats { 6142729Sdfr uint32_t rl_tx_pkts_lo; 6152729Sdfr uint32_t rl_tx_pkts_hi; 6162729Sdfr uint32_t rl_tx_errs_lo; 6172729Sdfr uint32_t rl_tx_errs_hi; 6182729Sdfr uint32_t rl_tx_errs; 6192729Sdfr uint16_t rl_missed_pkts; 6202729Sdfr uint16_t rl_rx_framealign_errs; 6212729Sdfr uint32_t rl_tx_onecoll; 6222729Sdfr uint32_t rl_tx_multicolls; 6232729Sdfr uint32_t rl_rx_ucasts_hi; 6242729Sdfr uint32_t rl_rx_ucasts_lo; 6252729Sdfr uint32_t rl_rx_bcasts_lo; 6262729Sdfr uint32_t rl_rx_bcasts_hi; 6272729Sdfr uint32_t rl_rx_mcasts; 6282729Sdfr uint16_t rl_tx_aborts; 6292729Sdfr uint16_t rl_rx_underruns; 6302729Sdfr}; 6312729Sdfr 6322729Sdfr/* 6332729Sdfr * Rx/Tx descriptor parameters (8139C+ and 8169 only) 6342729Sdfr * 6352729Sdfr * Tx/Rx count must be equal. Shared code like re_dma_map_desc assumes this. 6362729Sdfr * Buffers must be a multiple of 8 bytes. Currently limit to 64 descriptors 6372729Sdfr * due to the 8139C+. We need to put the number of descriptors in the ring 6382729Sdfr * structure and use that value instead. 6392729Sdfr */ 6402729Sdfr#ifndef __NO_STRICT_ALIGNMENT 6412729Sdfr#define RE_FIXUP_RX 1 6422729Sdfr#endif 6432729Sdfr 6442729Sdfr#define RL_TX_DESC_CNT 64 6452729Sdfr#define RL_RX_DESC_CNT RL_TX_DESC_CNT 6462729Sdfr 6472729Sdfr#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) 6482729Sdfr#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc)) 6492729Sdfr#define RL_RING_ALIGN 256 65017971Sbde#define RL_IFQ_MAXLEN 512 6512729Sdfr#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT) 6522729Sdfr#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 6532729Sdfr#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 6542729Sdfr#define RL_PKTSZ(x) ((x)/* >> 3*/) 6552729Sdfr#ifdef RE_FIXUP_RX 6562729Sdfr#define RE_ETHER_ALIGN sizeof(uint64_t) 6572729Sdfr#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 6582729Sdfr#else 6592729Sdfr#define RE_ETHER_ALIGN 0 6602729Sdfr#define RE_RX_DESC_BUFLEN MCLBYTES 6612729Sdfr#endif 6622729Sdfr 6632729Sdfr#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 6642729Sdfr#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 6652729Sdfr 6662729Sdfr/* see comment in dev/re/if_re.c */ 6672729Sdfr#define RL_JUMBO_FRAMELEN 7440 6682729Sdfr#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 6692729Sdfr 6702729Sdfrstruct rl_softc; 6712729Sdfr 6722729Sdfrstruct rl_dmaload_arg { 6732729Sdfr struct rl_softc *sc; 6742729Sdfr int rl_idx; 6752729Sdfr int rl_maxsegs; 6762729Sdfr uint32_t rl_flags; 6772729Sdfr struct rl_desc *rl_ring; 6782729Sdfr}; 6792729Sdfr 6802729Sdfrstruct rl_list_data { 6812729Sdfr struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT]; 6822729Sdfr struct mbuf *rl_rx_mbuf[RL_RX_DESC_CNT]; 6832729Sdfr int rl_tx_prodidx; 6842729Sdfr int rl_rx_prodidx; 6852729Sdfr int rl_tx_considx; 6862729Sdfr int rl_tx_free; 6872729Sdfr bus_dmamap_t rl_tx_dmamap[RL_TX_DESC_CNT]; 6882729Sdfr bus_dmamap_t rl_rx_dmamap[RL_RX_DESC_CNT]; 6892729Sdfr bus_dma_tag_t rl_mtag; /* mbuf mapping tag */ 6902729Sdfr bus_dma_tag_t rl_stag; /* stats mapping tag */ 6912729Sdfr bus_dmamap_t rl_smap; /* stats map */ 69217971Sbde struct rl_stats *rl_stats; 6932729Sdfr bus_addr_t rl_stats_addr; 6942729Sdfr bus_dma_tag_t rl_rx_list_tag; 6952729Sdfr bus_dmamap_t rl_rx_list_map; 6962729Sdfr struct rl_desc *rl_rx_list; 6972729Sdfr bus_addr_t rl_rx_list_addr; 6982729Sdfr bus_dma_tag_t rl_tx_list_tag; 6992729Sdfr bus_dmamap_t rl_tx_list_map; 7002729Sdfr struct rl_desc *rl_tx_list; 7012729Sdfr bus_addr_t rl_tx_list_addr; 7022729Sdfr}; 7032729Sdfr 7042729Sdfrstruct rl_softc { 7052729Sdfr struct ifnet *rl_ifp; /* interface info */ 7062729Sdfr bus_space_handle_t rl_bhandle; /* bus space handle */ 7072729Sdfr bus_space_tag_t rl_btag; /* bus space tag */ 7082729Sdfr device_t rl_dev; 7092729Sdfr struct resource *rl_res; 7102729Sdfr struct resource *rl_irq; 7112729Sdfr void *rl_intrhand; 7122729Sdfr device_t rl_miibus; 7132729Sdfr bus_dma_tag_t rl_parent_tag; 7142729Sdfr bus_dma_tag_t rl_tag; 7152729Sdfr uint8_t rl_type; 7162729Sdfr int rl_eecmd_read; 7172729Sdfr int rl_eewidth; 7182729Sdfr uint8_t rl_stats_no_timeout; 7192729Sdfr int rl_txthresh; 7202729Sdfr struct rl_chain_data rl_cdata; 7212729Sdfr struct rl_list_data rl_ldata; 7222729Sdfr struct callout rl_stat_callout; 7232729Sdfr struct mtx rl_mtx; 7242729Sdfr struct mbuf *rl_head; 7252729Sdfr struct mbuf *rl_tail; 7262729Sdfr uint32_t rl_hwrev; 7272729Sdfr uint32_t rl_rxlenmask; 7282729Sdfr int rl_testmode; 7292729Sdfr int suspended; /* 0 = normal 1 = suspended */ 7302729Sdfr#ifdef DEVICE_POLLING 7312729Sdfr int rxcycles; 7322729Sdfr#endif 7332729Sdfr 7342729Sdfr struct task rl_txtask; 7352729Sdfr struct task rl_inttask; 73634961Sphk 7372729Sdfr struct mtx rl_intlock; 7382729Sdfr int rl_txstart; 73930994Sphk int rl_link; 7402729Sdfr}; 7412729Sdfr 7422729Sdfr#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 74312866Speter#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 7442729Sdfr#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 7452729Sdfr 7462729Sdfr/* 7472729Sdfr * register space access macros 7482729Sdfr */ 7492729Sdfr#define CSR_WRITE_STREAM_4(sc, reg, val) \ 7502729Sdfr bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 75112866Speter#define CSR_WRITE_4(sc, reg, val) \ 7522729Sdfr bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 75312866Speter#define CSR_WRITE_2(sc, reg, val) \ 75430994Sphk bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 7552729Sdfr#define CSR_WRITE_1(sc, reg, val) \ 7562729Sdfr bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 7572729Sdfr 7582729Sdfr#define CSR_READ_4(sc, reg) \ 7592729Sdfr bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 7602729Sdfr#define CSR_READ_2(sc, reg) \ 7612729Sdfr bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 7622729Sdfr#define CSR_READ_1(sc, reg) \ 7632729Sdfr bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 7642729Sdfr 7652729Sdfr#define CSR_SETBIT_1(sc, offset, val) \ 7662729Sdfr CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 7672729Sdfr 7682729Sdfr#define CSR_CLRBIT_1(sc, offset, val) \ 7692729Sdfr CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 7702729Sdfr 7712729Sdfr#define CSR_SETBIT_2(sc, offset, val) \ 7722729Sdfr CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 7732729Sdfr 7742729Sdfr#define CSR_CLRBIT_2(sc, offset, val) \ 7752729Sdfr CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 7762729Sdfr 7772729Sdfr#define CSR_SETBIT_4(sc, offset, val) \ 7782729Sdfr CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 7792729Sdfr 7802729Sdfr#define CSR_CLRBIT_4(sc, offset, val) \ 7812729Sdfr CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 7822729Sdfr 7832729Sdfr#define RL_TIMEOUT 1000 7842729Sdfr 7852729Sdfr/* 7862729Sdfr * General constants that are fun to know. 7872729Sdfr * 7882729Sdfr * RealTek PCI vendor ID 7892729Sdfr */ 7902729Sdfr#define RT_VENDORID 0x10EC 7912729Sdfr 7922729Sdfr/* 7932729Sdfr * RealTek chip device IDs. 7942729Sdfr */ 7952729Sdfr#define RT_DEVICEID_8129 0x8129 7962729Sdfr#define RT_DEVICEID_8101E 0x8136 7972729Sdfr#define RT_DEVICEID_8138 0x8138 79846116Sphk#define RT_DEVICEID_8139 0x8139 7992729Sdfr#define RT_DEVICEID_8169SC 0x8167 8002729Sdfr#define RT_DEVICEID_8168 0x8168 8012729Sdfr#define RT_DEVICEID_8169 0x8169 8022729Sdfr#define RT_DEVICEID_8100 0x8100 8032729Sdfr 8042729Sdfr#define RT_REVID_8139CPLUS 0x20 8052729Sdfr 8062729Sdfr/* 8072729Sdfr * Accton PCI vendor ID 8082729Sdfr */ 8092729Sdfr#define ACCTON_VENDORID 0x1113 8102729Sdfr 8112729Sdfr/* 8122729Sdfr * Accton MPX 5030/5038 device ID. 8132729Sdfr */ 8142729Sdfr#define ACCTON_DEVICEID_5030 0x1211 8152729Sdfr 8162729Sdfr/* 8172729Sdfr * Nortel PCI vendor ID 8182729Sdfr */ 8192729Sdfr#define NORTEL_VENDORID 0x126C 8202729Sdfr 8212729Sdfr/* 8222729Sdfr * Delta Electronics Vendor ID. 8232729Sdfr */ 8242729Sdfr#define DELTA_VENDORID 0x1500 8252729Sdfr 8262729Sdfr/* 8272729Sdfr * Delta device IDs. 8282729Sdfr */ 8292729Sdfr#define DELTA_DEVICEID_8139 0x1360 8302729Sdfr 8312729Sdfr/* 8322729Sdfr * Addtron vendor ID. 8332729Sdfr */ 8342729Sdfr#define ADDTRON_VENDORID 0x4033 8352729Sdfr 8362729Sdfr/* 8372729Sdfr * Addtron device IDs. 8382729Sdfr */ 8392729Sdfr#define ADDTRON_DEVICEID_8139 0x1360 8402729Sdfr 8412729Sdfr/* 8422729Sdfr * D-Link vendor ID. 8432729Sdfr */ 8442729Sdfr#define DLINK_VENDORID 0x1186 8452729Sdfr 8462729Sdfr/* 8472729Sdfr * D-Link DFE-530TX+ device ID 8482729Sdfr */ 8492729Sdfr#define DLINK_DEVICEID_530TXPLUS 0x1300 8502729Sdfr 8512729Sdfr/* 8522729Sdfr * D-Link DFE-5280T device ID 8532729Sdfr */ 8542729Sdfr#define DLINK_DEVICEID_528T 0x4300 8552729Sdfr 8562729Sdfr/* 8572729Sdfr * D-Link DFE-690TXD device ID 8582729Sdfr */ 8592729Sdfr#define DLINK_DEVICEID_690TXD 0x1340 8602729Sdfr 8612729Sdfr/* 8622729Sdfr * Corega K.K vendor ID 8632729Sdfr */ 8642729Sdfr#define COREGA_VENDORID 0x1259 8652729Sdfr 8662729Sdfr/* 8672729Sdfr * Corega FEther CB-TXD device ID 8682729Sdfr */ 8692729Sdfr#define COREGA_DEVICEID_FETHERCBTXD 0xa117 8702729Sdfr 8712729Sdfr/* 8722729Sdfr * Corega FEtherII CB-TXD device ID 8732729Sdfr */ 8742729Sdfr#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 8752729Sdfr 8762729Sdfr/* 8772729Sdfr * Corega CG-LAPCIGT device ID 8782729Sdfr */ 8792729Sdfr#define COREGA_DEVICEID_CGLAPCIGT 0xc107 8802729Sdfr 8812729Sdfr/* 8822729Sdfr * Linksys vendor ID 8832729Sdfr */ 8842729Sdfr#define LINKSYS_VENDORID 0x1737 8852729Sdfr 8862729Sdfr/* 8872729Sdfr * Linksys EG1032 device ID 8882729Sdfr */ 8892729Sdfr#define LINKSYS_DEVICEID_EG1032 0x1032 8902729Sdfr 8912729Sdfr/* 8922729Sdfr * Linksys EG1032 rev 3 sub-device ID 8932729Sdfr */ 8942729Sdfr#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 8952729Sdfr 8962729Sdfr/* 8972729Sdfr * Peppercon vendor ID 8982729Sdfr */ 8992729Sdfr#define PEPPERCON_VENDORID 0x1743 9002729Sdfr 9012729Sdfr/* 9022729Sdfr * Peppercon ROL-F device ID 9032729Sdfr */ 9042729Sdfr#define PEPPERCON_DEVICEID_ROLF 0x8139 9052729Sdfr 9062729Sdfr/* 9072729Sdfr * Planex Communications, Inc. vendor ID 9082729Sdfr */ 9092729Sdfr#define PLANEX_VENDORID 0x14ea 9102729Sdfr 9112729Sdfr/* 9122729Sdfr * Planex FNW-3800-TX device ID 9132729Sdfr */ 9142729Sdfr#define PLANEX_DEVICEID_FNW3800TX 0xab07 9152729Sdfr 9162729Sdfr/* 9172729Sdfr * LevelOne vendor ID 9182729Sdfr */ 9192729Sdfr#define LEVEL1_VENDORID 0x018A 9202729Sdfr 9212729Sdfr/* 9222729Sdfr * LevelOne FPC-0106TX devide ID 9232729Sdfr */ 9242729Sdfr#define LEVEL1_DEVICEID_FPC0106TX 0x0106 9252729Sdfr 9262729Sdfr/* 9272729Sdfr * Compaq vendor ID 9282729Sdfr */ 9292729Sdfr#define CP_VENDORID 0x021B 9302729Sdfr 9312729Sdfr/* 9322729Sdfr * Edimax vendor ID 9332729Sdfr */ 9342729Sdfr#define EDIMAX_VENDORID 0x13D1 9352729Sdfr 9362729Sdfr/* 9372729Sdfr * Edimax EP-4103DL cardbus device ID 9382729Sdfr */ 9392729Sdfr#define EDIMAX_DEVICEID_EP4103DL 0xAB06 9402729Sdfr 9412729Sdfr/* US Robotics vendor ID */ 9422729Sdfr 9432729Sdfr#define USR_VENDORID 0x16EC 9442729Sdfr 9452729Sdfr/* US Robotics 997902 device ID */ 9462729Sdfr 9472729Sdfr#define USR_DEVICEID_997902 0x0116 9482729Sdfr 9492729Sdfr/* 9502729Sdfr * PCI low memory base and low I/O base register, and 9512729Sdfr * other PCI registers. 9522729Sdfr */ 9532729Sdfr 9542729Sdfr#define RL_PCI_VENDOR_ID 0x00 9552729Sdfr#define RL_PCI_DEVICE_ID 0x02 9562729Sdfr#define RL_PCI_COMMAND 0x04 95734961Sphk#define RL_PCI_STATUS 0x06 9582729Sdfr#define RL_PCI_CLASSCODE 0x09 9592729Sdfr#define RL_PCI_LATENCY_TIMER 0x0D 9602729Sdfr#define RL_PCI_HEADER_TYPE 0x0E 9612729Sdfr#define RL_PCI_LOIO 0x10 9622729Sdfr#define RL_PCI_LOMEM 0x14 9632729Sdfr#define RL_PCI_BIOSROM 0x30 9642729Sdfr#define RL_PCI_INTLINE 0x3C 9652729Sdfr#define RL_PCI_INTPIN 0x3D 9662729Sdfr#define RL_PCI_MINGNT 0x3E 9672729Sdfr#define RL_PCI_MINLAT 0x0F 9682729Sdfr#define RL_PCI_RESETOPT 0x48 9692729Sdfr#define RL_PCI_EEPROM_DATA 0x4C 9702729Sdfr 9712729Sdfr#define RL_PCI_CAPID 0x50 /* 8 bits */ 9722729Sdfr#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 9732729Sdfr#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 9742729Sdfr#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 9752729Sdfr 9762729Sdfr#define RL_PSTATE_MASK 0x0003 9772729Sdfr#define RL_PSTATE_D0 0x0000 9782729Sdfr#define RL_PSTATE_D1 0x0002 9792729Sdfr#define RL_PSTATE_D2 0x0002 9802729Sdfr#define RL_PSTATE_D3 0x0003 9812729Sdfr#define RL_PME_EN 0x0010 9822729Sdfr#define RL_PME_STATUS 0x8000 9832729Sdfr