if_rlreg.h revision 140642
1131509Stjr/*- 21590Srgrimes * Copyright (c) 1997, 1998-2003 31590Srgrimes * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 41590Srgrimes * 51590Srgrimes * Redistribution and use in source and binary forms, with or without 61590Srgrimes * modification, are permitted provided that the following conditions 71590Srgrimes * are met: 81590Srgrimes * 1. Redistributions of source code must retain the above copyright 91590Srgrimes * notice, this list of conditions and the following disclaimer. 101590Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 111590Srgrimes * notice, this list of conditions and the following disclaimer in the 121590Srgrimes * documentation and/or other materials provided with the distribution. 131590Srgrimes * 3. All advertising materials mentioning features or use of this software 141590Srgrimes * must display the following acknowledgement: 151590Srgrimes * This product includes software developed by Bill Paul. 161590Srgrimes * 4. Neither the name of the author nor the names of any co-contributors 171590Srgrimes * may be used to endorse or promote products derived from this software 181590Srgrimes * without specific prior written permission. 191590Srgrimes * 201590Srgrimes * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 211590Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 221590Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 231590Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 241590Srgrimes * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 251590Srgrimes * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 261590Srgrimes * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 271590Srgrimes * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 281590Srgrimes * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 291590Srgrimes * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 301590Srgrimes * THE POSSIBILITY OF SUCH DAMAGE. 3123695Speter * 3250477Speter * $FreeBSD: head/sys/pci/if_rlreg.h 140642 2005-01-22 22:40:53Z imp $ 331590Srgrimes */ 34264411Sjilles 351590Srgrimes/* 361590Srgrimes * RealTek 8129/8139 register offsets 371590Srgrimes */ 381590Srgrimes#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 391590Srgrimes#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 401590Srgrimes#define RL_IDR2 0x0002 4168963Sru#define RL_IDR3 0x0003 421590Srgrimes#define RL_IDR4 0x0004 4372945Sknu#define RL_IDR5 0x0005 44176761Sru /* 0006-0007 reserved */ 45176761Sru#define RL_MAR0 0x0008 /* Multicast hash table */ 46176761Sru#define RL_MAR1 0x0009 47160466Sstefanf#define RL_MAR2 0x000A 48160466Sstefanf#define RL_MAR3 0x000B 49160466Sstefanf#define RL_MAR4 0x000C 50176761Sru#define RL_MAR5 0x000D 51176761Sru#define RL_MAR6 0x000E 52176761Sru#define RL_MAR7 0x000F 531590Srgrimes 5495124Scharnier#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 5595124Scharnier#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 5695124Scharnier#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57176761Sru#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 581590Srgrimes 591590Srgrimes#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 6076681Sru#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 6176681Sru#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 6276681Sru#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6376681Sru 6476681Sru#define RL_RXADDR 0x0030 /* RX ring start address */ 651590Srgrimes#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 661590Srgrimes#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 671590Srgrimes#define RL_COMMAND 0x0037 /* command register */ 6876681Sru#define RL_CURRXADDR 0x0038 /* current address of packet read */ 6972945Sknu#define RL_CURRXBUF 0x003A /* current RX buffer address */ 7072945Sknu#define RL_IMR 0x003C /* interrupt mask register */ 7172945Sknu#define RL_ISR 0x003E /* interrupt status register */ 7272945Sknu#define RL_TXCFG 0x0040 /* transmit config */ 7372945Sknu#define RL_RXCFG 0x0044 /* receive config */ 74167102Sru#define RL_TIMERCNT 0x0048 /* timer count register */ 7576681Sru#define RL_MISSEDPKT 0x004C /* missed packet counter */ 7676681Sru#define RL_EECMD 0x0050 /* EEPROM command register */ 7772945Sknu#define RL_CFG0 0x0051 /* config register #0 */ 7872945Sknu#define RL_CFG1 0x0052 /* config register #1 */ 791590Srgrimes /* 0053-0057 reserved */ 80102498Scharnier#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 8157666Snik /* 0059-005A reserved */ 8276681Sru#define RL_MII 0x005A /* 8129 chip only */ 831590Srgrimes#define RL_HALTCLK 0x005B 841590Srgrimes#define RL_MULTIINTR 0x005C /* multiple interrupt */ 8541402Sbde#define RL_PCIREV 0x005E /* PCI revision value */ 8676681Sru /* 005F reserved */ 871590Srgrimes#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 881590Srgrimes 89102498Scharnier/* Direct PHY access registers only available on 8139 */ 9057666Snik#define RL_BMCR 0x0062 /* PHY basic mode control */ 911590Srgrimes#define RL_BMSR 0x0064 /* PHY basic mode status */ 921590Srgrimes#define RL_ANAR 0x0066 /* PHY autoneg advert */ 931590Srgrimes#define RL_LPAR 0x0068 /* PHY link partner ability */ 941590Srgrimes#define RL_ANER 0x006A /* PHY autoneg expansion */ 95128505Sdes 96128505Sdes#define RL_DISCCNT 0x006C /* disconnect counter */ 97128505Sdes#define RL_FALSECAR 0x006E /* false carrier counter */ 98128505Sdes#define RL_NWAYTST 0x0070 /* NWAY test register */ 991590Srgrimes#define RL_RX_ER 0x0072 /* RX_ER counter */ 100102498Scharnier#define RL_CSCFG 0x0074 /* CS configuration register */ 10157666Snik 1021590Srgrimes/* 10325941Sjdp * When operating in special C+ mode, some of the registers in an 1041590Srgrimes * 8139C+ chip have different definitions. These are also used for 105102498Scharnier * the 8169 gigE chip. 1061590Srgrimes */ 1071590Srgrimes#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 1081590Srgrimes#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 1091590Srgrimes#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 11076681Sru#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 1111590Srgrimes#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 1121590Srgrimes#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 11376681Sru#define RL_CFG2 0x0053 11476681Sru#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 11576681Sru#define RL_TXSTART 0x00D9 /* 8 bits */ 11676681Sru#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 11776681Sru#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 11876681Sru#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 11976681Sru#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 12094366Strhodes 12194366Strhodes/* 12294366Strhodes * Registers specific to the 8169 gigE chip 12394366Strhodes */ 12497496Sru#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 12594366Strhodes#define RL_PHYAR 0x0060 1261590Srgrimes#define RL_TBICSR 0x0064 127102498Scharnier#define RL_TBI_ANAR 0x0068 12868963Sru#define RL_TBI_LPAR 0x006A 129237035Sjilles#define RL_GMEDIASTAT 0x006C /* 8 bits */ 130128505Sdes#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 131237035Sjilles#define RL_GTXSTART 0x0038 /* 16 bits */ 132128505Sdes 133237035Sjilles/* 134129812Seik * TX config register bits 135237035Sjilles */ 136237035Sjilles#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 137237035Sjilles#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 13841391Swosch#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 139102498Scharnier#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 14068963Sru#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 14141402Sbde#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 14241402Sbde#define RL_TXCFG_HWREV 0x7CC00000 14376681Sru 14476681Sru#define RL_LOOPTEST_OFF 0x00000000 14576681Sru#define RL_LOOPTEST_ON 0x00020000 14676681Sru#define RL_LOOPTEST_ON_CPLUS 0x00060000 14741391Swosch 1481590Srgrimes#define RL_HWREV_8169 0x00000000 149102498Scharnier#define RL_HWREV_8169S 0x04000000 15068963Sru#define RL_HWREV_8169SB 0x10000000 1511590Srgrimes#define RL_HWREV_8110S 0x00800000 1521590Srgrimes#define RL_HWREV_8139 0x60000000 153128505Sdes#define RL_HWREV_8139A 0x70000000 154128505Sdes#define RL_HWREV_8139AG 0x70800000 155128505Sdes#define RL_HWREV_8139B 0x78000000 156128505Sdes#define RL_HWREV_8130 0x7C000000 1571590Srgrimes#define RL_HWREV_8139C 0x74000000 1581590Srgrimes#define RL_HWREV_8139D 0x74400000 159219455Sgjb#define RL_HWREV_8139CPLUS 0x74800000 160219455Sgjb#define RL_HWREV_8101 0x74c00000 161219455Sgjb#define RL_HWREV_8100 0x78800000 162219455Sgjb 163219455Sgjb#define RL_TXDMA_16BYTES 0x00000000 164219455Sgjb#define RL_TXDMA_32BYTES 0x00000100 165219455Sgjb#define RL_TXDMA_64BYTES 0x00000200 166219455Sgjb#define RL_TXDMA_128BYTES 0x00000300 167219455Sgjb#define RL_TXDMA_256BYTES 0x00000400 168219455Sgjb#define RL_TXDMA_512BYTES 0x00000500 169219455Sgjb#define RL_TXDMA_1024BYTES 0x00000600 17076681Sru#define RL_TXDMA_2048BYTES 0x00000700 171157440Sceri 172157440Sceri/* 173157440Sceri * Transmit descriptor status register bits. 174157440Sceri */ 175157440Sceri#define RL_TXSTAT_LENMASK 0x00001FFF 176157440Sceri#define RL_TXSTAT_OWN 0x00002000 177157440Sceri#define RL_TXSTAT_TX_UNDERRUN 0x00004000 178157440Sceri#define RL_TXSTAT_TX_OK 0x00008000 179157440Sceri#define RL_TXSTAT_EARLY_THRESH 0x003F0000 180157440Sceri#define RL_TXSTAT_COLLCNT 0x0F000000 181157440Sceri#define RL_TXSTAT_CARR_HBEAT 0x10000000 182157440Sceri#define RL_TXSTAT_OUTOFWIN 0x20000000 183157440Sceri#define RL_TXSTAT_TXABRT 0x40000000 184157440Sceri#define RL_TXSTAT_CARRLOSS 0x80000000 185157440Sceri 186157440Sceri/* 187157440Sceri * Interrupt status register bits. 188157440Sceri */ 189157440Sceri#define RL_ISR_RX_OK 0x0001 190157440Sceri#define RL_ISR_RX_ERR 0x0002 191165179Sru#define RL_ISR_TX_OK 0x0004 192165179Sru#define RL_ISR_TX_ERR 0x0008 193157440Sceri#define RL_ISR_RX_OVERRUN 0x0010 194157440Sceri#define RL_ISR_PKT_UNDERRUN 0x0020 195157440Sceri#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 196157440Sceri#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 197157440Sceri#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 198157440Sceri#define RL_ISR_SWI 0x0100 /* C+ only */ 199157440Sceri#define RL_ISR_CABLE_LEN_CHGD 0x2000 200128010Strhodes#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 201167102Sru#define RL_ISR_TIMEOUT_EXPIRED 0x4000 202128010Strhodes#define RL_ISR_SYSTEM_ERR 0x8000 203128010Strhodes 204128010Strhodes#define RL_INTRS \ 205128010Strhodes (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 206243239Seadler RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 20730395Swosch RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 20868963Sru 20968866Smph#define RL_INTRS_CPLUS \ 210243239Seadler (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 21130395Swosch RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 212243239Seadler RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 213243239Seadler 214243239Seadler/* 215243239Seadler * Media status register. (8139 only) 216243239Seadler */ 217243239Seadler#define RL_MEDIASTAT_RXPAUSE 0x01 218243239Seadler#define RL_MEDIASTAT_TXPAUSE 0x02 21976250Sphk#define RL_MEDIASTAT_LINK 0x04 22076250Sphk#define RL_MEDIASTAT_SPEED10 0x08 22176681Sru#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 22283450Sru#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 22383450Sru 22483450Sru/* 22568963Sru * Receive config register. 226129428Sru */ 2271590Srgrimes#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 228129428Sru#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 22983450Sru#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 23083450Sru#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 23183450Sru#define RL_RXCFG_RX_RUNT 0x00000010 23283450Sru#define RL_RXCFG_RX_ERRPKT 0x00000020 23383450Sru#define RL_RXCFG_WRAP 0x00000080 23483450Sru#define RL_RXCFG_MAXDMA 0x00000700 23583450Sru#define RL_RXCFG_BUFSZ 0x00001800 23683450Sru#define RL_RXCFG_FIFOTHRESH 0x0000E000 23783450Sru#define RL_RXCFG_EARLYTHRESH 0x07000000 23883450Sru 23983450Sru#define RL_RXDMA_16BYTES 0x00000000 24083450Sru#define RL_RXDMA_32BYTES 0x00000100 24183450Sru#define RL_RXDMA_64BYTES 0x00000200 24283450Sru#define RL_RXDMA_128BYTES 0x00000300 24383450Sru#define RL_RXDMA_256BYTES 0x00000400 24483450Sru#define RL_RXDMA_512BYTES 0x00000500 24583450Sru#define RL_RXDMA_1024BYTES 0x00000600 24683450Sru#define RL_RXDMA_UNLIMITED 0x00000700 24783450Sru 24883450Sru#define RL_RXBUF_8 0x00000000 24983450Sru#define RL_RXBUF_16 0x00000800 25083450Sru#define RL_RXBUF_32 0x00001000 25183450Sru#define RL_RXBUF_64 0x00001800 25283450Sru 25383450Sru#define RL_RXFIFO_16BYTES 0x00000000 25483450Sru#define RL_RXFIFO_32BYTES 0x00002000 25583450Sru#define RL_RXFIFO_64BYTES 0x00004000 25683450Sru#define RL_RXFIFO_128BYTES 0x00006000 25783450Sru#define RL_RXFIFO_256BYTES 0x00008000 25883450Sru#define RL_RXFIFO_512BYTES 0x0000A000 25983450Sru#define RL_RXFIFO_1024BYTES 0x0000C000 260243239Seadler#define RL_RXFIFO_NOTHRESH 0x0000E000 26130395Swosch 26230395Swosch/* 26368963Sru * Bits in RX status header (included with RX'ed packet 26468866Smph * in ring buffer). 265243239Seadler */ 26630395Swosch#define RL_RXSTAT_RXOK 0x00000001 267243239Seadler#define RL_RXSTAT_ALIGNERR 0x00000002 268243239Seadler#define RL_RXSTAT_CRCERR 0x00000004 269243239Seadler#define RL_RXSTAT_GIANT 0x00000008 270243239Seadler#define RL_RXSTAT_RUNT 0x00000010 271243239Seadler#define RL_RXSTAT_BADSYM 0x00000020 272243239Seadler#define RL_RXSTAT_BROAD 0x00002000 273243239Seadler#define RL_RXSTAT_INDIV 0x00004000 27476250Sphk#define RL_RXSTAT_MULTI 0x00008000 27576250Sphk#define RL_RXSTAT_LENMASK 0xFFFF0000 27676681Sru 27783450Sru#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 27883450Sru/* 27983450Sru * Command register. 2801590Srgrimes */ 28168963Sru#define RL_CMD_EMPTY_RXBUF 0x0001 282129428Sru#define RL_CMD_TX_ENB 0x0004 2831590Srgrimes#define RL_CMD_RX_ENB 0x0008 284129428Sru#define RL_CMD_RESET 0x0010 28583450Sru 28683450Sru/* 28783450Sru * EEPROM control register 28883450Sru */ 28983450Sru#define RL_EE_DATAOUT 0x01 /* Data out */ 29083450Sru#define RL_EE_DATAIN 0x02 /* Data in */ 29183450Sru#define RL_EE_CLK 0x04 /* clock */ 29283450Sru#define RL_EE_SEL 0x08 /* chip select */ 29383450Sru#define RL_EE_MODE (0x40|0x80) 29483450Sru 29583450Sru#define RL_EEMODE_OFF 0x00 296176478Simp#define RL_EEMODE_AUTOLOAD 0x40 297236860Sissyl0#define RL_EEMODE_PROGRAM 0x80 298176478Simp#define RL_EEMODE_WRITECFG (0x80|0x40) 299176478Simp 300176478Simp/* 9346 EEPROM commands */ 301243280Seadler#define RL_EECMD_WRITE 0x140 30218681Speter#define RL_EECMD_READ_6BIT 0x180 30341402Sbde#define RL_EECMD_READ_8BIT 0x600 30441402Sbde#define RL_EECMD_ERASE 0x1c0 30541402Sbde 30618681Speter#define RL_EE_ID 0x00 30718681Speter#define RL_EE_PCI_VID 0x01 30841402Sbde#define RL_EE_PCI_DID 0x02 30976681Sru/* Location of station address inside EEPROM */ 31076681Sru#define RL_EE_EADDR 0x07 31176681Sru 31276681Sru/* 31376681Sru * MII register (8129 only) 314129428Sru */ 315236433Seadler#define RL_MII_CLK 0x01 316236433Seadler#define RL_MII_DATAIN 0x02 317236433Seadler#define RL_MII_DATAOUT 0x04 318197363Sjilles#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 31984595Sobrien 32084595Sobrien/* 321236860Sissyl0 * Config 0 register 32284595Sobrien */ 323237035Sjilles#define RL_CFG0_ROM0 0x01 324237035Sjilles#define RL_CFG0_ROM1 0x02 325237035Sjilles#define RL_CFG0_ROM2 0x04 326237035Sjilles#define RL_CFG0_PL0 0x08 327237035Sjilles#define RL_CFG0_PL1 0x10 328237035Sjilles#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 329237035Sjilles#define RL_CFG0_PCS 0x40 330237035Sjilles#define RL_CFG0_SCR 0x80 331237035Sjilles 332237035Sjilles/* 333237035Sjilles * Config 1 register 334237035Sjilles */ 335237035Sjilles#define RL_CFG1_PWRDWN 0x01 336237035Sjilles#define RL_CFG1_SLEEP 0x02 337237035Sjilles#define RL_CFG1_IOMAP 0x04 338237035Sjilles#define RL_CFG1_MEMMAP 0x08 339237035Sjilles#define RL_CFG1_RSVD 0x10 340237035Sjilles#define RL_CFG1_DRVLOAD 0x20 341237035Sjilles#define RL_CFG1_LED0 0x40 342237035Sjilles#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 343237035Sjilles#define RL_CFG1_LED1 0x80 344237035Sjilles 345237035Sjilles/* 346129812Seik * 8139C+ register definitions 347129812Seik */ 348131754Sru 349129812Seik/* RL_DUMPSTATS_LO register */ 35071422Speter 35171422Speter#define RL_DUMPSTATS_START 0x00000008 352131754Sru 3531590Srgrimes/* Transmit start register */ 3541590Srgrimes 3551590Srgrimes#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 35676681Sru#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 35776681Sru#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 35876681Sru 35976681Sru/* 36076681Sru * Config 2 register, 8139C+/8169/8169S/8110S only 361118021Sschweikh */ 362118021Sschweikh#define RL_CFG2_BUSFREQ 0x07 363118021Sschweikh#define RL_CFG2_BUSWIDTH 0x08 364118021Sschweikh#define RL_CFG2_AUXPWRSTS 0x10 36576681Sru 36676681Sru#define RL_BUSFREQ_33MHZ 0x00 36776681Sru#define RL_BUSFREQ_66MHZ 0x01 3681590Srgrimes 3691590Srgrimes#define RL_BUSWIDTH_32BITS 0x00 3701590Srgrimes#define RL_BUSWIDTH_64BITS 0x08 37168963Sru 3721590Srgrimes/* C+ mode command register */ 37378966Syar 37478966Syar#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 37578966Syar#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 37678966Syar#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 37778966Syar#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 378107261Sru#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 37997736Stjr#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 38097736Stjr 38197736Stjr/* C+ early transmit threshold */ 38297736Stjr 38397736Stjr#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 38497736Stjr 38597736Stjr/* 38697736Stjr * Gigabit PHY access register (8169 only) 387264387Sjilles */ 388264387Sjilles 389264387Sjilles#define RL_PHYAR_PHYDATA 0x0000FFFF 390264387Sjilles#define RL_PHYAR_PHYREG 0x001F0000 391264387Sjilles#define RL_PHYAR_BUSY 0x80000000 392264387Sjilles 393107261Sru/* 39428914Simp * Gigabit media status (8169 only) 39576681Sru */ 39628914Simp#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 39728914Simp#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 39828914Simp#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 39976681Sru#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 40028914Simp#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 40141402Sbde#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 40241402Sbde#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 40376681Sru#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 40476681Sru 40576681Sru/* 406176478Simp * The RealTek doesn't use a fragment-based descriptor mechanism. 407176478Simp * Instead, there are only four register sets, each or which represents 408176478Simp * one 'descriptor.' Basically, each TX descriptor is just a contiguous 409176478Simp * packet buffer (32-bit aligned!) and we place the buffer addresses in 410176478Simp * the registers so the chip knows where they are. 411176478Simp * 412176478Simp * We can sort of kludge together the same kind of buffer management 413176478Simp * used in previous drivers, but we have to do buffer copies almost all 414176478Simp * the time, so it doesn't really buy us much. 415264387Sjilles * 416264387Sjilles * For reception, there's just one large buffer where the chip stores 417264387Sjilles * all received packets. 418264387Sjilles */ 419264387Sjilles 420264387Sjilles#define RL_RX_BUF_SZ RL_RXBUF_64 42182972Sru#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 42282972Sru#define RL_TX_LIST_CNT 4 42382972Sru#define RL_MIN_FRAMELEN 60 42482972Sru#define RL_TXTHRESH(x) ((x) << 11) 42582972Sru#define RL_TX_THRESH_INIT 96 42682972Sru#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 42782972Sru#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 42882972Sru#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 42982972Sru 43082972Sru#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 43182662Sru#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 43282972Sru 43382972Sru#define RL_ETHER_ALIGN 2 43482972Sru 43582972Srustruct rl_chain_data { 43682972Sru uint16_t cur_rx; 43782972Sru uint8_t *rl_rx_buf; 43882972Sru uint8_t *rl_rx_buf_ptr; 43982972Sru bus_dmamap_t rl_rx_dmamap; 44082662Sru 44182972Sru struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 44282972Sru bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 44382662Sru uint8_t last_tx; 44482972Sru uint8_t cur_tx; 44582972Sru}; 44682972Sru 44782972Sru#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 44882972Sru#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 44982972Sru#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 45082972Sru#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 45182972Sru#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 45282972Sru#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 45382972Sru#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 45482972Sru#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 45582972Sru#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 45682972Sru 45782972Srustruct rl_type { 45882972Sru uint16_t rl_vid; 45982972Sru uint16_t rl_did; 46082972Sru int rl_basetype; 46182972Sru char *rl_name; 46282972Sru}; 46382972Sru 46482972Srustruct rl_hwrev { 46576681Sru uint32_t rl_rev; 466107788Sru int rl_type; 4671590Srgrimes char *rl_desc; 46823695Speter}; 469205233Spjd 470107788Srustruct rl_mii_frame { 471205233Spjd uint8_t mii_stdelim; 47276681Sru uint8_t mii_opcode; 47376681Sru uint8_t mii_phyaddr; 47476681Sru uint8_t mii_regaddr; 47576681Sru uint8_t mii_turnaround; 476107788Sru uint16_t mii_data; 4771590Srgrimes}; 47868963Sru 479107788Sru/* 4801590Srgrimes * MII constants 481176478Simp */ 482176478Simp#define RL_MII_STARTDELIM 0x01 483233648Seadler#define RL_MII_READOP 0x02 484176478Simp#define RL_MII_WRITEOP 0x01 485176478Simp#define RL_MII_TURNAROUND 0x02 486233648Seadler 487176478Simp#define RL_8129 1 488243280Seadler#define RL_8139 2 489176478Simp#define RL_8139CPLUS 3 49076681Sru#define RL_8169 4 4911590Srgrimes 49276681Sru#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 4931590Srgrimes (x)->rl_type == RL_8169) 4941590Srgrimes 4951590Srgrimes/* 4961590Srgrimes * The 8139C+ and 8160 gigE chips support descriptor-based TX 49776681Sru * and RX. In fact, they even support TCP large send. Descriptors 498176478Simp * must be allocated in contiguous blocks that are aligned on a 499238780Sjilles * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 500238780Sjilles */ 501238780Sjilles 502176478Simp/* 503176478Simp * RX/TX descriptor definition. When large send mode is enabled, the 504176478Simp * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 505176478Simp * the checksum offload bits are disabled. The structure layout is 506176531Simp * the same for RX and TX descriptors 50782662Sru */ 50882662Sru 50982662Srustruct rl_desc { 51082662Sru uint32_t rl_cmdstat; 51176681Sru uint32_t rl_vlanctl; 5121590Srgrimes uint32_t rl_bufaddr_lo; 51376681Sru uint32_t rl_bufaddr_hi; 51482662Sru}; 51582662Sru 51682662Sru#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 51782662Sru#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 51882662Sru#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 51982662Sru#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 52082662Sru#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 52182662Sru#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 522176478Simp#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 523233648Seadler#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 524176478Simp#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 525176478Simp#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 52676681Sru 5271590Srgrimes#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 5281590Srgrimes#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 5291590Srgrimes 530176478Simp/* 531176478Simp * Error bits are valid only on the last descriptor of a frame 532176478Simp * (i.e. RL_TDESC_CMD_EOF == 1) 533176531Simp */ 534176531Simp 535260355Sjilles#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 536260355Sjilles#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 537176531Simp#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 5381590Srgrimes#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 5391590Srgrimes#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 5401590Srgrimes#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 541129428Sru#define RL_TDESC_STAT_OWN 0x80000000 5421590Srgrimes 543225847Sed/* 5441590Srgrimes * RX descriptor cmd/vlan definitions 545129428Sru */ 54676681Sru 54776681Sru#define RL_RDESC_CMD_EOR 0x40000000 54876681Sru#define RL_RDESC_CMD_OWN 0x80000000 54976681Sru#define RL_RDESC_CMD_BUFLEN 0x00001FFF 550167102Sru 55176681Sru#define RL_RDESC_STAT_OWN 0x80000000 55261575Sroberto#define RL_RDESC_STAT_EOR 0x40000000 553129273Seik#define RL_RDESC_STAT_SOF 0x20000000 554129273Seik#define RL_RDESC_STAT_EOF 0x10000000 555129273Seik#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 556129211Seik#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 557129211Seik#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 558129211Seik#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 559129211Seik#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 560167102Sru#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 561129211Seik#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 56261575Sroberto#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 563129273Seik#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 564129273Seik#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 565129211Seik#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 566129211Seik#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 567129211Seik#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 568129211Seik#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 569167102Sru#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 570129211Seik#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 571243239Seadler#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 57230395Swosch RL_RDESC_STAT_CRCERR) 57368963Sru 57468866Smph#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 57530395Swosch (rl_vlandata valid)*/ 576243239Seadler#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 577243239Seadler 578243239Seadler#define RL_PROTOID_NONIP 0x00000000 579243239Seadler#define RL_PROTOID_TCPIP 0x00010000 580243239Seadler#define RL_PROTOID_UDPIP 0x00020000 581243239Seadler#define RL_PROTOID_IP 0x00030000 582243239Seadler#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 58382662Sru RL_PROTOID_TCPIP) 58482662Sru#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 58582662Sru RL_PROTOID_UDPIP) 586176478Simp 587233648Seadler/* 588176478Simp * Statistics counter structure (8139C+ and 8169 only) 589176478Simp */ 59083450Srustruct rl_stats { 59183450Sru uint32_t rl_tx_pkts_lo; 59283450Sru uint32_t rl_tx_pkts_hi; 59368963Sru uint32_t rl_tx_errs_lo; 594129428Sru uint32_t rl_tx_errs_hi; 5951590Srgrimes uint32_t rl_tx_errs; 596129428Sru uint16_t rl_missed_pkts; 59783450Sru uint16_t rl_rx_framealign_errs; 59883450Sru uint32_t rl_tx_onecoll; 59983450Sru uint32_t rl_tx_multicolls; 60083450Sru uint32_t rl_rx_ucasts_hi; 60183450Sru uint32_t rl_rx_ucasts_lo; 60283450Sru uint32_t rl_rx_bcasts_lo; 60383450Sru uint32_t rl_rx_bcasts_hi; 60483450Sru uint32_t rl_rx_mcasts; 60583450Sru uint16_t rl_tx_aborts; 60683450Sru uint16_t rl_rx_underruns; 60776681Sru}; 6081590Srgrimes 60976681Sru/* 61076681Sru * Rx/Tx descriptor parameters (8139C+ and 8169 only) 61176681Sru * 61276681Sru * Tx/Rx count must be equal. Shared code like re_dma_map_desc assumes this. 61376681Sru * Buffers must be a multiple of 8 bytes. Currently limit to 64 descriptors 61476681Sru * due to the 8139C+. We need to put the number of descriptors in the ring 61576681Sru * structure and use that value instead. 6161590Srgrimes */ 61776681Sru#if !defined(__i386__) && !defined(__amd64__) 6181590Srgrimes#define RE_FIXUP_RX 1 61976681Sru#endif 62076681Sru 62176681Sru#define RL_TX_DESC_CNT 64 6221590Srgrimes#define RL_RX_DESC_CNT RL_TX_DESC_CNT 62376681Sru#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) 62476681Sru#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc)) 62576681Sru#define RL_RING_ALIGN 256 626167102Sru#define RL_IFQ_MAXLEN 512 627157440Sceri#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT) 628167102Sru#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 62976681Sru#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 630167102Sru#define RL_PKTSZ(x) ((x)/* >> 3*/) 63176681Sru#ifdef RE_FIXUP_RX 632167102Sru#define RE_ETHER_ALIGN sizeof(uint64_t) 63376681Sru#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 634167102Sru#else 635157440Sceri#define RE_ETHER_ALIGN 0 636167102Sru#define RE_RX_DESC_BUFLEN MCLBYTES 63776681Sru#endif 638167102Sru 63976681Sru#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 640167102Sru#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 64176681Sru 64276681Sru/* see comment in dev/re/if_re.c */ 64376250Sphk#define RL_JUMBO_FRAMELEN 7440 64476681Sru#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 64576250Sphk 64676250Sphkstruct rl_softc; 64776250Sphk 64876250Sphkstruct rl_dmaload_arg { 64976681Sru struct rl_softc *sc; 65076250Sphk int rl_idx; 65176250Sphk int rl_maxsegs; 65276250Sphk uint32_t rl_flags; 65376681Sru struct rl_desc *rl_ring; 65482662Sru}; 65582662Sru 656176478Simpstruct rl_list_data { 657238780Sjilles struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT]; 658238780Sjilles struct mbuf *rl_rx_mbuf[RL_TX_DESC_CNT]; 659238780Sjilles int rl_tx_prodidx; 660176478Simp int rl_rx_prodidx; 661176478Simp int rl_tx_considx; 662233648Seadler int rl_tx_free; 663243280Seadler bus_dmamap_t rl_tx_dmamap[RL_TX_DESC_CNT]; 664176478Simp bus_dmamap_t rl_rx_dmamap[RL_RX_DESC_CNT]; 6651590Srgrimes bus_dma_tag_t rl_mtag; /* mbuf mapping tag */ 6661590Srgrimes bus_dma_tag_t rl_stag; /* stats mapping tag */ 667107261Sru bus_dmamap_t rl_smap; /* stats map */ 66882662Sru struct rl_stats *rl_stats; 66982662Sru bus_addr_t rl_stats_addr; 67082662Sru bus_dma_tag_t rl_rx_list_tag; 67182662Sru bus_dmamap_t rl_rx_list_map; 67282662Sru struct rl_desc *rl_rx_list; 67382662Sru bus_addr_t rl_rx_list_addr; 67482662Sru bus_dma_tag_t rl_tx_list_tag; 67582662Sru bus_dmamap_t rl_tx_list_map; 67682662Sru struct rl_desc *rl_tx_list; 67782662Sru bus_addr_t rl_tx_list_addr; 678147370Sru}; 679147370Sru 680144526Stjrstruct rl_softc { 681144526Stjr struct arpcom arpcom; /* interface info */ 682144526Stjr bus_space_handle_t rl_bhandle; /* bus space handle */ 68382662Sru bus_space_tag_t rl_btag; /* bus space tag */ 68482662Sru struct resource *rl_res; 68582662Sru struct resource *rl_irq; 68682662Sru void *rl_intrhand; 687107261Sru device_t rl_miibus; 68882662Sru bus_dma_tag_t rl_parent_tag; 68982662Sru bus_dma_tag_t rl_tag; 69082662Sru uint8_t rl_unit; /* interface number */ 69182662Sru uint8_t rl_type; 69282662Sru int rl_eecmd_read; 69382662Sru uint8_t rl_stats_no_timeout; 69482662Sru int rl_txthresh; 69576681Sru struct rl_chain_data rl_cdata; 6961590Srgrimes struct rl_list_data rl_ldata; 69776681Sru struct callout_handle rl_stat_ch; 69876681Sru struct mtx rl_mtx; 69976681Sru struct mbuf *rl_head; 70076681Sru struct mbuf *rl_tail; 70176681Sru uint32_t rl_hwrev; 70276681Sru uint32_t rl_rxlenmask; 70376681Sru int rl_testmode; 7041590Srgrimes int suspended; /* 0 = normal 1 = suspended */ 70576681Sru#ifdef DEVICE_POLLING 7061590Srgrimes int rxcycles; 70776681Sru#endif 70876681Sru}; 70976681Sru 71076681Sru#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 71176681Sru#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 7121590Srgrimes#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 71382972Sru 7141590Srgrimes/* 7151590Srgrimes * register space access macros 7161590Srgrimes */ 71776681Sru#define CSR_WRITE_STREAM_4(sc, reg, val) \ 7181590Srgrimes bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 71982972Sru#define CSR_WRITE_4(sc, reg, val) \ 72082972Sru bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 72182972Sru#define CSR_WRITE_2(sc, reg, val) \ 72282972Sru bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 72382972Sru#define CSR_WRITE_1(sc, reg, val) \ 7241590Srgrimes bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 72582972Sru 72682972Sru#define CSR_READ_4(sc, reg) \ 72782972Sru bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 72876681Sru#define CSR_READ_2(sc, reg) \ 7291590Srgrimes bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 7301590Srgrimes#define CSR_READ_1(sc, reg) \ 73182972Sru bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 73282972Sru 73382972Sru#define RL_TIMEOUT 1000 73476681Sru 73570197Sru/* 73682972Sru * General constants that are fun to know. 73782972Sru * 73882972Sru * RealTek PCI vendor ID 73982972Sru */ 74082972Sru#define RT_VENDORID 0x10EC 74182972Sru 74276681Sru/* 74370197Sru * RealTek chip device IDs. 74482972Sru */ 74582972Sru#define RT_DEVICEID_8129 0x8129 74682972Sru#define RT_DEVICEID_8138 0x8138 74761573Sroberto#define RT_DEVICEID_8139 0x8139 74882972Sru#define RT_DEVICEID_8169 0x8169 74982972Sru#define RT_DEVICEID_8100 0x8100 75082972Sru 75176681Sru#define RT_REVID_8139CPLUS 0x20 75276681Sru 7531590Srgrimes/* 7541590Srgrimes * Accton PCI vendor ID 7551590Srgrimes */ 75623695Speter#define ACCTON_VENDORID 0x1113 75776681Sru 7581590Srgrimes/* 75976681Sru * Accton MPX 5030/5038 device ID. 76023695Speter */ 76176681Sru#define ACCTON_DEVICEID_5030 0x1211 7628389Swollman 7638389Swollman/* 76425395Smax * Nortel PCI vendor ID 765162792Sru */ 766162792Sru#define NORTEL_VENDORID 0x126C 7678389Swollman 7681590Srgrimes/* 7691590Srgrimes * Delta Electronics Vendor ID. 7701590Srgrimes */ 77168963Sru#define DELTA_VENDORID 0x1500 7721590Srgrimes 7731590Srgrimes/* 7741590Srgrimes * Delta device IDs. 7751590Srgrimes */ 7761590Srgrimes#define DELTA_DEVICEID_8139 0x1360 7771590Srgrimes 778240278Sdes/* 779240278Sdes * Addtron vendor ID. 780240278Sdes */ 781264411Sjilles#define ADDTRON_VENDORID 0x4033 78282662Sru 78382662Sru/* 78482662Sru * Addtron device IDs. 78582662Sru */ 78682662Sru#define ADDTRON_DEVICEID_8139 0x1360 78782662Sru 78882662Sru/* 78982662Sru * D-Link vendor ID. 79082662Sru */ 79182662Sru#define DLINK_VENDORID 0x1186 79282662Sru 79382662Sru/* 79482662Sru * D-Link DFE-530TX+ device ID 79582662Sru */ 796176478Simp#define DLINK_DEVICEID_530TXPLUS 0x1300 797176478Simp 798176478Simp/* 799176478Simp * D-Link DFE-690TXD device ID 800176478Simp */ 801176478Simp#define DLINK_DEVICEID_690TXD 0x1340 802233648Seadler 803176478Simp/* 804158986Skrion * Corega K.K vendor ID 805129428Sru */ 80676681Sru#define COREGA_VENDORID 0x1259 8071590Srgrimes 8081590Srgrimes/* 80976681Sru * Corega FEther CB-TXD device ID 81076681Sru */ 81176681Sru#define COREGA_DEVICEID_FETHERCBTXD 0xa117 8121590Srgrimes 8131590Srgrimes/* 81476681Sru * Corega FEtherII CB-TXD device ID 815158986Skrion */ 816158986Skrion#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 817158986Skrion 818158986Skrion/* 819158986Skrion * Corega CG-LAPCIGT device ID 820158986Skrion */ 821158986Skrion#define COREGA_DEVICEID_CGLAPCIGT 0xc107 822158986Skrion 823158986Skrion/* 824158986Skrion * Peppercon vendor ID 825158986Skrion */ 826158986Skrion#define PEPPERCON_VENDORID 0x1743 827158986Skrion 828158986Skrion/* 829158986Skrion * Peppercon ROL-F device ID 830158986Skrion */ 831158986Skrion#define PEPPERCON_DEVICEID_ROLF 0x8139 832158986Skrion 833247730Sdwmalone/* 834247730Sdwmalone * Planex Communications, Inc. vendor ID 835247730Sdwmalone */ 836247730Sdwmalone#define PLANEX_VENDORID 0x14ea 83776681Sru 8381590Srgrimes/* 8391590Srgrimes * Planex FNW-3800-TX device ID 8401590Srgrimes */ 84176681Sru#define PLANEX_DEVICEID_FNW3800TX 0xab07 8421590Srgrimes 8431590Srgrimes/* 8441590Srgrimes * LevelOne vendor ID 8451590Srgrimes */ 8461590Srgrimes#define LEVEL1_VENDORID 0x018A 8471590Srgrimes 8481590Srgrimes/* 8491590Srgrimes * LevelOne FPC-0106TX devide ID 8501590Srgrimes */ 8511590Srgrimes#define LEVEL1_DEVICEID_FPC0106TX 0x0106 8521590Srgrimes 8531590Srgrimes/* 8541590Srgrimes * Compaq vendor ID 8551590Srgrimes */ 8561590Srgrimes#define CP_VENDORID 0x021B 857176478Simp 858176478Simp/* 859233648Seadler * Edimax vendor ID 860176478Simp */ 861176478Simp#define EDIMAX_VENDORID 0x13D1 862233648Seadler 863176478Simp/* 864243280Seadler * Edimax EP-4103DL cardbus device ID 865176478Simp */ 86676681Sru#define EDIMAX_DEVICEID_EP4103DL 0xAB06 8671590Srgrimes 86876681Sru/* 8691590Srgrimes * PCI low memory base and low I/O base register, and 8701590Srgrimes * other PCI registers. 8711590Srgrimes */ 8721590Srgrimes 87376681Sru#define RL_PCI_VENDOR_ID 0x00 874176478Simp#define RL_PCI_DEVICE_ID 0x02 875233648Seadler#define RL_PCI_COMMAND 0x04 876176478Simp#define RL_PCI_STATUS 0x06 877176478Simp#define RL_PCI_CLASSCODE 0x09 8781590Srgrimes#define RL_PCI_LATENCY_TIMER 0x0D 8791590Srgrimes#define RL_PCI_HEADER_TYPE 0x0E 8801590Srgrimes#define RL_PCI_LOIO 0x10 8811590Srgrimes#define RL_PCI_LOMEM 0x14 88276681Sru#define RL_PCI_BIOSROM 0x30 883167102Sru#define RL_PCI_INTLINE 0x3C 88476681Sru#define RL_PCI_INTPIN 0x3D 8851590Srgrimes#define RL_PCI_MINGNT 0x3E 8861590Srgrimes#define RL_PCI_MINLAT 0x0F 8871590Srgrimes#define RL_PCI_RESETOPT 0x48 88876681Sru#define RL_PCI_EEPROM_DATA 0x4C 889102083Sjmallett 8901590Srgrimes#define RL_PCI_CAPID 0x50 /* 8 bits */ 8911590Srgrimes#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 8921590Srgrimes#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 8931590Srgrimes#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 8941590Srgrimes 895176478Simp#define RL_PSTATE_MASK 0x0003 896176478Simp#define RL_PSTATE_D0 0x0000 897176478Simp#define RL_PSTATE_D1 0x0002 898176478Simp#define RL_PSTATE_D2 0x0002 899176478Simp#define RL_PSTATE_D3 0x0003 90076681Sru#define RL_PME_EN 0x0010 90176681Sru#define RL_PME_STATUS 0x8000 9021590Srgrimes