if_rlreg.h revision 119976
1178431Sscf/* 2178431Sscf * Copyright (c) 1997, 1998-2003 3178431Sscf * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4178431Sscf * 5178431Sscf * Redistribution and use in source and binary forms, with or without 6178431Sscf * modification, are permitted provided that the following conditions 7178431Sscf * are met: 8178431Sscf * 1. Redistributions of source code must retain the above copyright 9178431Sscf * notice, this list of conditions and the following disclaimer. 10178431Sscf * 2. Redistributions in binary form must reproduce the above copyright 11178431Sscf * notice, this list of conditions and the following disclaimer in the 12178431Sscf * documentation and/or other materials provided with the distribution. 13178431Sscf * 3. All advertising materials mentioning features or use of this software 14178431Sscf * must display the following acknowledgement: 15178431Sscf * This product includes software developed by Bill Paul. 16178431Sscf * 4. Neither the name of the author nor the names of any co-contributors 17178431Sscf * may be used to endorse or promote products derived from this software 18178431Sscf * without specific prior written permission. 19178431Sscf * 20178431Sscf * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21178431Sscf * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22178431Sscf * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23178431Sscf * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24178431Sscf * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25178431Sscf * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26178431Sscf * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27178431Sscf * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28178431Sscf * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29178431Sscf * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30178431Sscf * THE POSSIBILITY OF SUCH DAMAGE. 31184831Sscf * 32178431Sscf * $FreeBSD: head/sys/pci/if_rlreg.h 119976 2003-09-11 03:53:46Z wpaul $ 33178431Sscf */ 34184831Sscf 35178431Sscf/* 36178431Sscf * RealTek 8129/8139 register offsets 37178431Sscf */ 38178431Sscf#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39178431Sscf#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40178431Sscf#define RL_IDR2 0x0002 41178431Sscf#define RL_IDR3 0x0003 42178431Sscf#define RL_IDR4 0x0004 43178431Sscf#define RL_IDR5 0x0005 44178431Sscf /* 0006-0007 reserved */ 45178431Sscf#define RL_MAR0 0x0008 /* Multicast hash table */ 46178431Sscf#define RL_MAR1 0x0009 47178431Sscf#define RL_MAR2 0x000A 48178431Sscf#define RL_MAR3 0x000B 49178431Sscf#define RL_MAR4 0x000C 50184831Sscf#define RL_MAR5 0x000D 51184831Sscf#define RL_MAR6 0x000E 52178431Sscf#define RL_MAR7 0x000F 53178431Sscf 54178431Sscf#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55178431Sscf#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56178431Sscf#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57178431Sscf#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 58178431Sscf 59178431Sscf#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60178431Sscf#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61178431Sscf#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62178431Sscf#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 63178431Sscf 64178431Sscf#define RL_RXADDR 0x0030 /* RX ring start address */ 65178431Sscf#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66178431Sscf#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67178431Sscf#define RL_COMMAND 0x0037 /* command register */ 68178431Sscf#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69178431Sscf#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70178431Sscf#define RL_IMR 0x003C /* interrupt mask register */ 71178431Sscf#define RL_ISR 0x003E /* interrupt status register */ 72178431Sscf#define RL_TXCFG 0x0040 /* transmit config */ 73178431Sscf#define RL_RXCFG 0x0044 /* receive config */ 74178431Sscf#define RL_TIMERCNT 0x0048 /* timer count register */ 75178431Sscf#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76178431Sscf#define RL_EECMD 0x0050 /* EEPROM command register */ 77178431Sscf#define RL_CFG0 0x0051 /* config register #0 */ 78178431Sscf#define RL_CFG1 0x0052 /* config register #1 */ 79178431Sscf /* 0053-0057 reserved */ 80178431Sscf#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 81178431Sscf /* 0059-005A reserved */ 82178431Sscf#define RL_MII 0x005A /* 8129 chip only */ 83178431Sscf#define RL_HALTCLK 0x005B 84178431Sscf#define RL_MULTIINTR 0x005C /* multiple interrupt */ 85178431Sscf#define RL_PCIREV 0x005E /* PCI revision value */ 86178431Sscf /* 005F reserved */ 87178431Sscf#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 88178431Sscf 89184831Sscf/* Direct PHY access registers only available on 8139 */ 90178431Sscf#define RL_BMCR 0x0062 /* PHY basic mode control */ 91178431Sscf#define RL_BMSR 0x0064 /* PHY basic mode status */ 92178431Sscf#define RL_ANAR 0x0066 /* PHY autoneg advert */ 93178431Sscf#define RL_LPAR 0x0068 /* PHY link partner ability */ 94178431Sscf#define RL_ANER 0x006A /* PHY autoneg expansion */ 95178431Sscf 96178431Sscf#define RL_DISCCNT 0x006C /* disconnect counter */ 97178431Sscf#define RL_FALSECAR 0x006E /* false carrier counter */ 98178431Sscf#define RL_NWAYTST 0x0070 /* NWAY test register */ 99178431Sscf#define RL_RX_ER 0x0072 /* RX_ER counter */ 100178431Sscf#define RL_CSCFG 0x0074 /* CS configuration register */ 101178431Sscf 102178431Sscf/* 103178431Sscf * When operating in special C+ mode, some of the registers in an 104178431Sscf * 8139C+ chip have different definitions. These are also used for 105178431Sscf * the 8169 gigE chip. 106178431Sscf */ 107178431Sscf#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 108178431Sscf#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 109178431Sscf#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 110178431Sscf#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 111178431Sscf#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 112178431Sscf#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 113178431Sscf#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 114178431Sscf#define RL_TXSTART 0x00D9 /* 8 bits */ 115178431Sscf#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 116178431Sscf#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 117178431Sscf#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 118178431Sscf#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 119178431Sscf 120184831Sscf/* 121184831Sscf * Registers specific to the 8169 gigE chip 122178431Sscf */ 123178431Sscf#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 124178431Sscf#define RL_PHYAR 0x0060 125178431Sscf#define RL_TBICSR 0x0064 126178431Sscf#define RL_TBI_ANAR 0x0068 127178431Sscf#define RL_TBI_LPAR 0x006A 128178431Sscf#define RL_GMEDIASTAT 0x006C /* 8 bits */ 129178431Sscf#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 130178431Sscf#define RL_GTXSTART 0x0038 /* 16 bits */ 131178431Sscf 132178431Sscf/* 133184831Sscf * TX config register bits 134178431Sscf */ 135178431Sscf#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 136178431Sscf#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 137178431Sscf#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 138178431Sscf#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 139178431Sscf#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 140178431Sscf#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 141178431Sscf#define RL_TXCFG_HWREV 0x7CC00000 142178431Sscf 143178431Sscf#define RL_LOOPTEST_OFF 0x00000000 144178431Sscf#define RL_LOOPTEST_ON 0x00020000 145178431Sscf 146178431Sscf#define RL_HWREV_8169 0x00000000 147178431Sscf#define RL_HWREV_8169S 0x04000000 148178431Sscf#define RL_HWREV_8110S 0x00800000 149178431Sscf#define RL_HWREV_8139 0x60000000 150178431Sscf#define RL_HWREV_8139A 0x70000000 151184831Sscf#define RL_HWREV_8139AG 0x70800000 152178431Sscf#define RL_HWREV_8139B 0x78000000 153178431Sscf#define RL_HWREV_8130 0x7C000000 154178431Sscf#define RL_HWREV_8139C 0x74000000 155178431Sscf#define RL_HWREV_8139D 0x74400000 156178431Sscf#define RL_HWREV_8139CPLUS 0x74800000 157178431Sscf#define RL_HWREV_8101 0x74c00000 158178431Sscf#define RL_HWREV_8100 0x78800000 159178431Sscf 160178431Sscf#define RL_TXDMA_16BYTES 0x00000000 161178431Sscf#define RL_TXDMA_32BYTES 0x00000100 162178431Sscf#define RL_TXDMA_64BYTES 0x00000200 163178431Sscf#define RL_TXDMA_128BYTES 0x00000300 164178431Sscf#define RL_TXDMA_256BYTES 0x00000400 165178431Sscf#define RL_TXDMA_512BYTES 0x00000500 166178431Sscf#define RL_TXDMA_1024BYTES 0x00000600 167178431Sscf#define RL_TXDMA_2048BYTES 0x00000700 168178431Sscf 169178431Sscf/* 170178431Sscf * Transmit descriptor status register bits. 171178431Sscf */ 172178431Sscf#define RL_TXSTAT_LENMASK 0x00001FFF 173178431Sscf#define RL_TXSTAT_OWN 0x00002000 174178431Sscf#define RL_TXSTAT_TX_UNDERRUN 0x00004000 175178431Sscf#define RL_TXSTAT_TX_OK 0x00008000 176178431Sscf#define RL_TXSTAT_EARLY_THRESH 0x003F0000 177178431Sscf#define RL_TXSTAT_COLLCNT 0x0F000000 178184831Sscf#define RL_TXSTAT_CARR_HBEAT 0x10000000 179184831Sscf#define RL_TXSTAT_OUTOFWIN 0x20000000 180178431Sscf#define RL_TXSTAT_TXABRT 0x40000000 181178431Sscf#define RL_TXSTAT_CARRLOSS 0x80000000 182178431Sscf 183178431Sscf/* 184178431Sscf * Interrupt status register bits. 185184831Sscf */ 186178431Sscf#define RL_ISR_RX_OK 0x0001 187178431Sscf#define RL_ISR_RX_ERR 0x0002 188178431Sscf#define RL_ISR_TX_OK 0x0004 189178431Sscf#define RL_ISR_TX_ERR 0x0008 190178431Sscf#define RL_ISR_RX_OVERRUN 0x0010 191178431Sscf#define RL_ISR_PKT_UNDERRUN 0x0020 192178431Sscf#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 193178431Sscf#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 194178431Sscf#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 195178431Sscf#define RL_ISR_SWI 0x0100 /* C+ only */ 196178431Sscf#define RL_ISR_CABLE_LEN_CHGD 0x2000 197184831Sscf#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 198178431Sscf#define RL_ISR_TIMEOUT_EXPIRED 0x4000 199178431Sscf#define RL_ISR_SYSTEM_ERR 0x8000 200178431Sscf 201178431Sscf#define RL_INTRS \ 202178431Sscf (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 203178431Sscf RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 204178431Sscf RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 205178431Sscf 206178431Sscf#define RL_INTRS_CPLUS \ 207178431Sscf (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 208178431Sscf RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 209178431Sscf RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 210178431Sscf 211178431Sscf/* 212184831Sscf * Media status register. (8139 only) 213178431Sscf */ 214178431Sscf#define RL_MEDIASTAT_RXPAUSE 0x01 215178431Sscf#define RL_MEDIASTAT_TXPAUSE 0x02 216178431Sscf#define RL_MEDIASTAT_LINK 0x04 217178431Sscf#define RL_MEDIASTAT_SPEED10 0x08 218178431Sscf#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 219178431Sscf#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 220178431Sscf 221178431Sscf/* 222178431Sscf * Receive config register. 223178431Sscf */ 224178431Sscf#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 225178431Sscf#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 226178431Sscf#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 227178431Sscf#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 228178431Sscf#define RL_RXCFG_RX_RUNT 0x00000010 229#define RL_RXCFG_RX_ERRPKT 0x00000020 230#define RL_RXCFG_WRAP 0x00000080 231#define RL_RXCFG_MAXDMA 0x00000700 232#define RL_RXCFG_BUFSZ 0x00001800 233#define RL_RXCFG_FIFOTHRESH 0x0000E000 234#define RL_RXCFG_EARLYTHRESH 0x07000000 235 236#define RL_RXDMA_16BYTES 0x00000000 237#define RL_RXDMA_32BYTES 0x00000100 238#define RL_RXDMA_64BYTES 0x00000200 239#define RL_RXDMA_128BYTES 0x00000300 240#define RL_RXDMA_256BYTES 0x00000400 241#define RL_RXDMA_512BYTES 0x00000500 242#define RL_RXDMA_1024BYTES 0x00000600 243#define RL_RXDMA_UNLIMITED 0x00000700 244 245#define RL_RXBUF_8 0x00000000 246#define RL_RXBUF_16 0x00000800 247#define RL_RXBUF_32 0x00001000 248#define RL_RXBUF_64 0x00001800 249 250#define RL_RXFIFO_16BYTES 0x00000000 251#define RL_RXFIFO_32BYTES 0x00002000 252#define RL_RXFIFO_64BYTES 0x00004000 253#define RL_RXFIFO_128BYTES 0x00006000 254#define RL_RXFIFO_256BYTES 0x00008000 255#define RL_RXFIFO_512BYTES 0x0000A000 256#define RL_RXFIFO_1024BYTES 0x0000C000 257#define RL_RXFIFO_NOTHRESH 0x0000E000 258 259/* 260 * Bits in RX status header (included with RX'ed packet 261 * in ring buffer). 262 */ 263#define RL_RXSTAT_RXOK 0x00000001 264#define RL_RXSTAT_ALIGNERR 0x00000002 265#define RL_RXSTAT_CRCERR 0x00000004 266#define RL_RXSTAT_GIANT 0x00000008 267#define RL_RXSTAT_RUNT 0x00000010 268#define RL_RXSTAT_BADSYM 0x00000020 269#define RL_RXSTAT_BROAD 0x00002000 270#define RL_RXSTAT_INDIV 0x00004000 271#define RL_RXSTAT_MULTI 0x00008000 272#define RL_RXSTAT_LENMASK 0xFFFF0000 273 274#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 275/* 276 * Command register. 277 */ 278#define RL_CMD_EMPTY_RXBUF 0x0001 279#define RL_CMD_TX_ENB 0x0004 280#define RL_CMD_RX_ENB 0x0008 281#define RL_CMD_RESET 0x0010 282 283/* 284 * EEPROM control register 285 */ 286#define RL_EE_DATAOUT 0x01 /* Data out */ 287#define RL_EE_DATAIN 0x02 /* Data in */ 288#define RL_EE_CLK 0x04 /* clock */ 289#define RL_EE_SEL 0x08 /* chip select */ 290#define RL_EE_MODE (0x40|0x80) 291 292#define RL_EEMODE_OFF 0x00 293#define RL_EEMODE_AUTOLOAD 0x40 294#define RL_EEMODE_PROGRAM 0x80 295#define RL_EEMODE_WRITECFG (0x80|0x40) 296 297/* 9346 EEPROM commands */ 298#define RL_EECMD_WRITE 0x140 299#define RL_EECMD_READ_6BIT 0x180 300#define RL_EECMD_READ_8BIT 0x600 301#define RL_EECMD_ERASE 0x1c0 302 303#define RL_EE_ID 0x00 304#define RL_EE_PCI_VID 0x01 305#define RL_EE_PCI_DID 0x02 306/* Location of station address inside EEPROM */ 307#define RL_EE_EADDR 0x07 308 309/* 310 * MII register (8129 only) 311 */ 312#define RL_MII_CLK 0x01 313#define RL_MII_DATAIN 0x02 314#define RL_MII_DATAOUT 0x04 315#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 316 317/* 318 * Config 0 register 319 */ 320#define RL_CFG0_ROM0 0x01 321#define RL_CFG0_ROM1 0x02 322#define RL_CFG0_ROM2 0x04 323#define RL_CFG0_PL0 0x08 324#define RL_CFG0_PL1 0x10 325#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 326#define RL_CFG0_PCS 0x40 327#define RL_CFG0_SCR 0x80 328 329/* 330 * Config 1 register 331 */ 332#define RL_CFG1_PWRDWN 0x01 333#define RL_CFG1_SLEEP 0x02 334#define RL_CFG1_IOMAP 0x04 335#define RL_CFG1_MEMMAP 0x08 336#define RL_CFG1_RSVD 0x10 337#define RL_CFG1_DRVLOAD 0x20 338#define RL_CFG1_LED0 0x40 339#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 340#define RL_CFG1_LED1 0x80 341 342/* 343 * 8139C+ register definitions 344 */ 345 346/* RL_DUMPSTATS_LO register */ 347 348#define RL_DUMPSTATS_START 0x00000008 349 350/* Transmit start register */ 351 352#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 353#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 354#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 355 356/* C+ mode command register */ 357 358#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 359#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 360#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 361#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 362#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 363#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 364 365/* C+ early transmit threshold */ 366 367#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 368 369/* 370 * Gigabit PHY access register (8169 only) 371 */ 372 373#define RL_PHYAR_PHYDATA 0x0000FFFF 374#define RL_PHYAR_PHYREG 0x001F0000 375#define RL_PHYAR_BUSY 0x80000000 376 377/* 378 * Gigabit media status (8169 only) 379 */ 380#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 381#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 382#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 383#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 384#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 385#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 386#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 387#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 388 389/* 390 * The RealTek doesn't use a fragment-based descriptor mechanism. 391 * Instead, there are only four register sets, each or which represents 392 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 393 * packet buffer (32-bit aligned!) and we place the buffer addresses in 394 * the registers so the chip knows where they are. 395 * 396 * We can sort of kludge together the same kind of buffer management 397 * used in previous drivers, but we have to do buffer copies almost all 398 * the time, so it doesn't really buy us much. 399 * 400 * For reception, there's just one large buffer where the chip stores 401 * all received packets. 402 */ 403 404#define RL_RX_BUF_SZ RL_RXBUF_64 405#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 406#define RL_TX_LIST_CNT 4 407#define RL_MIN_FRAMELEN 60 408#define RL_TXTHRESH(x) ((x) << 11) 409#define RL_TX_THRESH_INIT 96 410#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 411#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 412#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 413 414#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 415#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 416 417#define RL_ETHER_ALIGN 2 418 419struct rl_chain_data { 420 u_int16_t cur_rx; 421 caddr_t rl_rx_buf; 422 caddr_t rl_rx_buf_ptr; 423 bus_dmamap_t rl_rx_dmamap; 424 425 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 426 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 427 u_int8_t last_tx; 428 u_int8_t cur_tx; 429}; 430 431#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 432#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 433#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 434#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 435#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 436#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 437#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 438#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 439#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 440 441struct rl_type { 442 u_int16_t rl_vid; 443 u_int16_t rl_did; 444 int rl_basetype; 445 char *rl_name; 446}; 447 448struct rl_hwrev { 449 u_int32_t rl_rev; 450 int rl_type; 451 char *rl_desc; 452}; 453 454struct rl_mii_frame { 455 u_int8_t mii_stdelim; 456 u_int8_t mii_opcode; 457 u_int8_t mii_phyaddr; 458 u_int8_t mii_regaddr; 459 u_int8_t mii_turnaround; 460 u_int16_t mii_data; 461}; 462 463/* 464 * MII constants 465 */ 466#define RL_MII_STARTDELIM 0x01 467#define RL_MII_READOP 0x02 468#define RL_MII_WRITEOP 0x01 469#define RL_MII_TURNAROUND 0x02 470 471#define RL_8129 1 472#define RL_8139 2 473#define RL_8139CPLUS 3 474#define RL_8169 4 475 476#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 477 (x)->rl_type == RL_8169) 478 479/* 480 * The 8139C+ and 8160 gigE chips support descriptor-based TX 481 * and RX. In fact, they even support TCP large send. Descriptors 482 * must be allocated in contiguous blocks that are aligned on a 483 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 484 */ 485 486/* 487 * RX/TX descriptor definition. When large send mode is enabled, the 488 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 489 * the checksum offload bits are disabled. The structure layout is 490 * the same for RX and TX descriptors 491 */ 492 493struct rl_desc { 494 u_int32_t rl_cmdstat; 495 u_int32_t rl_vlanctl; 496 u_int32_t rl_bufaddr_lo; 497 u_int32_t rl_bufaddr_hi; 498}; 499 500#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 501#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 502#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 503#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 504#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 505#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 506#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 507#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 508#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 509#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 510 511#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 512#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 513 514/* 515 * Error bits are valid only on the last descriptor of a frame 516 * (i.e. RL_TDESC_CMD_EOF == 1) 517 */ 518 519#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 520#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 521#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 522#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 523#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 524#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 525#define RL_TDESC_STAT_OWN 0x80000000 526 527/* 528 * RX descriptor cmd/vlan definitions 529 */ 530 531#define RL_RDESC_CMD_EOR 0x40000000 532#define RL_RDESC_CMD_OWN 0x80000000 533#define RL_RDESC_CMD_BUFLEN 0x00003FFF 534 535#define RL_RDESC_STAT_OWN 0x80000000 536#define RL_RDESC_STAT_EOR 0x40000000 537#define RL_RDESC_STAT_SOF 0x20000000 538#define RL_RDESC_STAT_EOF 0x10000000 539#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 540#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 541#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 542#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 543#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 544#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 545#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 546#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 547#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 548#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 549#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 550#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 551#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 552#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 553#define RL_RDESC_STAT_FRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 554 555#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 556 (rl_vlandata valid)*/ 557#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 558 559#define RL_PROTOID_NONIP 0x00000000 560#define RL_PROTOID_TCPIP 0x00010000 561#define RL_PROTOID_UDPIP 0x00020000 562#define RL_PROTOID_IP 0x00030000 563#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 564 RL_PROTOID_TCPIP) 565#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 566 RL_PROTOID_UDPIP) 567 568/* 569 * Statistics counter structure (8139C+ and 8169 only) 570 */ 571struct rl_stats { 572 u_int32_t rl_tx_pkts_lo; 573 u_int32_t rl_tx_pkts_hi; 574 u_int32_t rl_tx_errs_lo; 575 u_int32_t rl_tx_errs_hi; 576 u_int32_t rl_tx_errs; 577 u_int16_t rl_missed_pkts; 578 u_int16_t rl_rx_framealign_errs; 579 u_int32_t rl_tx_onecoll; 580 u_int32_t rl_tx_multicolls; 581 u_int32_t rl_rx_ucasts_hi; 582 u_int32_t rl_rx_ucasts_lo; 583 u_int32_t rl_rx_bcasts_lo; 584 u_int32_t rl_rx_bcasts_hi; 585 u_int32_t rl_rx_mcasts; 586 u_int16_t rl_tx_aborts; 587 u_int16_t rl_rx_underruns; 588}; 589 590#define RL_RX_DESC_CNT 64 591#define RL_TX_DESC_CNT 64 592#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) 593#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc)) 594#define RL_RING_ALIGN 256 595#define RL_IFQ_MAXLEN 512 596#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT) 597#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 598#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & \ 599 RL_RDESC_STAT_FRAGLEN) 600#define RL_PKTSZ(x) ((x)/* >> 3*/) 601 602#define RL_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF) 603#define RL_ADDR_HI(y) ((u_int64_t) (y) >> 32) 604 605#define RL_JUMBO_FRAMELEN 9018 606#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 607#define RL_JSLOTS 128 608 609#define RL_JRAWLEN (RL_JUMBO_FRAMELEN + ETHER_ALIGN + sizeof(u_int64_t)) 610#define RL_JLEN (RL_JRAWLEN + (sizeof(u_int64_t) - \ 611 (RL_JRAWLEN % sizeof(u_int64_t)))) 612#define RL_JPAGESZ PAGE_SIZE 613#define RL_RESID (RL_JPAGESZ - (RL_JLEN * RL_JSLOTS) % RL_JPAGESZ) 614#define RL_JMEM ((RL_JLEN * RL_JSLOTS) + RL_RESID) 615 616struct rl_softc; 617 618struct rl_dmaload_arg { 619 struct rl_softc *sc; 620 int rl_idx; 621 int rl_maxsegs; 622 u_int32_t rl_flags; 623 struct rl_desc *rl_ring; 624}; 625 626struct rl_list_data { 627 struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT]; 628 struct mbuf *rl_rx_mbuf[RL_TX_DESC_CNT]; 629 int rl_tx_prodidx; 630 int rl_rx_prodidx; 631 int rl_tx_considx; 632 int rl_tx_free; 633 bus_dmamap_t rl_tx_dmamap[RL_TX_DESC_CNT]; 634 bus_dmamap_t rl_rx_dmamap[RL_RX_DESC_CNT]; 635 bus_dma_tag_t rl_mtag; /* mbuf mapping tag */ 636 bus_dma_tag_t rl_stag; /* stats mapping tag */ 637 bus_dmamap_t rl_smap; /* stats map */ 638 struct rl_stats *rl_stats; 639 bus_addr_t rl_stats_addr; 640 bus_dma_tag_t rl_rx_list_tag; 641 bus_dmamap_t rl_rx_list_map; 642 struct rl_desc *rl_rx_list; 643 bus_addr_t rl_rx_list_addr; 644 bus_dma_tag_t rl_tx_list_tag; 645 bus_dmamap_t rl_tx_list_map; 646 struct rl_desc *rl_tx_list; 647 bus_addr_t rl_tx_list_addr; 648}; 649 650struct rl_softc { 651 struct arpcom arpcom; /* interface info */ 652 bus_space_handle_t rl_bhandle; /* bus space handle */ 653 bus_space_tag_t rl_btag; /* bus space tag */ 654 struct resource *rl_res; 655 struct resource *rl_irq; 656 void *rl_intrhand; 657 device_t rl_miibus; 658 bus_dma_tag_t rl_parent_tag; 659 bus_dma_tag_t rl_tag; 660 u_int8_t rl_unit; /* interface number */ 661 u_int8_t rl_type; 662 int rl_eecmd_read; 663 u_int8_t rl_stats_no_timeout; 664 int rl_txthresh; 665 struct rl_chain_data rl_cdata; 666 struct rl_list_data rl_ldata; 667 struct callout_handle rl_stat_ch; 668 struct mtx rl_mtx; 669 struct mbuf *rl_head; 670 struct mbuf *rl_tail; 671 u_int32_t rl_hwrev; 672 int rl_testmode; 673 int suspended; /* 0 = normal 1 = suspended */ 674#ifdef DEVICE_POLLING 675 int rxcycles; 676#endif 677 678 u_int32_t saved_maps[5]; /* pci data */ 679 u_int32_t saved_biosaddr; 680 u_int8_t saved_intline; 681 u_int8_t saved_cachelnsz; 682 u_int8_t saved_lattimer; 683}; 684 685#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 686#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 687 688/* 689 * register space access macros 690 */ 691#define CSR_WRITE_STREAM_4(sc, reg, val) \ 692 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 693#define CSR_WRITE_4(sc, reg, val) \ 694 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 695#define CSR_WRITE_2(sc, reg, val) \ 696 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 697#define CSR_WRITE_1(sc, reg, val) \ 698 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 699 700#define CSR_READ_4(sc, reg) \ 701 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 702#define CSR_READ_2(sc, reg) \ 703 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 704#define CSR_READ_1(sc, reg) \ 705 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 706 707#define RL_TIMEOUT 1000 708 709/* 710 * General constants that are fun to know. 711 * 712 * RealTek PCI vendor ID 713 */ 714#define RT_VENDORID 0x10EC 715 716/* 717 * RealTek chip device IDs. 718 */ 719#define RT_DEVICEID_8129 0x8129 720#define RT_DEVICEID_8138 0x8138 721#define RT_DEVICEID_8139 0x8139 722#define RT_DEVICEID_8169 0x8169 723#define RT_DEVICEID_8100 0x8100 724 725#define RT_REVID_8139CPLUS 0x20 726 727/* 728 * Accton PCI vendor ID 729 */ 730#define ACCTON_VENDORID 0x1113 731 732/* 733 * Accton MPX 5030/5038 device ID. 734 */ 735#define ACCTON_DEVICEID_5030 0x1211 736 737/* 738 * Nortel PCI vendor ID 739 */ 740#define NORTEL_VENDORID 0x126C 741 742/* 743 * Delta Electronics Vendor ID. 744 */ 745#define DELTA_VENDORID 0x1500 746 747/* 748 * Delta device IDs. 749 */ 750#define DELTA_DEVICEID_8139 0x1360 751 752/* 753 * Addtron vendor ID. 754 */ 755#define ADDTRON_VENDORID 0x4033 756 757/* 758 * Addtron device IDs. 759 */ 760#define ADDTRON_DEVICEID_8139 0x1360 761 762/* 763 * D-Link vendor ID. 764 */ 765#define DLINK_VENDORID 0x1186 766 767/* 768 * D-Link DFE-530TX+ device ID 769 */ 770#define DLINK_DEVICEID_530TXPLUS 0x1300 771 772/* 773 * D-Link DFE-690TXD device ID 774 */ 775#define DLINK_DEVICEID_690TXD 0x1340 776 777/* 778 * Corega K.K vendor ID 779 */ 780#define COREGA_VENDORID 0x1259 781 782/* 783 * Corega FEther CB-TXD device ID 784 */ 785#define COREGA_DEVICEID_FETHERCBTXD 0xa117 786 787/* 788 * Corega FEtherII CB-TXD device ID 789 */ 790#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 791 792/* 793 * Peppercon vendor ID 794 */ 795#define PEPPERCON_VENDORID 0x1743 796 797/* 798 * Peppercon ROL-F device ID 799 */ 800#define PEPPERCON_DEVICEID_ROLF 0x8139 801 802/* 803 * Planex Communications, Inc. vendor ID 804 */ 805#define PLANEX_VENDORID 0x14ea 806 807/* 808 * Planex FNW-3800-TX device ID 809 */ 810#define PLANEX_DEVICEID_FNW3800TX 0xab07 811 812/* 813 * LevelOne vendor ID 814 */ 815#define LEVEL1_VENDORID 0x018A 816 817/* 818 * LevelOne FPC-0106TX devide ID 819 */ 820#define LEVEL1_DEVICEID_FPC0106TX 0x0106 821 822/* 823 * Compaq vendor ID 824 */ 825#define CP_VENDORID 0x021B 826 827/* 828 * Edimax vendor ID 829 */ 830#define EDIMAX_VENDORID 0x13D1 831 832/* 833 * Edimax EP-4103DL cardbus device ID 834 */ 835#define EDIMAX_DEVICEID_EP4103DL 0xAB06 836 837/* 838 * PCI low memory base and low I/O base register, and 839 * other PCI registers. 840 */ 841 842#define RL_PCI_VENDOR_ID 0x00 843#define RL_PCI_DEVICE_ID 0x02 844#define RL_PCI_COMMAND 0x04 845#define RL_PCI_STATUS 0x06 846#define RL_PCI_CLASSCODE 0x09 847#define RL_PCI_LATENCY_TIMER 0x0D 848#define RL_PCI_HEADER_TYPE 0x0E 849#define RL_PCI_LOIO 0x10 850#define RL_PCI_LOMEM 0x14 851#define RL_PCI_BIOSROM 0x30 852#define RL_PCI_INTLINE 0x3C 853#define RL_PCI_INTPIN 0x3D 854#define RL_PCI_MINGNT 0x3E 855#define RL_PCI_MINLAT 0x0F 856#define RL_PCI_RESETOPT 0x48 857#define RL_PCI_EEPROM_DATA 0x4C 858 859#define RL_PCI_CAPID 0x50 /* 8 bits */ 860#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 861#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 862#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 863 864#define RL_PSTATE_MASK 0x0003 865#define RL_PSTATE_D0 0x0000 866#define RL_PSTATE_D1 0x0002 867#define RL_PSTATE_D2 0x0002 868#define RL_PSTATE_D3 0x0003 869#define RL_PME_EN 0x0010 870#define RL_PME_STATUS 0x8000 871