if_rlreg.h revision 118712
1/* 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_rlreg.h 118712 2003-08-10 01:41:35Z wpaul $ 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 41#define RL_IDR3 0x0003 42#define RL_IDR4 0x0004 43#define RL_IDR5 0x0005 44 /* 0006-0007 reserved */ 45#define RL_MAR0 0x0008 /* Multicast hash table */ 46#define RL_MAR1 0x0009 47#define RL_MAR2 0x000A 48#define RL_MAR3 0x000B 49#define RL_MAR4 0x000C 50#define RL_MAR5 0x000D 51#define RL_MAR6 0x000E 52#define RL_MAR7 0x000F 53 54#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 58 59#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 63 64#define RL_RXADDR 0x0030 /* RX ring start address */ 65#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67#define RL_COMMAND 0x0037 /* command register */ 68#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70#define RL_IMR 0x003C /* interrupt mask register */ 71#define RL_ISR 0x003E /* interrupt status register */ 72#define RL_TXCFG 0x0040 /* transmit config */ 73#define RL_RXCFG 0x0044 /* receive config */ 74#define RL_TIMERCNT 0x0048 /* timer count register */ 75#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76#define RL_EECMD 0x0050 /* EEPROM command register */ 77#define RL_CFG0 0x0051 /* config register #0 */ 78#define RL_CFG1 0x0052 /* config register #1 */ 79 /* 0053-0057 reserved */ 80#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 81 /* 0059-005A reserved */ 82#define RL_MII 0x005A /* 8129 chip only */ 83#define RL_HALTCLK 0x005B 84#define RL_MULTIINTR 0x005C /* multiple interrupt */ 85#define RL_PCIREV 0x005E /* PCI revision value */ 86 /* 005F reserved */ 87#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 88 89/* Direct PHY access registers only available on 8139 */ 90#define RL_BMCR 0x0062 /* PHY basic mode control */ 91#define RL_BMSR 0x0064 /* PHY basic mode status */ 92#define RL_ANAR 0x0066 /* PHY autoneg advert */ 93#define RL_LPAR 0x0068 /* PHY link partner ability */ 94#define RL_ANER 0x006A /* PHY autoneg expansion */ 95 96#define RL_DISCCNT 0x006C /* disconnect counter */ 97#define RL_FALSECAR 0x006E /* false carrier counter */ 98#define RL_NWAYTST 0x0070 /* NWAY test register */ 99#define RL_RX_ER 0x0072 /* RX_ER counter */ 100#define RL_CSCFG 0x0074 /* CS configuration register */ 101 102/* 103 * When operating in special C+ mode, some of the registers in an 104 * 8139C+ chip have different definitions. These are also used for 105 * the 8169 gigE chip. 106 */ 107#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 108#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 109#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 110#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 111#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 112#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 113#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 114#define RL_TXSTART 0x00D9 /* 8 bits */ 115#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 116#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 117#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 118#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 119 120/* 121 * Registers specific to the 8169 gigE chip 122 */ 123#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 124#define RL_PHYAR 0x0060 125#define RL_TBICSR 0x0064 126#define RL_TBI_ANAR 0x0068 127#define RL_TBI_LPAR 0x006A 128#define RL_GMEDIASTAT 0x006C /* 8 bits */ 129#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 130#define RL_GTXSTART 0x0038 /* 16 bits */ 131 132/* 133 * TX config register bits 134 */ 135#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 136#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 137#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 138#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 139#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 140#define RL_TXCFG_HWREV 0x7CC00000 141 142#define RL_HWREV_8169 0x00000000 143#define RL_HWREV_8110 0x00800000 144#define RL_HWREV_8139 0x60000000 145#define RL_HWREV_8139A 0x70000000 146#define RL_HWREV_8139AG 0x70800000 147#define RL_HWREV_8139B 0x78000000 148#define RL_HWREV_8130 0x7C000000 149#define RL_HWREV_8139C 0x74000000 150#define RL_HWREV_8139D 0x74400000 151#define RL_HWREV_8139CPLUS 0x74800000 152#define RL_HWREV_8101 0x74c00000 153#define RL_HWREV_8100 0x78800000 154 155#define RL_TXDMA_16BYTES 0x00000000 156#define RL_TXDMA_32BYTES 0x00000100 157#define RL_TXDMA_64BYTES 0x00000200 158#define RL_TXDMA_128BYTES 0x00000300 159#define RL_TXDMA_256BYTES 0x00000400 160#define RL_TXDMA_512BYTES 0x00000500 161#define RL_TXDMA_1024BYTES 0x00000600 162#define RL_TXDMA_2048BYTES 0x00000700 163 164/* 165 * Transmit descriptor status register bits. 166 */ 167#define RL_TXSTAT_LENMASK 0x00001FFF 168#define RL_TXSTAT_OWN 0x00002000 169#define RL_TXSTAT_TX_UNDERRUN 0x00004000 170#define RL_TXSTAT_TX_OK 0x00008000 171#define RL_TXSTAT_EARLY_THRESH 0x003F0000 172#define RL_TXSTAT_COLLCNT 0x0F000000 173#define RL_TXSTAT_CARR_HBEAT 0x10000000 174#define RL_TXSTAT_OUTOFWIN 0x20000000 175#define RL_TXSTAT_TXABRT 0x40000000 176#define RL_TXSTAT_CARRLOSS 0x80000000 177 178/* 179 * Interrupt status register bits. 180 */ 181#define RL_ISR_RX_OK 0x0001 182#define RL_ISR_RX_ERR 0x0002 183#define RL_ISR_TX_OK 0x0004 184#define RL_ISR_TX_ERR 0x0008 185#define RL_ISR_RX_OVERRUN 0x0010 186#define RL_ISR_PKT_UNDERRUN 0x0020 187#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 188#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 189#define RL_ISR_SWI 0x0100 /* C+ only */ 190#define RL_ISR_CABLE_LEN_CHGD 0x2000 191#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 192#define RL_ISR_TIMEOUT_EXPIRED 0x4000 193#define RL_ISR_SYSTEM_ERR 0x8000 194 195#define RL_INTRS \ 196 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 197 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 198 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 199 200#define RL_INTRS_CPLUS \ 201 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 202 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 203 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 204 205/* 206 * Media status register. (8139 only) 207 */ 208#define RL_MEDIASTAT_RXPAUSE 0x01 209#define RL_MEDIASTAT_TXPAUSE 0x02 210#define RL_MEDIASTAT_LINK 0x04 211#define RL_MEDIASTAT_SPEED10 0x08 212#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 213#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 214 215/* 216 * Receive config register. 217 */ 218#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 219#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 220#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 221#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 222#define RL_RXCFG_RX_RUNT 0x00000010 223#define RL_RXCFG_RX_ERRPKT 0x00000020 224#define RL_RXCFG_WRAP 0x00000080 225#define RL_RXCFG_MAXDMA 0x00000700 226#define RL_RXCFG_BUFSZ 0x00001800 227#define RL_RXCFG_FIFOTHRESH 0x0000E000 228#define RL_RXCFG_EARLYTHRESH 0x07000000 229 230#define RL_RXDMA_16BYTES 0x00000000 231#define RL_RXDMA_32BYTES 0x00000100 232#define RL_RXDMA_64BYTES 0x00000200 233#define RL_RXDMA_128BYTES 0x00000300 234#define RL_RXDMA_256BYTES 0x00000400 235#define RL_RXDMA_512BYTES 0x00000500 236#define RL_RXDMA_1024BYTES 0x00000600 237#define RL_RXDMA_UNLIMITED 0x00000700 238 239#define RL_RXBUF_8 0x00000000 240#define RL_RXBUF_16 0x00000800 241#define RL_RXBUF_32 0x00001000 242#define RL_RXBUF_64 0x00001800 243 244#define RL_RXFIFO_16BYTES 0x00000000 245#define RL_RXFIFO_32BYTES 0x00002000 246#define RL_RXFIFO_64BYTES 0x00004000 247#define RL_RXFIFO_128BYTES 0x00006000 248#define RL_RXFIFO_256BYTES 0x00008000 249#define RL_RXFIFO_512BYTES 0x0000A000 250#define RL_RXFIFO_1024BYTES 0x0000C000 251#define RL_RXFIFO_NOTHRESH 0x0000E000 252 253/* 254 * Bits in RX status header (included with RX'ed packet 255 * in ring buffer). 256 */ 257#define RL_RXSTAT_RXOK 0x00000001 258#define RL_RXSTAT_ALIGNERR 0x00000002 259#define RL_RXSTAT_CRCERR 0x00000004 260#define RL_RXSTAT_GIANT 0x00000008 261#define RL_RXSTAT_RUNT 0x00000010 262#define RL_RXSTAT_BADSYM 0x00000020 263#define RL_RXSTAT_BROAD 0x00002000 264#define RL_RXSTAT_INDIV 0x00004000 265#define RL_RXSTAT_MULTI 0x00008000 266#define RL_RXSTAT_LENMASK 0xFFFF0000 267 268#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 269/* 270 * Command register. 271 */ 272#define RL_CMD_EMPTY_RXBUF 0x0001 273#define RL_CMD_TX_ENB 0x0004 274#define RL_CMD_RX_ENB 0x0008 275#define RL_CMD_RESET 0x0010 276 277/* 278 * EEPROM control register 279 */ 280#define RL_EE_DATAOUT 0x01 /* Data out */ 281#define RL_EE_DATAIN 0x02 /* Data in */ 282#define RL_EE_CLK 0x04 /* clock */ 283#define RL_EE_SEL 0x08 /* chip select */ 284#define RL_EE_MODE (0x40|0x80) 285 286#define RL_EEMODE_OFF 0x00 287#define RL_EEMODE_AUTOLOAD 0x40 288#define RL_EEMODE_PROGRAM 0x80 289#define RL_EEMODE_WRITECFG (0x80|0x40) 290 291/* 9346 EEPROM commands */ 292#define RL_EECMD_WRITE 0x140 293#define RL_EECMD_READ_6BIT 0x180 294#define RL_EECMD_READ_8BIT 0x600 295#define RL_EECMD_ERASE 0x1c0 296 297#define RL_EE_ID 0x00 298#define RL_EE_PCI_VID 0x01 299#define RL_EE_PCI_DID 0x02 300/* Location of station address inside EEPROM */ 301#define RL_EE_EADDR 0x07 302 303/* 304 * MII register (8129 only) 305 */ 306#define RL_MII_CLK 0x01 307#define RL_MII_DATAIN 0x02 308#define RL_MII_DATAOUT 0x04 309#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 310 311/* 312 * Config 0 register 313 */ 314#define RL_CFG0_ROM0 0x01 315#define RL_CFG0_ROM1 0x02 316#define RL_CFG0_ROM2 0x04 317#define RL_CFG0_PL0 0x08 318#define RL_CFG0_PL1 0x10 319#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 320#define RL_CFG0_PCS 0x40 321#define RL_CFG0_SCR 0x80 322 323/* 324 * Config 1 register 325 */ 326#define RL_CFG1_PWRDWN 0x01 327#define RL_CFG1_SLEEP 0x02 328#define RL_CFG1_IOMAP 0x04 329#define RL_CFG1_MEMMAP 0x08 330#define RL_CFG1_RSVD 0x10 331#define RL_CFG1_DRVLOAD 0x20 332#define RL_CFG1_LED0 0x40 333#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 334#define RL_CFG1_LED1 0x80 335 336/* 337 * 8139C+ register definitions 338 */ 339 340/* RL_DUMPSTATS_LO register */ 341 342#define RL_DUMPSTATS_START 0x00000008 343 344/* Transmit start register */ 345 346#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 347#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 348#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 349 350/* C+ mode command register */ 351 352#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 353#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 354#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 355#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 356#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 357#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 358 359/* C+ early transmit threshold */ 360 361#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 362 363/* 364 * Gigabit PHY access register (8169 only) 365 */ 366 367#define RL_PHYAR_PHYDATA 0x0000FFFF 368#define RL_PHYAR_PHYREG 0x001F0000 369#define RL_PHYAR_BUSY 0x80000000 370 371/* 372 * Gigabit media status (8169 only) 373 */ 374#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 375#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 376#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 377#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 378#define RL_GMEDIASTAT_1000MPS 0x10 /* gigE link */ 379#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 380#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 381#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 382 383/* 384 * The RealTek doesn't use a fragment-based descriptor mechanism. 385 * Instead, there are only four register sets, each or which represents 386 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 387 * packet buffer (32-bit aligned!) and we place the buffer addresses in 388 * the registers so the chip knows where they are. 389 * 390 * We can sort of kludge together the same kind of buffer management 391 * used in previous drivers, but we have to do buffer copies almost all 392 * the time, so it doesn't really buy us much. 393 * 394 * For reception, there's just one large buffer where the chip stores 395 * all received packets. 396 */ 397 398#define RL_RX_BUF_SZ RL_RXBUF_64 399#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 400#define RL_TX_LIST_CNT 4 401#define RL_MIN_FRAMELEN 60 402#define RL_TXTHRESH(x) ((x) << 11) 403#define RL_TX_THRESH_INIT 96 404#define RL_RX_FIFOTHRESH RL_RXFIFO_256BYTES 405#define RL_RX_MAXDMA RL_RXDMA_1024BYTES /*RL_RXDMA_UNLIMITED*/ 406#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 407 408#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 409#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 410 411#define RL_ETHER_ALIGN 2 412 413struct rl_chain_data { 414 u_int16_t cur_rx; 415 caddr_t rl_rx_buf; 416 caddr_t rl_rx_buf_ptr; 417 bus_dmamap_t rl_rx_dmamap; 418 419 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 420 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 421 u_int8_t last_tx; 422 u_int8_t cur_tx; 423}; 424 425#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 426#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 427#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 428#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 429#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 430#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 431#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 432#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 433#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 434 435struct rl_type { 436 u_int16_t rl_vid; 437 u_int16_t rl_did; 438 int rl_basetype; 439 char *rl_name; 440}; 441 442struct rl_hwrev { 443 u_int32_t rl_rev; 444 int rl_type; 445 char *rl_desc; 446}; 447 448struct rl_mii_frame { 449 u_int8_t mii_stdelim; 450 u_int8_t mii_opcode; 451 u_int8_t mii_phyaddr; 452 u_int8_t mii_regaddr; 453 u_int8_t mii_turnaround; 454 u_int16_t mii_data; 455}; 456 457/* 458 * MII constants 459 */ 460#define RL_MII_STARTDELIM 0x01 461#define RL_MII_READOP 0x02 462#define RL_MII_WRITEOP 0x01 463#define RL_MII_TURNAROUND 0x02 464 465#define RL_8129 1 466#define RL_8139 2 467#define RL_8139CPLUS 3 468#define RL_8169 4 469 470#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 471 (x)->rl_type == RL_8169) 472 473/* 474 * The 8139C+ and 8160 gigE chips support descriptor-based TX 475 * and RX. In fact, they even support TCP large send. Descriptors 476 * must be allocated in contiguous blocks that are aligned on a 477 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 478 */ 479 480/* 481 * RX/TX descriptor definition. When large send mode is enabled, the 482 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 483 * the checksum offload bits are disabled. The structure layout is 484 * the same for RX and TX descriptors 485 */ 486 487struct rl_desc { 488 u_int32_t rl_cmdstat; 489 u_int32_t rl_vlanctl; 490 u_int32_t rl_bufaddr_lo; 491 u_int32_t rl_bufaddr_hi; 492}; 493 494#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 495#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 496#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 497#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 498#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 499#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 500#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 501#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 502#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 503#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 504 505#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 506#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 507 508/* 509 * Error bits are valid only on the last descriptor of a frame 510 * (i.e. RL_TDESC_CMD_EOF == 1) 511 */ 512 513#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 514#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 515#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 516#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 517#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 518#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 519#define RL_TDESC_STAT_OWN 0x80000000 520 521/* 522 * RX descriptor cmd/vlan definitions 523 */ 524 525#define RL_RDESC_CMD_EOR 0x40000000 526#define RL_RDESC_CMD_OWN 0x80000000 527#define RL_RDESC_CMD_BUFLEN 0x00001FFF 528 529#define RL_RDESC_STAT_OWN 0x80000000 530#define RL_RDESC_STAT_EOR 0x40000000 531#define RL_RDESC_STAT_SOF 0x20000000 532#define RL_RDESC_STAT_EOF 0x10000000 533#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 534#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 535#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 536#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 537#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 538#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 539#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 540#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 541#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 542#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 543#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 544#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 545#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 546#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 547#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 548 549#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 550 (rl_vlandata valid)*/ 551#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 552 553#define RL_PROTOID_NONIP 0x00000000 554#define RL_PROTOID_TCPIP 0x00010000 555#define RL_PROTOID_UDPIP 0x00020000 556#define RL_PROTOID_IP 0x00030000 557#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 558 RL_PROTOID_TCPIP) 559#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 560 RL_PROTOID_UDPIP) 561 562/* 563 * Statistics counter structure (8139C+ and 8169 only) 564 */ 565struct rl_stats { 566 u_int32_t rl_tx_pkts_lo; 567 u_int32_t rl_tx_pkts_hi; 568 u_int32_t rl_tx_errs_lo; 569 u_int32_t rl_tx_errs_hi; 570 u_int32_t rl_tx_errs; 571 u_int16_t rl_missed_pkts; 572 u_int16_t rl_rx_framealign_errs; 573 u_int32_t rl_tx_onecoll; 574 u_int32_t rl_tx_multicolls; 575 u_int32_t rl_rx_ucasts_hi; 576 u_int32_t rl_rx_ucasts_lo; 577 u_int32_t rl_rx_bcasts_lo; 578 u_int32_t rl_rx_bcasts_hi; 579 u_int32_t rl_rx_mcasts; 580 u_int16_t rl_tx_aborts; 581 u_int16_t rl_rx_underruns; 582}; 583 584#define RL_RX_DESC_CNT 64 585#define RL_TX_DESC_CNT 64 586#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) 587#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc)) 588#define RL_RING_ALIGN 256 589#define RL_IFQ_MAXLEN 512 590#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT) 591#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 592#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & \ 593 RL_RDESC_STAT_FRAGLEN) 594#define RL_PKTSZ(x) ((x) >> 3) 595 596#define RL_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF) 597#define RL_ADDR_HI(y) ((u_int64_t) (y) >> 32) 598 599struct rl_softc; 600 601struct rl_dmaload_arg { 602 struct rl_softc *sc; 603 int rl_idx; 604 int rl_maxsegs; 605 struct rl_desc *rl_ring; 606}; 607 608struct rl_list_data { 609 struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT]; 610 struct mbuf *rl_rx_mbuf[RL_TX_DESC_CNT]; 611 int rl_tx_prodidx; 612 int rl_rx_prodidx; 613 int rl_tx_considx; 614 int rl_tx_free; 615 bus_dmamap_t rl_tx_dmamap[RL_TX_DESC_CNT]; 616 bus_dmamap_t rl_rx_dmamap[RL_RX_DESC_CNT]; 617 bus_dma_tag_t rl_mtag; /* mbuf mapping tag */ 618 bus_dma_tag_t rl_stag; /* stats mapping tag */ 619 bus_dmamap_t rl_smap; /* stats map */ 620 struct rl_stats *rl_stats; 621 bus_addr_t rl_stats_addr; 622 bus_dma_tag_t rl_rx_list_tag; 623 bus_dmamap_t rl_rx_list_map; 624 struct rl_desc *rl_rx_list; 625 bus_addr_t rl_rx_list_addr; 626 bus_dma_tag_t rl_tx_list_tag; 627 bus_dmamap_t rl_tx_list_map; 628 struct rl_desc *rl_tx_list; 629 bus_addr_t rl_tx_list_addr; 630}; 631 632struct rl_softc { 633 struct arpcom arpcom; /* interface info */ 634 bus_space_handle_t rl_bhandle; /* bus space handle */ 635 bus_space_tag_t rl_btag; /* bus space tag */ 636 struct resource *rl_res; 637 struct resource *rl_irq; 638 void *rl_intrhand; 639 device_t rl_miibus; 640 bus_dma_tag_t rl_parent_tag; 641 bus_dma_tag_t rl_tag; 642 u_int8_t rl_unit; /* interface number */ 643 u_int8_t rl_type; 644 int rl_eecmd_read; 645 u_int8_t rl_stats_no_timeout; 646 int rl_txthresh; 647 struct rl_chain_data rl_cdata; 648 struct rl_list_data rl_ldata; 649 struct callout_handle rl_stat_ch; 650 struct mtx rl_mtx; 651 int suspended; /* 0 = normal 1 = suspended */ 652#ifdef DEVICE_POLLING 653 int rxcycles; 654#endif 655 656 u_int32_t saved_maps[5]; /* pci data */ 657 u_int32_t saved_biosaddr; 658 u_int8_t saved_intline; 659 u_int8_t saved_cachelnsz; 660 u_int8_t saved_lattimer; 661}; 662 663#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 664#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 665 666/* 667 * register space access macros 668 */ 669#define CSR_WRITE_4(sc, reg, val) \ 670 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 671#define CSR_WRITE_2(sc, reg, val) \ 672 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 673#define CSR_WRITE_1(sc, reg, val) \ 674 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 675 676#define CSR_READ_4(sc, reg) \ 677 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 678#define CSR_READ_2(sc, reg) \ 679 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 680#define CSR_READ_1(sc, reg) \ 681 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 682 683#define RL_TIMEOUT 1000 684 685/* 686 * General constants that are fun to know. 687 * 688 * RealTek PCI vendor ID 689 */ 690#define RT_VENDORID 0x10EC 691 692/* 693 * RealTek chip device IDs. 694 */ 695#define RT_DEVICEID_8129 0x8129 696#define RT_DEVICEID_8138 0x8138 697#define RT_DEVICEID_8139 0x8139 698#define RT_DEVICEID_8169 0x8169 699 700#define RT_REVID_8139CPLUS 0x20 701 702/* 703 * Accton PCI vendor ID 704 */ 705#define ACCTON_VENDORID 0x1113 706 707/* 708 * Accton MPX 5030/5038 device ID. 709 */ 710#define ACCTON_DEVICEID_5030 0x1211 711 712/* 713 * Nortel PCI vendor ID 714 */ 715#define NORTEL_VENDORID 0x126C 716 717/* 718 * Delta Electronics Vendor ID. 719 */ 720#define DELTA_VENDORID 0x1500 721 722/* 723 * Delta device IDs. 724 */ 725#define DELTA_DEVICEID_8139 0x1360 726 727/* 728 * Addtron vendor ID. 729 */ 730#define ADDTRON_VENDORID 0x4033 731 732/* 733 * Addtron device IDs. 734 */ 735#define ADDTRON_DEVICEID_8139 0x1360 736 737/* 738 * D-Link vendor ID. 739 */ 740#define DLINK_VENDORID 0x1186 741 742/* 743 * D-Link DFE-530TX+ device ID 744 */ 745#define DLINK_DEVICEID_530TXPLUS 0x1300 746 747/* 748 * D-Link DFE-690TXD device ID 749 */ 750#define DLINK_DEVICEID_690TXD 0x1340 751 752/* 753 * Corega K.K vendor ID 754 */ 755#define COREGA_VENDORID 0x1259 756 757/* 758 * Corega FEther CB-TXD device ID 759 */ 760#define COREGA_DEVICEID_FETHERCBTXD 0xa117 761 762/* 763 * Corega FEtherII CB-TXD device ID 764 */ 765#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 766 767/* 768 * Peppercon vendor ID 769 */ 770#define PEPPERCON_VENDORID 0x1743 771 772/* 773 * Peppercon ROL-F device ID 774 */ 775#define PEPPERCON_DEVICEID_ROLF 0x8139 776 777/* 778 * Planex Communications, Inc. vendor ID 779 */ 780#define PLANEX_VENDORID 0x14ea 781 782/* 783 * Planex FNW-3800-TX device ID 784 */ 785#define PLANEX_DEVICEID_FNW3800TX 0xab07 786 787/* 788 * LevelOne vendor ID 789 */ 790#define LEVEL1_VENDORID 0x018A 791 792/* 793 * LevelOne FPC-0106TX devide ID 794 */ 795#define LEVEL1_DEVICEID_FPC0106TX 0x0106 796 797/* 798 * Compaq vendor ID 799 */ 800#define CP_VENDORID 0x021B 801 802/* 803 * Edimax vendor ID 804 */ 805#define EDIMAX_VENDORID 0x13D1 806 807/* 808 * Edimax EP-4103DL cardbus device ID 809 */ 810#define EDIMAX_DEVICEID_EP4103DL 0xAB06 811 812/* 813 * PCI low memory base and low I/O base register, and 814 * other PCI registers. 815 */ 816 817#define RL_PCI_VENDOR_ID 0x00 818#define RL_PCI_DEVICE_ID 0x02 819#define RL_PCI_COMMAND 0x04 820#define RL_PCI_STATUS 0x06 821#define RL_PCI_CLASSCODE 0x09 822#define RL_PCI_LATENCY_TIMER 0x0D 823#define RL_PCI_HEADER_TYPE 0x0E 824#define RL_PCI_LOIO 0x10 825#define RL_PCI_LOMEM 0x14 826#define RL_PCI_BIOSROM 0x30 827#define RL_PCI_INTLINE 0x3C 828#define RL_PCI_INTPIN 0x3D 829#define RL_PCI_MINGNT 0x3E 830#define RL_PCI_MINLAT 0x0F 831#define RL_PCI_RESETOPT 0x48 832#define RL_PCI_EEPROM_DATA 0x4C 833 834#define RL_PCI_CAPID 0x50 /* 8 bits */ 835#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 836#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 837#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 838 839#define RL_PSTATE_MASK 0x0003 840#define RL_PSTATE_D0 0x0000 841#define RL_PSTATE_D1 0x0002 842#define RL_PSTATE_D2 0x0002 843#define RL_PSTATE_D3 0x0003 844#define RL_PME_EN 0x0010 845#define RL_PME_STATUS 0x8000 846