if_rlreg.h revision 117388
1/* 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_rlreg.h 117388 2003-07-10 20:38:48Z wpaul $ 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 41#define RL_IDR3 0x0003 42#define RL_IDR4 0x0004 43#define RL_IDR5 0x0005 44 /* 0006-0007 reserved */ 45#define RL_MAR0 0x0008 /* Multicast hash table */ 46#define RL_MAR1 0x0009 47#define RL_MAR2 0x000A 48#define RL_MAR3 0x000B 49#define RL_MAR4 0x000C 50#define RL_MAR5 0x000D 51#define RL_MAR6 0x000E 52#define RL_MAR7 0x000F 53 54#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 58 59#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 63 64#define RL_RXADDR 0x0030 /* RX ring start address */ 65#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67#define RL_COMMAND 0x0037 /* command register */ 68#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70#define RL_IMR 0x003C /* interrupt mask register */ 71#define RL_ISR 0x003E /* interrupt status register */ 72#define RL_TXCFG 0x0040 /* transmit config */ 73#define RL_RXCFG 0x0044 /* receive config */ 74#define RL_TIMERCNT 0x0048 /* timer count register */ 75#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76#define RL_EECMD 0x0050 /* EEPROM command register */ 77#define RL_CFG0 0x0051 /* config register #0 */ 78#define RL_CFG1 0x0052 /* config register #1 */ 79 /* 0053-0057 reserved */ 80#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 81 /* 0059-005A reserved */ 82#define RL_MII 0x005A /* 8129 chip only */ 83#define RL_HALTCLK 0x005B 84#define RL_MULTIINTR 0x005C /* multiple interrupt */ 85#define RL_PCIREV 0x005E /* PCI revision value */ 86 /* 005F reserved */ 87#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 88 89/* Direct PHY access registers only available on 8139 */ 90#define RL_BMCR 0x0062 /* PHY basic mode control */ 91#define RL_BMSR 0x0064 /* PHY basic mode status */ 92#define RL_ANAR 0x0066 /* PHY autoneg advert */ 93#define RL_LPAR 0x0068 /* PHY link partner ability */ 94#define RL_ANER 0x006A /* PHY autoneg expansion */ 95 96#define RL_DISCCNT 0x006C /* disconnect counter */ 97#define RL_FALSECAR 0x006E /* false carrier counter */ 98#define RL_NWAYTST 0x0070 /* NWAY test register */ 99#define RL_RX_ER 0x0072 /* RX_ER counter */ 100#define RL_CSCFG 0x0074 /* CS configuration register */ 101 102/* 103 * When operating in special C+ mode, some of the registers in an 104 * 8139C+ chip have different definitions. These are also used for 105 * the 8169 gigE chip. 106 */ 107#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 108#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 109#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 110#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 111#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 112#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 113#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 114#define RL_TXSTART 0x00D9 /* 8 bits */ 115#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 116#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 117#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 118#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 119 120/* 121 * Registers specific to the 8169 gigE chip 122 */ 123#define RL_PHYAR 0x0060 124#define RL_TBICSR 0x0064 125#define RL_TBI_ANAR 0x0068 126#define RL_TBI_LPAR 0x006A 127#define RL_GMEDIASTAT 0x006C /* 8 bits */ 128#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 129#define RL_GTXSTART 0x0038 /* 16 bits */ 130 131/* 132 * TX config register bits 133 */ 134#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 135#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 136#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 137#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 138#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 139#define RL_TXCFG_HWREV 0x7CC00000 140 141#define RL_HWREV_8139 0x60000000 142#define RL_HWREV_8139A 0x70000000 143#define RL_HWREV_8139AG 0x70800000 144#define RL_HWREV_8139B 0x78000000 145#define RL_HWREV_8130 0x7C000000 146#define RL_HWREV_8139C 0x74000000 147#define RL_HWREV_8139D 0x74400000 148#define RL_HWREV_8139CPLUS 0x74800000 149 150#define RL_TXDMA_16BYTES 0x00000000 151#define RL_TXDMA_32BYTES 0x00000100 152#define RL_TXDMA_64BYTES 0x00000200 153#define RL_TXDMA_128BYTES 0x00000300 154#define RL_TXDMA_256BYTES 0x00000400 155#define RL_TXDMA_512BYTES 0x00000500 156#define RL_TXDMA_1024BYTES 0x00000600 157#define RL_TXDMA_2048BYTES 0x00000700 158 159/* 160 * Transmit descriptor status register bits. 161 */ 162#define RL_TXSTAT_LENMASK 0x00001FFF 163#define RL_TXSTAT_OWN 0x00002000 164#define RL_TXSTAT_TX_UNDERRUN 0x00004000 165#define RL_TXSTAT_TX_OK 0x00008000 166#define RL_TXSTAT_EARLY_THRESH 0x003F0000 167#define RL_TXSTAT_COLLCNT 0x0F000000 168#define RL_TXSTAT_CARR_HBEAT 0x10000000 169#define RL_TXSTAT_OUTOFWIN 0x20000000 170#define RL_TXSTAT_TXABRT 0x40000000 171#define RL_TXSTAT_CARRLOSS 0x80000000 172 173/* 174 * Interrupt status register bits. 175 */ 176#define RL_ISR_RX_OK 0x0001 177#define RL_ISR_RX_ERR 0x0002 178#define RL_ISR_TX_OK 0x0004 179#define RL_ISR_TX_ERR 0x0008 180#define RL_ISR_RX_OVERRUN 0x0010 181#define RL_ISR_PKT_UNDERRUN 0x0020 182#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 183#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 184#define RL_ISR_SWI 0x0100 /* C+ only */ 185#define RL_ISR_CABLE_LEN_CHGD 0x2000 186#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 187#define RL_ISR_TIMEOUT_EXPIRED 0x4000 188#define RL_ISR_SYSTEM_ERR 0x8000 189 190#define RL_INTRS \ 191 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 192 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 193 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 194 195#define RL_INTRS_CPLUS \ 196 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 197 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 198 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 199 200/* 201 * Media status register. (8139 only) 202 */ 203#define RL_MEDIASTAT_RXPAUSE 0x01 204#define RL_MEDIASTAT_TXPAUSE 0x02 205#define RL_MEDIASTAT_LINK 0x04 206#define RL_MEDIASTAT_SPEED10 0x08 207#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 208#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 209 210/* 211 * Receive config register. 212 */ 213#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 214#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 215#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 216#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 217#define RL_RXCFG_RX_RUNT 0x00000010 218#define RL_RXCFG_RX_ERRPKT 0x00000020 219#define RL_RXCFG_WRAP 0x00000080 220#define RL_RXCFG_MAXDMA 0x00000700 221#define RL_RXCFG_BUFSZ 0x00001800 222#define RL_RXCFG_FIFOTHRESH 0x0000E000 223#define RL_RXCFG_EARLYTHRESH 0x07000000 224 225#define RL_RXDMA_16BYTES 0x00000000 226#define RL_RXDMA_32BYTES 0x00000100 227#define RL_RXDMA_64BYTES 0x00000200 228#define RL_RXDMA_128BYTES 0x00000300 229#define RL_RXDMA_256BYTES 0x00000400 230#define RL_RXDMA_512BYTES 0x00000500 231#define RL_RXDMA_1024BYTES 0x00000600 232#define RL_RXDMA_UNLIMITED 0x00000700 233 234#define RL_RXBUF_8 0x00000000 235#define RL_RXBUF_16 0x00000800 236#define RL_RXBUF_32 0x00001000 237#define RL_RXBUF_64 0x00001800 238 239#define RL_RXFIFO_16BYTES 0x00000000 240#define RL_RXFIFO_32BYTES 0x00002000 241#define RL_RXFIFO_64BYTES 0x00004000 242#define RL_RXFIFO_128BYTES 0x00006000 243#define RL_RXFIFO_256BYTES 0x00008000 244#define RL_RXFIFO_512BYTES 0x0000A000 245#define RL_RXFIFO_1024BYTES 0x0000C000 246#define RL_RXFIFO_NOTHRESH 0x0000E000 247 248/* 249 * Bits in RX status header (included with RX'ed packet 250 * in ring buffer). 251 */ 252#define RL_RXSTAT_RXOK 0x00000001 253#define RL_RXSTAT_ALIGNERR 0x00000002 254#define RL_RXSTAT_CRCERR 0x00000004 255#define RL_RXSTAT_GIANT 0x00000008 256#define RL_RXSTAT_RUNT 0x00000010 257#define RL_RXSTAT_BADSYM 0x00000020 258#define RL_RXSTAT_BROAD 0x00002000 259#define RL_RXSTAT_INDIV 0x00004000 260#define RL_RXSTAT_MULTI 0x00008000 261#define RL_RXSTAT_LENMASK 0xFFFF0000 262 263#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 264/* 265 * Command register. 266 */ 267#define RL_CMD_EMPTY_RXBUF 0x0001 268#define RL_CMD_TX_ENB 0x0004 269#define RL_CMD_RX_ENB 0x0008 270#define RL_CMD_RESET 0x0010 271 272/* 273 * EEPROM control register 274 */ 275#define RL_EE_DATAOUT 0x01 /* Data out */ 276#define RL_EE_DATAIN 0x02 /* Data in */ 277#define RL_EE_CLK 0x04 /* clock */ 278#define RL_EE_SEL 0x08 /* chip select */ 279#define RL_EE_MODE (0x40|0x80) 280 281#define RL_EEMODE_OFF 0x00 282#define RL_EEMODE_AUTOLOAD 0x40 283#define RL_EEMODE_PROGRAM 0x80 284#define RL_EEMODE_WRITECFG (0x80|0x40) 285 286/* 9346 EEPROM commands */ 287#define RL_EECMD_WRITE 0x140 288#define RL_EECMD_READ_6BIT 0x180 289#define RL_EECMD_READ_8BIT 0x600 290#define RL_EECMD_ERASE 0x1c0 291 292#define RL_EE_ID 0x00 293#define RL_EE_PCI_VID 0x01 294#define RL_EE_PCI_DID 0x02 295/* Location of station address inside EEPROM */ 296#define RL_EE_EADDR 0x07 297 298/* 299 * MII register (8129 only) 300 */ 301#define RL_MII_CLK 0x01 302#define RL_MII_DATAIN 0x02 303#define RL_MII_DATAOUT 0x04 304#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 305 306/* 307 * Config 0 register 308 */ 309#define RL_CFG0_ROM0 0x01 310#define RL_CFG0_ROM1 0x02 311#define RL_CFG0_ROM2 0x04 312#define RL_CFG0_PL0 0x08 313#define RL_CFG0_PL1 0x10 314#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 315#define RL_CFG0_PCS 0x40 316#define RL_CFG0_SCR 0x80 317 318/* 319 * Config 1 register 320 */ 321#define RL_CFG1_PWRDWN 0x01 322#define RL_CFG1_SLEEP 0x02 323#define RL_CFG1_IOMAP 0x04 324#define RL_CFG1_MEMMAP 0x08 325#define RL_CFG1_RSVD 0x10 326#define RL_CFG1_DRVLOAD 0x20 327#define RL_CFG1_LED0 0x40 328#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 329#define RL_CFG1_LED1 0x80 330 331/* 332 * 8139C+ register definitions 333 */ 334 335/* RL_DUMPSTATS_LO register */ 336 337#define RL_DUMPSTATS_START 0x00000008 338 339/* Transmit start register */ 340 341#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 342#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 343#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 344 345/* C+ mode command register */ 346 347#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 348#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 349#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 350#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 351#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 352#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 353 354/* C+ early transmit threshold */ 355 356#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 357 358/* 359 * Gigabit PHY access register (8169 only) 360 */ 361 362#define RL_PHYAR_PHYDATA 0x0000FFFF 363#define RL_PHYAR_PHYREG 0x001F0000 364#define RL_PHYAR_BUSY 0x80000000 365 366/* 367 * Gigabit media status (8169 only) 368 */ 369#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 370#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 371#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 372#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 373#define RL_GMEDIASTAT_1000MPS 0x10 /* gigE link */ 374#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 375#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 376#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 377 378/* 379 * The RealTek doesn't use a fragment-based descriptor mechanism. 380 * Instead, there are only four register sets, each or which represents 381 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 382 * packet buffer (32-bit aligned!) and we place the buffer addresses in 383 * the registers so the chip knows where they are. 384 * 385 * We can sort of kludge together the same kind of buffer management 386 * used in previous drivers, but we have to do buffer copies almost all 387 * the time, so it doesn't really buy us much. 388 * 389 * For reception, there's just one large buffer where the chip stores 390 * all received packets. 391 */ 392 393#define RL_RX_BUF_SZ RL_RXBUF_64 394#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 395#define RL_TX_LIST_CNT 4 396#define RL_MIN_FRAMELEN 60 397#define RL_TXTHRESH(x) ((x) << 11) 398#define RL_TX_THRESH_INIT 96 399#define RL_RX_FIFOTHRESH RL_RXFIFO_256BYTES 400#define RL_RX_MAXDMA RL_RXDMA_1024BYTES /*RL_RXDMA_UNLIMITED*/ 401#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 402 403#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 404#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 405 406#define RL_ETHER_ALIGN 2 407 408struct rl_chain_data { 409 u_int16_t cur_rx; 410 caddr_t rl_rx_buf; 411 caddr_t rl_rx_buf_ptr; 412 bus_dmamap_t rl_rx_dmamap; 413 414 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 415 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 416 u_int8_t last_tx; 417 u_int8_t cur_tx; 418}; 419 420#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 421#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 422#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 423#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 424#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 425#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 426#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 427#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 428#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 429 430struct rl_type { 431 u_int16_t rl_vid; 432 u_int16_t rl_did; 433 int rl_basetype; 434 char *rl_name; 435}; 436 437struct rl_hwrev { 438 u_int32_t rl_rev; 439 int rl_type; 440 char *rl_desc; 441}; 442 443struct rl_mii_frame { 444 u_int8_t mii_stdelim; 445 u_int8_t mii_opcode; 446 u_int8_t mii_phyaddr; 447 u_int8_t mii_regaddr; 448 u_int8_t mii_turnaround; 449 u_int16_t mii_data; 450}; 451 452/* 453 * MII constants 454 */ 455#define RL_MII_STARTDELIM 0x01 456#define RL_MII_READOP 0x02 457#define RL_MII_WRITEOP 0x01 458#define RL_MII_TURNAROUND 0x02 459 460#define RL_8129 1 461#define RL_8139 2 462#define RL_8139CPLUS 3 463#define RL_8169 4 464 465#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 466 (x)->rl_type == RL_8169) 467 468/* 469 * The 8139C+ and 8160 gigE chips support descriptor-based TX 470 * and RX. In fact, they even support TCP large send. Descriptors 471 * must be allocated in contiguous blocks that are aligned on a 472 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 473 */ 474 475/* 476 * RX/TX descriptor definition. When large send mode is enabled, the 477 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 478 * the checksum offload bits are disabled. The structure layout is 479 * the same for RX and TX descriptors 480 */ 481 482struct rl_desc { 483 u_int32_t rl_cmdstat; 484 u_int32_t rl_vlanctl; 485 u_int32_t rl_bufaddr_lo; 486 u_int32_t rl_bufaddr_hi; 487}; 488 489#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 490#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 491#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 492#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 493#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 494#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 495#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 496#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 497#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 498#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 499 500#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 501#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 502 503/* 504 * Error bits are valid only on the last descriptor of a frame 505 * (i.e. RL_TDESC_CMD_EOF == 1) 506 */ 507 508#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 509#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 510#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 511#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 512#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 513#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 514#define RL_TDESC_STAT_OWN 0x80000000 515 516/* 517 * RX descriptor cmd/vlan definitions 518 */ 519 520#define RL_RDESC_CMD_EOR 0x40000000 521#define RL_RDESC_CMD_OWN 0x80000000 522#define RL_RDESC_CMD_BUFLEN 0x00001FFF 523 524#define RL_RDESC_STAT_OWN 0x80000000 525#define RL_RDESC_STAT_EOR 0x40000000 526#define RL_RDESC_STAT_SOF 0x20000000 527#define RL_RDESC_STAT_EOF 0x10000000 528#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 529#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 530#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 531#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 532#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 533#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 534#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 535#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 536#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 537#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 538#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 539#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 540#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 541#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 542#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 543 544#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 545 (rl_vlandata valid)*/ 546#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 547 548#define RL_PROTOID_NONIP 0x00000000 549#define RL_PROTOID_TCPIP 0x00010000 550#define RL_PROTOID_UDPIP 0x00020000 551#define RL_PROTOID_IP 0x00030000 552#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 553 RL_PROTOID_TCPIP) 554#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 555 RL_PROTOID_UDPIP) 556 557/* 558 * Statistics counter structure (8139C+ and 8169 only) 559 */ 560struct rl_stats { 561 u_int32_t rl_tx_pkts_lo; 562 u_int32_t rl_tx_pkts_hi; 563 u_int32_t rl_tx_errs_lo; 564 u_int32_t rl_tx_errs_hi; 565 u_int32_t rl_tx_errs; 566 u_int16_t rl_missed_pkts; 567 u_int16_t rl_rx_framealign_errs; 568 u_int32_t rl_tx_onecoll; 569 u_int32_t rl_tx_multicolls; 570 u_int32_t rl_rx_ucasts_hi; 571 u_int32_t rl_rx_ucasts_lo; 572 u_int32_t rl_rx_bcasts_lo; 573 u_int32_t rl_rx_bcasts_hi; 574 u_int32_t rl_rx_mcasts; 575 u_int16_t rl_tx_aborts; 576 u_int16_t rl_rx_underruns; 577}; 578 579#define RL_RX_DESC_CNT 64 580#define RL_TX_DESC_CNT 64 581#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) 582#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc)) 583#define RL_RING_ALIGN 256 584#define RL_IFQ_MAXLEN 512 585#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT) 586#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 587#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & \ 588 RL_RDESC_STAT_FRAGLEN) 589#define RL_PKTSZ(x) ((x) >> 3) 590 591struct rl_softc; 592 593struct rl_dmaload_arg { 594 struct rl_softc *sc; 595 int rl_idx; 596 int rl_maxsegs; 597 struct rl_desc *rl_ring; 598}; 599 600struct rl_list_data { 601 struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT]; 602 struct mbuf *rl_rx_mbuf[RL_TX_DESC_CNT]; 603 int rl_tx_prodidx; 604 int rl_rx_prodidx; 605 int rl_tx_considx; 606 int rl_tx_free; 607 bus_dmamap_t rl_tx_dmamap[RL_TX_DESC_CNT]; 608 bus_dmamap_t rl_rx_dmamap[RL_RX_DESC_CNT]; 609 bus_dma_tag_t rl_mtag; /* mbuf mapping tag */ 610 bus_dma_tag_t rl_stag; /* stats mapping tag */ 611 bus_dmamap_t rl_smap; /* stats map */ 612 struct rl_stats *rl_stats; 613 u_int32_t rl_stats_addr; 614 bus_dma_tag_t rl_rx_list_tag; 615 bus_dmamap_t rl_rx_list_map; 616 struct rl_desc *rl_rx_list; 617 u_int32_t rl_rx_list_addr; 618 bus_dma_tag_t rl_tx_list_tag; 619 bus_dmamap_t rl_tx_list_map; 620 struct rl_desc *rl_tx_list; 621 u_int32_t rl_tx_list_addr; 622}; 623 624struct rl_softc { 625 struct arpcom arpcom; /* interface info */ 626 bus_space_handle_t rl_bhandle; /* bus space handle */ 627 bus_space_tag_t rl_btag; /* bus space tag */ 628 struct resource *rl_res; 629 struct resource *rl_irq; 630 void *rl_intrhand; 631 device_t rl_miibus; 632 bus_dma_tag_t rl_parent_tag; 633 bus_dma_tag_t rl_tag; 634 u_int8_t rl_unit; /* interface number */ 635 u_int8_t rl_type; 636 int rl_eecmd_read; 637 u_int8_t rl_stats_no_timeout; 638 int rl_txthresh; 639 struct rl_chain_data rl_cdata; 640 struct rl_list_data rl_ldata; 641 struct callout_handle rl_stat_ch; 642 struct mtx rl_mtx; 643 int suspended; /* 0 = normal 1 = suspended */ 644#ifdef DEVICE_POLLING 645 int rxcycles; 646#endif 647 648 u_int32_t saved_maps[5]; /* pci data */ 649 u_int32_t saved_biosaddr; 650 u_int8_t saved_intline; 651 u_int8_t saved_cachelnsz; 652 u_int8_t saved_lattimer; 653}; 654 655#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 656#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 657 658/* 659 * register space access macros 660 */ 661#define CSR_WRITE_4(sc, reg, val) \ 662 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 663#define CSR_WRITE_2(sc, reg, val) \ 664 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 665#define CSR_WRITE_1(sc, reg, val) \ 666 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 667 668#define CSR_READ_4(sc, reg) \ 669 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 670#define CSR_READ_2(sc, reg) \ 671 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 672#define CSR_READ_1(sc, reg) \ 673 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 674 675#define RL_TIMEOUT 1000 676 677/* 678 * General constants that are fun to know. 679 * 680 * RealTek PCI vendor ID 681 */ 682#define RT_VENDORID 0x10EC 683 684/* 685 * RealTek chip device IDs. 686 */ 687#define RT_DEVICEID_8129 0x8129 688#define RT_DEVICEID_8138 0x8138 689#define RT_DEVICEID_8139 0x8139 690#define RT_DEVICEID_8169 0x8169 691 692#define RT_REVID_8139CPLUS 0x20 693 694/* 695 * Accton PCI vendor ID 696 */ 697#define ACCTON_VENDORID 0x1113 698 699/* 700 * Accton MPX 5030/5038 device ID. 701 */ 702#define ACCTON_DEVICEID_5030 0x1211 703 704/* 705 * Nortel PCI vendor ID 706 */ 707#define NORTEL_VENDORID 0x126C 708 709/* 710 * Delta Electronics Vendor ID. 711 */ 712#define DELTA_VENDORID 0x1500 713 714/* 715 * Delta device IDs. 716 */ 717#define DELTA_DEVICEID_8139 0x1360 718 719/* 720 * Addtron vendor ID. 721 */ 722#define ADDTRON_VENDORID 0x4033 723 724/* 725 * Addtron device IDs. 726 */ 727#define ADDTRON_DEVICEID_8139 0x1360 728 729/* 730 * D-Link vendor ID. 731 */ 732#define DLINK_VENDORID 0x1186 733 734/* 735 * D-Link DFE-530TX+ device ID 736 */ 737#define DLINK_DEVICEID_530TXPLUS 0x1300 738 739/* 740 * D-Link DFE-690TXD device ID 741 */ 742#define DLINK_DEVICEID_690TXD 0x1340 743 744/* 745 * Corega K.K vendor ID 746 */ 747#define COREGA_VENDORID 0x1259 748 749/* 750 * Corega FEther CB-TXD device ID 751 */ 752#define COREGA_DEVICEID_FETHERCBTXD 0xa117 753 754/* 755 * Corega FEtherII CB-TXD device ID 756 */ 757#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 758 759/* 760 * Peppercon vendor ID 761 */ 762#define PEPPERCON_VENDORID 0x1743 763 764/* 765 * Peppercon ROL-F device ID 766 */ 767#define PEPPERCON_DEVICEID_ROLF 0x8139 768 769/* 770 * Planex Communications, Inc. vendor ID 771 */ 772#define PLANEX_VENDORID 0x14ea 773 774/* 775 * Planex FNW-3800-TX device ID 776 */ 777#define PLANEX_DEVICEID_FNW3800TX 0xab07 778 779/* 780 * LevelOne vendor ID 781 */ 782#define LEVEL1_VENDORID 0x018A 783 784/* 785 * LevelOne FPC-0106TX devide ID 786 */ 787#define LEVEL1_DEVICEID_FPC0106TX 0x0106 788 789/* 790 * Compaq vendor ID 791 */ 792#define CP_VENDORID 0x021B 793 794/* 795 * Edimax vendor ID 796 */ 797#define EDIMAX_VENDORID 0x13D1 798 799/* 800 * Edimax EP-4103DL cardbus device ID 801 */ 802#define EDIMAX_DEVICEID_EP4103DL 0xAB06 803 804/* 805 * PCI low memory base and low I/O base register, and 806 * other PCI registers. 807 */ 808 809#define RL_PCI_VENDOR_ID 0x00 810#define RL_PCI_DEVICE_ID 0x02 811#define RL_PCI_COMMAND 0x04 812#define RL_PCI_STATUS 0x06 813#define RL_PCI_CLASSCODE 0x09 814#define RL_PCI_LATENCY_TIMER 0x0D 815#define RL_PCI_HEADER_TYPE 0x0E 816#define RL_PCI_LOIO 0x10 817#define RL_PCI_LOMEM 0x14 818#define RL_PCI_BIOSROM 0x30 819#define RL_PCI_INTLINE 0x3C 820#define RL_PCI_INTPIN 0x3D 821#define RL_PCI_MINGNT 0x3E 822#define RL_PCI_MINLAT 0x0F 823#define RL_PCI_RESETOPT 0x48 824#define RL_PCI_EEPROM_DATA 0x4C 825 826#define RL_PCI_CAPID 0x50 /* 8 bits */ 827#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 828#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 829#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 830 831#define RL_PSTATE_MASK 0x0003 832#define RL_PSTATE_D0 0x0000 833#define RL_PSTATE_D1 0x0002 834#define RL_PSTATE_D2 0x0002 835#define RL_PSTATE_D3 0x0003 836#define RL_PME_EN 0x0010 837#define RL_PME_STATUS 0x8000 838