if_rlreg.h revision 112379
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_rlreg.h 112379 2003-03-18 14:57:09Z sanpei $ 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 41#define RL_IDR3 0x0003 42#define RL_IDR4 0x0004 43#define RL_IDR5 0x0005 44 /* 0006-0007 reserved */ 45#define RL_MAR0 0x0008 /* Multicast hash table */ 46#define RL_MAR1 0x0009 47#define RL_MAR2 0x000A 48#define RL_MAR3 0x000B 49#define RL_MAR4 0x000C 50#define RL_MAR5 0x000D 51#define RL_MAR6 0x000E 52#define RL_MAR7 0x000F 53 54#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 58 59#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 63 64#define RL_RXADDR 0x0030 /* RX ring start address */ 65#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67#define RL_COMMAND 0x0037 /* command register */ 68#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70#define RL_IMR 0x003C /* interrupt mask register */ 71#define RL_ISR 0x003E /* interrupt status register */ 72#define RL_TXCFG 0x0040 /* transmit config */ 73#define RL_RXCFG 0x0044 /* receive config */ 74#define RL_TIMERCNT 0x0048 /* timer count register */ 75#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76#define RL_EECMD 0x0050 /* EEPROM command register */ 77#define RL_CFG0 0x0051 /* config register #0 */ 78#define RL_CFG1 0x0052 /* config register #1 */ 79 /* 0053-0057 reserved */ 80#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 81 /* 0059-005A reserved */ 82#define RL_MII 0x005A /* 8129 chip only */ 83#define RL_HALTCLK 0x005B 84#define RL_MULTIINTR 0x005C /* multiple interrupt */ 85#define RL_PCIREV 0x005E /* PCI revision value */ 86 /* 005F reserved */ 87#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 88 89/* Direct PHY access registers only available on 8139 */ 90#define RL_BMCR 0x0062 /* PHY basic mode control */ 91#define RL_BMSR 0x0064 /* PHY basic mode status */ 92#define RL_ANAR 0x0066 /* PHY autoneg advert */ 93#define RL_LPAR 0x0068 /* PHY link partner ability */ 94#define RL_ANER 0x006A /* PHY autoneg expansion */ 95 96#define RL_DISCCNT 0x006C /* disconnect counter */ 97#define RL_FALSECAR 0x006E /* false carrier counter */ 98#define RL_NWAYTST 0x0070 /* NWAY test register */ 99#define RL_RX_ER 0x0072 /* RX_ER counter */ 100#define RL_CSCFG 0x0074 /* CS configuration register */ 101 102 103/* 104 * TX config register bits 105 */ 106#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 107#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 108#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 109#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 110#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 111 112#define RL_TXDMA_16BYTES 0x00000000 113#define RL_TXDMA_32BYTES 0x00000100 114#define RL_TXDMA_64BYTES 0x00000200 115#define RL_TXDMA_128BYTES 0x00000300 116#define RL_TXDMA_256BYTES 0x00000400 117#define RL_TXDMA_512BYTES 0x00000500 118#define RL_TXDMA_1024BYTES 0x00000600 119#define RL_TXDMA_2048BYTES 0x00000700 120 121/* 122 * Transmit descriptor status register bits. 123 */ 124#define RL_TXSTAT_LENMASK 0x00001FFF 125#define RL_TXSTAT_OWN 0x00002000 126#define RL_TXSTAT_TX_UNDERRUN 0x00004000 127#define RL_TXSTAT_TX_OK 0x00008000 128#define RL_TXSTAT_EARLY_THRESH 0x003F0000 129#define RL_TXSTAT_COLLCNT 0x0F000000 130#define RL_TXSTAT_CARR_HBEAT 0x10000000 131#define RL_TXSTAT_OUTOFWIN 0x20000000 132#define RL_TXSTAT_TXABRT 0x40000000 133#define RL_TXSTAT_CARRLOSS 0x80000000 134 135/* 136 * Interrupt status register bits. 137 */ 138#define RL_ISR_RX_OK 0x0001 139#define RL_ISR_RX_ERR 0x0002 140#define RL_ISR_TX_OK 0x0004 141#define RL_ISR_TX_ERR 0x0008 142#define RL_ISR_RX_OVERRUN 0x0010 143#define RL_ISR_PKT_UNDERRUN 0x0020 144#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 145#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 146#define RL_ISR_SYSTEM_ERR 0x8000 147 148#define RL_INTRS \ 149 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 150 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 151 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 152 153/* 154 * Media status register. (8139 only) 155 */ 156#define RL_MEDIASTAT_RXPAUSE 0x01 157#define RL_MEDIASTAT_TXPAUSE 0x02 158#define RL_MEDIASTAT_LINK 0x04 159#define RL_MEDIASTAT_SPEED10 0x08 160#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 161#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 162 163/* 164 * Receive config register. 165 */ 166#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 167#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 168#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 169#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 170#define RL_RXCFG_RX_RUNT 0x00000010 171#define RL_RXCFG_RX_ERRPKT 0x00000020 172#define RL_RXCFG_WRAP 0x00000080 173#define RL_RXCFG_MAXDMA 0x00000700 174#define RL_RXCFG_BUFSZ 0x00001800 175#define RL_RXCFG_FIFOTHRESH 0x0000E000 176#define RL_RXCFG_EARLYTHRESH 0x07000000 177 178#define RL_RXDMA_16BYTES 0x00000000 179#define RL_RXDMA_32BYTES 0x00000100 180#define RL_RXDMA_64BYTES 0x00000200 181#define RL_RXDMA_128BYTES 0x00000300 182#define RL_RXDMA_256BYTES 0x00000400 183#define RL_RXDMA_512BYTES 0x00000500 184#define RL_RXDMA_1024BYTES 0x00000600 185#define RL_RXDMA_UNLIMITED 0x00000700 186 187#define RL_RXBUF_8 0x00000000 188#define RL_RXBUF_16 0x00000800 189#define RL_RXBUF_32 0x00001000 190#define RL_RXBUF_64 0x00001800 191 192#define RL_RXFIFO_16BYTES 0x00000000 193#define RL_RXFIFO_32BYTES 0x00002000 194#define RL_RXFIFO_64BYTES 0x00004000 195#define RL_RXFIFO_128BYTES 0x00006000 196#define RL_RXFIFO_256BYTES 0x00008000 197#define RL_RXFIFO_512BYTES 0x0000A000 198#define RL_RXFIFO_1024BYTES 0x0000C000 199#define RL_RXFIFO_NOTHRESH 0x0000E000 200 201/* 202 * Bits in RX status header (included with RX'ed packet 203 * in ring buffer). 204 */ 205#define RL_RXSTAT_RXOK 0x00000001 206#define RL_RXSTAT_ALIGNERR 0x00000002 207#define RL_RXSTAT_CRCERR 0x00000004 208#define RL_RXSTAT_GIANT 0x00000008 209#define RL_RXSTAT_RUNT 0x00000010 210#define RL_RXSTAT_BADSYM 0x00000020 211#define RL_RXSTAT_BROAD 0x00002000 212#define RL_RXSTAT_INDIV 0x00004000 213#define RL_RXSTAT_MULTI 0x00008000 214#define RL_RXSTAT_LENMASK 0xFFFF0000 215 216#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 217/* 218 * Command register. 219 */ 220#define RL_CMD_EMPTY_RXBUF 0x0001 221#define RL_CMD_TX_ENB 0x0004 222#define RL_CMD_RX_ENB 0x0008 223#define RL_CMD_RESET 0x0010 224 225/* 226 * EEPROM control register 227 */ 228#define RL_EE_DATAOUT 0x01 /* Data out */ 229#define RL_EE_DATAIN 0x02 /* Data in */ 230#define RL_EE_CLK 0x04 /* clock */ 231#define RL_EE_SEL 0x08 /* chip select */ 232#define RL_EE_MODE (0x40|0x80) 233 234#define RL_EEMODE_OFF 0x00 235#define RL_EEMODE_AUTOLOAD 0x40 236#define RL_EEMODE_PROGRAM 0x80 237#define RL_EEMODE_WRITECFG (0x80|0x40) 238 239/* 9346 EEPROM commands */ 240#define RL_EECMD_WRITE 0x140 241#define RL_EECMD_READ_6BIT 0x180 242#define RL_EECMD_READ_8BIT 0x600 243#define RL_EECMD_ERASE 0x1c0 244 245#define RL_EE_ID 0x00 246#define RL_EE_PCI_VID 0x01 247#define RL_EE_PCI_DID 0x02 248/* Location of station address inside EEPROM */ 249#define RL_EE_EADDR 0x07 250 251/* 252 * MII register (8129 only) 253 */ 254#define RL_MII_CLK 0x01 255#define RL_MII_DATAIN 0x02 256#define RL_MII_DATAOUT 0x04 257#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 258 259/* 260 * Config 0 register 261 */ 262#define RL_CFG0_ROM0 0x01 263#define RL_CFG0_ROM1 0x02 264#define RL_CFG0_ROM2 0x04 265#define RL_CFG0_PL0 0x08 266#define RL_CFG0_PL1 0x10 267#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 268#define RL_CFG0_PCS 0x40 269#define RL_CFG0_SCR 0x80 270 271/* 272 * Config 1 register 273 */ 274#define RL_CFG1_PWRDWN 0x01 275#define RL_CFG1_SLEEP 0x02 276#define RL_CFG1_IOMAP 0x04 277#define RL_CFG1_MEMMAP 0x08 278#define RL_CFG1_RSVD 0x10 279#define RL_CFG1_DRVLOAD 0x20 280#define RL_CFG1_LED0 0x40 281#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 282#define RL_CFG1_LED1 0x80 283 284/* 285 * The RealTek doesn't use a fragment-based descriptor mechanism. 286 * Instead, there are only four register sets, each or which represents 287 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 288 * packet buffer (32-bit aligned!) and we place the buffer addresses in 289 * the registers so the chip knows where they are. 290 * 291 * We can sort of kludge together the same kind of buffer management 292 * used in previous drivers, but we have to do buffer copies almost all 293 * the time, so it doesn't really buy us much. 294 * 295 * For reception, there's just one large buffer where the chip stores 296 * all received packets. 297 */ 298 299#define RL_RX_BUF_SZ RL_RXBUF_64 300#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 301#define RL_TX_LIST_CNT 4 302#define RL_MIN_FRAMELEN 60 303#define RL_TXTHRESH(x) ((x) << 11) 304#define RL_TX_THRESH_INIT 96 305#define RL_RX_FIFOTHRESH RL_RXFIFO_256BYTES 306#define RL_RX_MAXDMA RL_RXDMA_1024BYTES /*RL_RXDMA_UNLIMITED*/ 307#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 308 309#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 310#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 311 312#define RL_ETHER_ALIGN 2 313 314struct rl_chain_data { 315 u_int16_t cur_rx; 316 caddr_t rl_rx_buf; 317 caddr_t rl_rx_buf_ptr; 318 bus_dmamap_t rl_rx_dmamap; 319 320 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 321 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 322 u_int8_t last_tx; 323 u_int8_t cur_tx; 324}; 325 326#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 327#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 328#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 329#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 330#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 331#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 332#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 333#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 334#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 335 336struct rl_type { 337 u_int16_t rl_vid; 338 u_int16_t rl_did; 339 char *rl_name; 340}; 341 342struct rl_mii_frame { 343 u_int8_t mii_stdelim; 344 u_int8_t mii_opcode; 345 u_int8_t mii_phyaddr; 346 u_int8_t mii_regaddr; 347 u_int8_t mii_turnaround; 348 u_int16_t mii_data; 349}; 350 351/* 352 * MII constants 353 */ 354#define RL_MII_STARTDELIM 0x01 355#define RL_MII_READOP 0x02 356#define RL_MII_WRITEOP 0x01 357#define RL_MII_TURNAROUND 0x02 358 359#define RL_8129 1 360#define RL_8139 2 361 362struct rl_softc { 363 struct arpcom arpcom; /* interface info */ 364 bus_space_handle_t rl_bhandle; /* bus space handle */ 365 bus_space_tag_t rl_btag; /* bus space tag */ 366 struct resource *rl_res; 367 struct resource *rl_irq; 368 void *rl_intrhand; 369 device_t rl_miibus; 370 bus_dma_tag_t rl_parent_tag; 371 bus_dma_tag_t rl_tag; 372 u_int8_t rl_unit; /* interface number */ 373 u_int8_t rl_type; 374 int rl_eecmd_read; 375 u_int8_t rl_stats_no_timeout; 376 int rl_txthresh; 377 struct rl_chain_data rl_cdata; 378 struct callout_handle rl_stat_ch; 379 struct mtx rl_mtx; 380 int suspended; /* 0 = normal 1 = suspended */ 381#ifdef DEVICE_POLLING 382 int rxcycles; 383#endif 384 385 u_int32_t saved_maps[5]; /* pci data */ 386 u_int32_t saved_biosaddr; 387 u_int8_t saved_intline; 388 u_int8_t saved_cachelnsz; 389 u_int8_t saved_lattimer; 390}; 391 392#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 393#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 394 395/* 396 * register space access macros 397 */ 398#define CSR_WRITE_4(sc, reg, val) \ 399 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 400#define CSR_WRITE_2(sc, reg, val) \ 401 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 402#define CSR_WRITE_1(sc, reg, val) \ 403 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 404 405#define CSR_READ_4(sc, reg) \ 406 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 407#define CSR_READ_2(sc, reg) \ 408 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 409#define CSR_READ_1(sc, reg) \ 410 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 411 412#define RL_TIMEOUT 1000 413 414/* 415 * General constants that are fun to know. 416 * 417 * RealTek PCI vendor ID 418 */ 419#define RT_VENDORID 0x10EC 420 421/* 422 * RealTek chip device IDs. 423 */ 424#define RT_DEVICEID_8129 0x8129 425#define RT_DEVICEID_8138 0x8138 426#define RT_DEVICEID_8139 0x8139 427 428/* 429 * Accton PCI vendor ID 430 */ 431#define ACCTON_VENDORID 0x1113 432 433/* 434 * Accton MPX 5030/5038 device ID. 435 */ 436#define ACCTON_DEVICEID_5030 0x1211 437 438/* 439 * Nortel PCI vendor ID 440 */ 441#define NORTEL_VENDORID 0x126C 442 443/* 444 * Delta Electronics Vendor ID. 445 */ 446#define DELTA_VENDORID 0x1500 447 448/* 449 * Delta device IDs. 450 */ 451#define DELTA_DEVICEID_8139 0x1360 452 453/* 454 * Addtron vendor ID. 455 */ 456#define ADDTRON_VENDORID 0x4033 457 458/* 459 * Addtron device IDs. 460 */ 461#define ADDTRON_DEVICEID_8139 0x1360 462 463/* 464 * D-Link vendor ID. 465 */ 466#define DLINK_VENDORID 0x1186 467 468/* 469 * D-Link DFE-530TX+ device ID 470 */ 471#define DLINK_DEVICEID_530TXPLUS 0x1300 472 473/* 474 * D-Link DFE-690TXD device ID 475 */ 476#define DLINK_DEVICEID_690TXD 0x1340 477 478/* 479 * Corega K.K vendor ID 480 */ 481#define COREGA_VENDORID 0x1259 482 483/* 484 * Corega FEther CB-TXD device ID 485 */ 486#define COREGA_DEVICEID_FETHERCBTXD 0xa117 487 488/* 489 * Corega FEtherII CB-TXD device ID 490 */ 491#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 492 493/* 494 * Peppercon vendor ID 495 */ 496#define PEPPERCON_VENDORID 0x1743 497 498/* 499 * Peppercon ROL-F device ID 500 */ 501#define PEPPERCON_DEVICEID_ROLF 0x8139 502 503/* 504 * Planex Communications, Inc. vendor ID 505 */ 506#define PLANEX_VENDORID 0x14ea 507 508/* 509 * Planex FNW-3800-TX device ID 510 */ 511#define PLANEX_DEVICEID_FNW3800TX 0xab07 512 513/* 514 * PCI low memory base and low I/O base register, and 515 * other PCI registers. 516 */ 517 518#define RL_PCI_VENDOR_ID 0x00 519#define RL_PCI_DEVICE_ID 0x02 520#define RL_PCI_COMMAND 0x04 521#define RL_PCI_STATUS 0x06 522#define RL_PCI_CLASSCODE 0x09 523#define RL_PCI_LATENCY_TIMER 0x0D 524#define RL_PCI_HEADER_TYPE 0x0E 525#define RL_PCI_LOIO 0x10 526#define RL_PCI_LOMEM 0x14 527#define RL_PCI_BIOSROM 0x30 528#define RL_PCI_INTLINE 0x3C 529#define RL_PCI_INTPIN 0x3D 530#define RL_PCI_MINGNT 0x3E 531#define RL_PCI_MINLAT 0x0F 532#define RL_PCI_RESETOPT 0x48 533#define RL_PCI_EEPROM_DATA 0x4C 534 535#define RL_PCI_CAPID 0x50 /* 8 bits */ 536#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 537#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 538#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 539 540#define RL_PSTATE_MASK 0x0003 541#define RL_PSTATE_D0 0x0000 542#define RL_PSTATE_D1 0x0002 543#define RL_PSTATE_D2 0x0002 544#define RL_PSTATE_D3 0x0003 545#define RL_PME_EN 0x0010 546#define RL_PME_STATUS 0x8000 547