if_rl.c revision 94400
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_rl.c 94400 2002-04-11 06:12:51Z wpaul $ 33 */ 34 35/* 36 * RealTek 8129/8139 PCI NIC driver 37 * 38 * Supports several extremely cheap PCI 10/100 adapters based on 39 * the RealTek chipset. Datasheets can be obtained from 40 * www.realtek.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86#include <sys/param.h> 87#include <sys/systm.h> 88#include <sys/sockio.h> 89#include <sys/mbuf.h> 90#include <sys/malloc.h> 91#include <sys/kernel.h> 92#include <sys/socket.h> 93 94#include <net/if.h> 95#include <net/if_arp.h> 96#include <net/ethernet.h> 97#include <net/if_dl.h> 98#include <net/if_media.h> 99 100#include <net/bpf.h> 101 102#include <machine/bus_pio.h> 103#include <machine/bus_memio.h> 104#include <machine/bus.h> 105#include <machine/resource.h> 106#include <sys/bus.h> 107#include <sys/rman.h> 108 109#include <dev/mii/mii.h> 110#include <dev/mii/miivar.h> 111 112#include <pci/pcireg.h> 113#include <pci/pcivar.h> 114 115MODULE_DEPEND(rl, miibus, 1, 1, 1); 116 117/* "controller miibus0" required. See GENERIC if you get errors here. */ 118#include "miibus_if.h" 119 120/* 121 * Default to using PIO access for this driver. On SMP systems, 122 * there appear to be problems with memory mapped mode: it looks like 123 * doing too many memory mapped access back to back in rapid succession 124 * can hang the bus. I'm inclined to blame this on crummy design/construction 125 * on the part of RealTek. Memory mapped mode does appear to work on 126 * uniprocessor systems though. 127 */ 128#define RL_USEIOSPACE 129 130#include <pci/if_rlreg.h> 131 132#ifndef lint 133static const char rcsid[] = 134 "$FreeBSD: head/sys/pci/if_rl.c 94400 2002-04-11 06:12:51Z wpaul $"; 135#endif 136 137/* 138 * Various supported device vendors/types and their names. 139 */ 140static struct rl_type rl_devs[] = { 141 { RT_VENDORID, RT_DEVICEID_8129, 142 "RealTek 8129 10/100BaseTX" }, 143 { RT_VENDORID, RT_DEVICEID_8139, 144 "RealTek 8139 10/100BaseTX" }, 145 { RT_VENDORID, RT_DEVICEID_8138, 146 "RealTek 8139 10/100BaseTX CardBus" }, 147 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 148 "Accton MPX 5030/5038 10/100BaseTX" }, 149 { DELTA_VENDORID, DELTA_DEVICEID_8139, 150 "Delta Electronics 8139 10/100BaseTX" }, 151 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 152 "Addtron Technolgy 8139 10/100BaseTX" }, 153 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 154 "D-Link DFE-530TX+ 10/100BaseTX" }, 155 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, 156 "Nortel Networks 10/100BaseTX" }, 157 { 0, 0, NULL } 158}; 159 160static int rl_probe (device_t); 161static int rl_attach (device_t); 162static int rl_detach (device_t); 163 164static int rl_encap (struct rl_softc *, struct mbuf * ); 165 166static void rl_rxeof (struct rl_softc *); 167static void rl_txeof (struct rl_softc *); 168static void rl_intr (void *); 169static void rl_tick (void *); 170static void rl_start (struct ifnet *); 171static int rl_ioctl (struct ifnet *, u_long, caddr_t); 172static void rl_init (void *); 173static void rl_stop (struct rl_softc *); 174static void rl_watchdog (struct ifnet *); 175static int rl_suspend (device_t); 176static int rl_resume (device_t); 177static void rl_shutdown (device_t); 178static int rl_ifmedia_upd (struct ifnet *); 179static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 180 181static void rl_eeprom_putbyte (struct rl_softc *, int); 182static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 183static void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 184static void rl_mii_sync (struct rl_softc *); 185static void rl_mii_send (struct rl_softc *, u_int32_t, int); 186static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 187static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 188 189static int rl_miibus_readreg (device_t, int, int); 190static int rl_miibus_writereg (device_t, int, int, int); 191static void rl_miibus_statchg (device_t); 192 193static u_int8_t rl_calchash (caddr_t); 194static void rl_setmulti (struct rl_softc *); 195static void rl_reset (struct rl_softc *); 196static int rl_list_tx_init (struct rl_softc *); 197 198static void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 199static void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 200 201#ifdef RL_USEIOSPACE 202#define RL_RES SYS_RES_IOPORT 203#define RL_RID RL_PCI_LOIO 204#else 205#define RL_RES SYS_RES_MEMORY 206#define RL_RID RL_PCI_LOMEM 207#endif 208 209static device_method_t rl_methods[] = { 210 /* Device interface */ 211 DEVMETHOD(device_probe, rl_probe), 212 DEVMETHOD(device_attach, rl_attach), 213 DEVMETHOD(device_detach, rl_detach), 214 DEVMETHOD(device_suspend, rl_suspend), 215 DEVMETHOD(device_resume, rl_resume), 216 DEVMETHOD(device_shutdown, rl_shutdown), 217 218 /* bus interface */ 219 DEVMETHOD(bus_print_child, bus_generic_print_child), 220 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 221 222 /* MII interface */ 223 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 224 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 225 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 226 227 { 0, 0 } 228}; 229 230static driver_t rl_driver = { 231 "rl", 232 rl_methods, 233 sizeof(struct rl_softc) 234}; 235 236static devclass_t rl_devclass; 237 238DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 239DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 240DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 241 242#define EE_SET(x) \ 243 CSR_WRITE_1(sc, RL_EECMD, \ 244 CSR_READ_1(sc, RL_EECMD) | x) 245 246#define EE_CLR(x) \ 247 CSR_WRITE_1(sc, RL_EECMD, \ 248 CSR_READ_1(sc, RL_EECMD) & ~x) 249 250static void 251rl_dma_map_rxbuf(arg, segs, nseg, error) 252 void *arg; 253 bus_dma_segment_t *segs; 254 int nseg, error; 255{ 256 struct rl_softc *sc; 257 258 sc = arg; 259 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 260 261 return; 262} 263 264static void 265rl_dma_map_txbuf(arg, segs, nseg, error) 266 void *arg; 267 bus_dma_segment_t *segs; 268 int nseg, error; 269{ 270 struct rl_softc *sc; 271 272 sc = arg; 273 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 274 275 return; 276} 277 278/* 279 * Send a read command and address to the EEPROM, check for ACK. 280 */ 281static void rl_eeprom_putbyte(sc, addr) 282 struct rl_softc *sc; 283 int addr; 284{ 285 register int d, i; 286 287 d = addr | sc->rl_eecmd_read; 288 289 /* 290 * Feed in each bit and strobe the clock. 291 */ 292 for (i = 0x400; i; i >>= 1) { 293 if (d & i) { 294 EE_SET(RL_EE_DATAIN); 295 } else { 296 EE_CLR(RL_EE_DATAIN); 297 } 298 DELAY(100); 299 EE_SET(RL_EE_CLK); 300 DELAY(150); 301 EE_CLR(RL_EE_CLK); 302 DELAY(100); 303 } 304 305 return; 306} 307 308/* 309 * Read a word of data stored in the EEPROM at address 'addr.' 310 */ 311static void rl_eeprom_getword(sc, addr, dest) 312 struct rl_softc *sc; 313 int addr; 314 u_int16_t *dest; 315{ 316 register int i; 317 u_int16_t word = 0; 318 319 /* Enter EEPROM access mode. */ 320 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 321 322 /* 323 * Send address of word we want to read. 324 */ 325 rl_eeprom_putbyte(sc, addr); 326 327 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 328 329 /* 330 * Start reading bits from EEPROM. 331 */ 332 for (i = 0x8000; i; i >>= 1) { 333 EE_SET(RL_EE_CLK); 334 DELAY(100); 335 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 336 word |= i; 337 EE_CLR(RL_EE_CLK); 338 DELAY(100); 339 } 340 341 /* Turn off EEPROM access mode. */ 342 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 343 344 *dest = word; 345 346 return; 347} 348 349/* 350 * Read a sequence of words from the EEPROM. 351 */ 352static void rl_read_eeprom(sc, dest, off, cnt, swap) 353 struct rl_softc *sc; 354 caddr_t dest; 355 int off; 356 int cnt; 357 int swap; 358{ 359 int i; 360 u_int16_t word = 0, *ptr; 361 362 for (i = 0; i < cnt; i++) { 363 rl_eeprom_getword(sc, off + i, &word); 364 ptr = (u_int16_t *)(dest + (i * 2)); 365 if (swap) 366 *ptr = ntohs(word); 367 else 368 *ptr = word; 369 } 370 371 return; 372} 373 374 375/* 376 * MII access routines are provided for the 8129, which 377 * doesn't have a built-in PHY. For the 8139, we fake things 378 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 379 * direct access PHY registers. 380 */ 381#define MII_SET(x) \ 382 CSR_WRITE_1(sc, RL_MII, \ 383 CSR_READ_1(sc, RL_MII) | x) 384 385#define MII_CLR(x) \ 386 CSR_WRITE_1(sc, RL_MII, \ 387 CSR_READ_1(sc, RL_MII) & ~x) 388 389/* 390 * Sync the PHYs by setting data bit and strobing the clock 32 times. 391 */ 392static void rl_mii_sync(sc) 393 struct rl_softc *sc; 394{ 395 register int i; 396 397 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 398 399 for (i = 0; i < 32; i++) { 400 MII_SET(RL_MII_CLK); 401 DELAY(1); 402 MII_CLR(RL_MII_CLK); 403 DELAY(1); 404 } 405 406 return; 407} 408 409/* 410 * Clock a series of bits through the MII. 411 */ 412static void rl_mii_send(sc, bits, cnt) 413 struct rl_softc *sc; 414 u_int32_t bits; 415 int cnt; 416{ 417 int i; 418 419 MII_CLR(RL_MII_CLK); 420 421 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 422 if (bits & i) { 423 MII_SET(RL_MII_DATAOUT); 424 } else { 425 MII_CLR(RL_MII_DATAOUT); 426 } 427 DELAY(1); 428 MII_CLR(RL_MII_CLK); 429 DELAY(1); 430 MII_SET(RL_MII_CLK); 431 } 432} 433 434/* 435 * Read an PHY register through the MII. 436 */ 437static int rl_mii_readreg(sc, frame) 438 struct rl_softc *sc; 439 struct rl_mii_frame *frame; 440 441{ 442 int i, ack; 443 444 RL_LOCK(sc); 445 446 /* 447 * Set up frame for RX. 448 */ 449 frame->mii_stdelim = RL_MII_STARTDELIM; 450 frame->mii_opcode = RL_MII_READOP; 451 frame->mii_turnaround = 0; 452 frame->mii_data = 0; 453 454 CSR_WRITE_2(sc, RL_MII, 0); 455 456 /* 457 * Turn on data xmit. 458 */ 459 MII_SET(RL_MII_DIR); 460 461 rl_mii_sync(sc); 462 463 /* 464 * Send command/address info. 465 */ 466 rl_mii_send(sc, frame->mii_stdelim, 2); 467 rl_mii_send(sc, frame->mii_opcode, 2); 468 rl_mii_send(sc, frame->mii_phyaddr, 5); 469 rl_mii_send(sc, frame->mii_regaddr, 5); 470 471 /* Idle bit */ 472 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 473 DELAY(1); 474 MII_SET(RL_MII_CLK); 475 DELAY(1); 476 477 /* Turn off xmit. */ 478 MII_CLR(RL_MII_DIR); 479 480 /* Check for ack */ 481 MII_CLR(RL_MII_CLK); 482 DELAY(1); 483 MII_SET(RL_MII_CLK); 484 DELAY(1); 485 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 486 487 /* 488 * Now try reading data bits. If the ack failed, we still 489 * need to clock through 16 cycles to keep the PHY(s) in sync. 490 */ 491 if (ack) { 492 for(i = 0; i < 16; i++) { 493 MII_CLR(RL_MII_CLK); 494 DELAY(1); 495 MII_SET(RL_MII_CLK); 496 DELAY(1); 497 } 498 goto fail; 499 } 500 501 for (i = 0x8000; i; i >>= 1) { 502 MII_CLR(RL_MII_CLK); 503 DELAY(1); 504 if (!ack) { 505 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 506 frame->mii_data |= i; 507 DELAY(1); 508 } 509 MII_SET(RL_MII_CLK); 510 DELAY(1); 511 } 512 513fail: 514 515 MII_CLR(RL_MII_CLK); 516 DELAY(1); 517 MII_SET(RL_MII_CLK); 518 DELAY(1); 519 520 RL_UNLOCK(sc); 521 522 if (ack) 523 return(1); 524 return(0); 525} 526 527/* 528 * Write to a PHY register through the MII. 529 */ 530static int rl_mii_writereg(sc, frame) 531 struct rl_softc *sc; 532 struct rl_mii_frame *frame; 533 534{ 535 RL_LOCK(sc); 536 537 /* 538 * Set up frame for TX. 539 */ 540 541 frame->mii_stdelim = RL_MII_STARTDELIM; 542 frame->mii_opcode = RL_MII_WRITEOP; 543 frame->mii_turnaround = RL_MII_TURNAROUND; 544 545 /* 546 * Turn on data output. 547 */ 548 MII_SET(RL_MII_DIR); 549 550 rl_mii_sync(sc); 551 552 rl_mii_send(sc, frame->mii_stdelim, 2); 553 rl_mii_send(sc, frame->mii_opcode, 2); 554 rl_mii_send(sc, frame->mii_phyaddr, 5); 555 rl_mii_send(sc, frame->mii_regaddr, 5); 556 rl_mii_send(sc, frame->mii_turnaround, 2); 557 rl_mii_send(sc, frame->mii_data, 16); 558 559 /* Idle bit. */ 560 MII_SET(RL_MII_CLK); 561 DELAY(1); 562 MII_CLR(RL_MII_CLK); 563 DELAY(1); 564 565 /* 566 * Turn off xmit. 567 */ 568 MII_CLR(RL_MII_DIR); 569 570 RL_UNLOCK(sc); 571 572 return(0); 573} 574 575static int rl_miibus_readreg(dev, phy, reg) 576 device_t dev; 577 int phy, reg; 578{ 579 struct rl_softc *sc; 580 struct rl_mii_frame frame; 581 u_int16_t rval = 0; 582 u_int16_t rl8139_reg = 0; 583 584 sc = device_get_softc(dev); 585 RL_LOCK(sc); 586 587 if (sc->rl_type == RL_8139) { 588 /* Pretend the internal PHY is only at address 0 */ 589 if (phy) { 590 RL_UNLOCK(sc); 591 return(0); 592 } 593 switch(reg) { 594 case MII_BMCR: 595 rl8139_reg = RL_BMCR; 596 break; 597 case MII_BMSR: 598 rl8139_reg = RL_BMSR; 599 break; 600 case MII_ANAR: 601 rl8139_reg = RL_ANAR; 602 break; 603 case MII_ANER: 604 rl8139_reg = RL_ANER; 605 break; 606 case MII_ANLPAR: 607 rl8139_reg = RL_LPAR; 608 break; 609 case MII_PHYIDR1: 610 case MII_PHYIDR2: 611 RL_UNLOCK(sc); 612 return(0); 613 break; 614 /* 615 * Allow the rlphy driver to read the media status 616 * register. If we have a link partner which does not 617 * support NWAY, this is the register which will tell 618 * us the results of parallel detection. 619 */ 620 case RL_MEDIASTAT: 621 rval = CSR_READ_1(sc, RL_MEDIASTAT); 622 RL_UNLOCK(sc); 623 return(rval); 624 break; 625 default: 626 printf("rl%d: bad phy register\n", sc->rl_unit); 627 RL_UNLOCK(sc); 628 return(0); 629 } 630 rval = CSR_READ_2(sc, rl8139_reg); 631 RL_UNLOCK(sc); 632 return(rval); 633 } 634 635 bzero((char *)&frame, sizeof(frame)); 636 637 frame.mii_phyaddr = phy; 638 frame.mii_regaddr = reg; 639 rl_mii_readreg(sc, &frame); 640 RL_UNLOCK(sc); 641 642 return(frame.mii_data); 643} 644 645static int rl_miibus_writereg(dev, phy, reg, data) 646 device_t dev; 647 int phy, reg, data; 648{ 649 struct rl_softc *sc; 650 struct rl_mii_frame frame; 651 u_int16_t rl8139_reg = 0; 652 653 sc = device_get_softc(dev); 654 RL_LOCK(sc); 655 656 if (sc->rl_type == RL_8139) { 657 /* Pretend the internal PHY is only at address 0 */ 658 if (phy) { 659 RL_UNLOCK(sc); 660 return(0); 661 } 662 switch(reg) { 663 case MII_BMCR: 664 rl8139_reg = RL_BMCR; 665 break; 666 case MII_BMSR: 667 rl8139_reg = RL_BMSR; 668 break; 669 case MII_ANAR: 670 rl8139_reg = RL_ANAR; 671 break; 672 case MII_ANER: 673 rl8139_reg = RL_ANER; 674 break; 675 case MII_ANLPAR: 676 rl8139_reg = RL_LPAR; 677 break; 678 case MII_PHYIDR1: 679 case MII_PHYIDR2: 680 RL_UNLOCK(sc); 681 return(0); 682 break; 683 default: 684 printf("rl%d: bad phy register\n", sc->rl_unit); 685 RL_UNLOCK(sc); 686 return(0); 687 } 688 CSR_WRITE_2(sc, rl8139_reg, data); 689 RL_UNLOCK(sc); 690 return(0); 691 } 692 693 bzero((char *)&frame, sizeof(frame)); 694 695 frame.mii_phyaddr = phy; 696 frame.mii_regaddr = reg; 697 frame.mii_data = data; 698 699 rl_mii_writereg(sc, &frame); 700 701 RL_UNLOCK(sc); 702 return(0); 703} 704 705static void rl_miibus_statchg(dev) 706 device_t dev; 707{ 708 return; 709} 710 711/* 712 * Calculate CRC of a multicast group address, return the upper 6 bits. 713 */ 714static u_int8_t rl_calchash(addr) 715 caddr_t addr; 716{ 717 u_int32_t crc, carry; 718 int i, j; 719 u_int8_t c; 720 721 /* Compute CRC for the address value. */ 722 crc = 0xFFFFFFFF; /* initial value */ 723 724 for (i = 0; i < 6; i++) { 725 c = *(addr + i); 726 for (j = 0; j < 8; j++) { 727 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 728 crc <<= 1; 729 c >>= 1; 730 if (carry) 731 crc = (crc ^ 0x04c11db6) | carry; 732 } 733 } 734 735 /* return the filter bit position */ 736 return(crc >> 26); 737} 738 739/* 740 * Program the 64-bit multicast hash filter. 741 */ 742static void rl_setmulti(sc) 743 struct rl_softc *sc; 744{ 745 struct ifnet *ifp; 746 int h = 0; 747 u_int32_t hashes[2] = { 0, 0 }; 748 struct ifmultiaddr *ifma; 749 u_int32_t rxfilt; 750 int mcnt = 0; 751 752 ifp = &sc->arpcom.ac_if; 753 754 rxfilt = CSR_READ_4(sc, RL_RXCFG); 755 756 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 757 rxfilt |= RL_RXCFG_RX_MULTI; 758 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 759 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 760 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 761 return; 762 } 763 764 /* first, zot all the existing hash bits */ 765 CSR_WRITE_4(sc, RL_MAR0, 0); 766 CSR_WRITE_4(sc, RL_MAR4, 0); 767 768 /* now program new ones */ 769 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 770 if (ifma->ifma_addr->sa_family != AF_LINK) 771 continue; 772 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 773 if (h < 32) 774 hashes[0] |= (1 << h); 775 else 776 hashes[1] |= (1 << (h - 32)); 777 mcnt++; 778 } 779 780 if (mcnt) 781 rxfilt |= RL_RXCFG_RX_MULTI; 782 else 783 rxfilt &= ~RL_RXCFG_RX_MULTI; 784 785 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 786 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 787 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 788 789 return; 790} 791 792static void rl_reset(sc) 793 struct rl_softc *sc; 794{ 795 register int i; 796 797 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 798 799 for (i = 0; i < RL_TIMEOUT; i++) { 800 DELAY(10); 801 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 802 break; 803 } 804 if (i == RL_TIMEOUT) 805 printf("rl%d: reset never completed!\n", sc->rl_unit); 806 807 return; 808} 809 810/* 811 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 812 * IDs against our list and return a device name if we find a match. 813 */ 814static int rl_probe(dev) 815 device_t dev; 816{ 817 struct rl_type *t; 818 819 t = rl_devs; 820 821 while(t->rl_name != NULL) { 822 if ((pci_get_vendor(dev) == t->rl_vid) && 823 (pci_get_device(dev) == t->rl_did)) { 824 device_set_desc(dev, t->rl_name); 825 return(0); 826 } 827 t++; 828 } 829 830 return(ENXIO); 831} 832 833/* 834 * Attach the interface. Allocate softc structures, do ifmedia 835 * setup and ethernet/BPF attach. 836 */ 837static int rl_attach(dev) 838 device_t dev; 839{ 840 u_char eaddr[ETHER_ADDR_LEN]; 841 u_int32_t command; 842 struct rl_softc *sc; 843 struct ifnet *ifp; 844 u_int16_t rl_did = 0; 845 int unit, error = 0, rid; 846 847 sc = device_get_softc(dev); 848 unit = device_get_unit(dev); 849 bzero(sc, sizeof(struct rl_softc)); 850 851 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 852 MTX_DEF | MTX_RECURSE); 853 RL_LOCK(sc); 854 855 /* 856 * Handle power management nonsense. 857 */ 858 859 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 860 u_int32_t iobase, membase, irq; 861 862 /* Save important PCI config data. */ 863 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 864 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 865 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 866 867 /* Reset the power state. */ 868 printf("rl%d: chip is is in D%d power mode " 869 "-- setting to D0\n", unit, 870 pci_get_powerstate(dev)); 871 872 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 873 874 /* Restore PCI config data. */ 875 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 876 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 877 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 878 } 879 880 /* 881 * Map control/status registers. 882 */ 883 pci_enable_busmaster(dev); 884 pci_enable_io(dev, SYS_RES_IOPORT); 885 pci_enable_io(dev, SYS_RES_MEMORY); 886 command = pci_read_config(dev, PCIR_COMMAND, 4); 887 888#ifdef RL_USEIOSPACE 889 if (!(command & PCIM_CMD_PORTEN)) { 890 printf("rl%d: failed to enable I/O ports!\n", unit); 891 error = ENXIO; 892 goto fail; 893 } 894#else 895 if (!(command & PCIM_CMD_MEMEN)) { 896 printf("rl%d: failed to enable memory mapping!\n", unit); 897 error = ENXIO; 898 goto fail; 899 } 900#endif 901 902 rid = RL_RID; 903 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 904 0, ~0, 1, RF_ACTIVE); 905 906 if (sc->rl_res == NULL) { 907 printf ("rl%d: couldn't map ports/memory\n", unit); 908 error = ENXIO; 909 goto fail; 910 } 911 912 /* Detect the Realtek 8139B. For some reason, this chip is very 913 * unstable when left to autoselect the media 914 * The best workaround is to set the device to the required 915 * media type or to set it to the 10 Meg speed. 916 */ 917 918 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 919 printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit); 920 } 921 922 sc->rl_btag = rman_get_bustag(sc->rl_res); 923 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 924 925 rid = 0; 926 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 927 RF_SHAREABLE | RF_ACTIVE); 928 929 if (sc->rl_irq == NULL) { 930 printf("rl%d: couldn't map interrupt\n", unit); 931 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 932 error = ENXIO; 933 goto fail; 934 } 935 936 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 937 rl_intr, sc, &sc->rl_intrhand); 938 939 if (error) { 940 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 941 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 942 printf("rl%d: couldn't set up irq\n", unit); 943 goto fail; 944 } 945 946 callout_handle_init(&sc->rl_stat_ch); 947 948 /* Reset the adapter. */ 949 rl_reset(sc); 950 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 951 rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 952 if (rl_did != 0x8129) 953 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 954 955 /* 956 * Get station address from the EEPROM. 957 */ 958 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 959 960 /* 961 * A RealTek chip was detected. Inform the world. 962 */ 963 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 964 965 sc->rl_unit = unit; 966 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 967 968 /* 969 * Now read the exact device type from the EEPROM to find 970 * out if it's an 8129 or 8139. 971 */ 972 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 973 974 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 975 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 976 rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS) 977 sc->rl_type = RL_8139; 978 else if (rl_did == RT_DEVICEID_8129) 979 sc->rl_type = RL_8129; 980 else { 981 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 982 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 983 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 984 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 985 error = ENXIO; 986 goto fail; 987 } 988 989 /* 990 * Allocate the parent bus DMA tag appropriate for PCI. 991 */ 992#define RL_NSEG_NEW 32 993 error = bus_dma_tag_create(NULL, /* parent */ 994 1, 0, /* alignment, boundary */ 995 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 996 BUS_SPACE_MAXADDR, /* highaddr */ 997 NULL, NULL, /* filter, filterarg */ 998 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 999 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1000 BUS_DMA_ALLOCNOW, /* flags */ 1001 &sc->rl_parent_tag); 1002 1003 /* 1004 * Now allocate a tag for the DMA descriptor lists. 1005 * All of our lists are allocated as a contiguous block 1006 * of memory. 1007 */ 1008 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 1009 1, 0, /* alignment, boundary */ 1010 BUS_SPACE_MAXADDR, /* lowaddr */ 1011 BUS_SPACE_MAXADDR, /* highaddr */ 1012 NULL, NULL, /* filter, filterarg */ 1013 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 1014 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1015 0, /* flags */ 1016 &sc->rl_tag); 1017 1018 /* 1019 * Now allocate a chunk of DMA-able memory based on the 1020 * tag we just created. 1021 */ 1022 error = bus_dmamem_alloc(sc->rl_tag, 1023 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT, 1024 &sc->rl_cdata.rl_rx_dmamap); 1025 1026 if (sc->rl_cdata.rl_rx_buf == NULL) { 1027 printf("rl%d: no memory for list buffers!\n", unit); 1028 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1029 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1030 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1031 bus_dma_tag_destroy(sc->rl_tag); 1032 error = ENXIO; 1033 goto fail; 1034 } 1035 1036 /* Leave a few bytes before the start of the RX ring buffer. */ 1037 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1038 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1039 1040 /* Do MII setup */ 1041 if (mii_phy_probe(dev, &sc->rl_miibus, 1042 rl_ifmedia_upd, rl_ifmedia_sts)) { 1043 printf("rl%d: MII without any phy!\n", sc->rl_unit); 1044 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1045 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1046 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1047 bus_dmamem_free(sc->rl_tag, 1048 sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap); 1049 bus_dma_tag_destroy(sc->rl_tag); 1050 error = ENXIO; 1051 goto fail; 1052 } 1053 1054 ifp = &sc->arpcom.ac_if; 1055 ifp->if_softc = sc; 1056 ifp->if_unit = unit; 1057 ifp->if_name = "rl"; 1058 ifp->if_mtu = ETHERMTU; 1059 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1060 ifp->if_ioctl = rl_ioctl; 1061 ifp->if_output = ether_output; 1062 ifp->if_start = rl_start; 1063 ifp->if_watchdog = rl_watchdog; 1064 ifp->if_init = rl_init; 1065 ifp->if_baudrate = 10000000; 1066 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1067 1068 /* 1069 * Call MI attach routine. 1070 */ 1071 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1072 RL_UNLOCK(sc); 1073 return(0); 1074 1075fail: 1076 RL_UNLOCK(sc); 1077 mtx_destroy(&sc->rl_mtx); 1078 return(error); 1079} 1080 1081static int rl_detach(dev) 1082 device_t dev; 1083{ 1084 struct rl_softc *sc; 1085 struct ifnet *ifp; 1086 1087 sc = device_get_softc(dev); 1088 RL_LOCK(sc); 1089 ifp = &sc->arpcom.ac_if; 1090 1091 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1092 rl_stop(sc); 1093 1094 bus_generic_detach(dev); 1095 device_delete_child(dev, sc->rl_miibus); 1096 1097 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1098 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1099 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1100 1101 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1102 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1103 sc->rl_cdata.rl_rx_dmamap); 1104 bus_dma_tag_destroy(sc->rl_tag); 1105 bus_dma_tag_destroy(sc->rl_parent_tag); 1106 1107 RL_UNLOCK(sc); 1108 mtx_destroy(&sc->rl_mtx); 1109 1110 return(0); 1111} 1112 1113/* 1114 * Initialize the transmit descriptors. 1115 */ 1116static int rl_list_tx_init(sc) 1117 struct rl_softc *sc; 1118{ 1119 struct rl_chain_data *cd; 1120 int i; 1121 1122 cd = &sc->rl_cdata; 1123 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1124 cd->rl_tx_chain[i] = NULL; 1125 CSR_WRITE_4(sc, 1126 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1127 } 1128 1129 sc->rl_cdata.cur_tx = 0; 1130 sc->rl_cdata.last_tx = 0; 1131 1132 return(0); 1133} 1134 1135/* 1136 * A frame has been uploaded: pass the resulting mbuf chain up to 1137 * the higher level protocols. 1138 * 1139 * You know there's something wrong with a PCI bus-master chip design 1140 * when you have to use m_devget(). 1141 * 1142 * The receive operation is badly documented in the datasheet, so I'll 1143 * attempt to document it here. The driver provides a buffer area and 1144 * places its base address in the RX buffer start address register. 1145 * The chip then begins copying frames into the RX buffer. Each frame 1146 * is preceded by a 32-bit RX status word which specifies the length 1147 * of the frame and certain other status bits. Each frame (starting with 1148 * the status word) is also 32-bit aligned. The frame length is in the 1149 * first 16 bits of the status word; the lower 15 bits correspond with 1150 * the 'rx status register' mentioned in the datasheet. 1151 * 1152 * Note: to make the Alpha happy, the frame payload needs to be aligned 1153 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1154 * as the offset argument to m_devget(). 1155 */ 1156static void rl_rxeof(sc) 1157 struct rl_softc *sc; 1158{ 1159 struct ether_header *eh; 1160 struct mbuf *m; 1161 struct ifnet *ifp; 1162 int total_len = 0; 1163 u_int32_t rxstat; 1164 caddr_t rxbufpos; 1165 int wrap = 0; 1166 u_int16_t cur_rx; 1167 u_int16_t limit; 1168 u_int16_t rx_bytes = 0, max_bytes; 1169 1170 ifp = &sc->arpcom.ac_if; 1171 1172 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1173 BUS_DMASYNC_POSTWRITE); 1174 1175 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1176 1177 /* Do not try to read past this point. */ 1178 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1179 1180 if (limit < cur_rx) 1181 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1182 else 1183 max_bytes = limit - cur_rx; 1184 1185 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1186 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1187 rxstat = *(u_int32_t *)rxbufpos; 1188 1189 /* 1190 * Here's a totally undocumented fact for you. When the 1191 * RealTek chip is in the process of copying a packet into 1192 * RAM for you, the length will be 0xfff0. If you spot a 1193 * packet header with this value, you need to stop. The 1194 * datasheet makes absolutely no mention of this and 1195 * RealTek should be shot for this. 1196 */ 1197 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1198 break; 1199 1200 if (!(rxstat & RL_RXSTAT_RXOK)) { 1201 ifp->if_ierrors++; 1202 rl_init(sc); 1203 return; 1204 } 1205 1206 /* No errors; receive the packet. */ 1207 total_len = rxstat >> 16; 1208 rx_bytes += total_len + 4; 1209 1210 /* 1211 * XXX The RealTek chip includes the CRC with every 1212 * received frame, and there's no way to turn this 1213 * behavior off (at least, I can't find anything in 1214 * the manual that explains how to do it) so we have 1215 * to trim off the CRC manually. 1216 */ 1217 total_len -= ETHER_CRC_LEN; 1218 1219 /* 1220 * Avoid trying to read more bytes than we know 1221 * the chip has prepared for us. 1222 */ 1223 if (rx_bytes > max_bytes) 1224 break; 1225 1226 rxbufpos = sc->rl_cdata.rl_rx_buf + 1227 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1228 1229 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1230 rxbufpos = sc->rl_cdata.rl_rx_buf; 1231 1232 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1233 1234 if (total_len > wrap) { 1235 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1236 NULL); 1237 if (m == NULL) { 1238 ifp->if_ierrors++; 1239 } else { 1240 m_copyback(m, wrap, total_len - wrap, 1241 sc->rl_cdata.rl_rx_buf); 1242 } 1243 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1244 } else { 1245 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1246 NULL); 1247 if (m == NULL) { 1248 ifp->if_ierrors++; 1249 } 1250 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1251 } 1252 1253 /* 1254 * Round up to 32-bit boundary. 1255 */ 1256 cur_rx = (cur_rx + 3) & ~3; 1257 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1258 1259 if (m == NULL) 1260 continue; 1261 1262 eh = mtod(m, struct ether_header *); 1263 ifp->if_ipackets++; 1264 1265 /* Remove header from mbuf and pass it on. */ 1266 m_adj(m, sizeof(struct ether_header)); 1267 ether_input(ifp, eh, m); 1268 } 1269 1270 return; 1271} 1272 1273/* 1274 * A frame was downloaded to the chip. It's safe for us to clean up 1275 * the list buffers. 1276 */ 1277static void rl_txeof(sc) 1278 struct rl_softc *sc; 1279{ 1280 struct ifnet *ifp; 1281 u_int32_t txstat; 1282 1283 ifp = &sc->arpcom.ac_if; 1284 1285 /* Clear the timeout timer. */ 1286 ifp->if_timer = 0; 1287 1288 /* 1289 * Go through our tx list and free mbufs for those 1290 * frames that have been uploaded. 1291 */ 1292 do { 1293 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1294 if (!(txstat & (RL_TXSTAT_TX_OK| 1295 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1296 break; 1297 1298 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1299 1300 if (RL_LAST_TXMBUF(sc) != NULL) { 1301 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1302 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1303 m_freem(RL_LAST_TXMBUF(sc)); 1304 RL_LAST_TXMBUF(sc) = NULL; 1305 } 1306 if (txstat & RL_TXSTAT_TX_OK) 1307 ifp->if_opackets++; 1308 else { 1309 int oldthresh; 1310 ifp->if_oerrors++; 1311 if ((txstat & RL_TXSTAT_TXABRT) || 1312 (txstat & RL_TXSTAT_OUTOFWIN)) 1313 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1314 oldthresh = sc->rl_txthresh; 1315 /* error recovery */ 1316 rl_reset(sc); 1317 rl_init(sc); 1318 /* 1319 * If there was a transmit underrun, 1320 * bump the TX threshold. 1321 */ 1322 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1323 sc->rl_txthresh = oldthresh + 32; 1324 return; 1325 } 1326 RL_INC(sc->rl_cdata.last_tx); 1327 ifp->if_flags &= ~IFF_OACTIVE; 1328 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1329 1330 return; 1331} 1332 1333static void rl_tick(xsc) 1334 void *xsc; 1335{ 1336 struct rl_softc *sc; 1337 struct mii_data *mii; 1338 1339 sc = xsc; 1340 RL_LOCK(sc); 1341 mii = device_get_softc(sc->rl_miibus); 1342 1343 mii_tick(mii); 1344 1345 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1346 RL_UNLOCK(sc); 1347 1348 return; 1349} 1350 1351static void rl_intr(arg) 1352 void *arg; 1353{ 1354 struct rl_softc *sc; 1355 struct ifnet *ifp; 1356 u_int16_t status; 1357 1358 sc = arg; 1359 1360 if (sc->suspended) { 1361 return; 1362 } 1363 1364 RL_LOCK(sc); 1365 ifp = &sc->arpcom.ac_if; 1366 1367 /* Disable interrupts. */ 1368 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1369 1370 for (;;) { 1371 1372 status = CSR_READ_2(sc, RL_ISR); 1373 if (status) 1374 CSR_WRITE_2(sc, RL_ISR, status); 1375 1376 if ((status & RL_INTRS) == 0) 1377 break; 1378 1379 if (status & RL_ISR_RX_OK) 1380 rl_rxeof(sc); 1381 1382 if (status & RL_ISR_RX_ERR) 1383 rl_rxeof(sc); 1384 1385 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1386 rl_txeof(sc); 1387 1388 if (status & RL_ISR_SYSTEM_ERR) { 1389 rl_reset(sc); 1390 rl_init(sc); 1391 } 1392 1393 } 1394 1395 /* Re-enable interrupts. */ 1396 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1397 1398 if (ifp->if_snd.ifq_head != NULL) 1399 rl_start(ifp); 1400 1401 RL_UNLOCK(sc); 1402 1403 return; 1404} 1405 1406/* 1407 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1408 * pointers to the fragment pointers. 1409 */ 1410static int rl_encap(sc, m_head) 1411 struct rl_softc *sc; 1412 struct mbuf *m_head; 1413{ 1414 struct mbuf *m_new = NULL; 1415 1416 /* 1417 * The RealTek is brain damaged and wants longword-aligned 1418 * TX buffers, plus we can only have one fragment buffer 1419 * per packet. We have to copy pretty much all the time. 1420 */ 1421 1422 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1423 if (m_new == NULL) 1424 return(1); 1425 if (m_head->m_pkthdr.len > MHLEN) { 1426 MCLGET(m_new, M_DONTWAIT); 1427 if (!(m_new->m_flags & M_EXT)) { 1428 m_freem(m_new); 1429 return(1); 1430 } 1431 } 1432 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1433 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1434 m_freem(m_head); 1435 m_head = m_new; 1436 1437 /* Pad frames to at least 60 bytes. */ 1438 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1439 /* 1440 * Make security concious people happy: zero out the 1441 * bytes in the pad area, since we don't know what 1442 * this mbuf cluster buffer's previous user might 1443 * have left in it. 1444 */ 1445 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1446 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1447 m_head->m_pkthdr.len += 1448 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1449 m_head->m_len = m_head->m_pkthdr.len; 1450 } 1451 1452 RL_CUR_TXMBUF(sc) = m_head; 1453 1454 return(0); 1455} 1456 1457/* 1458 * Main transmit routine. 1459 */ 1460 1461static void rl_start(ifp) 1462 struct ifnet *ifp; 1463{ 1464 struct rl_softc *sc; 1465 struct mbuf *m_head = NULL; 1466 1467 sc = ifp->if_softc; 1468 RL_LOCK(sc); 1469 1470 while(RL_CUR_TXMBUF(sc) == NULL) { 1471 IF_DEQUEUE(&ifp->if_snd, m_head); 1472 if (m_head == NULL) 1473 break; 1474 1475 if (rl_encap(sc, m_head)) { 1476 IF_PREPEND(&ifp->if_snd, m_head); 1477 ifp->if_flags |= IFF_OACTIVE; 1478 break; 1479 } 1480 1481 /* 1482 * If there's a BPF listener, bounce a copy of this frame 1483 * to him. 1484 */ 1485 if (ifp->if_bpf) 1486 bpf_mtap(ifp, RL_CUR_TXMBUF(sc)); 1487 1488 /* 1489 * Transmit the frame. 1490 */ 1491 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1492 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1493 mtod(RL_CUR_TXMBUF(sc), void *), 1494 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 1495 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1496 BUS_DMASYNC_PREREAD); 1497 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1498 RL_TXTHRESH(sc->rl_txthresh) | 1499 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1500 1501 RL_INC(sc->rl_cdata.cur_tx); 1502 } 1503 1504 /* 1505 * We broke out of the loop because all our TX slots are 1506 * full. Mark the NIC as busy until it drains some of the 1507 * packets from the queue. 1508 */ 1509 if (RL_CUR_TXMBUF(sc) != NULL) 1510 ifp->if_flags |= IFF_OACTIVE; 1511 1512 /* 1513 * Set a timeout in case the chip goes out to lunch. 1514 */ 1515 ifp->if_timer = 5; 1516 RL_UNLOCK(sc); 1517 1518 return; 1519} 1520 1521static void rl_init(xsc) 1522 void *xsc; 1523{ 1524 struct rl_softc *sc = xsc; 1525 struct ifnet *ifp = &sc->arpcom.ac_if; 1526 struct mii_data *mii; 1527 int i; 1528 u_int32_t rxcfg = 0; 1529 1530 RL_LOCK(sc); 1531 mii = device_get_softc(sc->rl_miibus); 1532 1533 /* 1534 * Cancel pending I/O and free all RX/TX buffers. 1535 */ 1536 rl_stop(sc); 1537 1538 /* Init our MAC address */ 1539 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1540 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 1541 } 1542 1543 /* Init the RX buffer pointer register. */ 1544 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1545 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 1546 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1547 BUS_DMASYNC_PREWRITE); 1548 1549 /* Init TX descriptors. */ 1550 rl_list_tx_init(sc); 1551 1552 /* 1553 * Enable transmit and receive. 1554 */ 1555 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1556 1557 /* 1558 * Set the initial TX and RX configuration. 1559 */ 1560 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1561 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1562 1563 /* Set the individual bit to receive frames for this host only. */ 1564 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1565 rxcfg |= RL_RXCFG_RX_INDIV; 1566 1567 /* If we want promiscuous mode, set the allframes bit. */ 1568 if (ifp->if_flags & IFF_PROMISC) { 1569 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1570 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1571 } else { 1572 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1573 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1574 } 1575 1576 /* 1577 * Set capture broadcast bit to capture broadcast frames. 1578 */ 1579 if (ifp->if_flags & IFF_BROADCAST) { 1580 rxcfg |= RL_RXCFG_RX_BROAD; 1581 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1582 } else { 1583 rxcfg &= ~RL_RXCFG_RX_BROAD; 1584 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1585 } 1586 1587 /* 1588 * Program the multicast filter, if necessary. 1589 */ 1590 rl_setmulti(sc); 1591 1592 /* 1593 * Enable interrupts. 1594 */ 1595 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1596 1597 /* Set initial TX threshold */ 1598 sc->rl_txthresh = RL_TX_THRESH_INIT; 1599 1600 /* Start RX/TX process. */ 1601 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1602 1603 /* Enable receiver and transmitter. */ 1604 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1605 1606 mii_mediachg(mii); 1607 1608 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1609 1610 ifp->if_flags |= IFF_RUNNING; 1611 ifp->if_flags &= ~IFF_OACTIVE; 1612 1613 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1614 RL_UNLOCK(sc); 1615 1616 return; 1617} 1618 1619/* 1620 * Set media options. 1621 */ 1622static int rl_ifmedia_upd(ifp) 1623 struct ifnet *ifp; 1624{ 1625 struct rl_softc *sc; 1626 struct mii_data *mii; 1627 1628 sc = ifp->if_softc; 1629 mii = device_get_softc(sc->rl_miibus); 1630 mii_mediachg(mii); 1631 1632 return(0); 1633} 1634 1635/* 1636 * Report current media status. 1637 */ 1638static void rl_ifmedia_sts(ifp, ifmr) 1639 struct ifnet *ifp; 1640 struct ifmediareq *ifmr; 1641{ 1642 struct rl_softc *sc; 1643 struct mii_data *mii; 1644 1645 sc = ifp->if_softc; 1646 mii = device_get_softc(sc->rl_miibus); 1647 1648 mii_pollstat(mii); 1649 ifmr->ifm_active = mii->mii_media_active; 1650 ifmr->ifm_status = mii->mii_media_status; 1651 1652 return; 1653} 1654 1655static int rl_ioctl(ifp, command, data) 1656 struct ifnet *ifp; 1657 u_long command; 1658 caddr_t data; 1659{ 1660 struct rl_softc *sc = ifp->if_softc; 1661 struct ifreq *ifr = (struct ifreq *) data; 1662 struct mii_data *mii; 1663 int error = 0; 1664 1665 RL_LOCK(sc); 1666 1667 switch(command) { 1668 case SIOCSIFADDR: 1669 case SIOCGIFADDR: 1670 case SIOCSIFMTU: 1671 error = ether_ioctl(ifp, command, data); 1672 break; 1673 case SIOCSIFFLAGS: 1674 if (ifp->if_flags & IFF_UP) { 1675 rl_init(sc); 1676 } else { 1677 if (ifp->if_flags & IFF_RUNNING) 1678 rl_stop(sc); 1679 } 1680 error = 0; 1681 break; 1682 case SIOCADDMULTI: 1683 case SIOCDELMULTI: 1684 rl_setmulti(sc); 1685 error = 0; 1686 break; 1687 case SIOCGIFMEDIA: 1688 case SIOCSIFMEDIA: 1689 mii = device_get_softc(sc->rl_miibus); 1690 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1691 break; 1692 default: 1693 error = EINVAL; 1694 break; 1695 } 1696 1697 RL_UNLOCK(sc); 1698 1699 return(error); 1700} 1701 1702static void rl_watchdog(ifp) 1703 struct ifnet *ifp; 1704{ 1705 struct rl_softc *sc; 1706 1707 sc = ifp->if_softc; 1708 RL_LOCK(sc); 1709 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1710 ifp->if_oerrors++; 1711 1712 rl_txeof(sc); 1713 rl_rxeof(sc); 1714 rl_init(sc); 1715 RL_UNLOCK(sc); 1716 1717 return; 1718} 1719 1720/* 1721 * Stop the adapter and free any mbufs allocated to the 1722 * RX and TX lists. 1723 */ 1724static void rl_stop(sc) 1725 struct rl_softc *sc; 1726{ 1727 register int i; 1728 struct ifnet *ifp; 1729 1730 RL_LOCK(sc); 1731 ifp = &sc->arpcom.ac_if; 1732 ifp->if_timer = 0; 1733 1734 untimeout(rl_tick, sc, sc->rl_stat_ch); 1735 1736 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1737 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1738 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1739 1740 /* 1741 * Free the TX list buffers. 1742 */ 1743 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1744 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1745 bus_dmamap_unload(sc->rl_tag, 1746 sc->rl_cdata.rl_tx_dmamap[i]); 1747 bus_dmamap_destroy(sc->rl_tag, 1748 sc->rl_cdata.rl_tx_dmamap[i]); 1749 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1750 sc->rl_cdata.rl_tx_chain[i] = NULL; 1751 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1752 } 1753 } 1754 1755 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1756 RL_UNLOCK(sc); 1757 return; 1758} 1759 1760/* 1761 * Device suspend routine. Stop the interface and save some PCI 1762 * settings in case the BIOS doesn't restore them properly on 1763 * resume. 1764 */ 1765static int rl_suspend(dev) 1766 device_t dev; 1767{ 1768 register int i; 1769 struct rl_softc *sc; 1770 1771 sc = device_get_softc(dev); 1772 1773 rl_stop(sc); 1774 1775 for (i = 0; i < 5; i++) 1776 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 1777 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1778 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1779 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1780 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1781 1782 sc->suspended = 1; 1783 1784 return (0); 1785} 1786 1787/* 1788 * Device resume routine. Restore some PCI settings in case the BIOS 1789 * doesn't, re-enable busmastering, and restart the interface if 1790 * appropriate. 1791 */ 1792static int rl_resume(dev) 1793 device_t dev; 1794{ 1795 register int i; 1796 struct rl_softc *sc; 1797 struct ifnet *ifp; 1798 1799 sc = device_get_softc(dev); 1800 ifp = &sc->arpcom.ac_if; 1801 1802 /* better way to do this? */ 1803 for (i = 0; i < 5; i++) 1804 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 1805 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1806 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1807 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1808 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1809 1810 /* reenable busmastering */ 1811 pci_enable_busmaster(dev); 1812 pci_enable_io(dev, RL_RES); 1813 1814 /* reinitialize interface if necessary */ 1815 if (ifp->if_flags & IFF_UP) 1816 rl_init(sc); 1817 1818 sc->suspended = 0; 1819 1820 return (0); 1821} 1822 1823/* 1824 * Stop all chip I/O so that the kernel's probe routines don't 1825 * get confused by errant DMAs when rebooting. 1826 */ 1827static void rl_shutdown(dev) 1828 device_t dev; 1829{ 1830 struct rl_softc *sc; 1831 1832 sc = device_get_softc(dev); 1833 1834 rl_stop(sc); 1835 1836 return; 1837} 1838