if_rl.c revision 93818
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_rl.c 93818 2002-04-04 21:03:38Z jhb $ 33 */ 34 35/* 36 * RealTek 8129/8139 PCI NIC driver 37 * 38 * Supports several extremely cheap PCI 10/100 adapters based on 39 * the RealTek chipset. Datasheets can be obtained from 40 * www.realtek.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86#include <sys/param.h> 87#include <sys/systm.h> 88#include <sys/sockio.h> 89#include <sys/mbuf.h> 90#include <sys/malloc.h> 91#include <sys/kernel.h> 92#include <sys/socket.h> 93 94#include <net/if.h> 95#include <net/if_arp.h> 96#include <net/ethernet.h> 97#include <net/if_dl.h> 98#include <net/if_media.h> 99 100#include <net/bpf.h> 101 102#include <machine/bus_pio.h> 103#include <machine/bus_memio.h> 104#include <machine/bus.h> 105#include <machine/resource.h> 106#include <sys/bus.h> 107#include <sys/rman.h> 108 109#include <dev/mii/mii.h> 110#include <dev/mii/miivar.h> 111 112#include <pci/pcireg.h> 113#include <pci/pcivar.h> 114 115MODULE_DEPEND(rl, miibus, 1, 1, 1); 116 117/* "controller miibus0" required. See GENERIC if you get errors here. */ 118#include "miibus_if.h" 119 120/* 121 * Default to using PIO access for this driver. On SMP systems, 122 * there appear to be problems with memory mapped mode: it looks like 123 * doing too many memory mapped access back to back in rapid succession 124 * can hang the bus. I'm inclined to blame this on crummy design/construction 125 * on the part of RealTek. Memory mapped mode does appear to work on 126 * uniprocessor systems though. 127 */ 128#define RL_USEIOSPACE 129 130#include <pci/if_rlreg.h> 131 132#ifndef lint 133static const char rcsid[] = 134 "$FreeBSD: head/sys/pci/if_rl.c 93818 2002-04-04 21:03:38Z jhb $"; 135#endif 136 137/* 138 * Various supported device vendors/types and their names. 139 */ 140static struct rl_type rl_devs[] = { 141 { RT_VENDORID, RT_DEVICEID_8129, 142 "RealTek 8129 10/100BaseTX" }, 143 { RT_VENDORID, RT_DEVICEID_8139, 144 "RealTek 8139 10/100BaseTX" }, 145 { RT_VENDORID, RT_DEVICEID_8138, 146 "RealTek 8139 10/100BaseTX CardBus" }, 147 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 148 "Accton MPX 5030/5038 10/100BaseTX" }, 149 { DELTA_VENDORID, DELTA_DEVICEID_8139, 150 "Delta Electronics 8139 10/100BaseTX" }, 151 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 152 "Addtron Technolgy 8139 10/100BaseTX" }, 153 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 154 "D-Link DFE-530TX+ 10/100BaseTX" }, 155 { 0, 0, NULL } 156}; 157 158static int rl_probe (device_t); 159static int rl_attach (device_t); 160static int rl_detach (device_t); 161 162static int rl_encap (struct rl_softc *, struct mbuf * ); 163 164static void rl_rxeof (struct rl_softc *); 165static void rl_txeof (struct rl_softc *); 166static void rl_intr (void *); 167static void rl_tick (void *); 168static void rl_start (struct ifnet *); 169static int rl_ioctl (struct ifnet *, u_long, caddr_t); 170static void rl_init (void *); 171static void rl_stop (struct rl_softc *); 172static void rl_watchdog (struct ifnet *); 173static int rl_suspend (device_t); 174static int rl_resume (device_t); 175static void rl_shutdown (device_t); 176static int rl_ifmedia_upd (struct ifnet *); 177static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 178 179static void rl_eeprom_putbyte (struct rl_softc *, int); 180static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 181static void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 182static void rl_mii_sync (struct rl_softc *); 183static void rl_mii_send (struct rl_softc *, u_int32_t, int); 184static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 185static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 186 187static int rl_miibus_readreg (device_t, int, int); 188static int rl_miibus_writereg (device_t, int, int, int); 189static void rl_miibus_statchg (device_t); 190 191static u_int8_t rl_calchash (caddr_t); 192static void rl_setmulti (struct rl_softc *); 193static void rl_reset (struct rl_softc *); 194static int rl_list_tx_init (struct rl_softc *); 195 196static void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 197static void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 198 199#ifdef RL_USEIOSPACE 200#define RL_RES SYS_RES_IOPORT 201#define RL_RID RL_PCI_LOIO 202#else 203#define RL_RES SYS_RES_MEMORY 204#define RL_RID RL_PCI_LOMEM 205#endif 206 207static device_method_t rl_methods[] = { 208 /* Device interface */ 209 DEVMETHOD(device_probe, rl_probe), 210 DEVMETHOD(device_attach, rl_attach), 211 DEVMETHOD(device_detach, rl_detach), 212 DEVMETHOD(device_suspend, rl_suspend), 213 DEVMETHOD(device_resume, rl_resume), 214 DEVMETHOD(device_shutdown, rl_shutdown), 215 216 /* bus interface */ 217 DEVMETHOD(bus_print_child, bus_generic_print_child), 218 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 219 220 /* MII interface */ 221 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 222 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 223 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 224 225 { 0, 0 } 226}; 227 228static driver_t rl_driver = { 229 "rl", 230 rl_methods, 231 sizeof(struct rl_softc) 232}; 233 234static devclass_t rl_devclass; 235 236DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 237DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 238DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 239 240#define EE_SET(x) \ 241 CSR_WRITE_1(sc, RL_EECMD, \ 242 CSR_READ_1(sc, RL_EECMD) | x) 243 244#define EE_CLR(x) \ 245 CSR_WRITE_1(sc, RL_EECMD, \ 246 CSR_READ_1(sc, RL_EECMD) & ~x) 247 248static void 249rl_dma_map_rxbuf(arg, segs, nseg, error) 250 void *arg; 251 bus_dma_segment_t *segs; 252 int nseg, error; 253{ 254 struct rl_softc *sc; 255 256 sc = arg; 257 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 258 259 return; 260} 261 262static void 263rl_dma_map_txbuf(arg, segs, nseg, error) 264 void *arg; 265 bus_dma_segment_t *segs; 266 int nseg, error; 267{ 268 struct rl_softc *sc; 269 270 sc = arg; 271 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 272 273 return; 274} 275 276/* 277 * Send a read command and address to the EEPROM, check for ACK. 278 */ 279static void rl_eeprom_putbyte(sc, addr) 280 struct rl_softc *sc; 281 int addr; 282{ 283 register int d, i; 284 285 d = addr | sc->rl_eecmd_read; 286 287 /* 288 * Feed in each bit and strobe the clock. 289 */ 290 for (i = 0x400; i; i >>= 1) { 291 if (d & i) { 292 EE_SET(RL_EE_DATAIN); 293 } else { 294 EE_CLR(RL_EE_DATAIN); 295 } 296 DELAY(100); 297 EE_SET(RL_EE_CLK); 298 DELAY(150); 299 EE_CLR(RL_EE_CLK); 300 DELAY(100); 301 } 302 303 return; 304} 305 306/* 307 * Read a word of data stored in the EEPROM at address 'addr.' 308 */ 309static void rl_eeprom_getword(sc, addr, dest) 310 struct rl_softc *sc; 311 int addr; 312 u_int16_t *dest; 313{ 314 register int i; 315 u_int16_t word = 0; 316 317 /* Enter EEPROM access mode. */ 318 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 319 320 /* 321 * Send address of word we want to read. 322 */ 323 rl_eeprom_putbyte(sc, addr); 324 325 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 326 327 /* 328 * Start reading bits from EEPROM. 329 */ 330 for (i = 0x8000; i; i >>= 1) { 331 EE_SET(RL_EE_CLK); 332 DELAY(100); 333 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 334 word |= i; 335 EE_CLR(RL_EE_CLK); 336 DELAY(100); 337 } 338 339 /* Turn off EEPROM access mode. */ 340 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 341 342 *dest = word; 343 344 return; 345} 346 347/* 348 * Read a sequence of words from the EEPROM. 349 */ 350static void rl_read_eeprom(sc, dest, off, cnt, swap) 351 struct rl_softc *sc; 352 caddr_t dest; 353 int off; 354 int cnt; 355 int swap; 356{ 357 int i; 358 u_int16_t word = 0, *ptr; 359 360 for (i = 0; i < cnt; i++) { 361 rl_eeprom_getword(sc, off + i, &word); 362 ptr = (u_int16_t *)(dest + (i * 2)); 363 if (swap) 364 *ptr = ntohs(word); 365 else 366 *ptr = word; 367 } 368 369 return; 370} 371 372 373/* 374 * MII access routines are provided for the 8129, which 375 * doesn't have a built-in PHY. For the 8139, we fake things 376 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 377 * direct access PHY registers. 378 */ 379#define MII_SET(x) \ 380 CSR_WRITE_1(sc, RL_MII, \ 381 CSR_READ_1(sc, RL_MII) | x) 382 383#define MII_CLR(x) \ 384 CSR_WRITE_1(sc, RL_MII, \ 385 CSR_READ_1(sc, RL_MII) & ~x) 386 387/* 388 * Sync the PHYs by setting data bit and strobing the clock 32 times. 389 */ 390static void rl_mii_sync(sc) 391 struct rl_softc *sc; 392{ 393 register int i; 394 395 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 396 397 for (i = 0; i < 32; i++) { 398 MII_SET(RL_MII_CLK); 399 DELAY(1); 400 MII_CLR(RL_MII_CLK); 401 DELAY(1); 402 } 403 404 return; 405} 406 407/* 408 * Clock a series of bits through the MII. 409 */ 410static void rl_mii_send(sc, bits, cnt) 411 struct rl_softc *sc; 412 u_int32_t bits; 413 int cnt; 414{ 415 int i; 416 417 MII_CLR(RL_MII_CLK); 418 419 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 420 if (bits & i) { 421 MII_SET(RL_MII_DATAOUT); 422 } else { 423 MII_CLR(RL_MII_DATAOUT); 424 } 425 DELAY(1); 426 MII_CLR(RL_MII_CLK); 427 DELAY(1); 428 MII_SET(RL_MII_CLK); 429 } 430} 431 432/* 433 * Read an PHY register through the MII. 434 */ 435static int rl_mii_readreg(sc, frame) 436 struct rl_softc *sc; 437 struct rl_mii_frame *frame; 438 439{ 440 int i, ack; 441 442 RL_LOCK(sc); 443 444 /* 445 * Set up frame for RX. 446 */ 447 frame->mii_stdelim = RL_MII_STARTDELIM; 448 frame->mii_opcode = RL_MII_READOP; 449 frame->mii_turnaround = 0; 450 frame->mii_data = 0; 451 452 CSR_WRITE_2(sc, RL_MII, 0); 453 454 /* 455 * Turn on data xmit. 456 */ 457 MII_SET(RL_MII_DIR); 458 459 rl_mii_sync(sc); 460 461 /* 462 * Send command/address info. 463 */ 464 rl_mii_send(sc, frame->mii_stdelim, 2); 465 rl_mii_send(sc, frame->mii_opcode, 2); 466 rl_mii_send(sc, frame->mii_phyaddr, 5); 467 rl_mii_send(sc, frame->mii_regaddr, 5); 468 469 /* Idle bit */ 470 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 471 DELAY(1); 472 MII_SET(RL_MII_CLK); 473 DELAY(1); 474 475 /* Turn off xmit. */ 476 MII_CLR(RL_MII_DIR); 477 478 /* Check for ack */ 479 MII_CLR(RL_MII_CLK); 480 DELAY(1); 481 MII_SET(RL_MII_CLK); 482 DELAY(1); 483 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 484 485 /* 486 * Now try reading data bits. If the ack failed, we still 487 * need to clock through 16 cycles to keep the PHY(s) in sync. 488 */ 489 if (ack) { 490 for(i = 0; i < 16; i++) { 491 MII_CLR(RL_MII_CLK); 492 DELAY(1); 493 MII_SET(RL_MII_CLK); 494 DELAY(1); 495 } 496 goto fail; 497 } 498 499 for (i = 0x8000; i; i >>= 1) { 500 MII_CLR(RL_MII_CLK); 501 DELAY(1); 502 if (!ack) { 503 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 504 frame->mii_data |= i; 505 DELAY(1); 506 } 507 MII_SET(RL_MII_CLK); 508 DELAY(1); 509 } 510 511fail: 512 513 MII_CLR(RL_MII_CLK); 514 DELAY(1); 515 MII_SET(RL_MII_CLK); 516 DELAY(1); 517 518 RL_UNLOCK(sc); 519 520 if (ack) 521 return(1); 522 return(0); 523} 524 525/* 526 * Write to a PHY register through the MII. 527 */ 528static int rl_mii_writereg(sc, frame) 529 struct rl_softc *sc; 530 struct rl_mii_frame *frame; 531 532{ 533 RL_LOCK(sc); 534 535 /* 536 * Set up frame for TX. 537 */ 538 539 frame->mii_stdelim = RL_MII_STARTDELIM; 540 frame->mii_opcode = RL_MII_WRITEOP; 541 frame->mii_turnaround = RL_MII_TURNAROUND; 542 543 /* 544 * Turn on data output. 545 */ 546 MII_SET(RL_MII_DIR); 547 548 rl_mii_sync(sc); 549 550 rl_mii_send(sc, frame->mii_stdelim, 2); 551 rl_mii_send(sc, frame->mii_opcode, 2); 552 rl_mii_send(sc, frame->mii_phyaddr, 5); 553 rl_mii_send(sc, frame->mii_regaddr, 5); 554 rl_mii_send(sc, frame->mii_turnaround, 2); 555 rl_mii_send(sc, frame->mii_data, 16); 556 557 /* Idle bit. */ 558 MII_SET(RL_MII_CLK); 559 DELAY(1); 560 MII_CLR(RL_MII_CLK); 561 DELAY(1); 562 563 /* 564 * Turn off xmit. 565 */ 566 MII_CLR(RL_MII_DIR); 567 568 RL_UNLOCK(sc); 569 570 return(0); 571} 572 573static int rl_miibus_readreg(dev, phy, reg) 574 device_t dev; 575 int phy, reg; 576{ 577 struct rl_softc *sc; 578 struct rl_mii_frame frame; 579 u_int16_t rval = 0; 580 u_int16_t rl8139_reg = 0; 581 582 sc = device_get_softc(dev); 583 RL_LOCK(sc); 584 585 if (sc->rl_type == RL_8139) { 586 /* Pretend the internal PHY is only at address 0 */ 587 if (phy) { 588 RL_UNLOCK(sc); 589 return(0); 590 } 591 switch(reg) { 592 case MII_BMCR: 593 rl8139_reg = RL_BMCR; 594 break; 595 case MII_BMSR: 596 rl8139_reg = RL_BMSR; 597 break; 598 case MII_ANAR: 599 rl8139_reg = RL_ANAR; 600 break; 601 case MII_ANER: 602 rl8139_reg = RL_ANER; 603 break; 604 case MII_ANLPAR: 605 rl8139_reg = RL_LPAR; 606 break; 607 case MII_PHYIDR1: 608 case MII_PHYIDR2: 609 RL_UNLOCK(sc); 610 return(0); 611 break; 612 default: 613 printf("rl%d: bad phy register\n", sc->rl_unit); 614 RL_UNLOCK(sc); 615 return(0); 616 } 617 rval = CSR_READ_2(sc, rl8139_reg); 618 RL_UNLOCK(sc); 619 return(rval); 620 } 621 622 bzero((char *)&frame, sizeof(frame)); 623 624 frame.mii_phyaddr = phy; 625 frame.mii_regaddr = reg; 626 rl_mii_readreg(sc, &frame); 627 RL_UNLOCK(sc); 628 629 return(frame.mii_data); 630} 631 632static int rl_miibus_writereg(dev, phy, reg, data) 633 device_t dev; 634 int phy, reg, data; 635{ 636 struct rl_softc *sc; 637 struct rl_mii_frame frame; 638 u_int16_t rl8139_reg = 0; 639 640 sc = device_get_softc(dev); 641 RL_LOCK(sc); 642 643 if (sc->rl_type == RL_8139) { 644 /* Pretend the internal PHY is only at address 0 */ 645 if (phy) { 646 RL_UNLOCK(sc); 647 return(0); 648 } 649 switch(reg) { 650 case MII_BMCR: 651 rl8139_reg = RL_BMCR; 652 break; 653 case MII_BMSR: 654 rl8139_reg = RL_BMSR; 655 break; 656 case MII_ANAR: 657 rl8139_reg = RL_ANAR; 658 break; 659 case MII_ANER: 660 rl8139_reg = RL_ANER; 661 break; 662 case MII_ANLPAR: 663 rl8139_reg = RL_LPAR; 664 break; 665 case MII_PHYIDR1: 666 case MII_PHYIDR2: 667 RL_UNLOCK(sc); 668 return(0); 669 break; 670 default: 671 printf("rl%d: bad phy register\n", sc->rl_unit); 672 RL_UNLOCK(sc); 673 return(0); 674 } 675 CSR_WRITE_2(sc, rl8139_reg, data); 676 RL_UNLOCK(sc); 677 return(0); 678 } 679 680 bzero((char *)&frame, sizeof(frame)); 681 682 frame.mii_phyaddr = phy; 683 frame.mii_regaddr = reg; 684 frame.mii_data = data; 685 686 rl_mii_writereg(sc, &frame); 687 688 RL_UNLOCK(sc); 689 return(0); 690} 691 692static void rl_miibus_statchg(dev) 693 device_t dev; 694{ 695 return; 696} 697 698/* 699 * Calculate CRC of a multicast group address, return the upper 6 bits. 700 */ 701static u_int8_t rl_calchash(addr) 702 caddr_t addr; 703{ 704 u_int32_t crc, carry; 705 int i, j; 706 u_int8_t c; 707 708 /* Compute CRC for the address value. */ 709 crc = 0xFFFFFFFF; /* initial value */ 710 711 for (i = 0; i < 6; i++) { 712 c = *(addr + i); 713 for (j = 0; j < 8; j++) { 714 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 715 crc <<= 1; 716 c >>= 1; 717 if (carry) 718 crc = (crc ^ 0x04c11db6) | carry; 719 } 720 } 721 722 /* return the filter bit position */ 723 return(crc >> 26); 724} 725 726/* 727 * Program the 64-bit multicast hash filter. 728 */ 729static void rl_setmulti(sc) 730 struct rl_softc *sc; 731{ 732 struct ifnet *ifp; 733 int h = 0; 734 u_int32_t hashes[2] = { 0, 0 }; 735 struct ifmultiaddr *ifma; 736 u_int32_t rxfilt; 737 int mcnt = 0; 738 739 ifp = &sc->arpcom.ac_if; 740 741 rxfilt = CSR_READ_4(sc, RL_RXCFG); 742 743 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 744 rxfilt |= RL_RXCFG_RX_MULTI; 745 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 746 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 747 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 748 return; 749 } 750 751 /* first, zot all the existing hash bits */ 752 CSR_WRITE_4(sc, RL_MAR0, 0); 753 CSR_WRITE_4(sc, RL_MAR4, 0); 754 755 /* now program new ones */ 756 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 757 if (ifma->ifma_addr->sa_family != AF_LINK) 758 continue; 759 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 760 if (h < 32) 761 hashes[0] |= (1 << h); 762 else 763 hashes[1] |= (1 << (h - 32)); 764 mcnt++; 765 } 766 767 if (mcnt) 768 rxfilt |= RL_RXCFG_RX_MULTI; 769 else 770 rxfilt &= ~RL_RXCFG_RX_MULTI; 771 772 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 773 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 774 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 775 776 return; 777} 778 779static void rl_reset(sc) 780 struct rl_softc *sc; 781{ 782 register int i; 783 784 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 785 786 for (i = 0; i < RL_TIMEOUT; i++) { 787 DELAY(10); 788 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 789 break; 790 } 791 if (i == RL_TIMEOUT) 792 printf("rl%d: reset never completed!\n", sc->rl_unit); 793 794 return; 795} 796 797/* 798 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 799 * IDs against our list and return a device name if we find a match. 800 */ 801static int rl_probe(dev) 802 device_t dev; 803{ 804 struct rl_type *t; 805 806 t = rl_devs; 807 808 while(t->rl_name != NULL) { 809 if ((pci_get_vendor(dev) == t->rl_vid) && 810 (pci_get_device(dev) == t->rl_did)) { 811 device_set_desc(dev, t->rl_name); 812 return(0); 813 } 814 t++; 815 } 816 817 return(ENXIO); 818} 819 820/* 821 * Attach the interface. Allocate softc structures, do ifmedia 822 * setup and ethernet/BPF attach. 823 */ 824static int rl_attach(dev) 825 device_t dev; 826{ 827 u_char eaddr[ETHER_ADDR_LEN]; 828 u_int32_t command; 829 struct rl_softc *sc; 830 struct ifnet *ifp; 831 u_int16_t rl_did = 0; 832 int unit, error = 0, rid; 833 834 sc = device_get_softc(dev); 835 unit = device_get_unit(dev); 836 bzero(sc, sizeof(struct rl_softc)); 837 838 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 839 MTX_DEF | MTX_RECURSE); 840 RL_LOCK(sc); 841 842 /* 843 * Handle power management nonsense. 844 */ 845 846 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 847 u_int32_t iobase, membase, irq; 848 849 /* Save important PCI config data. */ 850 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 851 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 852 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 853 854 /* Reset the power state. */ 855 printf("rl%d: chip is is in D%d power mode " 856 "-- setting to D0\n", unit, 857 pci_get_powerstate(dev)); 858 859 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 860 861 /* Restore PCI config data. */ 862 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 863 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 864 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 865 } 866 867 /* 868 * Map control/status registers. 869 */ 870 pci_enable_busmaster(dev); 871 pci_enable_io(dev, SYS_RES_IOPORT); 872 pci_enable_io(dev, SYS_RES_MEMORY); 873 command = pci_read_config(dev, PCIR_COMMAND, 4); 874 875#ifdef RL_USEIOSPACE 876 if (!(command & PCIM_CMD_PORTEN)) { 877 printf("rl%d: failed to enable I/O ports!\n", unit); 878 error = ENXIO; 879 goto fail; 880 } 881#else 882 if (!(command & PCIM_CMD_MEMEN)) { 883 printf("rl%d: failed to enable memory mapping!\n", unit); 884 error = ENXIO; 885 goto fail; 886 } 887#endif 888 889 rid = RL_RID; 890 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 891 0, ~0, 1, RF_ACTIVE); 892 893 if (sc->rl_res == NULL) { 894 printf ("rl%d: couldn't map ports/memory\n", unit); 895 error = ENXIO; 896 goto fail; 897 } 898 899 /* Detect the Realtek 8139B. For some reason, this chip is very 900 * unstable when left to autoselect the media 901 * The best workaround is to set the device to the required 902 * media type or to set it to the 10 Meg speed. 903 */ 904 905 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 906 printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit); 907 } 908 909 sc->rl_btag = rman_get_bustag(sc->rl_res); 910 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 911 912 rid = 0; 913 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 914 RF_SHAREABLE | RF_ACTIVE); 915 916 if (sc->rl_irq == NULL) { 917 printf("rl%d: couldn't map interrupt\n", unit); 918 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 919 error = ENXIO; 920 goto fail; 921 } 922 923 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 924 rl_intr, sc, &sc->rl_intrhand); 925 926 if (error) { 927 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 928 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 929 printf("rl%d: couldn't set up irq\n", unit); 930 goto fail; 931 } 932 933 callout_handle_init(&sc->rl_stat_ch); 934 935 /* Reset the adapter. */ 936 rl_reset(sc); 937 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 938 rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 939 if (rl_did != 0x8129) 940 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 941 942 /* 943 * Get station address from the EEPROM. 944 */ 945 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 946 947 /* 948 * A RealTek chip was detected. Inform the world. 949 */ 950 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 951 952 sc->rl_unit = unit; 953 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 954 955 /* 956 * Now read the exact device type from the EEPROM to find 957 * out if it's an 8129 or 8139. 958 */ 959 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 960 961 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 962 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 963 rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS) 964 sc->rl_type = RL_8139; 965 else if (rl_did == RT_DEVICEID_8129) 966 sc->rl_type = RL_8129; 967 else { 968 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 969 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 970 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 971 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 972 error = ENXIO; 973 goto fail; 974 } 975 976 /* 977 * Allocate the parent bus DMA tag appropriate for PCI. 978 */ 979#define RL_NSEG_NEW 32 980 error = bus_dma_tag_create(NULL, /* parent */ 981 1, 0, /* alignment, boundary */ 982 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 983 BUS_SPACE_MAXADDR, /* highaddr */ 984 NULL, NULL, /* filter, filterarg */ 985 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 986 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 987 BUS_DMA_ALLOCNOW, /* flags */ 988 &sc->rl_parent_tag); 989 990 /* 991 * Now allocate a tag for the DMA descriptor lists. 992 * All of our lists are allocated as a contiguous block 993 * of memory. 994 */ 995 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 996 1, 0, /* alignment, boundary */ 997 BUS_SPACE_MAXADDR, /* lowaddr */ 998 BUS_SPACE_MAXADDR, /* highaddr */ 999 NULL, NULL, /* filter, filterarg */ 1000 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 1001 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1002 0, /* flags */ 1003 &sc->rl_tag); 1004 1005 /* 1006 * Now allocate a chunk of DMA-able memory based on the 1007 * tag we just created. 1008 */ 1009 error = bus_dmamem_alloc(sc->rl_tag, 1010 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT, 1011 &sc->rl_cdata.rl_rx_dmamap); 1012 1013 if (sc->rl_cdata.rl_rx_buf == NULL) { 1014 printf("rl%d: no memory for list buffers!\n", unit); 1015 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1016 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1017 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1018 bus_dma_tag_destroy(sc->rl_tag); 1019 error = ENXIO; 1020 goto fail; 1021 } 1022 1023 /* Leave a few bytes before the start of the RX ring buffer. */ 1024 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1025 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1026 1027 /* Do MII setup */ 1028 if (mii_phy_probe(dev, &sc->rl_miibus, 1029 rl_ifmedia_upd, rl_ifmedia_sts)) { 1030 printf("rl%d: MII without any phy!\n", sc->rl_unit); 1031 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1032 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1033 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1034 bus_dmamem_free(sc->rl_tag, 1035 sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap); 1036 bus_dma_tag_destroy(sc->rl_tag); 1037 error = ENXIO; 1038 goto fail; 1039 } 1040 1041 ifp = &sc->arpcom.ac_if; 1042 ifp->if_softc = sc; 1043 ifp->if_unit = unit; 1044 ifp->if_name = "rl"; 1045 ifp->if_mtu = ETHERMTU; 1046 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1047 ifp->if_ioctl = rl_ioctl; 1048 ifp->if_output = ether_output; 1049 ifp->if_start = rl_start; 1050 ifp->if_watchdog = rl_watchdog; 1051 ifp->if_init = rl_init; 1052 ifp->if_baudrate = 10000000; 1053 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1054 1055 /* 1056 * Call MI attach routine. 1057 */ 1058 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1059 RL_UNLOCK(sc); 1060 return(0); 1061 1062fail: 1063 RL_UNLOCK(sc); 1064 mtx_destroy(&sc->rl_mtx); 1065 return(error); 1066} 1067 1068static int rl_detach(dev) 1069 device_t dev; 1070{ 1071 struct rl_softc *sc; 1072 struct ifnet *ifp; 1073 1074 sc = device_get_softc(dev); 1075 RL_LOCK(sc); 1076 ifp = &sc->arpcom.ac_if; 1077 1078 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1079 rl_stop(sc); 1080 1081 bus_generic_detach(dev); 1082 device_delete_child(dev, sc->rl_miibus); 1083 1084 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1085 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1086 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1087 1088 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1089 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1090 sc->rl_cdata.rl_rx_dmamap); 1091 bus_dma_tag_destroy(sc->rl_tag); 1092 bus_dma_tag_destroy(sc->rl_parent_tag); 1093 1094 RL_UNLOCK(sc); 1095 mtx_destroy(&sc->rl_mtx); 1096 1097 return(0); 1098} 1099 1100/* 1101 * Initialize the transmit descriptors. 1102 */ 1103static int rl_list_tx_init(sc) 1104 struct rl_softc *sc; 1105{ 1106 struct rl_chain_data *cd; 1107 int i; 1108 1109 cd = &sc->rl_cdata; 1110 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1111 cd->rl_tx_chain[i] = NULL; 1112 CSR_WRITE_4(sc, 1113 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1114 } 1115 1116 sc->rl_cdata.cur_tx = 0; 1117 sc->rl_cdata.last_tx = 0; 1118 1119 return(0); 1120} 1121 1122/* 1123 * A frame has been uploaded: pass the resulting mbuf chain up to 1124 * the higher level protocols. 1125 * 1126 * You know there's something wrong with a PCI bus-master chip design 1127 * when you have to use m_devget(). 1128 * 1129 * The receive operation is badly documented in the datasheet, so I'll 1130 * attempt to document it here. The driver provides a buffer area and 1131 * places its base address in the RX buffer start address register. 1132 * The chip then begins copying frames into the RX buffer. Each frame 1133 * is preceded by a 32-bit RX status word which specifies the length 1134 * of the frame and certain other status bits. Each frame (starting with 1135 * the status word) is also 32-bit aligned. The frame length is in the 1136 * first 16 bits of the status word; the lower 15 bits correspond with 1137 * the 'rx status register' mentioned in the datasheet. 1138 * 1139 * Note: to make the Alpha happy, the frame payload needs to be aligned 1140 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1141 * as the offset argument to m_devget(). 1142 */ 1143static void rl_rxeof(sc) 1144 struct rl_softc *sc; 1145{ 1146 struct ether_header *eh; 1147 struct mbuf *m; 1148 struct ifnet *ifp; 1149 int total_len = 0; 1150 u_int32_t rxstat; 1151 caddr_t rxbufpos; 1152 int wrap = 0; 1153 u_int16_t cur_rx; 1154 u_int16_t limit; 1155 u_int16_t rx_bytes = 0, max_bytes; 1156 1157 ifp = &sc->arpcom.ac_if; 1158 1159 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1160 BUS_DMASYNC_POSTWRITE); 1161 1162 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1163 1164 /* Do not try to read past this point. */ 1165 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1166 1167 if (limit < cur_rx) 1168 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1169 else 1170 max_bytes = limit - cur_rx; 1171 1172 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1173 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1174 rxstat = *(u_int32_t *)rxbufpos; 1175 1176 /* 1177 * Here's a totally undocumented fact for you. When the 1178 * RealTek chip is in the process of copying a packet into 1179 * RAM for you, the length will be 0xfff0. If you spot a 1180 * packet header with this value, you need to stop. The 1181 * datasheet makes absolutely no mention of this and 1182 * RealTek should be shot for this. 1183 */ 1184 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1185 break; 1186 1187 if (!(rxstat & RL_RXSTAT_RXOK)) { 1188 ifp->if_ierrors++; 1189 rl_init(sc); 1190 return; 1191 } 1192 1193 /* No errors; receive the packet. */ 1194 total_len = rxstat >> 16; 1195 rx_bytes += total_len + 4; 1196 1197 /* 1198 * XXX The RealTek chip includes the CRC with every 1199 * received frame, and there's no way to turn this 1200 * behavior off (at least, I can't find anything in 1201 * the manual that explains how to do it) so we have 1202 * to trim off the CRC manually. 1203 */ 1204 total_len -= ETHER_CRC_LEN; 1205 1206 /* 1207 * Avoid trying to read more bytes than we know 1208 * the chip has prepared for us. 1209 */ 1210 if (rx_bytes > max_bytes) 1211 break; 1212 1213 rxbufpos = sc->rl_cdata.rl_rx_buf + 1214 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1215 1216 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1217 rxbufpos = sc->rl_cdata.rl_rx_buf; 1218 1219 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1220 1221 if (total_len > wrap) { 1222 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1223 NULL); 1224 if (m == NULL) { 1225 ifp->if_ierrors++; 1226 } else { 1227 m_copyback(m, wrap, total_len - wrap, 1228 sc->rl_cdata.rl_rx_buf); 1229 } 1230 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1231 } else { 1232 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1233 NULL); 1234 if (m == NULL) { 1235 ifp->if_ierrors++; 1236 } 1237 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1238 } 1239 1240 /* 1241 * Round up to 32-bit boundary. 1242 */ 1243 cur_rx = (cur_rx + 3) & ~3; 1244 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1245 1246 if (m == NULL) 1247 continue; 1248 1249 eh = mtod(m, struct ether_header *); 1250 ifp->if_ipackets++; 1251 1252 /* Remove header from mbuf and pass it on. */ 1253 m_adj(m, sizeof(struct ether_header)); 1254 ether_input(ifp, eh, m); 1255 } 1256 1257 return; 1258} 1259 1260/* 1261 * A frame was downloaded to the chip. It's safe for us to clean up 1262 * the list buffers. 1263 */ 1264static void rl_txeof(sc) 1265 struct rl_softc *sc; 1266{ 1267 struct ifnet *ifp; 1268 u_int32_t txstat; 1269 1270 ifp = &sc->arpcom.ac_if; 1271 1272 /* Clear the timeout timer. */ 1273 ifp->if_timer = 0; 1274 1275 /* 1276 * Go through our tx list and free mbufs for those 1277 * frames that have been uploaded. 1278 */ 1279 do { 1280 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1281 if (!(txstat & (RL_TXSTAT_TX_OK| 1282 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1283 break; 1284 1285 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1286 1287 if (RL_LAST_TXMBUF(sc) != NULL) { 1288 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1289 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1290 m_freem(RL_LAST_TXMBUF(sc)); 1291 RL_LAST_TXMBUF(sc) = NULL; 1292 } 1293 if (txstat & RL_TXSTAT_TX_OK) 1294 ifp->if_opackets++; 1295 else { 1296 int oldthresh; 1297 ifp->if_oerrors++; 1298 if ((txstat & RL_TXSTAT_TXABRT) || 1299 (txstat & RL_TXSTAT_OUTOFWIN)) 1300 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1301 oldthresh = sc->rl_txthresh; 1302 /* error recovery */ 1303 rl_reset(sc); 1304 rl_init(sc); 1305 /* 1306 * If there was a transmit underrun, 1307 * bump the TX threshold. 1308 */ 1309 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1310 sc->rl_txthresh = oldthresh + 32; 1311 return; 1312 } 1313 RL_INC(sc->rl_cdata.last_tx); 1314 ifp->if_flags &= ~IFF_OACTIVE; 1315 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1316 1317 return; 1318} 1319 1320static void rl_tick(xsc) 1321 void *xsc; 1322{ 1323 struct rl_softc *sc; 1324 struct mii_data *mii; 1325 1326 sc = xsc; 1327 RL_LOCK(sc); 1328 mii = device_get_softc(sc->rl_miibus); 1329 1330 mii_tick(mii); 1331 1332 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1333 RL_UNLOCK(sc); 1334 1335 return; 1336} 1337 1338static void rl_intr(arg) 1339 void *arg; 1340{ 1341 struct rl_softc *sc; 1342 struct ifnet *ifp; 1343 u_int16_t status; 1344 1345 sc = arg; 1346 1347 if (sc->suspended) { 1348 return; 1349 } 1350 1351 RL_LOCK(sc); 1352 ifp = &sc->arpcom.ac_if; 1353 1354 /* Disable interrupts. */ 1355 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1356 1357 for (;;) { 1358 1359 status = CSR_READ_2(sc, RL_ISR); 1360 if (status) 1361 CSR_WRITE_2(sc, RL_ISR, status); 1362 1363 if ((status & RL_INTRS) == 0) 1364 break; 1365 1366 if (status & RL_ISR_RX_OK) 1367 rl_rxeof(sc); 1368 1369 if (status & RL_ISR_RX_ERR) 1370 rl_rxeof(sc); 1371 1372 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1373 rl_txeof(sc); 1374 1375 if (status & RL_ISR_SYSTEM_ERR) { 1376 rl_reset(sc); 1377 rl_init(sc); 1378 } 1379 1380 } 1381 1382 /* Re-enable interrupts. */ 1383 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1384 1385 if (ifp->if_snd.ifq_head != NULL) 1386 rl_start(ifp); 1387 1388 RL_UNLOCK(sc); 1389 1390 return; 1391} 1392 1393/* 1394 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1395 * pointers to the fragment pointers. 1396 */ 1397static int rl_encap(sc, m_head) 1398 struct rl_softc *sc; 1399 struct mbuf *m_head; 1400{ 1401 struct mbuf *m_new = NULL; 1402 1403 /* 1404 * The RealTek is brain damaged and wants longword-aligned 1405 * TX buffers, plus we can only have one fragment buffer 1406 * per packet. We have to copy pretty much all the time. 1407 */ 1408 1409 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1410 if (m_new == NULL) 1411 return(1); 1412 if (m_head->m_pkthdr.len > MHLEN) { 1413 MCLGET(m_new, M_DONTWAIT); 1414 if (!(m_new->m_flags & M_EXT)) { 1415 m_freem(m_new); 1416 return(1); 1417 } 1418 } 1419 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1420 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1421 m_freem(m_head); 1422 m_head = m_new; 1423 1424 /* Pad frames to at least 60 bytes. */ 1425 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1426 /* 1427 * Make security concious people happy: zero out the 1428 * bytes in the pad area, since we don't know what 1429 * this mbuf cluster buffer's previous user might 1430 * have left in it. 1431 */ 1432 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1433 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1434 m_head->m_pkthdr.len += 1435 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1436 m_head->m_len = m_head->m_pkthdr.len; 1437 } 1438 1439 RL_CUR_TXMBUF(sc) = m_head; 1440 1441 return(0); 1442} 1443 1444/* 1445 * Main transmit routine. 1446 */ 1447 1448static void rl_start(ifp) 1449 struct ifnet *ifp; 1450{ 1451 struct rl_softc *sc; 1452 struct mbuf *m_head = NULL; 1453 1454 sc = ifp->if_softc; 1455 RL_LOCK(sc); 1456 1457 while(RL_CUR_TXMBUF(sc) == NULL) { 1458 IF_DEQUEUE(&ifp->if_snd, m_head); 1459 if (m_head == NULL) 1460 break; 1461 1462 if (rl_encap(sc, m_head)) { 1463 IF_PREPEND(&ifp->if_snd, m_head); 1464 ifp->if_flags |= IFF_OACTIVE; 1465 break; 1466 } 1467 1468 /* 1469 * If there's a BPF listener, bounce a copy of this frame 1470 * to him. 1471 */ 1472 if (ifp->if_bpf) 1473 bpf_mtap(ifp, RL_CUR_TXMBUF(sc)); 1474 1475 /* 1476 * Transmit the frame. 1477 */ 1478 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1479 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1480 mtod(RL_CUR_TXMBUF(sc), void *), 1481 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 1482 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1483 BUS_DMASYNC_PREREAD); 1484 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1485 RL_TXTHRESH(sc->rl_txthresh) | 1486 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1487 1488 RL_INC(sc->rl_cdata.cur_tx); 1489 } 1490 1491 /* 1492 * We broke out of the loop because all our TX slots are 1493 * full. Mark the NIC as busy until it drains some of the 1494 * packets from the queue. 1495 */ 1496 if (RL_CUR_TXMBUF(sc) != NULL) 1497 ifp->if_flags |= IFF_OACTIVE; 1498 1499 /* 1500 * Set a timeout in case the chip goes out to lunch. 1501 */ 1502 ifp->if_timer = 5; 1503 RL_UNLOCK(sc); 1504 1505 return; 1506} 1507 1508static void rl_init(xsc) 1509 void *xsc; 1510{ 1511 struct rl_softc *sc = xsc; 1512 struct ifnet *ifp = &sc->arpcom.ac_if; 1513 struct mii_data *mii; 1514 int i; 1515 u_int32_t rxcfg = 0; 1516 1517 RL_LOCK(sc); 1518 mii = device_get_softc(sc->rl_miibus); 1519 1520 /* 1521 * Cancel pending I/O and free all RX/TX buffers. 1522 */ 1523 rl_stop(sc); 1524 1525 /* Init our MAC address */ 1526 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1527 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 1528 } 1529 1530 /* Init the RX buffer pointer register. */ 1531 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1532 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 1533 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1534 BUS_DMASYNC_PREWRITE); 1535 1536 /* Init TX descriptors. */ 1537 rl_list_tx_init(sc); 1538 1539 /* 1540 * Enable transmit and receive. 1541 */ 1542 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1543 1544 /* 1545 * Set the initial TX and RX configuration. 1546 */ 1547 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1548 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1549 1550 /* Set the individual bit to receive frames for this host only. */ 1551 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1552 rxcfg |= RL_RXCFG_RX_INDIV; 1553 1554 /* If we want promiscuous mode, set the allframes bit. */ 1555 if (ifp->if_flags & IFF_PROMISC) { 1556 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1557 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1558 } else { 1559 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1560 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1561 } 1562 1563 /* 1564 * Set capture broadcast bit to capture broadcast frames. 1565 */ 1566 if (ifp->if_flags & IFF_BROADCAST) { 1567 rxcfg |= RL_RXCFG_RX_BROAD; 1568 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1569 } else { 1570 rxcfg &= ~RL_RXCFG_RX_BROAD; 1571 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1572 } 1573 1574 /* 1575 * Program the multicast filter, if necessary. 1576 */ 1577 rl_setmulti(sc); 1578 1579 /* 1580 * Enable interrupts. 1581 */ 1582 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1583 1584 /* Set initial TX threshold */ 1585 sc->rl_txthresh = RL_TX_THRESH_INIT; 1586 1587 /* Start RX/TX process. */ 1588 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1589 1590 /* Enable receiver and transmitter. */ 1591 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1592 1593 mii_mediachg(mii); 1594 1595 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1596 1597 ifp->if_flags |= IFF_RUNNING; 1598 ifp->if_flags &= ~IFF_OACTIVE; 1599 1600 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1601 RL_UNLOCK(sc); 1602 1603 return; 1604} 1605 1606/* 1607 * Set media options. 1608 */ 1609static int rl_ifmedia_upd(ifp) 1610 struct ifnet *ifp; 1611{ 1612 struct rl_softc *sc; 1613 struct mii_data *mii; 1614 1615 sc = ifp->if_softc; 1616 mii = device_get_softc(sc->rl_miibus); 1617 mii_mediachg(mii); 1618 1619 return(0); 1620} 1621 1622/* 1623 * Report current media status. 1624 */ 1625static void rl_ifmedia_sts(ifp, ifmr) 1626 struct ifnet *ifp; 1627 struct ifmediareq *ifmr; 1628{ 1629 struct rl_softc *sc; 1630 struct mii_data *mii; 1631 1632 sc = ifp->if_softc; 1633 mii = device_get_softc(sc->rl_miibus); 1634 1635 mii_pollstat(mii); 1636 ifmr->ifm_active = mii->mii_media_active; 1637 ifmr->ifm_status = mii->mii_media_status; 1638 1639 return; 1640} 1641 1642static int rl_ioctl(ifp, command, data) 1643 struct ifnet *ifp; 1644 u_long command; 1645 caddr_t data; 1646{ 1647 struct rl_softc *sc = ifp->if_softc; 1648 struct ifreq *ifr = (struct ifreq *) data; 1649 struct mii_data *mii; 1650 int error = 0; 1651 1652 RL_LOCK(sc); 1653 1654 switch(command) { 1655 case SIOCSIFADDR: 1656 case SIOCGIFADDR: 1657 case SIOCSIFMTU: 1658 error = ether_ioctl(ifp, command, data); 1659 break; 1660 case SIOCSIFFLAGS: 1661 if (ifp->if_flags & IFF_UP) { 1662 rl_init(sc); 1663 } else { 1664 if (ifp->if_flags & IFF_RUNNING) 1665 rl_stop(sc); 1666 } 1667 error = 0; 1668 break; 1669 case SIOCADDMULTI: 1670 case SIOCDELMULTI: 1671 rl_setmulti(sc); 1672 error = 0; 1673 break; 1674 case SIOCGIFMEDIA: 1675 case SIOCSIFMEDIA: 1676 mii = device_get_softc(sc->rl_miibus); 1677 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1678 break; 1679 default: 1680 error = EINVAL; 1681 break; 1682 } 1683 1684 RL_UNLOCK(sc); 1685 1686 return(error); 1687} 1688 1689static void rl_watchdog(ifp) 1690 struct ifnet *ifp; 1691{ 1692 struct rl_softc *sc; 1693 1694 sc = ifp->if_softc; 1695 RL_LOCK(sc); 1696 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1697 ifp->if_oerrors++; 1698 1699 rl_txeof(sc); 1700 rl_rxeof(sc); 1701 rl_init(sc); 1702 RL_UNLOCK(sc); 1703 1704 return; 1705} 1706 1707/* 1708 * Stop the adapter and free any mbufs allocated to the 1709 * RX and TX lists. 1710 */ 1711static void rl_stop(sc) 1712 struct rl_softc *sc; 1713{ 1714 register int i; 1715 struct ifnet *ifp; 1716 1717 RL_LOCK(sc); 1718 ifp = &sc->arpcom.ac_if; 1719 ifp->if_timer = 0; 1720 1721 untimeout(rl_tick, sc, sc->rl_stat_ch); 1722 1723 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1724 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1725 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1726 1727 /* 1728 * Free the TX list buffers. 1729 */ 1730 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1731 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1732 bus_dmamap_unload(sc->rl_tag, 1733 sc->rl_cdata.rl_tx_dmamap[i]); 1734 bus_dmamap_destroy(sc->rl_tag, 1735 sc->rl_cdata.rl_tx_dmamap[i]); 1736 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1737 sc->rl_cdata.rl_tx_chain[i] = NULL; 1738 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1739 } 1740 } 1741 1742 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1743 RL_UNLOCK(sc); 1744 return; 1745} 1746 1747/* 1748 * Device suspend routine. Stop the interface and save some PCI 1749 * settings in case the BIOS doesn't restore them properly on 1750 * resume. 1751 */ 1752static int rl_suspend(dev) 1753 device_t dev; 1754{ 1755 register int i; 1756 struct rl_softc *sc; 1757 1758 sc = device_get_softc(dev); 1759 1760 rl_stop(sc); 1761 1762 for (i = 0; i < 5; i++) 1763 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 1764 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1765 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1766 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1767 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1768 1769 sc->suspended = 1; 1770 1771 return (0); 1772} 1773 1774/* 1775 * Device resume routine. Restore some PCI settings in case the BIOS 1776 * doesn't, re-enable busmastering, and restart the interface if 1777 * appropriate. 1778 */ 1779static int rl_resume(dev) 1780 device_t dev; 1781{ 1782 register int i; 1783 struct rl_softc *sc; 1784 struct ifnet *ifp; 1785 1786 sc = device_get_softc(dev); 1787 ifp = &sc->arpcom.ac_if; 1788 1789 /* better way to do this? */ 1790 for (i = 0; i < 5; i++) 1791 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 1792 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1793 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1794 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1795 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1796 1797 /* reenable busmastering */ 1798 pci_enable_busmaster(dev); 1799 pci_enable_io(dev, RL_RES); 1800 1801 /* reinitialize interface if necessary */ 1802 if (ifp->if_flags & IFF_UP) 1803 rl_init(sc); 1804 1805 sc->suspended = 0; 1806 1807 return (0); 1808} 1809 1810/* 1811 * Stop all chip I/O so that the kernel's probe routines don't 1812 * get confused by errant DMAs when rebooting. 1813 */ 1814static void rl_shutdown(dev) 1815 device_t dev; 1816{ 1817 struct rl_softc *sc; 1818 1819 sc = device_get_softc(dev); 1820 1821 rl_stop(sc); 1822 1823 return; 1824} 1825