if_rl.c revision 67771
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_rl.c 67771 2000-10-28 09:00:20Z wpaul $ 33 */ 34 35/* 36 * RealTek 8129/8139 PCI NIC driver 37 * 38 * Supports several extremely cheap PCI 10/100 adapters based on 39 * the RealTek chipset. Datasheets can be obtained from 40 * www.realtek.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86#include <sys/param.h> 87#include <sys/systm.h> 88#include <sys/sockio.h> 89#include <sys/mbuf.h> 90#include <sys/malloc.h> 91#include <sys/kernel.h> 92#include <sys/socket.h> 93 94#include <net/if.h> 95#include <net/if_arp.h> 96#include <net/ethernet.h> 97#include <net/if_dl.h> 98#include <net/if_media.h> 99 100#include <net/bpf.h> 101 102#include <vm/vm.h> /* for vtophys */ 103#include <vm/pmap.h> /* for vtophys */ 104#include <machine/bus_pio.h> 105#include <machine/bus_memio.h> 106#include <machine/bus.h> 107#include <machine/resource.h> 108#include <sys/bus.h> 109#include <sys/rman.h> 110 111#include <dev/mii/mii.h> 112#include <dev/mii/miivar.h> 113 114#include <pci/pcireg.h> 115#include <pci/pcivar.h> 116 117MODULE_DEPEND(rl, miibus, 1, 1, 1); 118 119/* "controller miibus0" required. See GENERIC if you get errors here. */ 120#include "miibus_if.h" 121 122/* 123 * Default to using PIO access for this driver. On SMP systems, 124 * there appear to be problems with memory mapped mode: it looks like 125 * doing too many memory mapped access back to back in rapid succession 126 * can hang the bus. I'm inclined to blame this on crummy design/construction 127 * on the part of RealTek. Memory mapped mode does appear to work on 128 * uniprocessor systems though. 129 */ 130#define RL_USEIOSPACE 131 132#include <pci/if_rlreg.h> 133 134#ifndef lint 135static const char rcsid[] = 136 "$FreeBSD: head/sys/pci/if_rl.c 67771 2000-10-28 09:00:20Z wpaul $"; 137#endif 138 139/* 140 * Various supported device vendors/types and their names. 141 */ 142static struct rl_type rl_devs[] = { 143 { RT_VENDORID, RT_DEVICEID_8129, 144 "RealTek 8129 10/100BaseTX" }, 145 { RT_VENDORID, RT_DEVICEID_8139, 146 "RealTek 8139 10/100BaseTX" }, 147 { RT_VENDORID, RT_DEVICEID_8138, 148 "RealTek 8139 10/100BaseTX CardBus" }, 149 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 150 "Accton MPX 5030/5038 10/100BaseTX" }, 151 { DELTA_VENDORID, DELTA_DEVICEID_8139, 152 "Delta Electronics 8139 10/100BaseTX" }, 153 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 154 "Addtron Technolgy 8139 10/100BaseTX" }, 155 { 0, 0, NULL } 156}; 157 158static int rl_probe __P((device_t)); 159static int rl_attach __P((device_t)); 160static int rl_detach __P((device_t)); 161 162static int rl_encap __P((struct rl_softc *, struct mbuf * )); 163 164static void rl_rxeof __P((struct rl_softc *)); 165static void rl_txeof __P((struct rl_softc *)); 166static void rl_intr __P((void *)); 167static void rl_tick __P((void *)); 168static void rl_start __P((struct ifnet *)); 169static int rl_ioctl __P((struct ifnet *, u_long, caddr_t)); 170static void rl_init __P((void *)); 171static void rl_stop __P((struct rl_softc *)); 172static void rl_watchdog __P((struct ifnet *)); 173static void rl_shutdown __P((device_t)); 174static int rl_ifmedia_upd __P((struct ifnet *)); 175static void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 176 177static void rl_eeprom_putbyte __P((struct rl_softc *, int)); 178static void rl_eeprom_getword __P((struct rl_softc *, int, u_int16_t *)); 179static void rl_read_eeprom __P((struct rl_softc *, caddr_t, 180 int, int, int)); 181static void rl_mii_sync __P((struct rl_softc *)); 182static void rl_mii_send __P((struct rl_softc *, u_int32_t, int)); 183static int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *)); 184static int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *)); 185 186static int rl_miibus_readreg __P((device_t, int, int)); 187static int rl_miibus_writereg __P((device_t, int, int, int)); 188static void rl_miibus_statchg __P((device_t)); 189 190static u_int8_t rl_calchash __P((caddr_t)); 191static void rl_setmulti __P((struct rl_softc *)); 192static void rl_reset __P((struct rl_softc *)); 193static int rl_list_tx_init __P((struct rl_softc *)); 194 195#ifdef RL_USEIOSPACE 196#define RL_RES SYS_RES_IOPORT 197#define RL_RID RL_PCI_LOIO 198#else 199#define RL_RES SYS_RES_MEMORY 200#define RL_RID RL_PCI_LOMEM 201#endif 202 203static device_method_t rl_methods[] = { 204 /* Device interface */ 205 DEVMETHOD(device_probe, rl_probe), 206 DEVMETHOD(device_attach, rl_attach), 207 DEVMETHOD(device_detach, rl_detach), 208 DEVMETHOD(device_shutdown, rl_shutdown), 209 210 /* bus interface */ 211 DEVMETHOD(bus_print_child, bus_generic_print_child), 212 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 213 214 /* MII interface */ 215 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 216 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 217 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 218 219 { 0, 0 } 220}; 221 222static driver_t rl_driver = { 223 "rl", 224 rl_methods, 225 sizeof(struct rl_softc) 226}; 227 228static devclass_t rl_devclass; 229 230DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 231DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 232 233#define EE_SET(x) \ 234 CSR_WRITE_1(sc, RL_EECMD, \ 235 CSR_READ_1(sc, RL_EECMD) | x) 236 237#define EE_CLR(x) \ 238 CSR_WRITE_1(sc, RL_EECMD, \ 239 CSR_READ_1(sc, RL_EECMD) & ~x) 240 241/* 242 * Send a read command and address to the EEPROM, check for ACK. 243 */ 244static void rl_eeprom_putbyte(sc, addr) 245 struct rl_softc *sc; 246 int addr; 247{ 248 register int d, i; 249 250 d = addr | RL_EECMD_READ; 251 252 /* 253 * Feed in each bit and strobe the clock. 254 */ 255 for (i = 0x400; i; i >>= 1) { 256 if (d & i) { 257 EE_SET(RL_EE_DATAIN); 258 } else { 259 EE_CLR(RL_EE_DATAIN); 260 } 261 DELAY(100); 262 EE_SET(RL_EE_CLK); 263 DELAY(150); 264 EE_CLR(RL_EE_CLK); 265 DELAY(100); 266 } 267 268 return; 269} 270 271/* 272 * Read a word of data stored in the EEPROM at address 'addr.' 273 */ 274static void rl_eeprom_getword(sc, addr, dest) 275 struct rl_softc *sc; 276 int addr; 277 u_int16_t *dest; 278{ 279 register int i; 280 u_int16_t word = 0; 281 282 /* Enter EEPROM access mode. */ 283 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 284 285 /* 286 * Send address of word we want to read. 287 */ 288 rl_eeprom_putbyte(sc, addr); 289 290 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 291 292 /* 293 * Start reading bits from EEPROM. 294 */ 295 for (i = 0x8000; i; i >>= 1) { 296 EE_SET(RL_EE_CLK); 297 DELAY(100); 298 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 299 word |= i; 300 EE_CLR(RL_EE_CLK); 301 DELAY(100); 302 } 303 304 /* Turn off EEPROM access mode. */ 305 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 306 307 *dest = word; 308 309 return; 310} 311 312/* 313 * Read a sequence of words from the EEPROM. 314 */ 315static void rl_read_eeprom(sc, dest, off, cnt, swap) 316 struct rl_softc *sc; 317 caddr_t dest; 318 int off; 319 int cnt; 320 int swap; 321{ 322 int i; 323 u_int16_t word = 0, *ptr; 324 325 for (i = 0; i < cnt; i++) { 326 rl_eeprom_getword(sc, off + i, &word); 327 ptr = (u_int16_t *)(dest + (i * 2)); 328 if (swap) 329 *ptr = ntohs(word); 330 else 331 *ptr = word; 332 } 333 334 return; 335} 336 337 338/* 339 * MII access routines are provided for the 8129, which 340 * doesn't have a built-in PHY. For the 8139, we fake things 341 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 342 * direct access PHY registers. 343 */ 344#define MII_SET(x) \ 345 CSR_WRITE_1(sc, RL_MII, \ 346 CSR_READ_1(sc, RL_MII) | x) 347 348#define MII_CLR(x) \ 349 CSR_WRITE_1(sc, RL_MII, \ 350 CSR_READ_1(sc, RL_MII) & ~x) 351 352/* 353 * Sync the PHYs by setting data bit and strobing the clock 32 times. 354 */ 355static void rl_mii_sync(sc) 356 struct rl_softc *sc; 357{ 358 register int i; 359 360 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 361 362 for (i = 0; i < 32; i++) { 363 MII_SET(RL_MII_CLK); 364 DELAY(1); 365 MII_CLR(RL_MII_CLK); 366 DELAY(1); 367 } 368 369 return; 370} 371 372/* 373 * Clock a series of bits through the MII. 374 */ 375static void rl_mii_send(sc, bits, cnt) 376 struct rl_softc *sc; 377 u_int32_t bits; 378 int cnt; 379{ 380 int i; 381 382 MII_CLR(RL_MII_CLK); 383 384 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 385 if (bits & i) { 386 MII_SET(RL_MII_DATAOUT); 387 } else { 388 MII_CLR(RL_MII_DATAOUT); 389 } 390 DELAY(1); 391 MII_CLR(RL_MII_CLK); 392 DELAY(1); 393 MII_SET(RL_MII_CLK); 394 } 395} 396 397/* 398 * Read an PHY register through the MII. 399 */ 400static int rl_mii_readreg(sc, frame) 401 struct rl_softc *sc; 402 struct rl_mii_frame *frame; 403 404{ 405 int i, ack; 406 407 RL_LOCK(sc); 408 409 /* 410 * Set up frame for RX. 411 */ 412 frame->mii_stdelim = RL_MII_STARTDELIM; 413 frame->mii_opcode = RL_MII_READOP; 414 frame->mii_turnaround = 0; 415 frame->mii_data = 0; 416 417 CSR_WRITE_2(sc, RL_MII, 0); 418 419 /* 420 * Turn on data xmit. 421 */ 422 MII_SET(RL_MII_DIR); 423 424 rl_mii_sync(sc); 425 426 /* 427 * Send command/address info. 428 */ 429 rl_mii_send(sc, frame->mii_stdelim, 2); 430 rl_mii_send(sc, frame->mii_opcode, 2); 431 rl_mii_send(sc, frame->mii_phyaddr, 5); 432 rl_mii_send(sc, frame->mii_regaddr, 5); 433 434 /* Idle bit */ 435 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 436 DELAY(1); 437 MII_SET(RL_MII_CLK); 438 DELAY(1); 439 440 /* Turn off xmit. */ 441 MII_CLR(RL_MII_DIR); 442 443 /* Check for ack */ 444 MII_CLR(RL_MII_CLK); 445 DELAY(1); 446 MII_SET(RL_MII_CLK); 447 DELAY(1); 448 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 449 450 /* 451 * Now try reading data bits. If the ack failed, we still 452 * need to clock through 16 cycles to keep the PHY(s) in sync. 453 */ 454 if (ack) { 455 for(i = 0; i < 16; i++) { 456 MII_CLR(RL_MII_CLK); 457 DELAY(1); 458 MII_SET(RL_MII_CLK); 459 DELAY(1); 460 } 461 goto fail; 462 } 463 464 for (i = 0x8000; i; i >>= 1) { 465 MII_CLR(RL_MII_CLK); 466 DELAY(1); 467 if (!ack) { 468 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 469 frame->mii_data |= i; 470 DELAY(1); 471 } 472 MII_SET(RL_MII_CLK); 473 DELAY(1); 474 } 475 476fail: 477 478 MII_CLR(RL_MII_CLK); 479 DELAY(1); 480 MII_SET(RL_MII_CLK); 481 DELAY(1); 482 483 RL_UNLOCK(sc); 484 485 if (ack) 486 return(1); 487 return(0); 488} 489 490/* 491 * Write to a PHY register through the MII. 492 */ 493static int rl_mii_writereg(sc, frame) 494 struct rl_softc *sc; 495 struct rl_mii_frame *frame; 496 497{ 498 RL_LOCK(sc); 499 500 /* 501 * Set up frame for TX. 502 */ 503 504 frame->mii_stdelim = RL_MII_STARTDELIM; 505 frame->mii_opcode = RL_MII_WRITEOP; 506 frame->mii_turnaround = RL_MII_TURNAROUND; 507 508 /* 509 * Turn on data output. 510 */ 511 MII_SET(RL_MII_DIR); 512 513 rl_mii_sync(sc); 514 515 rl_mii_send(sc, frame->mii_stdelim, 2); 516 rl_mii_send(sc, frame->mii_opcode, 2); 517 rl_mii_send(sc, frame->mii_phyaddr, 5); 518 rl_mii_send(sc, frame->mii_regaddr, 5); 519 rl_mii_send(sc, frame->mii_turnaround, 2); 520 rl_mii_send(sc, frame->mii_data, 16); 521 522 /* Idle bit. */ 523 MII_SET(RL_MII_CLK); 524 DELAY(1); 525 MII_CLR(RL_MII_CLK); 526 DELAY(1); 527 528 /* 529 * Turn off xmit. 530 */ 531 MII_CLR(RL_MII_DIR); 532 533 RL_UNLOCK(sc); 534 535 return(0); 536} 537 538static int rl_miibus_readreg(dev, phy, reg) 539 device_t dev; 540 int phy, reg; 541{ 542 struct rl_softc *sc; 543 struct rl_mii_frame frame; 544 u_int16_t rval = 0; 545 u_int16_t rl8139_reg = 0; 546 547 sc = device_get_softc(dev); 548 RL_LOCK(sc); 549 550 if (sc->rl_type == RL_8139) { 551 /* Pretend the internal PHY is only at address 0 */ 552 if (phy) { 553 RL_UNLOCK(sc); 554 return(0); 555 } 556 switch(reg) { 557 case MII_BMCR: 558 rl8139_reg = RL_BMCR; 559 break; 560 case MII_BMSR: 561 rl8139_reg = RL_BMSR; 562 break; 563 case MII_ANAR: 564 rl8139_reg = RL_ANAR; 565 break; 566 case MII_ANER: 567 rl8139_reg = RL_ANER; 568 break; 569 case MII_ANLPAR: 570 rl8139_reg = RL_LPAR; 571 break; 572 case MII_PHYIDR1: 573 case MII_PHYIDR2: 574 RL_UNLOCK(sc); 575 return(0); 576 break; 577 default: 578 printf("rl%d: bad phy register\n", sc->rl_unit); 579 RL_UNLOCK(sc); 580 return(0); 581 } 582 rval = CSR_READ_2(sc, rl8139_reg); 583 RL_UNLOCK(sc); 584 return(rval); 585 } 586 587 bzero((char *)&frame, sizeof(frame)); 588 589 frame.mii_phyaddr = phy; 590 frame.mii_regaddr = reg; 591 rl_mii_readreg(sc, &frame); 592 RL_UNLOCK(sc); 593 594 return(frame.mii_data); 595} 596 597static int rl_miibus_writereg(dev, phy, reg, data) 598 device_t dev; 599 int phy, reg, data; 600{ 601 struct rl_softc *sc; 602 struct rl_mii_frame frame; 603 u_int16_t rl8139_reg = 0; 604 605 sc = device_get_softc(dev); 606 RL_LOCK(sc); 607 608 if (sc->rl_type == RL_8139) { 609 /* Pretend the internal PHY is only at address 0 */ 610 if (phy) { 611 RL_UNLOCK(sc); 612 return(0); 613 } 614 switch(reg) { 615 case MII_BMCR: 616 rl8139_reg = RL_BMCR; 617 break; 618 case MII_BMSR: 619 rl8139_reg = RL_BMSR; 620 break; 621 case MII_ANAR: 622 rl8139_reg = RL_ANAR; 623 break; 624 case MII_ANER: 625 rl8139_reg = RL_ANER; 626 break; 627 case MII_ANLPAR: 628 rl8139_reg = RL_LPAR; 629 break; 630 case MII_PHYIDR1: 631 case MII_PHYIDR2: 632 RL_UNLOCK(sc); 633 return(0); 634 break; 635 default: 636 printf("rl%d: bad phy register\n", sc->rl_unit); 637 RL_UNLOCK(sc); 638 return(0); 639 } 640 CSR_WRITE_2(sc, rl8139_reg, data); 641 RL_UNLOCK(sc); 642 return(0); 643 } 644 645 bzero((char *)&frame, sizeof(frame)); 646 647 frame.mii_phyaddr = phy; 648 frame.mii_regaddr = reg; 649 frame.mii_data = data; 650 651 rl_mii_writereg(sc, &frame); 652 653 RL_UNLOCK(sc); 654 return(0); 655} 656 657static void rl_miibus_statchg(dev) 658 device_t dev; 659{ 660 return; 661} 662 663/* 664 * Calculate CRC of a multicast group address, return the upper 6 bits. 665 */ 666static u_int8_t rl_calchash(addr) 667 caddr_t addr; 668{ 669 u_int32_t crc, carry; 670 int i, j; 671 u_int8_t c; 672 673 /* Compute CRC for the address value. */ 674 crc = 0xFFFFFFFF; /* initial value */ 675 676 for (i = 0; i < 6; i++) { 677 c = *(addr + i); 678 for (j = 0; j < 8; j++) { 679 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 680 crc <<= 1; 681 c >>= 1; 682 if (carry) 683 crc = (crc ^ 0x04c11db6) | carry; 684 } 685 } 686 687 /* return the filter bit position */ 688 return(crc >> 26); 689} 690 691/* 692 * Program the 64-bit multicast hash filter. 693 */ 694static void rl_setmulti(sc) 695 struct rl_softc *sc; 696{ 697 struct ifnet *ifp; 698 int h = 0; 699 u_int32_t hashes[2] = { 0, 0 }; 700 struct ifmultiaddr *ifma; 701 u_int32_t rxfilt; 702 int mcnt = 0; 703 704 ifp = &sc->arpcom.ac_if; 705 706 rxfilt = CSR_READ_4(sc, RL_RXCFG); 707 708 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 709 rxfilt |= RL_RXCFG_RX_MULTI; 710 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 711 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 712 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 713 return; 714 } 715 716 /* first, zot all the existing hash bits */ 717 CSR_WRITE_4(sc, RL_MAR0, 0); 718 CSR_WRITE_4(sc, RL_MAR4, 0); 719 720 /* now program new ones */ 721 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 722 ifma = ifma->ifma_link.le_next) { 723 if (ifma->ifma_addr->sa_family != AF_LINK) 724 continue; 725 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 726 if (h < 32) 727 hashes[0] |= (1 << h); 728 else 729 hashes[1] |= (1 << (h - 32)); 730 mcnt++; 731 } 732 733 if (mcnt) 734 rxfilt |= RL_RXCFG_RX_MULTI; 735 else 736 rxfilt &= ~RL_RXCFG_RX_MULTI; 737 738 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 739 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 740 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 741 742 return; 743} 744 745static void rl_reset(sc) 746 struct rl_softc *sc; 747{ 748 register int i; 749 750 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 751 752 for (i = 0; i < RL_TIMEOUT; i++) { 753 DELAY(10); 754 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 755 break; 756 } 757 if (i == RL_TIMEOUT) 758 printf("rl%d: reset never completed!\n", sc->rl_unit); 759 760 return; 761} 762 763/* 764 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 765 * IDs against our list and return a device name if we find a match. 766 */ 767static int rl_probe(dev) 768 device_t dev; 769{ 770 struct rl_type *t; 771 772 t = rl_devs; 773 774 while(t->rl_name != NULL) { 775 if ((pci_get_vendor(dev) == t->rl_vid) && 776 (pci_get_device(dev) == t->rl_did)) { 777 device_set_desc(dev, t->rl_name); 778 return(0); 779 } 780 t++; 781 } 782 783 return(ENXIO); 784} 785 786/* 787 * Attach the interface. Allocate softc structures, do ifmedia 788 * setup and ethernet/BPF attach. 789 */ 790static int rl_attach(dev) 791 device_t dev; 792{ 793 u_char eaddr[ETHER_ADDR_LEN]; 794 u_int32_t command; 795 struct rl_softc *sc; 796 struct ifnet *ifp; 797 u_int16_t rl_did = 0; 798 int unit, error = 0, rid; 799 800 sc = device_get_softc(dev); 801 unit = device_get_unit(dev); 802 bzero(sc, sizeof(struct rl_softc)); 803 804 /* 805 * Handle power management nonsense. 806 */ 807 808 command = pci_read_config(dev, RL_PCI_CAPID, 4) & 0x000000FF; 809 if (command == 0x01) { 810 811 command = pci_read_config(dev, RL_PCI_PWRMGMTCTRL, 4); 812 if (command & RL_PSTATE_MASK) { 813 u_int32_t iobase, membase, irq; 814 815 /* Save important PCI config data. */ 816 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 817 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 818 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 819 820 /* Reset the power state. */ 821 printf("rl%d: chip is is in D%d power mode " 822 "-- setting to D0\n", unit, command & RL_PSTATE_MASK); 823 command &= 0xFFFFFFFC; 824 pci_write_config(dev, RL_PCI_PWRMGMTCTRL, command, 4); 825 826 /* Restore PCI config data. */ 827 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 828 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 829 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 830 } 831 } 832 833 /* 834 * Map control/status registers. 835 */ 836 command = pci_read_config(dev, PCIR_COMMAND, 4); 837 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 838 pci_write_config(dev, PCIR_COMMAND, command, 4); 839 command = pci_read_config(dev, PCIR_COMMAND, 4); 840 841#ifdef RL_USEIOSPACE 842 if (!(command & PCIM_CMD_PORTEN)) { 843 printf("rl%d: failed to enable I/O ports!\n", unit); 844 error = ENXIO; 845 goto fail; 846 } 847#else 848 if (!(command & PCIM_CMD_MEMEN)) { 849 printf("rl%d: failed to enable memory mapping!\n", unit); 850 error = ENXIO; 851 goto fail; 852 } 853#endif 854 855 rid = RL_RID; 856 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 857 0, ~0, 1, RF_ACTIVE); 858 859 if (sc->rl_res == NULL) { 860 printf ("rl%d: couldn't map ports/memory\n", unit); 861 error = ENXIO; 862 goto fail; 863 } 864 865 sc->rl_btag = rman_get_bustag(sc->rl_res); 866 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 867 868 rid = 0; 869 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 870 RF_SHAREABLE | RF_ACTIVE); 871 872 if (sc->rl_irq == NULL) { 873 printf("rl%d: couldn't map interrupt\n", unit); 874 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 875 error = ENXIO; 876 goto fail; 877 } 878 879 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 880 rl_intr, sc, &sc->rl_intrhand); 881 882 if (error) { 883 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res); 884 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 885 printf("rl%d: couldn't set up irq\n", unit); 886 goto fail; 887 } 888 889 callout_handle_init(&sc->rl_stat_ch); 890 891 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_DEF); 892 RL_LOCK(sc); 893 894 /* Reset the adapter. */ 895 rl_reset(sc); 896 897 /* 898 * Get station address from the EEPROM. 899 */ 900 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 901 902 /* 903 * A RealTek chip was detected. Inform the world. 904 */ 905 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 906 907 sc->rl_unit = unit; 908 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 909 910 /* 911 * Now read the exact device type from the EEPROM to find 912 * out if it's an 8129 or 8139. 913 */ 914 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 915 916 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 917 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 918 rl_did == RT_DEVICEID_8138) 919 sc->rl_type = RL_8139; 920 else if (rl_did == RT_DEVICEID_8129) 921 sc->rl_type = RL_8129; 922 else { 923 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 924 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 925 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res); 926 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 927 error = ENXIO; 928 goto fail; 929 } 930 931 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 1518, M_DEVBUF, 932 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 933 934 if (sc->rl_cdata.rl_rx_buf == NULL) { 935 printf("rl%d: no memory for list buffers!\n", unit); 936 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 937 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res); 938 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 939 error = ENXIO; 940 goto fail; 941 } 942 943 /* Leave a few bytes before the start of the RX ring buffer. */ 944 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 945 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 946 947 /* Do MII setup */ 948 if (mii_phy_probe(dev, &sc->rl_miibus, 949 rl_ifmedia_upd, rl_ifmedia_sts)) { 950 printf("rl%d: MII without any phy!\n", sc->rl_unit); 951 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 952 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res); 953 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 954 free(sc->rl_cdata.rl_rx_buf, M_DEVBUF); 955 error = ENXIO; 956 goto fail; 957 } 958 959 ifp = &sc->arpcom.ac_if; 960 ifp->if_softc = sc; 961 ifp->if_unit = unit; 962 ifp->if_name = "rl"; 963 ifp->if_mtu = ETHERMTU; 964 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 965 ifp->if_ioctl = rl_ioctl; 966 ifp->if_output = ether_output; 967 ifp->if_start = rl_start; 968 ifp->if_watchdog = rl_watchdog; 969 ifp->if_init = rl_init; 970 ifp->if_baudrate = 10000000; 971 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 972 973 /* 974 * Call MI attach routine. 975 */ 976 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 977 RL_UNLOCK(sc); 978 return(0); 979 980fail: 981 RL_UNLOCK(sc); 982 mtx_destroy(&sc->rl_mtx); 983 return(error); 984} 985 986static int rl_detach(dev) 987 device_t dev; 988{ 989 struct rl_softc *sc; 990 struct ifnet *ifp; 991 992 sc = device_get_softc(dev); 993 RL_LOCK(sc); 994 ifp = &sc->arpcom.ac_if; 995 996 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 997 rl_stop(sc); 998 999 bus_generic_detach(dev); 1000 device_delete_child(dev, sc->rl_miibus); 1001 1002 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1003 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res); 1004 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1005 1006 contigfree(sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 32, M_DEVBUF); 1007 1008 RL_UNLOCK(sc); 1009 mtx_destroy(&sc->rl_mtx); 1010 1011 return(0); 1012} 1013 1014/* 1015 * Initialize the transmit descriptors. 1016 */ 1017static int rl_list_tx_init(sc) 1018 struct rl_softc *sc; 1019{ 1020 struct rl_chain_data *cd; 1021 int i; 1022 1023 cd = &sc->rl_cdata; 1024 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1025 cd->rl_tx_chain[i] = NULL; 1026 CSR_WRITE_4(sc, 1027 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1028 } 1029 1030 sc->rl_cdata.cur_tx = 0; 1031 sc->rl_cdata.last_tx = 0; 1032 1033 return(0); 1034} 1035 1036/* 1037 * A frame has been uploaded: pass the resulting mbuf chain up to 1038 * the higher level protocols. 1039 * 1040 * You know there's something wrong with a PCI bus-master chip design 1041 * when you have to use m_devget(). 1042 * 1043 * The receive operation is badly documented in the datasheet, so I'll 1044 * attempt to document it here. The driver provides a buffer area and 1045 * places its base address in the RX buffer start address register. 1046 * The chip then begins copying frames into the RX buffer. Each frame 1047 * is preceeded by a 32-bit RX status word which specifies the length 1048 * of the frame and certain other status bits. Each frame (starting with 1049 * the status word) is also 32-bit aligned. The frame length is in the 1050 * first 16 bits of the status word; the lower 15 bits correspond with 1051 * the 'rx status register' mentioned in the datasheet. 1052 * 1053 * Note: to make the Alpha happy, the frame payload needs to be aligned 1054 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 1055 * the ring buffer starting at an address two bytes before the actual 1056 * data location. We can then shave off the first two bytes using m_adj(). 1057 * The reason we do this is because m_devget() doesn't let us specify an 1058 * offset into the mbuf storage space, so we have to artificially create 1059 * one. The ring is allocated in such a way that there are a few unused 1060 * bytes of space preceecing it so that it will be safe for us to do the 1061 * 2-byte backstep even if reading from the ring at offset 0. 1062 */ 1063static void rl_rxeof(sc) 1064 struct rl_softc *sc; 1065{ 1066 struct ether_header *eh; 1067 struct mbuf *m; 1068 struct ifnet *ifp; 1069 int total_len = 0; 1070 u_int32_t rxstat; 1071 caddr_t rxbufpos; 1072 int wrap = 0; 1073 u_int16_t cur_rx; 1074 u_int16_t limit; 1075 u_int16_t rx_bytes = 0, max_bytes; 1076 1077 ifp = &sc->arpcom.ac_if; 1078 1079 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1080 1081 /* Do not try to read past this point. */ 1082 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1083 1084 if (limit < cur_rx) 1085 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1086 else 1087 max_bytes = limit - cur_rx; 1088 1089 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1090 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1091 rxstat = *(u_int32_t *)rxbufpos; 1092 1093 /* 1094 * Here's a totally undocumented fact for you. When the 1095 * RealTek chip is in the process of copying a packet into 1096 * RAM for you, the length will be 0xfff0. If you spot a 1097 * packet header with this value, you need to stop. The 1098 * datasheet makes absolutely no mention of this and 1099 * RealTek should be shot for this. 1100 */ 1101 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1102 break; 1103 1104 if (!(rxstat & RL_RXSTAT_RXOK)) { 1105 ifp->if_ierrors++; 1106 rl_init(sc); 1107 return; 1108 } 1109 1110 /* No errors; receive the packet. */ 1111 total_len = rxstat >> 16; 1112 rx_bytes += total_len + 4; 1113 1114 /* 1115 * XXX The RealTek chip includes the CRC with every 1116 * received frame, and there's no way to turn this 1117 * behavior off (at least, I can't find anything in 1118 * the manual that explains how to do it) so we have 1119 * to trim off the CRC manually. 1120 */ 1121 total_len -= ETHER_CRC_LEN; 1122 1123 /* 1124 * Avoid trying to read more bytes than we know 1125 * the chip has prepared for us. 1126 */ 1127 if (rx_bytes > max_bytes) 1128 break; 1129 1130 rxbufpos = sc->rl_cdata.rl_rx_buf + 1131 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1132 1133 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1134 rxbufpos = sc->rl_cdata.rl_rx_buf; 1135 1136 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1137 1138 if (total_len > wrap) { 1139 /* 1140 * Fool m_devget() into thinking we want to copy 1141 * the whole buffer so we don't end up fragmenting 1142 * the data. 1143 */ 1144 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1145 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1146 if (m == NULL) { 1147 ifp->if_ierrors++; 1148 printf("rl%d: out of mbufs, tried to " 1149 "copy %d bytes\n", sc->rl_unit, wrap); 1150 } else { 1151 m_adj(m, RL_ETHER_ALIGN); 1152 m_copyback(m, wrap, total_len - wrap, 1153 sc->rl_cdata.rl_rx_buf); 1154 } 1155 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1156 } else { 1157 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1158 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1159 if (m == NULL) { 1160 ifp->if_ierrors++; 1161 printf("rl%d: out of mbufs, tried to " 1162 "copy %d bytes\n", sc->rl_unit, total_len); 1163 } else 1164 m_adj(m, RL_ETHER_ALIGN); 1165 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1166 } 1167 1168 /* 1169 * Round up to 32-bit boundary. 1170 */ 1171 cur_rx = (cur_rx + 3) & ~3; 1172 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1173 1174 if (m == NULL) 1175 continue; 1176 1177 eh = mtod(m, struct ether_header *); 1178 ifp->if_ipackets++; 1179 1180 /* Remove header from mbuf and pass it on. */ 1181 m_adj(m, sizeof(struct ether_header)); 1182 ether_input(ifp, eh, m); 1183 } 1184 1185 return; 1186} 1187 1188/* 1189 * A frame was downloaded to the chip. It's safe for us to clean up 1190 * the list buffers. 1191 */ 1192static void rl_txeof(sc) 1193 struct rl_softc *sc; 1194{ 1195 struct ifnet *ifp; 1196 u_int32_t txstat; 1197 1198 ifp = &sc->arpcom.ac_if; 1199 1200 /* Clear the timeout timer. */ 1201 ifp->if_timer = 0; 1202 1203 /* 1204 * Go through our tx list and free mbufs for those 1205 * frames that have been uploaded. 1206 */ 1207 do { 1208 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1209 if (!(txstat & (RL_TXSTAT_TX_OK| 1210 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1211 break; 1212 1213 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1214 1215 if (RL_LAST_TXMBUF(sc) != NULL) { 1216 m_freem(RL_LAST_TXMBUF(sc)); 1217 RL_LAST_TXMBUF(sc) = NULL; 1218 } 1219 if (txstat & RL_TXSTAT_TX_OK) 1220 ifp->if_opackets++; 1221 else { 1222 int oldthresh; 1223 ifp->if_oerrors++; 1224 if ((txstat & RL_TXSTAT_TXABRT) || 1225 (txstat & RL_TXSTAT_OUTOFWIN)) 1226 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1227 oldthresh = sc->rl_txthresh; 1228 /* error recovery */ 1229 rl_reset(sc); 1230 rl_init(sc); 1231 /* 1232 * If there was a transmit underrun, 1233 * bump the TX threshold. 1234 */ 1235 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1236 sc->rl_txthresh = oldthresh + 32; 1237 return; 1238 } 1239 RL_INC(sc->rl_cdata.last_tx); 1240 ifp->if_flags &= ~IFF_OACTIVE; 1241 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1242 1243 return; 1244} 1245 1246static void rl_tick(xsc) 1247 void *xsc; 1248{ 1249 struct rl_softc *sc; 1250 struct mii_data *mii; 1251 1252 sc = xsc; 1253 RL_LOCK(sc); 1254 mii = device_get_softc(sc->rl_miibus); 1255 1256 mii_tick(mii); 1257 1258 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1259 RL_UNLOCK(sc); 1260 1261 return; 1262} 1263 1264static void rl_intr(arg) 1265 void *arg; 1266{ 1267 struct rl_softc *sc; 1268 struct ifnet *ifp; 1269 u_int16_t status; 1270 1271 sc = arg; 1272 RL_LOCK(sc); 1273 ifp = &sc->arpcom.ac_if; 1274 1275 /* Disable interrupts. */ 1276 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1277 1278 for (;;) { 1279 1280 status = CSR_READ_2(sc, RL_ISR); 1281 if (status) 1282 CSR_WRITE_2(sc, RL_ISR, status); 1283 1284 if ((status & RL_INTRS) == 0) 1285 break; 1286 1287 if (status & RL_ISR_RX_OK) 1288 rl_rxeof(sc); 1289 1290 if (status & RL_ISR_RX_ERR) 1291 rl_rxeof(sc); 1292 1293 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1294 rl_txeof(sc); 1295 1296 if (status & RL_ISR_SYSTEM_ERR) { 1297 rl_reset(sc); 1298 rl_init(sc); 1299 } 1300 1301 } 1302 1303 /* Re-enable interrupts. */ 1304 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1305 1306 if (ifp->if_snd.ifq_head != NULL) 1307 rl_start(ifp); 1308 1309 RL_UNLOCK(sc); 1310 1311 return; 1312} 1313 1314/* 1315 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1316 * pointers to the fragment pointers. 1317 */ 1318static int rl_encap(sc, m_head) 1319 struct rl_softc *sc; 1320 struct mbuf *m_head; 1321{ 1322 struct mbuf *m_new = NULL; 1323 1324 /* 1325 * The RealTek is brain damaged and wants longword-aligned 1326 * TX buffers, plus we can only have one fragment buffer 1327 * per packet. We have to copy pretty much all the time. 1328 */ 1329 1330 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1331 if (m_new == NULL) { 1332 printf("rl%d: no memory for tx list", sc->rl_unit); 1333 return(1); 1334 } 1335 if (m_head->m_pkthdr.len > MHLEN) { 1336 MCLGET(m_new, M_DONTWAIT); 1337 if (!(m_new->m_flags & M_EXT)) { 1338 m_freem(m_new); 1339 printf("rl%d: no memory for tx list", 1340 sc->rl_unit); 1341 return(1); 1342 } 1343 } 1344 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1345 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1346 m_freem(m_head); 1347 m_head = m_new; 1348 1349 /* Pad frames to at least 60 bytes. */ 1350 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1351 /* 1352 * Make security concious people happy: zero out the 1353 * bytes in the pad area, since we don't know what 1354 * this mbuf cluster buffer's previous user might 1355 * have left in it. 1356 */ 1357 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1358 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1359 m_head->m_pkthdr.len += 1360 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1361 m_head->m_len = m_head->m_pkthdr.len; 1362 } 1363 1364 RL_CUR_TXMBUF(sc) = m_head; 1365 1366 return(0); 1367} 1368 1369/* 1370 * Main transmit routine. 1371 */ 1372 1373static void rl_start(ifp) 1374 struct ifnet *ifp; 1375{ 1376 struct rl_softc *sc; 1377 struct mbuf *m_head = NULL; 1378 1379 sc = ifp->if_softc; 1380 RL_LOCK(sc); 1381 1382 while(RL_CUR_TXMBUF(sc) == NULL) { 1383 IF_DEQUEUE(&ifp->if_snd, m_head); 1384 if (m_head == NULL) 1385 break; 1386 1387 if (rl_encap(sc, m_head)) { 1388 IF_PREPEND(&ifp->if_snd, m_head); 1389 ifp->if_flags |= IFF_OACTIVE; 1390 break; 1391 } 1392 1393 /* 1394 * If there's a BPF listener, bounce a copy of this frame 1395 * to him. 1396 */ 1397 if (ifp->if_bpf) 1398 bpf_mtap(ifp, RL_CUR_TXMBUF(sc)); 1399 1400 /* 1401 * Transmit the frame. 1402 */ 1403 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), 1404 vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t))); 1405 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1406 RL_TXTHRESH(sc->rl_txthresh) | 1407 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1408 1409 RL_INC(sc->rl_cdata.cur_tx); 1410 } 1411 1412 /* 1413 * We broke out of the loop because all our TX slots are 1414 * full. Mark the NIC as busy until it drains some of the 1415 * packets from the queue. 1416 */ 1417 if (RL_CUR_TXMBUF(sc) != NULL) 1418 ifp->if_flags |= IFF_OACTIVE; 1419 1420 /* 1421 * Set a timeout in case the chip goes out to lunch. 1422 */ 1423 ifp->if_timer = 5; 1424 RL_UNLOCK(sc); 1425 1426 return; 1427} 1428 1429static void rl_init(xsc) 1430 void *xsc; 1431{ 1432 struct rl_softc *sc = xsc; 1433 struct ifnet *ifp = &sc->arpcom.ac_if; 1434 struct mii_data *mii; 1435 int i; 1436 u_int32_t rxcfg = 0; 1437 1438 RL_LOCK(sc); 1439 mii = device_get_softc(sc->rl_miibus); 1440 1441 /* 1442 * Cancel pending I/O and free all RX/TX buffers. 1443 */ 1444 rl_stop(sc); 1445 1446 /* Init our MAC address */ 1447 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1448 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 1449 } 1450 1451 /* Init the RX buffer pointer register. */ 1452 CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf)); 1453 1454 /* Init TX descriptors. */ 1455 rl_list_tx_init(sc); 1456 1457 /* 1458 * Enable transmit and receive. 1459 */ 1460 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1461 1462 /* 1463 * Set the initial TX and RX configuration. 1464 */ 1465 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1466 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1467 1468 /* Set the individual bit to receive frames for this host only. */ 1469 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1470 rxcfg |= RL_RXCFG_RX_INDIV; 1471 1472 /* If we want promiscuous mode, set the allframes bit. */ 1473 if (ifp->if_flags & IFF_PROMISC) { 1474 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1475 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1476 } else { 1477 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1478 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1479 } 1480 1481 /* 1482 * Set capture broadcast bit to capture broadcast frames. 1483 */ 1484 if (ifp->if_flags & IFF_BROADCAST) { 1485 rxcfg |= RL_RXCFG_RX_BROAD; 1486 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1487 } else { 1488 rxcfg &= ~RL_RXCFG_RX_BROAD; 1489 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1490 } 1491 1492 /* 1493 * Program the multicast filter, if necessary. 1494 */ 1495 rl_setmulti(sc); 1496 1497 /* 1498 * Enable interrupts. 1499 */ 1500 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1501 1502 /* Set initial TX threshold */ 1503 sc->rl_txthresh = RL_TX_THRESH_INIT; 1504 1505 /* Start RX/TX process. */ 1506 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1507 1508 /* Enable receiver and transmitter. */ 1509 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1510 1511 mii_mediachg(mii); 1512 1513 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1514 1515 ifp->if_flags |= IFF_RUNNING; 1516 ifp->if_flags &= ~IFF_OACTIVE; 1517 1518 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1519 RL_UNLOCK(sc); 1520 1521 return; 1522} 1523 1524/* 1525 * Set media options. 1526 */ 1527static int rl_ifmedia_upd(ifp) 1528 struct ifnet *ifp; 1529{ 1530 struct rl_softc *sc; 1531 struct mii_data *mii; 1532 1533 sc = ifp->if_softc; 1534 mii = device_get_softc(sc->rl_miibus); 1535 mii_mediachg(mii); 1536 1537 return(0); 1538} 1539 1540/* 1541 * Report current media status. 1542 */ 1543static void rl_ifmedia_sts(ifp, ifmr) 1544 struct ifnet *ifp; 1545 struct ifmediareq *ifmr; 1546{ 1547 struct rl_softc *sc; 1548 struct mii_data *mii; 1549 1550 sc = ifp->if_softc; 1551 mii = device_get_softc(sc->rl_miibus); 1552 1553 mii_pollstat(mii); 1554 ifmr->ifm_active = mii->mii_media_active; 1555 ifmr->ifm_status = mii->mii_media_status; 1556 1557 return; 1558} 1559 1560static int rl_ioctl(ifp, command, data) 1561 struct ifnet *ifp; 1562 u_long command; 1563 caddr_t data; 1564{ 1565 struct rl_softc *sc = ifp->if_softc; 1566 struct ifreq *ifr = (struct ifreq *) data; 1567 struct mii_data *mii; 1568 int error = 0; 1569 1570 RL_LOCK(sc); 1571 1572 switch(command) { 1573 case SIOCSIFADDR: 1574 case SIOCGIFADDR: 1575 case SIOCSIFMTU: 1576 error = ether_ioctl(ifp, command, data); 1577 break; 1578 case SIOCSIFFLAGS: 1579 if (ifp->if_flags & IFF_UP) { 1580 rl_init(sc); 1581 } else { 1582 if (ifp->if_flags & IFF_RUNNING) 1583 rl_stop(sc); 1584 } 1585 error = 0; 1586 break; 1587 case SIOCADDMULTI: 1588 case SIOCDELMULTI: 1589 rl_setmulti(sc); 1590 error = 0; 1591 break; 1592 case SIOCGIFMEDIA: 1593 case SIOCSIFMEDIA: 1594 mii = device_get_softc(sc->rl_miibus); 1595 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1596 break; 1597 default: 1598 error = EINVAL; 1599 break; 1600 } 1601 1602 RL_UNLOCK(sc); 1603 1604 return(error); 1605} 1606 1607static void rl_watchdog(ifp) 1608 struct ifnet *ifp; 1609{ 1610 struct rl_softc *sc; 1611 1612 sc = ifp->if_softc; 1613 RL_LOCK(sc); 1614 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1615 ifp->if_oerrors++; 1616 1617 rl_txeof(sc); 1618 rl_rxeof(sc); 1619 rl_init(sc); 1620 RL_UNLOCK(sc); 1621 1622 return; 1623} 1624 1625/* 1626 * Stop the adapter and free any mbufs allocated to the 1627 * RX and TX lists. 1628 */ 1629static void rl_stop(sc) 1630 struct rl_softc *sc; 1631{ 1632 register int i; 1633 struct ifnet *ifp; 1634 1635 RL_LOCK(sc); 1636 ifp = &sc->arpcom.ac_if; 1637 ifp->if_timer = 0; 1638 1639 untimeout(rl_tick, sc, sc->rl_stat_ch); 1640 1641 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1642 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1643 1644 /* 1645 * Free the TX list buffers. 1646 */ 1647 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1648 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1649 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1650 sc->rl_cdata.rl_tx_chain[i] = NULL; 1651 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1652 } 1653 } 1654 1655 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1656 RL_UNLOCK(sc); 1657 return; 1658} 1659 1660/* 1661 * Stop all chip I/O so that the kernel's probe routines don't 1662 * get confused by errant DMAs when rebooting. 1663 */ 1664static void rl_shutdown(dev) 1665 device_t dev; 1666{ 1667 struct rl_softc *sc; 1668 1669 sc = device_get_softc(dev); 1670 1671 rl_stop(sc); 1672 1673 return; 1674} 1675