if_rl.c revision 51533
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_rl.c 51533 1999-09-22 06:08:11Z wpaul $ 33 */ 34 35/* 36 * RealTek 8129/8139 PCI NIC driver 37 * 38 * Supports several extremely cheap PCI 10/100 adapters based on 39 * the RealTek chipset. Datasheets can be obtained from 40 * www.realtek.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86#include "bpf.h" 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/socket.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> 98#include <net/ethernet.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101 102#if NBPF > 0 103#include <net/bpf.h> 104#endif 105 106#include <vm/vm.h> /* for vtophys */ 107#include <vm/pmap.h> /* for vtophys */ 108#include <machine/clock.h> /* for DELAY */ 109#include <machine/bus_pio.h> 110#include <machine/bus_memio.h> 111#include <machine/bus.h> 112#include <machine/resource.h> 113#include <sys/bus.h> 114#include <sys/rman.h> 115 116#include <dev/mii/mii.h> 117#include <dev/mii/miivar.h> 118 119#include <pci/pcireg.h> 120#include <pci/pcivar.h> 121 122/* "controller miibus0" required. See GENERIC if you get errors here. */ 123#include "miibus_if.h" 124 125/* 126 * Default to using PIO access for this driver. On SMP systems, 127 * there appear to be problems with memory mapped mode: it looks like 128 * doing too many memory mapped access back to back in rapid succession 129 * can hang the bus. I'm inclined to blame this on crummy design/construction 130 * on the part of RealTek. Memory mapped mode does appear to work on 131 * uniprocessor systems though. 132 */ 133#define RL_USEIOSPACE 134 135#include <pci/if_rlreg.h> 136 137#ifndef lint 138static const char rcsid[] = 139 "$FreeBSD: head/sys/pci/if_rl.c 51533 1999-09-22 06:08:11Z wpaul $"; 140#endif 141 142/* 143 * Various supported device vendors/types and their names. 144 */ 145static struct rl_type rl_devs[] = { 146 { RT_VENDORID, RT_DEVICEID_8129, 147 "RealTek 8129 10/100BaseTX" }, 148 { RT_VENDORID, RT_DEVICEID_8139, 149 "RealTek 8139 10/100BaseTX" }, 150 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 151 "Accton MPX 5030/5038 10/100BaseTX" }, 152 { DELTA_VENDORID, DELTA_DEVICEID_8139, 153 "Delta Electronics 8139 10/100BaseTX" }, 154 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 155 "Addtron Technolgy 8139 10/100BaseTX" }, 156 { 0, 0, NULL } 157}; 158 159static int rl_probe __P((device_t)); 160static int rl_attach __P((device_t)); 161static int rl_detach __P((device_t)); 162 163static int rl_encap __P((struct rl_softc *, struct mbuf * )); 164 165static void rl_rxeof __P((struct rl_softc *)); 166static void rl_txeof __P((struct rl_softc *)); 167static void rl_intr __P((void *)); 168static void rl_tick __P((void *)); 169static void rl_start __P((struct ifnet *)); 170static int rl_ioctl __P((struct ifnet *, u_long, caddr_t)); 171static void rl_init __P((void *)); 172static void rl_stop __P((struct rl_softc *)); 173static void rl_watchdog __P((struct ifnet *)); 174static void rl_shutdown __P((device_t)); 175static int rl_ifmedia_upd __P((struct ifnet *)); 176static void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 177 178static void rl_eeprom_putbyte __P((struct rl_softc *, int)); 179static void rl_eeprom_getword __P((struct rl_softc *, int, u_int16_t *)); 180static void rl_read_eeprom __P((struct rl_softc *, caddr_t, 181 int, int, int)); 182static void rl_mii_sync __P((struct rl_softc *)); 183static void rl_mii_send __P((struct rl_softc *, u_int32_t, int)); 184static int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *)); 185static int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *)); 186 187static int rl_miibus_readreg __P((device_t, int, int)); 188static int rl_miibus_writereg __P((device_t, int, int, int)); 189static void rl_miibus_statchg __P((device_t)); 190 191static u_int8_t rl_calchash __P((caddr_t)); 192static void rl_setmulti __P((struct rl_softc *)); 193static void rl_reset __P((struct rl_softc *)); 194static int rl_list_tx_init __P((struct rl_softc *)); 195 196#ifdef RL_USEIOSPACE 197#define RL_RES SYS_RES_IOPORT 198#define RL_RID RL_PCI_LOIO 199#else 200#define RL_RES SYS_RES_MEMORY 201#define RL_RID RL_PCI_LOMEM 202#endif 203 204static device_method_t rl_methods[] = { 205 /* Device interface */ 206 DEVMETHOD(device_probe, rl_probe), 207 DEVMETHOD(device_attach, rl_attach), 208 DEVMETHOD(device_detach, rl_detach), 209 DEVMETHOD(device_shutdown, rl_shutdown), 210 211 /* bus interface */ 212 DEVMETHOD(bus_print_child, bus_generic_print_child), 213 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 214 215 /* MII interface */ 216 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 217 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 218 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 219 220 { 0, 0 } 221}; 222 223static driver_t rl_driver = { 224 "rl", 225 rl_methods, 226 sizeof(struct rl_softc) 227}; 228 229static devclass_t rl_devclass; 230 231DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 232DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 233 234#define EE_SET(x) \ 235 CSR_WRITE_1(sc, RL_EECMD, \ 236 CSR_READ_1(sc, RL_EECMD) | x) 237 238#define EE_CLR(x) \ 239 CSR_WRITE_1(sc, RL_EECMD, \ 240 CSR_READ_1(sc, RL_EECMD) & ~x) 241 242/* 243 * Send a read command and address to the EEPROM, check for ACK. 244 */ 245static void rl_eeprom_putbyte(sc, addr) 246 struct rl_softc *sc; 247 int addr; 248{ 249 register int d, i; 250 251 d = addr | RL_EECMD_READ; 252 253 /* 254 * Feed in each bit and stobe the clock. 255 */ 256 for (i = 0x400; i; i >>= 1) { 257 if (d & i) { 258 EE_SET(RL_EE_DATAIN); 259 } else { 260 EE_CLR(RL_EE_DATAIN); 261 } 262 DELAY(100); 263 EE_SET(RL_EE_CLK); 264 DELAY(150); 265 EE_CLR(RL_EE_CLK); 266 DELAY(100); 267 } 268 269 return; 270} 271 272/* 273 * Read a word of data stored in the EEPROM at address 'addr.' 274 */ 275static void rl_eeprom_getword(sc, addr, dest) 276 struct rl_softc *sc; 277 int addr; 278 u_int16_t *dest; 279{ 280 register int i; 281 u_int16_t word = 0; 282 283 /* Enter EEPROM access mode. */ 284 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 285 286 /* 287 * Send address of word we want to read. 288 */ 289 rl_eeprom_putbyte(sc, addr); 290 291 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 292 293 /* 294 * Start reading bits from EEPROM. 295 */ 296 for (i = 0x8000; i; i >>= 1) { 297 EE_SET(RL_EE_CLK); 298 DELAY(100); 299 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 300 word |= i; 301 EE_CLR(RL_EE_CLK); 302 DELAY(100); 303 } 304 305 /* Turn off EEPROM access mode. */ 306 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 307 308 *dest = word; 309 310 return; 311} 312 313/* 314 * Read a sequence of words from the EEPROM. 315 */ 316static void rl_read_eeprom(sc, dest, off, cnt, swap) 317 struct rl_softc *sc; 318 caddr_t dest; 319 int off; 320 int cnt; 321 int swap; 322{ 323 int i; 324 u_int16_t word = 0, *ptr; 325 326 for (i = 0; i < cnt; i++) { 327 rl_eeprom_getword(sc, off + i, &word); 328 ptr = (u_int16_t *)(dest + (i * 2)); 329 if (swap) 330 *ptr = ntohs(word); 331 else 332 *ptr = word; 333 } 334 335 return; 336} 337 338 339/* 340 * MII access routines are provided for the 8129, which 341 * doesn't have a built-in PHY. For the 8139, we fake things 342 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 343 * direct access PHY registers. 344 */ 345#define MII_SET(x) \ 346 CSR_WRITE_1(sc, RL_MII, \ 347 CSR_READ_1(sc, RL_MII) | x) 348 349#define MII_CLR(x) \ 350 CSR_WRITE_1(sc, RL_MII, \ 351 CSR_READ_1(sc, RL_MII) & ~x) 352 353/* 354 * Sync the PHYs by setting data bit and strobing the clock 32 times. 355 */ 356static void rl_mii_sync(sc) 357 struct rl_softc *sc; 358{ 359 register int i; 360 361 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 362 363 for (i = 0; i < 32; i++) { 364 MII_SET(RL_MII_CLK); 365 DELAY(1); 366 MII_CLR(RL_MII_CLK); 367 DELAY(1); 368 } 369 370 return; 371} 372 373/* 374 * Clock a series of bits through the MII. 375 */ 376static void rl_mii_send(sc, bits, cnt) 377 struct rl_softc *sc; 378 u_int32_t bits; 379 int cnt; 380{ 381 int i; 382 383 MII_CLR(RL_MII_CLK); 384 385 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 386 if (bits & i) { 387 MII_SET(RL_MII_DATAOUT); 388 } else { 389 MII_CLR(RL_MII_DATAOUT); 390 } 391 DELAY(1); 392 MII_CLR(RL_MII_CLK); 393 DELAY(1); 394 MII_SET(RL_MII_CLK); 395 } 396} 397 398/* 399 * Read an PHY register through the MII. 400 */ 401static int rl_mii_readreg(sc, frame) 402 struct rl_softc *sc; 403 struct rl_mii_frame *frame; 404 405{ 406 int i, ack, s; 407 408 s = splimp(); 409 410 /* 411 * Set up frame for RX. 412 */ 413 frame->mii_stdelim = RL_MII_STARTDELIM; 414 frame->mii_opcode = RL_MII_READOP; 415 frame->mii_turnaround = 0; 416 frame->mii_data = 0; 417 418 CSR_WRITE_2(sc, RL_MII, 0); 419 420 /* 421 * Turn on data xmit. 422 */ 423 MII_SET(RL_MII_DIR); 424 425 rl_mii_sync(sc); 426 427 /* 428 * Send command/address info. 429 */ 430 rl_mii_send(sc, frame->mii_stdelim, 2); 431 rl_mii_send(sc, frame->mii_opcode, 2); 432 rl_mii_send(sc, frame->mii_phyaddr, 5); 433 rl_mii_send(sc, frame->mii_regaddr, 5); 434 435 /* Idle bit */ 436 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 437 DELAY(1); 438 MII_SET(RL_MII_CLK); 439 DELAY(1); 440 441 /* Turn off xmit. */ 442 MII_CLR(RL_MII_DIR); 443 444 /* Check for ack */ 445 MII_CLR(RL_MII_CLK); 446 DELAY(1); 447 MII_SET(RL_MII_CLK); 448 DELAY(1); 449 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 450 451 /* 452 * Now try reading data bits. If the ack failed, we still 453 * need to clock through 16 cycles to keep the PHY(s) in sync. 454 */ 455 if (ack) { 456 for(i = 0; i < 16; i++) { 457 MII_CLR(RL_MII_CLK); 458 DELAY(1); 459 MII_SET(RL_MII_CLK); 460 DELAY(1); 461 } 462 goto fail; 463 } 464 465 for (i = 0x8000; i; i >>= 1) { 466 MII_CLR(RL_MII_CLK); 467 DELAY(1); 468 if (!ack) { 469 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 470 frame->mii_data |= i; 471 DELAY(1); 472 } 473 MII_SET(RL_MII_CLK); 474 DELAY(1); 475 } 476 477fail: 478 479 MII_CLR(RL_MII_CLK); 480 DELAY(1); 481 MII_SET(RL_MII_CLK); 482 DELAY(1); 483 484 splx(s); 485 486 if (ack) 487 return(1); 488 return(0); 489} 490 491/* 492 * Write to a PHY register through the MII. 493 */ 494static int rl_mii_writereg(sc, frame) 495 struct rl_softc *sc; 496 struct rl_mii_frame *frame; 497 498{ 499 int s; 500 501 s = splimp(); 502 /* 503 * Set up frame for TX. 504 */ 505 506 frame->mii_stdelim = RL_MII_STARTDELIM; 507 frame->mii_opcode = RL_MII_WRITEOP; 508 frame->mii_turnaround = RL_MII_TURNAROUND; 509 510 /* 511 * Turn on data output. 512 */ 513 MII_SET(RL_MII_DIR); 514 515 rl_mii_sync(sc); 516 517 rl_mii_send(sc, frame->mii_stdelim, 2); 518 rl_mii_send(sc, frame->mii_opcode, 2); 519 rl_mii_send(sc, frame->mii_phyaddr, 5); 520 rl_mii_send(sc, frame->mii_regaddr, 5); 521 rl_mii_send(sc, frame->mii_turnaround, 2); 522 rl_mii_send(sc, frame->mii_data, 16); 523 524 /* Idle bit. */ 525 MII_SET(RL_MII_CLK); 526 DELAY(1); 527 MII_CLR(RL_MII_CLK); 528 DELAY(1); 529 530 /* 531 * Turn off xmit. 532 */ 533 MII_CLR(RL_MII_DIR); 534 535 splx(s); 536 537 return(0); 538} 539 540static int rl_miibus_readreg(dev, phy, reg) 541 device_t dev; 542 int phy, reg; 543{ 544 struct rl_softc *sc; 545 struct rl_mii_frame frame; 546 u_int16_t rval = 0; 547 u_int16_t rl8139_reg = 0; 548 549 sc = device_get_softc(dev); 550 551 if (sc->rl_type == RL_8139) { 552 /* Pretend the internal PHY is only at address 0 */ 553 if (phy) 554 return(0); 555 switch(reg) { 556 case MII_BMCR: 557 rl8139_reg = RL_BMCR; 558 break; 559 case MII_BMSR: 560 rl8139_reg = RL_BMSR; 561 break; 562 case MII_ANAR: 563 rl8139_reg = RL_ANAR; 564 break; 565 case MII_ANER: 566 rl8139_reg = RL_ANER; 567 break; 568 case MII_ANLPAR: 569 rl8139_reg = RL_LPAR; 570 break; 571 case MII_PHYIDR1: 572 case MII_PHYIDR2: 573 return(0); 574 break; 575 default: 576 printf("rl%d: bad phy register\n", sc->rl_unit); 577 return(0); 578 } 579 rval = CSR_READ_2(sc, rl8139_reg); 580 return(rval); 581 } 582 583 bzero((char *)&frame, sizeof(frame)); 584 585 frame.mii_phyaddr = phy; 586 frame.mii_regaddr = reg; 587 rl_mii_readreg(sc, &frame); 588 589 return(frame.mii_data); 590} 591 592static int rl_miibus_writereg(dev, phy, reg, data) 593 device_t dev; 594 int phy, reg, data; 595{ 596 struct rl_softc *sc; 597 struct rl_mii_frame frame; 598 u_int16_t rl8139_reg = 0; 599 600 sc = device_get_softc(dev); 601 602 if (sc->rl_type == RL_8139) { 603 /* Pretend the internal PHY is only at address 0 */ 604 if (phy) 605 return(0); 606 switch(reg) { 607 case MII_BMCR: 608 rl8139_reg = RL_BMCR; 609 break; 610 case MII_BMSR: 611 rl8139_reg = RL_BMSR; 612 break; 613 case MII_ANAR: 614 rl8139_reg = RL_ANAR; 615 break; 616 case MII_ANER: 617 rl8139_reg = RL_ANER; 618 break; 619 case MII_ANLPAR: 620 rl8139_reg = RL_LPAR; 621 break; 622 case MII_PHYIDR1: 623 case MII_PHYIDR2: 624 return(0); 625 break; 626 default: 627 printf("rl%d: bad phy register\n", sc->rl_unit); 628 return(0); 629 } 630 CSR_WRITE_2(sc, rl8139_reg, data); 631 return(0); 632 } 633 634 bzero((char *)&frame, sizeof(frame)); 635 636 frame.mii_phyaddr = phy; 637 frame.mii_regaddr = reg; 638 frame.mii_data = data; 639 640 rl_mii_writereg(sc, &frame); 641 642 return(0); 643} 644 645static void rl_miibus_statchg(dev) 646 device_t dev; 647{ 648 return; 649} 650 651/* 652 * Calculate CRC of a multicast group address, return the upper 6 bits. 653 */ 654static u_int8_t rl_calchash(addr) 655 caddr_t addr; 656{ 657 u_int32_t crc, carry; 658 int i, j; 659 u_int8_t c; 660 661 /* Compute CRC for the address value. */ 662 crc = 0xFFFFFFFF; /* initial value */ 663 664 for (i = 0; i < 6; i++) { 665 c = *(addr + i); 666 for (j = 0; j < 8; j++) { 667 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 668 crc <<= 1; 669 c >>= 1; 670 if (carry) 671 crc = (crc ^ 0x04c11db6) | carry; 672 } 673 } 674 675 /* return the filter bit position */ 676 return(crc >> 26); 677} 678 679/* 680 * Program the 64-bit multicast hash filter. 681 */ 682static void rl_setmulti(sc) 683 struct rl_softc *sc; 684{ 685 struct ifnet *ifp; 686 int h = 0; 687 u_int32_t hashes[2] = { 0, 0 }; 688 struct ifmultiaddr *ifma; 689 u_int32_t rxfilt; 690 int mcnt = 0; 691 692 ifp = &sc->arpcom.ac_if; 693 694 rxfilt = CSR_READ_4(sc, RL_RXCFG); 695 696 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 697 rxfilt |= RL_RXCFG_RX_MULTI; 698 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 699 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 700 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 701 return; 702 } 703 704 /* first, zot all the existing hash bits */ 705 CSR_WRITE_4(sc, RL_MAR0, 0); 706 CSR_WRITE_4(sc, RL_MAR4, 0); 707 708 /* now program new ones */ 709 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 710 ifma = ifma->ifma_link.le_next) { 711 if (ifma->ifma_addr->sa_family != AF_LINK) 712 continue; 713 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 714 if (h < 32) 715 hashes[0] |= (1 << h); 716 else 717 hashes[1] |= (1 << (h - 32)); 718 mcnt++; 719 } 720 721 if (mcnt) 722 rxfilt |= RL_RXCFG_RX_MULTI; 723 else 724 rxfilt &= ~RL_RXCFG_RX_MULTI; 725 726 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 727 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 728 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 729 730 return; 731} 732 733static void rl_reset(sc) 734 struct rl_softc *sc; 735{ 736 register int i; 737 738 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 739 740 for (i = 0; i < RL_TIMEOUT; i++) { 741 DELAY(10); 742 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 743 break; 744 } 745 if (i == RL_TIMEOUT) 746 printf("rl%d: reset never completed!\n", sc->rl_unit); 747 748 return; 749} 750 751/* 752 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 753 * IDs against our list and return a device name if we find a match. 754 */ 755static int rl_probe(dev) 756 device_t dev; 757{ 758 struct rl_type *t; 759 760 t = rl_devs; 761 762 while(t->rl_name != NULL) { 763 if ((pci_get_vendor(dev) == t->rl_vid) && 764 (pci_get_device(dev) == t->rl_did)) { 765 device_set_desc(dev, t->rl_name); 766 return(0); 767 } 768 t++; 769 } 770 771 return(ENXIO); 772} 773 774/* 775 * Attach the interface. Allocate softc structures, do ifmedia 776 * setup and ethernet/BPF attach. 777 */ 778static int rl_attach(dev) 779 device_t dev; 780{ 781 int s; 782 u_char eaddr[ETHER_ADDR_LEN]; 783 u_int32_t command; 784 struct rl_softc *sc; 785 struct ifnet *ifp; 786 u_int16_t rl_did = 0; 787 int unit, error = 0, rid; 788 789 s = splimp(); 790 791 sc = device_get_softc(dev); 792 unit = device_get_unit(dev); 793 bzero(sc, sizeof(struct rl_softc)); 794 795 /* 796 * Handle power management nonsense. 797 */ 798 799 command = pci_read_config(dev, RL_PCI_CAPID, 4) & 0x000000FF; 800 if (command == 0x01) { 801 802 command = pci_read_config(dev, RL_PCI_PWRMGMTCTRL, 4); 803 if (command & RL_PSTATE_MASK) { 804 u_int32_t iobase, membase, irq; 805 806 /* Save important PCI config data. */ 807 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 808 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 809 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 810 811 /* Reset the power state. */ 812 printf("rl%d: chip is is in D%d power mode " 813 "-- setting to D0\n", unit, command & RL_PSTATE_MASK); 814 command &= 0xFFFFFFFC; 815 pci_write_config(dev, RL_PCI_PWRMGMTCTRL, command, 4); 816 817 /* Restore PCI config data. */ 818 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 819 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 820 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 821 } 822 } 823 824 /* 825 * Map control/status registers. 826 */ 827 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 828 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 829 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 830 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 831 832#ifdef RL_USEIOSPACE 833 if (!(command & PCIM_CMD_PORTEN)) { 834 printf("rl%d: failed to enable I/O ports!\n", unit); 835 error = ENXIO; 836 goto fail; 837 } 838#else 839 if (!(command & PCIM_CMD_MEMEN)) { 840 printf("rl%d: failed to enable memory mapping!\n", unit); 841 error = ENXIO; 842 goto fail; 843 } 844#endif 845 846 rid = RL_RID; 847 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 848 0, ~0, 1, RF_ACTIVE); 849 850 if (sc->rl_res == NULL) { 851 printf ("rl%d: couldn't map ports/memory\n", unit); 852 error = ENXIO; 853 goto fail; 854 } 855 856 sc->rl_btag = rman_get_bustag(sc->rl_res); 857 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 858 859 rid = 0; 860 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 861 RF_SHAREABLE | RF_ACTIVE); 862 863 if (sc->rl_irq == NULL) { 864 printf("rl%d: couldn't map interrupt\n", unit); 865 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 866 error = ENXIO; 867 goto fail; 868 } 869 870 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 871 rl_intr, sc, &sc->rl_intrhand); 872 873 if (error) { 874 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res); 875 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 876 printf("rl%d: couldn't set up irq\n", unit); 877 goto fail; 878 } 879 880 callout_handle_init(&sc->rl_stat_ch); 881 882 /* Reset the adapter. */ 883 rl_reset(sc); 884 885 /* 886 * Get station address from the EEPROM. 887 */ 888 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 889 890 /* 891 * A RealTek chip was detected. Inform the world. 892 */ 893 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 894 895 sc->rl_unit = unit; 896 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 897 898 /* 899 * Now read the exact device type from the EEPROM to find 900 * out if it's an 8129 or 8139. 901 */ 902 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 903 904 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 905 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139) 906 sc->rl_type = RL_8139; 907 else if (rl_did == RT_DEVICEID_8129) 908 sc->rl_type = RL_8129; 909 else { 910 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 911 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 912 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res); 913 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 914 error = ENXIO; 915 goto fail; 916 } 917 918 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 32, M_DEVBUF, 919 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 920 921 if (sc->rl_cdata.rl_rx_buf == NULL) { 922 printf("rl%d: no memory for list buffers!\n", unit); 923 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 924 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res); 925 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 926 error = ENXIO; 927 goto fail; 928 } 929 930 /* Leave a few bytes before the start of the RX ring buffer. */ 931 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 932 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 933 934 /* Do MII setup */ 935 if (mii_phy_probe(dev, &sc->rl_miibus, 936 rl_ifmedia_upd, rl_ifmedia_sts)) { 937 printf("rl%d: MII without any phy!\n", sc->rl_unit); 938 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 939 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res); 940 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 941 free(sc->rl_cdata.rl_rx_buf, M_DEVBUF); 942 error = ENXIO; 943 goto fail; 944 } 945 946 ifp = &sc->arpcom.ac_if; 947 ifp->if_softc = sc; 948 ifp->if_unit = unit; 949 ifp->if_name = "rl"; 950 ifp->if_mtu = ETHERMTU; 951 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 952 ifp->if_ioctl = rl_ioctl; 953 ifp->if_output = ether_output; 954 ifp->if_start = rl_start; 955 ifp->if_watchdog = rl_watchdog; 956 ifp->if_init = rl_init; 957 ifp->if_baudrate = 10000000; 958 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 959 960 /* 961 * Call MI attach routines. 962 */ 963 if_attach(ifp); 964 ether_ifattach(ifp); 965 966#if NBPF > 0 967 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 968#endif 969 970fail: 971 splx(s); 972 return(error); 973} 974 975static int rl_detach(dev) 976 device_t dev; 977{ 978 struct rl_softc *sc; 979 struct ifnet *ifp; 980 int s; 981 982 s = splimp(); 983 984 sc = device_get_softc(dev); 985 ifp = &sc->arpcom.ac_if; 986 987 if_detach(ifp); 988 rl_stop(sc); 989 990 bus_generic_detach(dev); 991 device_delete_child(dev, sc->rl_miibus); 992 993 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 994 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res); 995 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 996 997 free(sc->rl_cdata.rl_rx_buf, M_DEVBUF); 998 999 splx(s); 1000 1001 return(0); 1002} 1003 1004/* 1005 * Initialize the transmit descriptors. 1006 */ 1007static int rl_list_tx_init(sc) 1008 struct rl_softc *sc; 1009{ 1010 struct rl_chain_data *cd; 1011 int i; 1012 1013 cd = &sc->rl_cdata; 1014 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1015 cd->rl_tx_chain[i] = NULL; 1016 CSR_WRITE_4(sc, 1017 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1018 } 1019 1020 sc->rl_cdata.cur_tx = 0; 1021 sc->rl_cdata.last_tx = 0; 1022 1023 return(0); 1024} 1025 1026/* 1027 * A frame has been uploaded: pass the resulting mbuf chain up to 1028 * the higher level protocols. 1029 * 1030 * You know there's something wrong with a PCI bus-master chip design 1031 * when you have to use m_devget(). 1032 * 1033 * The receive operation is badly documented in the datasheet, so I'll 1034 * attempt to document it here. The driver provides a buffer area and 1035 * places its base address in the RX buffer start address register. 1036 * The chip then begins copying frames into the RX buffer. Each frame 1037 * is preceeded by a 32-bit RX status word which specifies the length 1038 * of the frame and certain other status bits. Each frame (starting with 1039 * the status word) is also 32-bit aligned. The frame length is in the 1040 * first 16 bits of the status word; the lower 15 bits correspond with 1041 * the 'rx status register' mentioned in the datasheet. 1042 * 1043 * Note: to make the Alpha happy, the frame payload needs to be aligned 1044 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 1045 * the ring buffer starting at an address two bytes before the actual 1046 * data location. We can then shave off the first two bytes using m_adj(). 1047 * The reason we do this is because m_devget() doesn't let us specify an 1048 * offset into the mbuf storage space, so we have to artificially create 1049 * one. The ring is allocated in such a way that there are a few unused 1050 * bytes of space preceecing it so that it will be safe for us to do the 1051 * 2-byte backstep even if reading from the ring at offset 0. 1052 */ 1053static void rl_rxeof(sc) 1054 struct rl_softc *sc; 1055{ 1056 struct ether_header *eh; 1057 struct mbuf *m; 1058 struct ifnet *ifp; 1059 int total_len = 0; 1060 u_int32_t rxstat; 1061 caddr_t rxbufpos; 1062 int wrap = 0; 1063 u_int16_t cur_rx; 1064 u_int16_t limit; 1065 u_int16_t rx_bytes = 0, max_bytes; 1066 1067 ifp = &sc->arpcom.ac_if; 1068 1069 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1070 1071 /* Do not try to read past this point. */ 1072 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1073 1074 if (limit < cur_rx) 1075 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1076 else 1077 max_bytes = limit - cur_rx; 1078 1079 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1080 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1081 rxstat = *(u_int32_t *)rxbufpos; 1082 1083 /* 1084 * Here's a totally undocumented fact for you. When the 1085 * RealTek chip is in the process of copying a packet into 1086 * RAM for you, the length will be 0xfff0. If you spot a 1087 * packet header with this value, you need to stop. The 1088 * datasheet makes absolutely no mention of this and 1089 * RealTek should be shot for this. 1090 */ 1091 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1092 break; 1093 1094 if (!(rxstat & RL_RXSTAT_RXOK)) { 1095 ifp->if_ierrors++; 1096 rl_init(sc); 1097 return; 1098 } 1099 1100 /* No errors; receive the packet. */ 1101 total_len = rxstat >> 16; 1102 rx_bytes += total_len + 4; 1103 1104 /* 1105 * XXX The RealTek chip includes the CRC with every 1106 * received frame, and there's no way to turn this 1107 * behavior off (at least, I can't find anything in 1108 * the manual that explains how to do it) so we have 1109 * to trim off the CRC manually. 1110 */ 1111 total_len -= ETHER_CRC_LEN; 1112 1113 /* 1114 * Avoid trying to read more bytes than we know 1115 * the chip has prepared for us. 1116 */ 1117 if (rx_bytes > max_bytes) 1118 break; 1119 1120 rxbufpos = sc->rl_cdata.rl_rx_buf + 1121 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1122 1123 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1124 rxbufpos = sc->rl_cdata.rl_rx_buf; 1125 1126 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1127 1128 if (total_len > wrap) { 1129 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1130 wrap + RL_ETHER_ALIGN, 0, ifp, NULL); 1131 if (m == NULL) { 1132 ifp->if_ierrors++; 1133 printf("rl%d: out of mbufs, tried to " 1134 "copy %d bytes\n", sc->rl_unit, wrap); 1135 } 1136 else { 1137 m_adj(m, RL_ETHER_ALIGN); 1138 m_copyback(m, wrap, total_len - wrap, 1139 sc->rl_cdata.rl_rx_buf); 1140 } 1141 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1142 } else { 1143 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1144 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1145 if (m == NULL) { 1146 ifp->if_ierrors++; 1147 printf("rl%d: out of mbufs, tried to " 1148 "copy %d bytes\n", sc->rl_unit, total_len); 1149 } else 1150 m_adj(m, RL_ETHER_ALIGN); 1151 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1152 } 1153 1154 /* 1155 * Round up to 32-bit boundary. 1156 */ 1157 cur_rx = (cur_rx + 3) & ~3; 1158 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1159 1160 if (m == NULL) 1161 continue; 1162 1163 eh = mtod(m, struct ether_header *); 1164 ifp->if_ipackets++; 1165 1166#if NBPF > 0 1167 /* 1168 * Handle BPF listeners. Let the BPF user see the packet, but 1169 * don't pass it up to the ether_input() layer unless it's 1170 * a broadcast packet, multicast packet, matches our ethernet 1171 * address or the interface is in promiscuous mode. 1172 */ 1173 if (ifp->if_bpf) { 1174 bpf_mtap(ifp, m); 1175 if (ifp->if_flags & IFF_PROMISC && 1176 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1177 ETHER_ADDR_LEN) && 1178 (eh->ether_dhost[0] & 1) == 0)) { 1179 m_freem(m); 1180 continue; 1181 } 1182 } 1183#endif 1184 /* Remove header from mbuf and pass it on. */ 1185 m_adj(m, sizeof(struct ether_header)); 1186 ether_input(ifp, eh, m); 1187 } 1188 1189 return; 1190} 1191 1192/* 1193 * A frame was downloaded to the chip. It's safe for us to clean up 1194 * the list buffers. 1195 */ 1196static void rl_txeof(sc) 1197 struct rl_softc *sc; 1198{ 1199 struct ifnet *ifp; 1200 u_int32_t txstat; 1201 1202 ifp = &sc->arpcom.ac_if; 1203 1204 /* Clear the timeout timer. */ 1205 ifp->if_timer = 0; 1206 1207 /* 1208 * Go through our tx list and free mbufs for those 1209 * frames that have been uploaded. 1210 */ 1211 do { 1212 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1213 if (!(txstat & (RL_TXSTAT_TX_OK| 1214 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1215 break; 1216 1217 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1218 1219 if (RL_LAST_TXMBUF(sc) != NULL) { 1220 m_freem(RL_LAST_TXMBUF(sc)); 1221 RL_LAST_TXMBUF(sc) = NULL; 1222 } 1223 if (txstat & RL_TXSTAT_TX_OK) 1224 ifp->if_opackets++; 1225 else { 1226 ifp->if_oerrors++; 1227 if ((txstat & RL_TXSTAT_TXABRT) || 1228 (txstat & RL_TXSTAT_OUTOFWIN)) 1229 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1230 } 1231 RL_INC(sc->rl_cdata.last_tx); 1232 ifp->if_flags &= ~IFF_OACTIVE; 1233 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1234 1235 return; 1236} 1237 1238static void rl_tick(xsc) 1239 void *xsc; 1240{ 1241 struct rl_softc *sc; 1242 struct mii_data *mii; 1243 int s; 1244 1245 s = splimp(); 1246 1247 sc = xsc; 1248 mii = device_get_softc(sc->rl_miibus); 1249 1250 mii_tick(mii); 1251 1252 splx(s); 1253 1254 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1255 1256 return; 1257} 1258 1259static void rl_intr(arg) 1260 void *arg; 1261{ 1262 struct rl_softc *sc; 1263 struct ifnet *ifp; 1264 u_int16_t status; 1265 1266 sc = arg; 1267 ifp = &sc->arpcom.ac_if; 1268 1269 /* Disable interrupts. */ 1270 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1271 1272 for (;;) { 1273 1274 status = CSR_READ_2(sc, RL_ISR); 1275 if (status) 1276 CSR_WRITE_2(sc, RL_ISR, status); 1277 1278 if ((status & RL_INTRS) == 0) 1279 break; 1280 1281 if (status & RL_ISR_RX_OK) 1282 rl_rxeof(sc); 1283 1284 if (status & RL_ISR_RX_ERR) 1285 rl_rxeof(sc); 1286 1287 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1288 rl_txeof(sc); 1289 1290 if (status & RL_ISR_SYSTEM_ERR) { 1291 rl_reset(sc); 1292 rl_init(sc); 1293 } 1294 1295 } 1296 1297 /* Re-enable interrupts. */ 1298 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1299 1300 if (ifp->if_snd.ifq_head != NULL) { 1301 rl_start(ifp); 1302 } 1303 1304 return; 1305} 1306 1307/* 1308 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1309 * pointers to the fragment pointers. 1310 */ 1311static int rl_encap(sc, m_head) 1312 struct rl_softc *sc; 1313 struct mbuf *m_head; 1314{ 1315 struct mbuf *m_new = NULL; 1316 1317 /* 1318 * The RealTek is brain damaged and wants longword-aligned 1319 * TX buffers, plus we can only have one fragment buffer 1320 * per packet. We have to copy pretty much all the time. 1321 */ 1322 1323 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1324 if (m_new == NULL) { 1325 printf("rl%d: no memory for tx list", sc->rl_unit); 1326 return(1); 1327 } 1328 if (m_head->m_pkthdr.len > MHLEN) { 1329 MCLGET(m_new, M_DONTWAIT); 1330 if (!(m_new->m_flags & M_EXT)) { 1331 m_freem(m_new); 1332 printf("rl%d: no memory for tx list", 1333 sc->rl_unit); 1334 return(1); 1335 } 1336 } 1337 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1338 mtod(m_new, caddr_t)); 1339 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1340 m_freem(m_head); 1341 m_head = m_new; 1342 1343 /* Pad frames to at least 60 bytes. */ 1344 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1345 m_head->m_pkthdr.len += 1346 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1347 m_head->m_len = m_head->m_pkthdr.len; 1348 } 1349 1350 RL_CUR_TXMBUF(sc) = m_head; 1351 1352 return(0); 1353} 1354 1355/* 1356 * Main transmit routine. 1357 */ 1358 1359static void rl_start(ifp) 1360 struct ifnet *ifp; 1361{ 1362 struct rl_softc *sc; 1363 struct mbuf *m_head = NULL; 1364 1365 sc = ifp->if_softc; 1366 1367 while(RL_CUR_TXMBUF(sc) == NULL) { 1368 IF_DEQUEUE(&ifp->if_snd, m_head); 1369 if (m_head == NULL) 1370 break; 1371 1372 rl_encap(sc, m_head); 1373 1374#if NBPF > 0 1375 /* 1376 * If there's a BPF listener, bounce a copy of this frame 1377 * to him. 1378 */ 1379 if (ifp->if_bpf) 1380 bpf_mtap(ifp, RL_CUR_TXMBUF(sc)); 1381#endif 1382 /* 1383 * Transmit the frame. 1384 */ 1385 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), 1386 vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t))); 1387 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1388 RL_TX_EARLYTHRESH | RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1389 1390 RL_INC(sc->rl_cdata.cur_tx); 1391 } 1392 1393 /* 1394 * We broke out of the loop because all our TX slots are 1395 * full. Mark the NIC as busy until it drains some of the 1396 * packets from the queue. 1397 */ 1398 if (RL_CUR_TXMBUF(sc) != NULL) 1399 ifp->if_flags |= IFF_OACTIVE; 1400 1401 /* 1402 * Set a timeout in case the chip goes out to lunch. 1403 */ 1404 ifp->if_timer = 5; 1405 1406 return; 1407} 1408 1409static void rl_init(xsc) 1410 void *xsc; 1411{ 1412 struct rl_softc *sc = xsc; 1413 struct ifnet *ifp = &sc->arpcom.ac_if; 1414 struct mii_data *mii; 1415 int s, i; 1416 u_int32_t rxcfg = 0; 1417 1418 s = splimp(); 1419 1420 mii = device_get_softc(sc->rl_miibus); 1421 1422 /* 1423 * Cancel pending I/O and free all RX/TX buffers. 1424 */ 1425 rl_stop(sc); 1426 1427 /* Init our MAC address */ 1428 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1429 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 1430 } 1431 1432 /* Init the RX buffer pointer register. */ 1433 CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf)); 1434 1435 /* Init TX descriptors. */ 1436 rl_list_tx_init(sc); 1437 1438 /* 1439 * Enable transmit and receive. 1440 */ 1441 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1442 1443 /* 1444 * Set the initial TX and RX configuration. 1445 */ 1446 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1447 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1448 1449 /* Set the individual bit to receive frames for this host only. */ 1450 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1451 rxcfg |= RL_RXCFG_RX_INDIV; 1452 1453 /* If we want promiscuous mode, set the allframes bit. */ 1454 if (ifp->if_flags & IFF_PROMISC) { 1455 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1456 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1457 } else { 1458 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1459 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1460 } 1461 1462 /* 1463 * Set capture broadcast bit to capture broadcast frames. 1464 */ 1465 if (ifp->if_flags & IFF_BROADCAST) { 1466 rxcfg |= RL_RXCFG_RX_BROAD; 1467 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1468 } else { 1469 rxcfg &= ~RL_RXCFG_RX_BROAD; 1470 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1471 } 1472 1473 /* 1474 * Program the multicast filter, if necessary. 1475 */ 1476 rl_setmulti(sc); 1477 1478 /* 1479 * Enable interrupts. 1480 */ 1481 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1482 1483 /* Start RX/TX process. */ 1484 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1485 1486 /* Enable receiver and transmitter. */ 1487 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1488 1489 mii_mediachg(mii); 1490 1491 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1492 1493 ifp->if_flags |= IFF_RUNNING; 1494 ifp->if_flags &= ~IFF_OACTIVE; 1495 1496 (void)splx(s); 1497 1498 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1499 1500 return; 1501} 1502 1503/* 1504 * Set media options. 1505 */ 1506static int rl_ifmedia_upd(ifp) 1507 struct ifnet *ifp; 1508{ 1509 struct rl_softc *sc; 1510 struct mii_data *mii; 1511 1512 sc = ifp->if_softc; 1513 mii = device_get_softc(sc->rl_miibus); 1514 mii_mediachg(mii); 1515 1516 return(0); 1517} 1518 1519/* 1520 * Report current media status. 1521 */ 1522static void rl_ifmedia_sts(ifp, ifmr) 1523 struct ifnet *ifp; 1524 struct ifmediareq *ifmr; 1525{ 1526 struct rl_softc *sc; 1527 struct mii_data *mii; 1528 1529 sc = ifp->if_softc; 1530 mii = device_get_softc(sc->rl_miibus); 1531 1532 mii_pollstat(mii); 1533 ifmr->ifm_active = mii->mii_media_active; 1534 ifmr->ifm_status = mii->mii_media_status; 1535 1536 return; 1537} 1538 1539static int rl_ioctl(ifp, command, data) 1540 struct ifnet *ifp; 1541 u_long command; 1542 caddr_t data; 1543{ 1544 struct rl_softc *sc = ifp->if_softc; 1545 struct ifreq *ifr = (struct ifreq *) data; 1546 struct mii_data *mii; 1547 int s, error = 0; 1548 1549 s = splimp(); 1550 1551 switch(command) { 1552 case SIOCSIFADDR: 1553 case SIOCGIFADDR: 1554 case SIOCSIFMTU: 1555 error = ether_ioctl(ifp, command, data); 1556 break; 1557 case SIOCSIFFLAGS: 1558 if (ifp->if_flags & IFF_UP) { 1559 rl_init(sc); 1560 } else { 1561 if (ifp->if_flags & IFF_RUNNING) 1562 rl_stop(sc); 1563 } 1564 error = 0; 1565 break; 1566 case SIOCADDMULTI: 1567 case SIOCDELMULTI: 1568 rl_setmulti(sc); 1569 error = 0; 1570 break; 1571 case SIOCGIFMEDIA: 1572 case SIOCSIFMEDIA: 1573 mii = device_get_softc(sc->rl_miibus); 1574 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1575 break; 1576 default: 1577 error = EINVAL; 1578 break; 1579 } 1580 1581 (void)splx(s); 1582 1583 return(error); 1584} 1585 1586static void rl_watchdog(ifp) 1587 struct ifnet *ifp; 1588{ 1589 struct rl_softc *sc; 1590 1591 sc = ifp->if_softc; 1592 1593 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1594 ifp->if_oerrors++; 1595 1596 rl_txeof(sc); 1597 rl_rxeof(sc); 1598 rl_init(sc); 1599 1600 return; 1601} 1602 1603/* 1604 * Stop the adapter and free any mbufs allocated to the 1605 * RX and TX lists. 1606 */ 1607static void rl_stop(sc) 1608 struct rl_softc *sc; 1609{ 1610 register int i; 1611 struct ifnet *ifp; 1612 1613 ifp = &sc->arpcom.ac_if; 1614 ifp->if_timer = 0; 1615 1616 untimeout(rl_tick, sc, sc->rl_stat_ch); 1617 1618 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1619 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1620 1621 /* 1622 * Free the TX list buffers. 1623 */ 1624 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1625 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1626 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1627 sc->rl_cdata.rl_tx_chain[i] = NULL; 1628 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1629 } 1630 } 1631 1632 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1633 1634 return; 1635} 1636 1637/* 1638 * Stop all chip I/O so that the kernel's probe routines don't 1639 * get confused by errant DMAs when rebooting. 1640 */ 1641static void rl_shutdown(dev) 1642 device_t dev; 1643{ 1644 struct rl_softc *sc; 1645 1646 sc = device_get_softc(dev); 1647 1648 rl_stop(sc); 1649 1650 return; 1651} 1652