if_rl.c revision 50135
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $Id: if_rl.c,v 1.21 1999/08/21 06:24:35 msmith Exp $ 33 */ 34 35/* 36 * RealTek 8129/8139 PCI NIC driver 37 * 38 * Supports several extremely cheap PCI 10/100 adapters based on 39 * the RealTek chipset. Datasheets can be obtained from 40 * www.realtek.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86#include "bpf.h" 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/eventhandler.h> 91#include <sys/sockio.h> 92#include <sys/mbuf.h> 93#include <sys/malloc.h> 94#include <sys/kernel.h> 95#include <sys/socket.h> 96 97#include <net/if.h> 98#include <net/if_arp.h> 99#include <net/ethernet.h> 100#include <net/if_dl.h> 101#include <net/if_media.h> 102 103#if NBPF > 0 104#include <net/bpf.h> 105#endif 106 107#include <vm/vm.h> /* for vtophys */ 108#include <vm/pmap.h> /* for vtophys */ 109#include <machine/clock.h> /* for DELAY */ 110#include <machine/bus_pio.h> 111#include <machine/bus_memio.h> 112#include <machine/bus.h> 113 114#include <pci/pcireg.h> 115#include <pci/pcivar.h> 116 117/* 118 * Default to using PIO access for this driver. On SMP systems, 119 * there appear to be problems with memory mapped mode: it looks like 120 * doing too many memory mapped access back to back in rapid succession 121 * can hang the bus. I'm inclined to blame this on crummy design/construction 122 * on the part of RealTek. Memory mapped mode does appear to work on 123 * uniprocessor systems though. 124 */ 125#define RL_USEIOSPACE 126 127#include <pci/if_rlreg.h> 128 129#ifndef lint 130static const char rcsid[] = 131 "$Id: if_rl.c,v 1.21 1999/08/21 06:24:35 msmith Exp $"; 132#endif 133 134/* 135 * Various supported device vendors/types and their names. 136 */ 137static struct rl_type rl_devs[] = { 138 { RT_VENDORID, RT_DEVICEID_8129, 139 "RealTek 8129 10/100BaseTX" }, 140 { RT_VENDORID, RT_DEVICEID_8139, 141 "RealTek 8139 10/100BaseTX" }, 142 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 143 "Accton MPX 5030/5038 10/100BaseTX" }, 144 { DELTA_VENDORID, DELTA_DEVICEID_8139, 145 "Delta Electronics 8139 10/100BaseTX" }, 146 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 147 "Addtron Technolgy 8139 10/100BaseTX" }, 148 { 0, 0, NULL } 149}; 150 151/* 152 * Various supported PHY vendors/types and their names. Note that 153 * this driver will work with pretty much any MII-compliant PHY, 154 * so failure to positively identify the chip is not a fatal error. 155 */ 156 157static struct rl_type rl_phys[] = { 158 { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" }, 159 { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" }, 160 { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"}, 161 { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" }, 162 { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" }, 163 { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" }, 164 { 0, 0, "<MII-compliant physical interface>" } 165}; 166 167static unsigned long rl_count = 0; 168static const char *rl_probe __P((pcici_t, pcidi_t)); 169static void rl_attach __P((pcici_t, int)); 170 171static int rl_encap __P((struct rl_softc *, struct mbuf * )); 172 173static void rl_rxeof __P((struct rl_softc *)); 174static void rl_txeof __P((struct rl_softc *)); 175static void rl_intr __P((void *)); 176static void rl_start __P((struct ifnet *)); 177static int rl_ioctl __P((struct ifnet *, u_long, caddr_t)); 178static void rl_init __P((void *)); 179static void rl_stop __P((struct rl_softc *)); 180static void rl_watchdog __P((struct ifnet *)); 181static void rl_shutdown __P((void *, int)); 182static int rl_ifmedia_upd __P((struct ifnet *)); 183static void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 184 185static void rl_eeprom_putbyte __P((struct rl_softc *, int)); 186static void rl_eeprom_getword __P((struct rl_softc *, int, u_int16_t *)); 187static void rl_read_eeprom __P((struct rl_softc *, caddr_t, 188 int, int, int)); 189static void rl_mii_sync __P((struct rl_softc *)); 190static void rl_mii_send __P((struct rl_softc *, u_int32_t, int)); 191static int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *)); 192static int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *)); 193 194static u_int16_t rl_phy_readreg __P((struct rl_softc *, int)); 195static void rl_phy_writereg __P((struct rl_softc *, int, int)); 196 197static void rl_autoneg_xmit __P((struct rl_softc *)); 198static void rl_autoneg_mii __P((struct rl_softc *, int, int)); 199static void rl_setmode_mii __P((struct rl_softc *, int)); 200static void rl_getmode_mii __P((struct rl_softc *)); 201static u_int8_t rl_calchash __P((caddr_t)); 202static void rl_setmulti __P((struct rl_softc *)); 203static void rl_reset __P((struct rl_softc *)); 204static int rl_list_tx_init __P((struct rl_softc *)); 205 206#define EE_SET(x) \ 207 CSR_WRITE_1(sc, RL_EECMD, \ 208 CSR_READ_1(sc, RL_EECMD) | x) 209 210#define EE_CLR(x) \ 211 CSR_WRITE_1(sc, RL_EECMD, \ 212 CSR_READ_1(sc, RL_EECMD) & ~x) 213 214/* 215 * Send a read command and address to the EEPROM, check for ACK. 216 */ 217static void rl_eeprom_putbyte(sc, addr) 218 struct rl_softc *sc; 219 int addr; 220{ 221 register int d, i; 222 223 d = addr | RL_EECMD_READ; 224 225 /* 226 * Feed in each bit and stobe the clock. 227 */ 228 for (i = 0x400; i; i >>= 1) { 229 if (d & i) { 230 EE_SET(RL_EE_DATAIN); 231 } else { 232 EE_CLR(RL_EE_DATAIN); 233 } 234 DELAY(100); 235 EE_SET(RL_EE_CLK); 236 DELAY(150); 237 EE_CLR(RL_EE_CLK); 238 DELAY(100); 239 } 240 241 return; 242} 243 244/* 245 * Read a word of data stored in the EEPROM at address 'addr.' 246 */ 247static void rl_eeprom_getword(sc, addr, dest) 248 struct rl_softc *sc; 249 int addr; 250 u_int16_t *dest; 251{ 252 register int i; 253 u_int16_t word = 0; 254 255 /* Enter EEPROM access mode. */ 256 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 257 258 /* 259 * Send address of word we want to read. 260 */ 261 rl_eeprom_putbyte(sc, addr); 262 263 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 264 265 /* 266 * Start reading bits from EEPROM. 267 */ 268 for (i = 0x8000; i; i >>= 1) { 269 EE_SET(RL_EE_CLK); 270 DELAY(100); 271 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 272 word |= i; 273 EE_CLR(RL_EE_CLK); 274 DELAY(100); 275 } 276 277 /* Turn off EEPROM access mode. */ 278 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 279 280 *dest = word; 281 282 return; 283} 284 285/* 286 * Read a sequence of words from the EEPROM. 287 */ 288static void rl_read_eeprom(sc, dest, off, cnt, swap) 289 struct rl_softc *sc; 290 caddr_t dest; 291 int off; 292 int cnt; 293 int swap; 294{ 295 int i; 296 u_int16_t word = 0, *ptr; 297 298 for (i = 0; i < cnt; i++) { 299 rl_eeprom_getword(sc, off + i, &word); 300 ptr = (u_int16_t *)(dest + (i * 2)); 301 if (swap) 302 *ptr = ntohs(word); 303 else 304 *ptr = word; 305 } 306 307 return; 308} 309 310 311/* 312 * MII access routines are provided for the 8129, which 313 * doesn't have a built-in PHY. For the 8139, we fake things 314 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 315 * direct access PHY registers. 316 */ 317#define MII_SET(x) \ 318 CSR_WRITE_1(sc, RL_MII, \ 319 CSR_READ_1(sc, RL_MII) | x) 320 321#define MII_CLR(x) \ 322 CSR_WRITE_1(sc, RL_MII, \ 323 CSR_READ_1(sc, RL_MII) & ~x) 324 325/* 326 * Sync the PHYs by setting data bit and strobing the clock 32 times. 327 */ 328static void rl_mii_sync(sc) 329 struct rl_softc *sc; 330{ 331 register int i; 332 333 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 334 335 for (i = 0; i < 32; i++) { 336 MII_SET(RL_MII_CLK); 337 DELAY(1); 338 MII_CLR(RL_MII_CLK); 339 DELAY(1); 340 } 341 342 return; 343} 344 345/* 346 * Clock a series of bits through the MII. 347 */ 348static void rl_mii_send(sc, bits, cnt) 349 struct rl_softc *sc; 350 u_int32_t bits; 351 int cnt; 352{ 353 int i; 354 355 MII_CLR(RL_MII_CLK); 356 357 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 358 if (bits & i) { 359 MII_SET(RL_MII_DATAOUT); 360 } else { 361 MII_CLR(RL_MII_DATAOUT); 362 } 363 DELAY(1); 364 MII_CLR(RL_MII_CLK); 365 DELAY(1); 366 MII_SET(RL_MII_CLK); 367 } 368} 369 370/* 371 * Read an PHY register through the MII. 372 */ 373static int rl_mii_readreg(sc, frame) 374 struct rl_softc *sc; 375 struct rl_mii_frame *frame; 376 377{ 378 int i, ack, s; 379 380 s = splimp(); 381 382 /* 383 * Set up frame for RX. 384 */ 385 frame->mii_stdelim = RL_MII_STARTDELIM; 386 frame->mii_opcode = RL_MII_READOP; 387 frame->mii_turnaround = 0; 388 frame->mii_data = 0; 389 390 CSR_WRITE_2(sc, RL_MII, 0); 391 392 /* 393 * Turn on data xmit. 394 */ 395 MII_SET(RL_MII_DIR); 396 397 rl_mii_sync(sc); 398 399 /* 400 * Send command/address info. 401 */ 402 rl_mii_send(sc, frame->mii_stdelim, 2); 403 rl_mii_send(sc, frame->mii_opcode, 2); 404 rl_mii_send(sc, frame->mii_phyaddr, 5); 405 rl_mii_send(sc, frame->mii_regaddr, 5); 406 407 /* Idle bit */ 408 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 409 DELAY(1); 410 MII_SET(RL_MII_CLK); 411 DELAY(1); 412 413 /* Turn off xmit. */ 414 MII_CLR(RL_MII_DIR); 415 416 /* Check for ack */ 417 MII_CLR(RL_MII_CLK); 418 DELAY(1); 419 MII_SET(RL_MII_CLK); 420 DELAY(1); 421 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 422 423 /* 424 * Now try reading data bits. If the ack failed, we still 425 * need to clock through 16 cycles to keep the PHY(s) in sync. 426 */ 427 if (ack) { 428 for(i = 0; i < 16; i++) { 429 MII_CLR(RL_MII_CLK); 430 DELAY(1); 431 MII_SET(RL_MII_CLK); 432 DELAY(1); 433 } 434 goto fail; 435 } 436 437 for (i = 0x8000; i; i >>= 1) { 438 MII_CLR(RL_MII_CLK); 439 DELAY(1); 440 if (!ack) { 441 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 442 frame->mii_data |= i; 443 DELAY(1); 444 } 445 MII_SET(RL_MII_CLK); 446 DELAY(1); 447 } 448 449fail: 450 451 MII_CLR(RL_MII_CLK); 452 DELAY(1); 453 MII_SET(RL_MII_CLK); 454 DELAY(1); 455 456 splx(s); 457 458 if (ack) 459 return(1); 460 return(0); 461} 462 463/* 464 * Write to a PHY register through the MII. 465 */ 466static int rl_mii_writereg(sc, frame) 467 struct rl_softc *sc; 468 struct rl_mii_frame *frame; 469 470{ 471 int s; 472 473 s = splimp(); 474 /* 475 * Set up frame for TX. 476 */ 477 478 frame->mii_stdelim = RL_MII_STARTDELIM; 479 frame->mii_opcode = RL_MII_WRITEOP; 480 frame->mii_turnaround = RL_MII_TURNAROUND; 481 482 /* 483 * Turn on data output. 484 */ 485 MII_SET(RL_MII_DIR); 486 487 rl_mii_sync(sc); 488 489 rl_mii_send(sc, frame->mii_stdelim, 2); 490 rl_mii_send(sc, frame->mii_opcode, 2); 491 rl_mii_send(sc, frame->mii_phyaddr, 5); 492 rl_mii_send(sc, frame->mii_regaddr, 5); 493 rl_mii_send(sc, frame->mii_turnaround, 2); 494 rl_mii_send(sc, frame->mii_data, 16); 495 496 /* Idle bit. */ 497 MII_SET(RL_MII_CLK); 498 DELAY(1); 499 MII_CLR(RL_MII_CLK); 500 DELAY(1); 501 502 /* 503 * Turn off xmit. 504 */ 505 MII_CLR(RL_MII_DIR); 506 507 splx(s); 508 509 return(0); 510} 511 512static u_int16_t rl_phy_readreg(sc, reg) 513 struct rl_softc *sc; 514 int reg; 515{ 516 struct rl_mii_frame frame; 517 u_int16_t rval = 0; 518 u_int16_t rl8139_reg = 0; 519 520 if (sc->rl_type == RL_8139) { 521 switch(reg) { 522 case PHY_BMCR: 523 rl8139_reg = RL_BMCR; 524 break; 525 case PHY_BMSR: 526 rl8139_reg = RL_BMSR; 527 break; 528 case PHY_ANAR: 529 rl8139_reg = RL_ANAR; 530 break; 531 case PHY_LPAR: 532 rl8139_reg = RL_LPAR; 533 break; 534 default: 535 printf("rl%d: bad phy register\n", sc->rl_unit); 536 return(0); 537 } 538 rval = CSR_READ_2(sc, rl8139_reg); 539 return(rval); 540 } 541 542 bzero((char *)&frame, sizeof(frame)); 543 544 frame.mii_phyaddr = sc->rl_phy_addr; 545 frame.mii_regaddr = reg; 546 rl_mii_readreg(sc, &frame); 547 548 return(frame.mii_data); 549} 550 551static void rl_phy_writereg(sc, reg, data) 552 struct rl_softc *sc; 553 int reg; 554 int data; 555{ 556 struct rl_mii_frame frame; 557 u_int16_t rl8139_reg = 0; 558 559 if (sc->rl_type == RL_8139) { 560 switch(reg) { 561 case PHY_BMCR: 562 rl8139_reg = RL_BMCR; 563 break; 564 case PHY_BMSR: 565 rl8139_reg = RL_BMSR; 566 break; 567 case PHY_ANAR: 568 rl8139_reg = RL_ANAR; 569 break; 570 case PHY_LPAR: 571 rl8139_reg = RL_LPAR; 572 break; 573 default: 574 printf("rl%d: bad phy register\n", sc->rl_unit); 575 return; 576 } 577 CSR_WRITE_2(sc, rl8139_reg, data); 578 return; 579 } 580 581 bzero((char *)&frame, sizeof(frame)); 582 583 frame.mii_phyaddr = sc->rl_phy_addr; 584 frame.mii_regaddr = reg; 585 frame.mii_data = data; 586 587 rl_mii_writereg(sc, &frame); 588 589 return; 590} 591 592/* 593 * Calculate CRC of a multicast group address, return the upper 6 bits. 594 */ 595static u_int8_t rl_calchash(addr) 596 caddr_t addr; 597{ 598 u_int32_t crc, carry; 599 int i, j; 600 u_int8_t c; 601 602 /* Compute CRC for the address value. */ 603 crc = 0xFFFFFFFF; /* initial value */ 604 605 for (i = 0; i < 6; i++) { 606 c = *(addr + i); 607 for (j = 0; j < 8; j++) { 608 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 609 crc <<= 1; 610 c >>= 1; 611 if (carry) 612 crc = (crc ^ 0x04c11db6) | carry; 613 } 614 } 615 616 /* return the filter bit position */ 617 return(crc >> 26); 618} 619 620/* 621 * Program the 64-bit multicast hash filter. 622 */ 623static void rl_setmulti(sc) 624 struct rl_softc *sc; 625{ 626 struct ifnet *ifp; 627 int h = 0; 628 u_int32_t hashes[2] = { 0, 0 }; 629 struct ifmultiaddr *ifma; 630 u_int32_t rxfilt; 631 int mcnt = 0; 632 633 ifp = &sc->arpcom.ac_if; 634 635 rxfilt = CSR_READ_4(sc, RL_RXCFG); 636 637 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 638 rxfilt |= RL_RXCFG_RX_MULTI; 639 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 640 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 641 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 642 return; 643 } 644 645 /* first, zot all the existing hash bits */ 646 CSR_WRITE_4(sc, RL_MAR0, 0); 647 CSR_WRITE_4(sc, RL_MAR4, 0); 648 649 /* now program new ones */ 650 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 651 ifma = ifma->ifma_link.le_next) { 652 if (ifma->ifma_addr->sa_family != AF_LINK) 653 continue; 654 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 655 if (h < 32) 656 hashes[0] |= (1 << h); 657 else 658 hashes[1] |= (1 << (h - 32)); 659 mcnt++; 660 } 661 662 if (mcnt) 663 rxfilt |= RL_RXCFG_RX_MULTI; 664 else 665 rxfilt &= ~RL_RXCFG_RX_MULTI; 666 667 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 668 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 669 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 670 671 return; 672} 673 674/* 675 * Initiate an autonegotiation session. 676 */ 677static void rl_autoneg_xmit(sc) 678 struct rl_softc *sc; 679{ 680 u_int16_t phy_sts; 681 682 rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 683 DELAY(500); 684 while(rl_phy_readreg(sc, PHY_BMCR) 685 & PHY_BMCR_RESET); 686 687 phy_sts = rl_phy_readreg(sc, PHY_BMCR); 688 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR; 689 rl_phy_writereg(sc, PHY_BMCR, phy_sts); 690 691 return; 692} 693 694/* 695 * Invoke autonegotiation on a PHY. Also used with the 8139 internal 696 * transceiver. 697 */ 698static void rl_autoneg_mii(sc, flag, verbose) 699 struct rl_softc *sc; 700 int flag; 701 int verbose; 702{ 703 u_int16_t phy_sts = 0, media, advert, ability; 704 struct ifnet *ifp; 705 struct ifmedia *ifm; 706 707 ifm = &sc->ifmedia; 708 ifp = &sc->arpcom.ac_if; 709 710 /* 711 * The 100baseT4 PHY sometimes has the 'autoneg supported' 712 * bit cleared in the status register, but has the 'autoneg enabled' 713 * bit set in the control register. This is a contradiction, and 714 * I'm not sure how to handle it. If you want to force an attempt 715 * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR 716 * and see what happens. 717 */ 718#ifndef FORCE_AUTONEG_TFOUR 719 /* 720 * First, see if autoneg is supported. If not, there's 721 * no point in continuing. 722 */ 723 phy_sts = rl_phy_readreg(sc, PHY_BMSR); 724 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 725 if (verbose) 726 printf("rl%d: autonegotiation not supported\n", 727 sc->rl_unit); 728 return; 729 } 730#endif 731 732 switch (flag) { 733 case RL_FLAG_FORCEDELAY: 734 /* 735 * XXX Never use this option anywhere but in the probe 736 * routine: making the kernel stop dead in its tracks 737 * for three whole seconds after we've gone multi-user 738 * is really bad manners. 739 */ 740 rl_autoneg_xmit(sc); 741 DELAY(5000000); 742 break; 743 case RL_FLAG_SCHEDDELAY: 744 /* 745 * Wait for the transmitter to go idle before starting 746 * an autoneg session, otherwise rl_start() may clobber 747 * our timeout, and we don't want to allow transmission 748 * during an autoneg session since that can screw it up. 749 */ 750 if (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx) { 751 sc->rl_want_auto = 1; 752 return; 753 } 754 rl_autoneg_xmit(sc); 755 ifp->if_timer = 5; 756 sc->rl_autoneg = 1; 757 sc->rl_want_auto = 0; 758 return; 759 break; 760 case RL_FLAG_DELAYTIMEO: 761 ifp->if_timer = 0; 762 sc->rl_autoneg = 0; 763 break; 764 default: 765 printf("rl%d: invalid autoneg flag: %d\n", sc->rl_unit, flag); 766 return; 767 } 768 769 if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 770 if (verbose) 771 printf("rl%d: autoneg complete, ", sc->rl_unit); 772 phy_sts = rl_phy_readreg(sc, PHY_BMSR); 773 } else { 774 if (verbose) 775 printf("rl%d: autoneg not complete, ", sc->rl_unit); 776 } 777 778 media = rl_phy_readreg(sc, PHY_BMCR); 779 780 /* Link is good. Report modes and set duplex mode. */ 781 if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 782 if (verbose) 783 printf("link status good "); 784 advert = rl_phy_readreg(sc, PHY_ANAR); 785 ability = rl_phy_readreg(sc, PHY_LPAR); 786 787 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 788 ifm->ifm_media = IFM_ETHER|IFM_100_T4; 789 media |= PHY_BMCR_SPEEDSEL; 790 media &= ~PHY_BMCR_DUPLEX; 791 printf("(100baseT4)\n"); 792 } else if (advert & PHY_ANAR_100BTXFULL && 793 ability & PHY_ANAR_100BTXFULL) { 794 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; 795 media |= PHY_BMCR_SPEEDSEL; 796 media |= PHY_BMCR_DUPLEX; 797 printf("(full-duplex, 100Mbps)\n"); 798 } else if (advert & PHY_ANAR_100BTXHALF && 799 ability & PHY_ANAR_100BTXHALF) { 800 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; 801 media |= PHY_BMCR_SPEEDSEL; 802 media &= ~PHY_BMCR_DUPLEX; 803 printf("(half-duplex, 100Mbps)\n"); 804 } else if (advert & PHY_ANAR_10BTFULL && 805 ability & PHY_ANAR_10BTFULL) { 806 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; 807 media &= ~PHY_BMCR_SPEEDSEL; 808 media |= PHY_BMCR_DUPLEX; 809 printf("(full-duplex, 10Mbps)\n"); 810 } else { 811 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 812 media &= ~PHY_BMCR_SPEEDSEL; 813 media &= ~PHY_BMCR_DUPLEX; 814 printf("(half-duplex, 10Mbps)\n"); 815 } 816 817 /* Set ASIC's duplex mode to match the PHY. */ 818 rl_phy_writereg(sc, PHY_BMCR, media); 819 } else { 820 if (verbose) 821 printf("no carrier\n"); 822 } 823 824 rl_init(sc); 825 826 if (sc->rl_tx_pend) { 827 sc->rl_autoneg = 0; 828 sc->rl_tx_pend = 0; 829 rl_start(ifp); 830 } 831 832 return; 833} 834 835static void rl_getmode_mii(sc) 836 struct rl_softc *sc; 837{ 838 u_int16_t bmsr; 839 struct ifnet *ifp; 840 841 ifp = &sc->arpcom.ac_if; 842 843 bmsr = rl_phy_readreg(sc, PHY_BMSR); 844 if (bootverbose) 845 printf("rl%d: PHY status word: %x\n", sc->rl_unit, bmsr); 846 847 /* fallback */ 848 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 849 850 if (bmsr & PHY_BMSR_10BTHALF) { 851 if (bootverbose) 852 printf("rl%d: 10Mbps half-duplex mode supported\n", 853 sc->rl_unit); 854 ifmedia_add(&sc->ifmedia, 855 IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 856 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 857 } 858 859 if (bmsr & PHY_BMSR_10BTFULL) { 860 if (bootverbose) 861 printf("rl%d: 10Mbps full-duplex mode supported\n", 862 sc->rl_unit); 863 ifmedia_add(&sc->ifmedia, 864 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 865 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; 866 } 867 868 if (bmsr & PHY_BMSR_100BTXHALF) { 869 if (bootverbose) 870 printf("rl%d: 100Mbps half-duplex mode supported\n", 871 sc->rl_unit); 872 ifp->if_baudrate = 100000000; 873 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 874 ifmedia_add(&sc->ifmedia, 875 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 876 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; 877 } 878 879 if (bmsr & PHY_BMSR_100BTXFULL) { 880 if (bootverbose) 881 printf("rl%d: 100Mbps full-duplex mode supported\n", 882 sc->rl_unit); 883 ifp->if_baudrate = 100000000; 884 ifmedia_add(&sc->ifmedia, 885 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 886 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; 887 } 888 889 /* Some also support 100BaseT4. */ 890 if (bmsr & PHY_BMSR_100BT4) { 891 if (bootverbose) 892 printf("rl%d: 100baseT4 mode supported\n", sc->rl_unit); 893 ifp->if_baudrate = 100000000; 894 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL); 895 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4; 896#ifdef FORCE_AUTONEG_TFOUR 897 if (bootverbose) 898 printf("rl%d: forcing on autoneg support for BT4\n", 899 sc->rl_unit); 900 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL): 901 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; 902#endif 903 } 904 905 if (bmsr & PHY_BMSR_CANAUTONEG) { 906 if (bootverbose) 907 printf("rl%d: autoneg supported\n", sc->rl_unit); 908 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 909 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; 910 } 911 912 return; 913} 914 915/* 916 * Set speed and duplex mode. 917 */ 918static void rl_setmode_mii(sc, media) 919 struct rl_softc *sc; 920 int media; 921{ 922 u_int16_t bmcr; 923 924 printf("rl%d: selecting MII, ", sc->rl_unit); 925 926 bmcr = rl_phy_readreg(sc, PHY_BMCR); 927 928 bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL| 929 PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK); 930 931 if (IFM_SUBTYPE(media) == IFM_100_T4) { 932 printf("100Mbps/T4, half-duplex\n"); 933 bmcr |= PHY_BMCR_SPEEDSEL; 934 bmcr &= ~PHY_BMCR_DUPLEX; 935 } 936 937 if (IFM_SUBTYPE(media) == IFM_100_TX) { 938 printf("100Mbps, "); 939 bmcr |= PHY_BMCR_SPEEDSEL; 940 } 941 942 if (IFM_SUBTYPE(media) == IFM_10_T) { 943 printf("10Mbps, "); 944 bmcr &= ~PHY_BMCR_SPEEDSEL; 945 } 946 947 if ((media & IFM_GMASK) == IFM_FDX) { 948 printf("full duplex\n"); 949 bmcr |= PHY_BMCR_DUPLEX; 950 } else { 951 printf("half duplex\n"); 952 bmcr &= ~PHY_BMCR_DUPLEX; 953 } 954 955 rl_phy_writereg(sc, PHY_BMCR, bmcr); 956 957 return; 958} 959 960static void rl_reset(sc) 961 struct rl_softc *sc; 962{ 963 register int i; 964 965 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 966 967 for (i = 0; i < RL_TIMEOUT; i++) { 968 DELAY(10); 969 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 970 break; 971 } 972 if (i == RL_TIMEOUT) 973 printf("rl%d: reset never completed!\n", sc->rl_unit); 974 975 return; 976} 977 978/* 979 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 980 * IDs against our list and return a device name if we find a match. 981 */ 982static const char * 983rl_probe(config_id, device_id) 984 pcici_t config_id; 985 pcidi_t device_id; 986{ 987 struct rl_type *t; 988 989 t = rl_devs; 990 991 while(t->rl_name != NULL) { 992 if ((device_id & 0xFFFF) == t->rl_vid && 993 ((device_id >> 16) & 0xFFFF) == t->rl_did) { 994 return(t->rl_name); 995 } 996 t++; 997 } 998 999 return(NULL); 1000} 1001 1002/* 1003 * Attach the interface. Allocate softc structures, do ifmedia 1004 * setup and ethernet/BPF attach. 1005 */ 1006static void 1007rl_attach(config_id, unit) 1008 pcici_t config_id; 1009 int unit; 1010{ 1011 int s, i; 1012#ifndef RL_USEIOSPACE 1013 vm_offset_t pbase, vbase; 1014#endif 1015 u_char eaddr[ETHER_ADDR_LEN]; 1016 u_int32_t command; 1017 struct rl_softc *sc; 1018 struct ifnet *ifp; 1019 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1020 struct rl_type *p; 1021 u_int16_t phy_vid, phy_did, phy_sts; 1022 u_int16_t rl_did = 0; 1023 1024 s = splimp(); 1025 1026 sc = malloc(sizeof(struct rl_softc), M_DEVBUF, M_NOWAIT); 1027 if (sc == NULL) { 1028 printf("rl%d: no memory for softc struct!\n", unit); 1029 goto fail; 1030 } 1031 bzero(sc, sizeof(struct rl_softc)); 1032 1033 /* 1034 * Handle power management nonsense. 1035 */ 1036 1037 command = pci_conf_read(config_id, RL_PCI_CAPID) & 0x000000FF; 1038 if (command == 0x01) { 1039 1040 command = pci_conf_read(config_id, RL_PCI_PWRMGMTCTRL); 1041 if (command & RL_PSTATE_MASK) { 1042 u_int32_t iobase, membase, irq; 1043 1044 /* Save important PCI config data. */ 1045 iobase = pci_conf_read(config_id, RL_PCI_LOIO); 1046 membase = pci_conf_read(config_id, RL_PCI_LOMEM); 1047 irq = pci_conf_read(config_id, RL_PCI_INTLINE); 1048 1049 /* Reset the power state. */ 1050 printf("rl%d: chip is is in D%d power mode " 1051 "-- setting to D0\n", unit, command & RL_PSTATE_MASK); 1052 command &= 0xFFFFFFFC; 1053 pci_conf_write(config_id, RL_PCI_PWRMGMTCTRL, command); 1054 1055 /* Restore PCI config data. */ 1056 pci_conf_write(config_id, RL_PCI_LOIO, iobase); 1057 pci_conf_write(config_id, RL_PCI_LOMEM, membase); 1058 pci_conf_write(config_id, RL_PCI_INTLINE, irq); 1059 } 1060 } 1061 1062 /* 1063 * Map control/status registers. 1064 */ 1065 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1066 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1067 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command); 1068 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1069 1070#ifdef RL_USEIOSPACE 1071 if (!(command & PCIM_CMD_PORTEN)) { 1072 printf("rl%d: failed to enable I/O ports!\n", unit); 1073 free(sc, M_DEVBUF); 1074 goto fail; 1075 } 1076 1077 if (!pci_map_port(config_id, RL_PCI_LOIO, 1078 (pci_port_t *)&(sc->rl_bhandle))) { 1079 printf ("rl%d: couldn't map ports\n", unit); 1080 goto fail; 1081 } 1082#ifdef __i386__ 1083 sc->rl_btag = I386_BUS_SPACE_IO; 1084#endif 1085#ifdef __alpha__ 1086 sc->rl_btag = ALPHA_BUS_SPACE_IO; 1087#endif 1088#else 1089 if (!(command & PCIM_CMD_MEMEN)) { 1090 printf("rl%d: failed to enable memory mapping!\n", unit); 1091 goto fail; 1092 } 1093 1094 if (!pci_map_mem(config_id, RL_PCI_LOMEM, &vbase, &pbase)) { 1095 printf ("rl%d: couldn't map memory\n", unit); 1096 goto fail; 1097 } 1098#ifdef __i386__ 1099 sc->rl_btag = I386_BUS_SPACE_MEM; 1100#endif 1101#ifdef __alpha__ 1102 sc->rl_btag = ALPHA_BUS_SPACE_MEM; 1103#endif 1104 sc->rl_bhandle = vbase; 1105#endif 1106 1107 /* Allocate interrupt */ 1108 if (!pci_map_int(config_id, rl_intr, sc, &net_imask)) { 1109 printf("rl%d: couldn't map interrupt\n", unit); 1110 goto fail; 1111 } 1112 1113 /* Reset the adapter. */ 1114 rl_reset(sc); 1115 1116 /* 1117 * Get station address from the EEPROM. 1118 */ 1119 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 1120 1121 /* 1122 * A RealTek chip was detected. Inform the world. 1123 */ 1124 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1125 1126 sc->rl_unit = unit; 1127 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1128 1129 /* 1130 * Now read the exact device type from the EEPROM to find 1131 * out if it's an 8129 or 8139. 1132 */ 1133 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 1134 1135 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 1136 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139) 1137 sc->rl_type = RL_8139; 1138 else if (rl_did == RT_DEVICEID_8129) 1139 sc->rl_type = RL_8129; 1140 else { 1141 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 1142 free(sc, M_DEVBUF); 1143 goto fail; 1144 } 1145 1146 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 32, M_DEVBUF, 1147 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 1148 1149 if (sc->rl_cdata.rl_rx_buf == NULL) { 1150 free(sc, M_DEVBUF); 1151 printf("rl%d: no memory for list buffers!\n", unit); 1152 goto fail; 1153 } 1154 1155 /* Leave a few bytes before the start of the RX ring buffer. */ 1156 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1157 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1158 1159 ifp = &sc->arpcom.ac_if; 1160 ifp->if_softc = sc; 1161 ifp->if_unit = unit; 1162 ifp->if_name = "rl"; 1163 ifp->if_mtu = ETHERMTU; 1164 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1165 ifp->if_ioctl = rl_ioctl; 1166 ifp->if_output = ether_output; 1167 ifp->if_start = rl_start; 1168 ifp->if_watchdog = rl_watchdog; 1169 ifp->if_init = rl_init; 1170 ifp->if_baudrate = 10000000; 1171 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1172 1173 if (sc->rl_type == RL_8129) { 1174 if (bootverbose) 1175 printf("rl%d: probing for a PHY\n", sc->rl_unit); 1176 for (i = RL_PHYADDR_MIN; i < RL_PHYADDR_MAX + 1; i++) { 1177 if (bootverbose) 1178 printf("rl%d: checking address: %d\n", 1179 sc->rl_unit, i); 1180 sc->rl_phy_addr = i; 1181 rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 1182 DELAY(500); 1183 while(rl_phy_readreg(sc, PHY_BMCR) 1184 & PHY_BMCR_RESET); 1185 if ((phy_sts = rl_phy_readreg(sc, PHY_BMSR))) 1186 break; 1187 } 1188 if (phy_sts) { 1189 phy_vid = rl_phy_readreg(sc, PHY_VENID); 1190 phy_did = rl_phy_readreg(sc, PHY_DEVID); 1191 if (bootverbose) 1192 printf("rl%d: found PHY at address %d, ", 1193 sc->rl_unit, sc->rl_phy_addr); 1194 if (bootverbose) 1195 printf("vendor id: %x device id: %x\n", 1196 phy_vid, phy_did); 1197 p = rl_phys; 1198 while(p->rl_vid) { 1199 if (phy_vid == p->rl_vid && 1200 (phy_did | 0x000F) == p->rl_did) { 1201 sc->rl_pinfo = p; 1202 break; 1203 } 1204 p++; 1205 } 1206 if (sc->rl_pinfo == NULL) 1207 sc->rl_pinfo = &rl_phys[PHY_UNKNOWN]; 1208 if (bootverbose) 1209 printf("rl%d: PHY type: %s\n", 1210 sc->rl_unit, sc->rl_pinfo->rl_name); 1211 } else { 1212 printf("rl%d: MII without any phy!\n", sc->rl_unit); 1213 } 1214 } 1215 1216 /* 1217 * Do ifmedia setup. 1218 */ 1219 ifmedia_init(&sc->ifmedia, 0, rl_ifmedia_upd, rl_ifmedia_sts); 1220 1221 rl_getmode_mii(sc); 1222 1223 /* Choose a default media. */ 1224 media = IFM_ETHER|IFM_AUTO; 1225 ifmedia_set(&sc->ifmedia, media); 1226 1227 rl_autoneg_mii(sc, RL_FLAG_FORCEDELAY, 1); 1228 1229 /* 1230 * Call MI attach routines. 1231 */ 1232 if_attach(ifp); 1233 ether_ifattach(ifp); 1234 1235#if NBPF > 0 1236 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1237#endif 1238 EVENTHANDLER_REGISTER(shutdown_post_sync, rl_shutdown, sc, 1239 SHUTDOWN_PRI_DEFAULT); 1240 1241fail: 1242 splx(s); 1243 return; 1244} 1245 1246/* 1247 * Initialize the transmit descriptors. 1248 */ 1249static int rl_list_tx_init(sc) 1250 struct rl_softc *sc; 1251{ 1252 struct rl_chain_data *cd; 1253 int i; 1254 1255 cd = &sc->rl_cdata; 1256 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1257 cd->rl_tx_chain[i] = NULL; 1258 CSR_WRITE_4(sc, 1259 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1260 } 1261 1262 sc->rl_cdata.cur_tx = 0; 1263 sc->rl_cdata.last_tx = 0; 1264 1265 return(0); 1266} 1267 1268/* 1269 * A frame has been uploaded: pass the resulting mbuf chain up to 1270 * the higher level protocols. 1271 * 1272 * You know there's something wrong with a PCI bus-master chip design 1273 * when you have to use m_devget(). 1274 * 1275 * The receive operation is badly documented in the datasheet, so I'll 1276 * attempt to document it here. The driver provides a buffer area and 1277 * places its base address in the RX buffer start address register. 1278 * The chip then begins copying frames into the RX buffer. Each frame 1279 * is preceeded by a 32-bit RX status word which specifies the length 1280 * of the frame and certain other status bits. Each frame (starting with 1281 * the status word) is also 32-bit aligned. The frame length is in the 1282 * first 16 bits of the status word; the lower 15 bits correspond with 1283 * the 'rx status register' mentioned in the datasheet. 1284 * 1285 * Note: to make the Alpha happy, the frame payload needs to be aligned 1286 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 1287 * the ring buffer starting at an address two bytes before the actual 1288 * data location. We can then shave off the first two bytes using m_adj(). 1289 * The reason we do this is because m_devget() doesn't let us specify an 1290 * offset into the mbuf storage space, so we have to artificially create 1291 * one. The ring is allocated in such a way that there are a few unused 1292 * bytes of space preceecing it so that it will be safe for us to do the 1293 * 2-byte backstep even if reading from the ring at offset 0. 1294 */ 1295static void rl_rxeof(sc) 1296 struct rl_softc *sc; 1297{ 1298 struct ether_header *eh; 1299 struct mbuf *m; 1300 struct ifnet *ifp; 1301 int total_len = 0; 1302 u_int32_t rxstat; 1303 caddr_t rxbufpos; 1304 int wrap = 0; 1305 u_int16_t cur_rx; 1306 u_int16_t limit; 1307 u_int16_t rx_bytes = 0, max_bytes; 1308 1309 ifp = &sc->arpcom.ac_if; 1310 1311 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1312 1313 /* Do not try to read past this point. */ 1314 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1315 1316 if (limit < cur_rx) 1317 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1318 else 1319 max_bytes = limit - cur_rx; 1320 1321 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1322 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1323 rxstat = *(u_int32_t *)rxbufpos; 1324 1325 /* 1326 * Here's a totally undocumented fact for you. When the 1327 * RealTek chip is in the process of copying a packet into 1328 * RAM for you, the length will be 0xfff0. If you spot a 1329 * packet header with this value, you need to stop. The 1330 * datasheet makes absolutely no mention of this and 1331 * RealTek should be shot for this. 1332 */ 1333 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1334 break; 1335 1336 if (!(rxstat & RL_RXSTAT_RXOK)) { 1337 ifp->if_ierrors++; 1338 if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT| 1339 RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR| 1340 RL_RXSTAT_ALIGNERR)) { 1341 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB); 1342 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB| 1343 RL_CMD_RX_ENB); 1344 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1345 CSR_WRITE_4(sc, RL_RXADDR, 1346 vtophys(sc->rl_cdata.rl_rx_buf)); 1347 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1348 cur_rx = 0; 1349 } 1350 break; 1351 } 1352 1353 /* No errors; receive the packet. */ 1354 total_len = rxstat >> 16; 1355 rx_bytes += total_len + 4; 1356 1357 /* 1358 * XXX The RealTek chip includes the CRC with every 1359 * received frame, and there's no way to turn this 1360 * behavior off (at least, I can't find anything in 1361 * the manual that explains how to do it) so we have 1362 * to trim off the CRC manually. 1363 */ 1364 total_len -= ETHER_CRC_LEN; 1365 1366 /* 1367 * Avoid trying to read more bytes than we know 1368 * the chip has prepared for us. 1369 */ 1370 if (rx_bytes > max_bytes) 1371 break; 1372 1373 rxbufpos = sc->rl_cdata.rl_rx_buf + 1374 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1375 1376 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1377 rxbufpos = sc->rl_cdata.rl_rx_buf; 1378 1379 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1380 1381 if (total_len > wrap) { 1382 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1383 wrap + RL_ETHER_ALIGN, 0, ifp, NULL); 1384 if (m == NULL) { 1385 ifp->if_ierrors++; 1386 printf("rl%d: out of mbufs, tried to " 1387 "copy %d bytes\n", sc->rl_unit, wrap); 1388 } 1389 else { 1390 m_adj(m, RL_ETHER_ALIGN); 1391 m_copyback(m, wrap, total_len - wrap, 1392 sc->rl_cdata.rl_rx_buf); 1393 } 1394 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1395 } else { 1396 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1397 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1398 if (m == NULL) { 1399 ifp->if_ierrors++; 1400 printf("rl%d: out of mbufs, tried to " 1401 "copy %d bytes\n", sc->rl_unit, total_len); 1402 } else 1403 m_adj(m, RL_ETHER_ALIGN); 1404 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1405 } 1406 1407 /* 1408 * Round up to 32-bit boundary. 1409 */ 1410 cur_rx = (cur_rx + 3) & ~3; 1411 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1412 1413 if (m == NULL) 1414 continue; 1415 1416 eh = mtod(m, struct ether_header *); 1417 ifp->if_ipackets++; 1418 1419#if NBPF > 0 1420 /* 1421 * Handle BPF listeners. Let the BPF user see the packet, but 1422 * don't pass it up to the ether_input() layer unless it's 1423 * a broadcast packet, multicast packet, matches our ethernet 1424 * address or the interface is in promiscuous mode. 1425 */ 1426 if (ifp->if_bpf) { 1427 bpf_mtap(ifp, m); 1428 if (ifp->if_flags & IFF_PROMISC && 1429 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1430 ETHER_ADDR_LEN) && 1431 (eh->ether_dhost[0] & 1) == 0)) { 1432 m_freem(m); 1433 continue; 1434 } 1435 } 1436#endif 1437 /* Remove header from mbuf and pass it on. */ 1438 m_adj(m, sizeof(struct ether_header)); 1439 ether_input(ifp, eh, m); 1440 } 1441 1442 return; 1443} 1444 1445/* 1446 * A frame was downloaded to the chip. It's safe for us to clean up 1447 * the list buffers. 1448 */ 1449static void rl_txeof(sc) 1450 struct rl_softc *sc; 1451{ 1452 struct ifnet *ifp; 1453 u_int32_t txstat; 1454 1455 ifp = &sc->arpcom.ac_if; 1456 1457 /* Clear the timeout timer. */ 1458 ifp->if_timer = 0; 1459 1460 /* 1461 * Go through our tx list and free mbufs for those 1462 * frames that have been uploaded. 1463 */ 1464 do { 1465 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1466 if (!(txstat & (RL_TXSTAT_TX_OK| 1467 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1468 break; 1469 1470 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1471 1472 if (RL_LAST_TXMBUF(sc) != NULL) { 1473 m_freem(RL_LAST_TXMBUF(sc)); 1474 RL_LAST_TXMBUF(sc) = NULL; 1475 } 1476 if (txstat & RL_TXSTAT_TX_OK) 1477 ifp->if_opackets++; 1478 else { 1479 ifp->if_oerrors++; 1480 if ((txstat & RL_TXSTAT_TXABRT) || 1481 (txstat & RL_TXSTAT_OUTOFWIN)) 1482 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1483 } 1484 RL_INC(sc->rl_cdata.last_tx); 1485 ifp->if_flags &= ~IFF_OACTIVE; 1486 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1487 1488 if (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) { 1489 if (sc->rl_want_auto) 1490 rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1); 1491 } 1492 1493 return; 1494} 1495 1496static void rl_intr(arg) 1497 void *arg; 1498{ 1499 struct rl_softc *sc; 1500 struct ifnet *ifp; 1501 u_int16_t status; 1502 1503 sc = arg; 1504 ifp = &sc->arpcom.ac_if; 1505 1506 /* Disable interrupts. */ 1507 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1508 1509 for (;;) { 1510 1511 status = CSR_READ_2(sc, RL_ISR); 1512 if (status) 1513 CSR_WRITE_2(sc, RL_ISR, status); 1514 1515 if ((status & RL_INTRS) == 0) 1516 break; 1517 1518 if (status & RL_ISR_RX_OK) 1519 rl_rxeof(sc); 1520 1521 if (status & RL_ISR_RX_ERR) 1522 rl_rxeof(sc); 1523 1524 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1525 rl_txeof(sc); 1526 1527 if (status & RL_ISR_SYSTEM_ERR) { 1528 rl_reset(sc); 1529 rl_init(sc); 1530 } 1531 1532 } 1533 1534 /* Re-enable interrupts. */ 1535 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1536 1537 if (ifp->if_snd.ifq_head != NULL) { 1538 rl_start(ifp); 1539 } 1540 1541 return; 1542} 1543 1544/* 1545 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1546 * pointers to the fragment pointers. 1547 */ 1548static int rl_encap(sc, m_head) 1549 struct rl_softc *sc; 1550 struct mbuf *m_head; 1551{ 1552 struct mbuf *m_new = NULL; 1553 1554 /* 1555 * The RealTek is brain damaged and wants longword-aligned 1556 * TX buffers, plus we can only have one fragment buffer 1557 * per packet. We have to copy pretty much all the time. 1558 */ 1559 1560 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1561 if (m_new == NULL) { 1562 printf("rl%d: no memory for tx list", sc->rl_unit); 1563 return(1); 1564 } 1565 if (m_head->m_pkthdr.len > MHLEN) { 1566 MCLGET(m_new, M_DONTWAIT); 1567 if (!(m_new->m_flags & M_EXT)) { 1568 m_freem(m_new); 1569 printf("rl%d: no memory for tx list", 1570 sc->rl_unit); 1571 return(1); 1572 } 1573 } 1574 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1575 mtod(m_new, caddr_t)); 1576 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1577 m_freem(m_head); 1578 m_head = m_new; 1579 1580 /* Pad frames to at least 60 bytes. */ 1581 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1582 m_head->m_pkthdr.len += 1583 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1584 m_head->m_len = m_head->m_pkthdr.len; 1585 } 1586 1587 RL_CUR_TXMBUF(sc) = m_head; 1588 1589 return(0); 1590} 1591 1592/* 1593 * Main transmit routine. 1594 */ 1595 1596static void rl_start(ifp) 1597 struct ifnet *ifp; 1598{ 1599 struct rl_softc *sc; 1600 struct mbuf *m_head = NULL; 1601 1602 sc = ifp->if_softc; 1603 1604 if (sc->rl_autoneg) { 1605 sc->rl_tx_pend = 1; 1606 return; 1607 } 1608 1609 while(RL_CUR_TXMBUF(sc) == NULL) { 1610 IF_DEQUEUE(&ifp->if_snd, m_head); 1611 if (m_head == NULL) 1612 break; 1613 1614 rl_encap(sc, m_head); 1615 1616#if NBPF > 0 1617 /* 1618 * If there's a BPF listener, bounce a copy of this frame 1619 * to him. 1620 */ 1621 if (ifp->if_bpf) 1622 bpf_mtap(ifp, RL_CUR_TXMBUF(sc)); 1623#endif 1624 /* 1625 * Transmit the frame. 1626 */ 1627 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), 1628 vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t))); 1629 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1630 RL_TX_EARLYTHRESH | RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1631 1632 RL_INC(sc->rl_cdata.cur_tx); 1633 } 1634 1635 /* 1636 * We broke out of the loop because all our TX slots are 1637 * full. Mark the NIC as busy until it drains some of the 1638 * packets from the queue. 1639 */ 1640 if (RL_CUR_TXMBUF(sc) != NULL) 1641 ifp->if_flags |= IFF_OACTIVE; 1642 1643 /* 1644 * Set a timeout in case the chip goes out to lunch. 1645 */ 1646 ifp->if_timer = 5; 1647 1648 return; 1649} 1650 1651static void rl_init(xsc) 1652 void *xsc; 1653{ 1654 struct rl_softc *sc = xsc; 1655 struct ifnet *ifp = &sc->arpcom.ac_if; 1656 int s, i; 1657 u_int32_t rxcfg = 0; 1658 u_int16_t phy_bmcr = 0; 1659 1660 if (sc->rl_autoneg) 1661 return; 1662 1663 s = splimp(); 1664 1665 /* 1666 * XXX Hack for the 8139: the built-in autoneg logic's state 1667 * gets reset by rl_init() when we don't want it to. Try 1668 * to preserve it. (For 8129 cards with real external PHYs, 1669 * the BMCR register doesn't change, but this doesn't hurt.) 1670 */ 1671 if (sc->rl_type == RL_8139) 1672 phy_bmcr = rl_phy_readreg(sc, PHY_BMCR); 1673 1674 /* 1675 * Cancel pending I/O and free all RX/TX buffers. 1676 */ 1677 rl_stop(sc); 1678 1679 /* Init our MAC address */ 1680 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1681 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 1682 } 1683 1684 /* Init the RX buffer pointer register. */ 1685 CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf)); 1686 1687 /* Init TX descriptors. */ 1688 rl_list_tx_init(sc); 1689 1690 /* 1691 * Enable transmit and receive. 1692 */ 1693 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1694 1695 /* 1696 * Set the initial TX and RX configuration. 1697 */ 1698 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1699 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1700 1701 /* Set the individual bit to receive frames for this host only. */ 1702 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1703 rxcfg |= RL_RXCFG_RX_INDIV; 1704 1705 /* If we want promiscuous mode, set the allframes bit. */ 1706 if (ifp->if_flags & IFF_PROMISC) { 1707 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1708 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1709 } else { 1710 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1711 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1712 } 1713 1714 /* 1715 * Set capture broadcast bit to capture broadcast frames. 1716 */ 1717 if (ifp->if_flags & IFF_BROADCAST) { 1718 rxcfg |= RL_RXCFG_RX_BROAD; 1719 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1720 } else { 1721 rxcfg &= ~RL_RXCFG_RX_BROAD; 1722 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1723 } 1724 1725 /* 1726 * Program the multicast filter, if necessary. 1727 */ 1728 rl_setmulti(sc); 1729 1730 /* 1731 * Enable interrupts. 1732 */ 1733 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1734 1735 /* Start RX/TX process. */ 1736 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1737 1738 /* Enable receiver and transmitter. */ 1739 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1740 1741 /* Restore state of BMCR */ 1742 if (sc->rl_pinfo != NULL) 1743 rl_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1744 1745 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1746 1747 ifp->if_flags |= IFF_RUNNING; 1748 ifp->if_flags &= ~IFF_OACTIVE; 1749 1750 (void)splx(s); 1751 1752 return; 1753} 1754 1755/* 1756 * Set media options. 1757 */ 1758static int rl_ifmedia_upd(ifp) 1759 struct ifnet *ifp; 1760{ 1761 struct rl_softc *sc; 1762 struct ifmedia *ifm; 1763 1764 sc = ifp->if_softc; 1765 ifm = &sc->ifmedia; 1766 1767 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1768 return(EINVAL); 1769 1770 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1771 rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1); 1772 else 1773 rl_setmode_mii(sc, ifm->ifm_media); 1774 1775 return(0); 1776} 1777 1778/* 1779 * Report current media status. 1780 */ 1781static void rl_ifmedia_sts(ifp, ifmr) 1782 struct ifnet *ifp; 1783 struct ifmediareq *ifmr; 1784{ 1785 struct rl_softc *sc; 1786 u_int16_t advert = 0, ability = 0; 1787 1788 sc = ifp->if_softc; 1789 1790 if (!(rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1791 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1792 ifmr->ifm_active = IFM_ETHER|IFM_100_TX; 1793 else 1794 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 1795 1796 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1797 ifmr->ifm_active |= IFM_FDX; 1798 else 1799 ifmr->ifm_active |= IFM_HDX; 1800 return; 1801 } 1802 1803 ability = rl_phy_readreg(sc, PHY_LPAR); 1804 advert = rl_phy_readreg(sc, PHY_ANAR); 1805 if (advert & PHY_ANAR_100BT4 && 1806 ability & PHY_ANAR_100BT4) { 1807 ifmr->ifm_active = IFM_ETHER|IFM_100_T4; 1808 } else if (advert & PHY_ANAR_100BTXFULL && 1809 ability & PHY_ANAR_100BTXFULL) { 1810 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX; 1811 } else if (advert & PHY_ANAR_100BTXHALF && 1812 ability & PHY_ANAR_100BTXHALF) { 1813 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX; 1814 } else if (advert & PHY_ANAR_10BTFULL && 1815 ability & PHY_ANAR_10BTFULL) { 1816 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX; 1817 } else if (advert & PHY_ANAR_10BTHALF && 1818 ability & PHY_ANAR_10BTHALF) { 1819 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX; 1820 } 1821 1822 return; 1823} 1824 1825static int rl_ioctl(ifp, command, data) 1826 struct ifnet *ifp; 1827 u_long command; 1828 caddr_t data; 1829{ 1830 struct rl_softc *sc = ifp->if_softc; 1831 struct ifreq *ifr = (struct ifreq *) data; 1832 int s, error = 0; 1833 1834 s = splimp(); 1835 1836 switch(command) { 1837 case SIOCSIFADDR: 1838 case SIOCGIFADDR: 1839 case SIOCSIFMTU: 1840 error = ether_ioctl(ifp, command, data); 1841 break; 1842 case SIOCSIFFLAGS: 1843 if (ifp->if_flags & IFF_UP) { 1844 rl_init(sc); 1845 } else { 1846 if (ifp->if_flags & IFF_RUNNING) 1847 rl_stop(sc); 1848 } 1849 error = 0; 1850 break; 1851 case SIOCADDMULTI: 1852 case SIOCDELMULTI: 1853 rl_setmulti(sc); 1854 error = 0; 1855 break; 1856 case SIOCGIFMEDIA: 1857 case SIOCSIFMEDIA: 1858 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1859 break; 1860 default: 1861 error = EINVAL; 1862 break; 1863 } 1864 1865 (void)splx(s); 1866 1867 return(error); 1868} 1869 1870static void rl_watchdog(ifp) 1871 struct ifnet *ifp; 1872{ 1873 struct rl_softc *sc; 1874 1875 sc = ifp->if_softc; 1876 1877 if (sc->rl_autoneg) { 1878 rl_autoneg_mii(sc, RL_FLAG_DELAYTIMEO, 1); 1879 return; 1880 } 1881 1882 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1883 ifp->if_oerrors++; 1884 if (!(rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1885 printf("rl%d: no carrier - transceiver cable problem?\n", 1886 sc->rl_unit); 1887 rl_txeof(sc); 1888 rl_rxeof(sc); 1889 rl_init(sc); 1890 1891 return; 1892} 1893 1894/* 1895 * Stop the adapter and free any mbufs allocated to the 1896 * RX and TX lists. 1897 */ 1898static void rl_stop(sc) 1899 struct rl_softc *sc; 1900{ 1901 register int i; 1902 struct ifnet *ifp; 1903 1904 ifp = &sc->arpcom.ac_if; 1905 ifp->if_timer = 0; 1906 1907 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1908 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1909 1910 /* 1911 * Free the TX list buffers. 1912 */ 1913 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1914 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1915 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1916 sc->rl_cdata.rl_tx_chain[i] = NULL; 1917 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1918 } 1919 } 1920 1921 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1922 1923 return; 1924} 1925 1926/* 1927 * Stop all chip I/O so that the kernel's probe routines don't 1928 * get confused by errant DMAs when rebooting. 1929 */ 1930static void rl_shutdown(arg, howto) 1931 void *arg; 1932 int howto; 1933{ 1934 struct rl_softc *sc = (struct rl_softc *)arg; 1935 1936 rl_stop(sc); 1937 1938 return; 1939} 1940 1941 1942static struct pci_device rl_device = { 1943 "rl", 1944 rl_probe, 1945 rl_attach, 1946 &rl_count, 1947 NULL 1948}; 1949COMPAT_PCI_DRIVER(rl, rl_device); 1950