if_rl.c revision 184243
1/*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 184243 2008-10-25 03:06:47Z yongari $"); 35 36/* 37 * RealTek 8129/8139 PCI NIC driver 38 * 39 * Supports several extremely cheap PCI 10/100 adapters based on 40 * the RealTek chipset. Datasheets can be obtained from 41 * www.realtek.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86#ifdef HAVE_KERNEL_OPTION_HEADERS 87#include "opt_device_polling.h" 88#endif 89 90#include <sys/param.h> 91#include <sys/endian.h> 92#include <sys/systm.h> 93#include <sys/sockio.h> 94#include <sys/mbuf.h> 95#include <sys/malloc.h> 96#include <sys/kernel.h> 97#include <sys/module.h> 98#include <sys/socket.h> 99 100#include <net/if.h> 101#include <net/if_arp.h> 102#include <net/ethernet.h> 103#include <net/if_dl.h> 104#include <net/if_media.h> 105#include <net/if_types.h> 106 107#include <net/bpf.h> 108 109#include <machine/bus.h> 110#include <machine/resource.h> 111#include <sys/bus.h> 112#include <sys/rman.h> 113 114#include <dev/mii/mii.h> 115#include <dev/mii/miivar.h> 116 117#include <dev/pci/pcireg.h> 118#include <dev/pci/pcivar.h> 119 120MODULE_DEPEND(rl, pci, 1, 1, 1); 121MODULE_DEPEND(rl, ether, 1, 1, 1); 122MODULE_DEPEND(rl, miibus, 1, 1, 1); 123 124/* "device miibus" required. See GENERIC if you get errors here. */ 125#include "miibus_if.h" 126 127/* 128 * Default to using PIO access for this driver. On SMP systems, 129 * there appear to be problems with memory mapped mode: it looks like 130 * doing too many memory mapped access back to back in rapid succession 131 * can hang the bus. I'm inclined to blame this on crummy design/construction 132 * on the part of RealTek. Memory mapped mode does appear to work on 133 * uniprocessor systems though. 134 */ 135#define RL_USEIOSPACE 136 137#include <pci/if_rlreg.h> 138 139/* 140 * Various supported device vendors/types and their names. 141 */ 142static struct rl_type rl_devs[] = { 143 { RT_VENDORID, RT_DEVICEID_8129, RL_8129, 144 "RealTek 8129 10/100BaseTX" }, 145 { RT_VENDORID, RT_DEVICEID_8139, RL_8139, 146 "RealTek 8139 10/100BaseTX" }, 147 { RT_VENDORID, RT_DEVICEID_8139D, RL_8139, 148 "RealTek 8139 10/100BaseTX" }, 149 { RT_VENDORID, RT_DEVICEID_8138, RL_8139, 150 "RealTek 8139 10/100BaseTX CardBus" }, 151 { RT_VENDORID, RT_DEVICEID_8100, RL_8139, 152 "RealTek 8100 10/100BaseTX" }, 153 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 154 "Accton MPX 5030/5038 10/100BaseTX" }, 155 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139, 156 "Delta Electronics 8139 10/100BaseTX" }, 157 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139, 158 "Addtron Technolgy 8139 10/100BaseTX" }, 159 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139, 160 "D-Link DFE-530TX+ 10/100BaseTX" }, 161 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139, 162 "D-Link DFE-690TXD 10/100BaseTX" }, 163 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 164 "Nortel Networks 10/100BaseTX" }, 165 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139, 166 "Corega FEther CB-TXD" }, 167 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139, 168 "Corega FEtherII CB-TXD" }, 169 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139, 170 "Peppercon AG ROL-F" }, 171 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139, 172 "Planex FNW-3603-TX" }, 173 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139, 174 "Planex FNW-3800-TX" }, 175 { CP_VENDORID, RT_DEVICEID_8139, RL_8139, 176 "Compaq HNE-300" }, 177 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139, 178 "LevelOne FPC-0106TX" }, 179 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139, 180 "Edimax EP-4103DL CardBus" } 181}; 182 183static int rl_attach(device_t); 184static int rl_detach(device_t); 185static void rl_dmamap_cb(void *, bus_dma_segment_t *, int, int); 186static int rl_dma_alloc(struct rl_softc *); 187static void rl_dma_free(struct rl_softc *); 188static void rl_eeprom_putbyte(struct rl_softc *, int); 189static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *); 190static int rl_encap(struct rl_softc *, struct mbuf **); 191static int rl_list_tx_init(struct rl_softc *); 192static int rl_list_rx_init(struct rl_softc *); 193static int rl_ifmedia_upd(struct ifnet *); 194static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 195static int rl_ioctl(struct ifnet *, u_long, caddr_t); 196static void rl_intr(void *); 197static void rl_init(void *); 198static void rl_init_locked(struct rl_softc *sc); 199static void rl_mii_send(struct rl_softc *, uint32_t, int); 200static void rl_mii_sync(struct rl_softc *); 201static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *); 202static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *); 203static int rl_miibus_readreg(device_t, int, int); 204static void rl_miibus_statchg(device_t); 205static int rl_miibus_writereg(device_t, int, int, int); 206#ifdef DEVICE_POLLING 207static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 208static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); 209#endif 210static int rl_probe(device_t); 211static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int); 212static void rl_reset(struct rl_softc *); 213static int rl_resume(device_t); 214static void rl_rxeof(struct rl_softc *); 215static void rl_setmulti(struct rl_softc *); 216static int rl_shutdown(device_t); 217static void rl_start(struct ifnet *); 218static void rl_start_locked(struct ifnet *); 219static void rl_stop(struct rl_softc *); 220static int rl_suspend(device_t); 221static void rl_tick(void *); 222static void rl_txeof(struct rl_softc *); 223static void rl_watchdog(struct rl_softc *); 224 225#ifdef RL_USEIOSPACE 226#define RL_RES SYS_RES_IOPORT 227#define RL_RID RL_PCI_LOIO 228#else 229#define RL_RES SYS_RES_MEMORY 230#define RL_RID RL_PCI_LOMEM 231#endif 232 233static device_method_t rl_methods[] = { 234 /* Device interface */ 235 DEVMETHOD(device_probe, rl_probe), 236 DEVMETHOD(device_attach, rl_attach), 237 DEVMETHOD(device_detach, rl_detach), 238 DEVMETHOD(device_suspend, rl_suspend), 239 DEVMETHOD(device_resume, rl_resume), 240 DEVMETHOD(device_shutdown, rl_shutdown), 241 242 /* bus interface */ 243 DEVMETHOD(bus_print_child, bus_generic_print_child), 244 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 245 246 /* MII interface */ 247 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 248 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 249 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 250 251 { 0, 0 } 252}; 253 254static driver_t rl_driver = { 255 "rl", 256 rl_methods, 257 sizeof(struct rl_softc) 258}; 259 260static devclass_t rl_devclass; 261 262DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0); 263DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0); 264DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 265 266#define EE_SET(x) \ 267 CSR_WRITE_1(sc, RL_EECMD, \ 268 CSR_READ_1(sc, RL_EECMD) | x) 269 270#define EE_CLR(x) \ 271 CSR_WRITE_1(sc, RL_EECMD, \ 272 CSR_READ_1(sc, RL_EECMD) & ~x) 273 274/* 275 * Send a read command and address to the EEPROM, check for ACK. 276 */ 277static void 278rl_eeprom_putbyte(struct rl_softc *sc, int addr) 279{ 280 register int d, i; 281 282 d = addr | sc->rl_eecmd_read; 283 284 /* 285 * Feed in each bit and strobe the clock. 286 */ 287 for (i = 0x400; i; i >>= 1) { 288 if (d & i) { 289 EE_SET(RL_EE_DATAIN); 290 } else { 291 EE_CLR(RL_EE_DATAIN); 292 } 293 DELAY(100); 294 EE_SET(RL_EE_CLK); 295 DELAY(150); 296 EE_CLR(RL_EE_CLK); 297 DELAY(100); 298 } 299} 300 301/* 302 * Read a word of data stored in the EEPROM at address 'addr.' 303 */ 304static void 305rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest) 306{ 307 register int i; 308 uint16_t word = 0; 309 310 /* Enter EEPROM access mode. */ 311 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 312 313 /* 314 * Send address of word we want to read. 315 */ 316 rl_eeprom_putbyte(sc, addr); 317 318 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 319 320 /* 321 * Start reading bits from EEPROM. 322 */ 323 for (i = 0x8000; i; i >>= 1) { 324 EE_SET(RL_EE_CLK); 325 DELAY(100); 326 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 327 word |= i; 328 EE_CLR(RL_EE_CLK); 329 DELAY(100); 330 } 331 332 /* Turn off EEPROM access mode. */ 333 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 334 335 *dest = word; 336} 337 338/* 339 * Read a sequence of words from the EEPROM. 340 */ 341static void 342rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap) 343{ 344 int i; 345 uint16_t word = 0, *ptr; 346 347 for (i = 0; i < cnt; i++) { 348 rl_eeprom_getword(sc, off + i, &word); 349 ptr = (uint16_t *)(dest + (i * 2)); 350 if (swap) 351 *ptr = ntohs(word); 352 else 353 *ptr = word; 354 } 355} 356 357/* 358 * MII access routines are provided for the 8129, which 359 * doesn't have a built-in PHY. For the 8139, we fake things 360 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 361 * direct access PHY registers. 362 */ 363#define MII_SET(x) \ 364 CSR_WRITE_1(sc, RL_MII, \ 365 CSR_READ_1(sc, RL_MII) | (x)) 366 367#define MII_CLR(x) \ 368 CSR_WRITE_1(sc, RL_MII, \ 369 CSR_READ_1(sc, RL_MII) & ~(x)) 370 371/* 372 * Sync the PHYs by setting data bit and strobing the clock 32 times. 373 */ 374static void 375rl_mii_sync(struct rl_softc *sc) 376{ 377 register int i; 378 379 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 380 381 for (i = 0; i < 32; i++) { 382 MII_SET(RL_MII_CLK); 383 DELAY(1); 384 MII_CLR(RL_MII_CLK); 385 DELAY(1); 386 } 387} 388 389/* 390 * Clock a series of bits through the MII. 391 */ 392static void 393rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt) 394{ 395 int i; 396 397 MII_CLR(RL_MII_CLK); 398 399 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 400 if (bits & i) { 401 MII_SET(RL_MII_DATAOUT); 402 } else { 403 MII_CLR(RL_MII_DATAOUT); 404 } 405 DELAY(1); 406 MII_CLR(RL_MII_CLK); 407 DELAY(1); 408 MII_SET(RL_MII_CLK); 409 } 410} 411 412/* 413 * Read an PHY register through the MII. 414 */ 415static int 416rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame) 417{ 418 int i, ack; 419 420 /* Set up frame for RX. */ 421 frame->mii_stdelim = RL_MII_STARTDELIM; 422 frame->mii_opcode = RL_MII_READOP; 423 frame->mii_turnaround = 0; 424 frame->mii_data = 0; 425 426 CSR_WRITE_2(sc, RL_MII, 0); 427 428 /* Turn on data xmit. */ 429 MII_SET(RL_MII_DIR); 430 431 rl_mii_sync(sc); 432 433 /* Send command/address info. */ 434 rl_mii_send(sc, frame->mii_stdelim, 2); 435 rl_mii_send(sc, frame->mii_opcode, 2); 436 rl_mii_send(sc, frame->mii_phyaddr, 5); 437 rl_mii_send(sc, frame->mii_regaddr, 5); 438 439 /* Idle bit */ 440 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 441 DELAY(1); 442 MII_SET(RL_MII_CLK); 443 DELAY(1); 444 445 /* Turn off xmit. */ 446 MII_CLR(RL_MII_DIR); 447 448 /* Check for ack */ 449 MII_CLR(RL_MII_CLK); 450 DELAY(1); 451 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 452 MII_SET(RL_MII_CLK); 453 DELAY(1); 454 455 /* 456 * Now try reading data bits. If the ack failed, we still 457 * need to clock through 16 cycles to keep the PHY(s) in sync. 458 */ 459 if (ack) { 460 for(i = 0; i < 16; i++) { 461 MII_CLR(RL_MII_CLK); 462 DELAY(1); 463 MII_SET(RL_MII_CLK); 464 DELAY(1); 465 } 466 goto fail; 467 } 468 469 for (i = 0x8000; i; i >>= 1) { 470 MII_CLR(RL_MII_CLK); 471 DELAY(1); 472 if (!ack) { 473 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 474 frame->mii_data |= i; 475 DELAY(1); 476 } 477 MII_SET(RL_MII_CLK); 478 DELAY(1); 479 } 480 481fail: 482 MII_CLR(RL_MII_CLK); 483 DELAY(1); 484 MII_SET(RL_MII_CLK); 485 DELAY(1); 486 487 return (ack ? 1 : 0); 488} 489 490/* 491 * Write to a PHY register through the MII. 492 */ 493static int 494rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame) 495{ 496 497 /* Set up frame for TX. */ 498 frame->mii_stdelim = RL_MII_STARTDELIM; 499 frame->mii_opcode = RL_MII_WRITEOP; 500 frame->mii_turnaround = RL_MII_TURNAROUND; 501 502 /* Turn on data output. */ 503 MII_SET(RL_MII_DIR); 504 505 rl_mii_sync(sc); 506 507 rl_mii_send(sc, frame->mii_stdelim, 2); 508 rl_mii_send(sc, frame->mii_opcode, 2); 509 rl_mii_send(sc, frame->mii_phyaddr, 5); 510 rl_mii_send(sc, frame->mii_regaddr, 5); 511 rl_mii_send(sc, frame->mii_turnaround, 2); 512 rl_mii_send(sc, frame->mii_data, 16); 513 514 /* Idle bit. */ 515 MII_SET(RL_MII_CLK); 516 DELAY(1); 517 MII_CLR(RL_MII_CLK); 518 DELAY(1); 519 520 /* Turn off xmit. */ 521 MII_CLR(RL_MII_DIR); 522 523 return (0); 524} 525 526static int 527rl_miibus_readreg(device_t dev, int phy, int reg) 528{ 529 struct rl_softc *sc; 530 struct rl_mii_frame frame; 531 uint16_t rval = 0; 532 uint16_t rl8139_reg = 0; 533 534 sc = device_get_softc(dev); 535 536 if (sc->rl_type == RL_8139) { 537 /* Pretend the internal PHY is only at address 0 */ 538 if (phy) { 539 return (0); 540 } 541 switch (reg) { 542 case MII_BMCR: 543 rl8139_reg = RL_BMCR; 544 break; 545 case MII_BMSR: 546 rl8139_reg = RL_BMSR; 547 break; 548 case MII_ANAR: 549 rl8139_reg = RL_ANAR; 550 break; 551 case MII_ANER: 552 rl8139_reg = RL_ANER; 553 break; 554 case MII_ANLPAR: 555 rl8139_reg = RL_LPAR; 556 break; 557 case MII_PHYIDR1: 558 case MII_PHYIDR2: 559 return (0); 560 /* 561 * Allow the rlphy driver to read the media status 562 * register. If we have a link partner which does not 563 * support NWAY, this is the register which will tell 564 * us the results of parallel detection. 565 */ 566 case RL_MEDIASTAT: 567 rval = CSR_READ_1(sc, RL_MEDIASTAT); 568 return (rval); 569 default: 570 device_printf(sc->rl_dev, "bad phy register\n"); 571 return (0); 572 } 573 rval = CSR_READ_2(sc, rl8139_reg); 574 return (rval); 575 } 576 577 bzero((char *)&frame, sizeof(frame)); 578 frame.mii_phyaddr = phy; 579 frame.mii_regaddr = reg; 580 rl_mii_readreg(sc, &frame); 581 582 return (frame.mii_data); 583} 584 585static int 586rl_miibus_writereg(device_t dev, int phy, int reg, int data) 587{ 588 struct rl_softc *sc; 589 struct rl_mii_frame frame; 590 uint16_t rl8139_reg = 0; 591 592 sc = device_get_softc(dev); 593 594 if (sc->rl_type == RL_8139) { 595 /* Pretend the internal PHY is only at address 0 */ 596 if (phy) { 597 return (0); 598 } 599 switch (reg) { 600 case MII_BMCR: 601 rl8139_reg = RL_BMCR; 602 break; 603 case MII_BMSR: 604 rl8139_reg = RL_BMSR; 605 break; 606 case MII_ANAR: 607 rl8139_reg = RL_ANAR; 608 break; 609 case MII_ANER: 610 rl8139_reg = RL_ANER; 611 break; 612 case MII_ANLPAR: 613 rl8139_reg = RL_LPAR; 614 break; 615 case MII_PHYIDR1: 616 case MII_PHYIDR2: 617 return (0); 618 break; 619 default: 620 device_printf(sc->rl_dev, "bad phy register\n"); 621 return (0); 622 } 623 CSR_WRITE_2(sc, rl8139_reg, data); 624 return (0); 625 } 626 627 bzero((char *)&frame, sizeof(frame)); 628 frame.mii_phyaddr = phy; 629 frame.mii_regaddr = reg; 630 frame.mii_data = data; 631 rl_mii_writereg(sc, &frame); 632 633 return (0); 634} 635 636static void 637rl_miibus_statchg(device_t dev) 638{ 639} 640 641/* 642 * Program the 64-bit multicast hash filter. 643 */ 644static void 645rl_setmulti(struct rl_softc *sc) 646{ 647 struct ifnet *ifp = sc->rl_ifp; 648 int h = 0; 649 uint32_t hashes[2] = { 0, 0 }; 650 struct ifmultiaddr *ifma; 651 uint32_t rxfilt; 652 int mcnt = 0; 653 654 RL_LOCK_ASSERT(sc); 655 656 rxfilt = CSR_READ_4(sc, RL_RXCFG); 657 658 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 659 rxfilt |= RL_RXCFG_RX_MULTI; 660 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 661 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 662 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 663 return; 664 } 665 666 /* first, zot all the existing hash bits */ 667 CSR_WRITE_4(sc, RL_MAR0, 0); 668 CSR_WRITE_4(sc, RL_MAR4, 0); 669 670 /* now program new ones */ 671 IF_ADDR_LOCK(ifp); 672 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 673 if (ifma->ifma_addr->sa_family != AF_LINK) 674 continue; 675 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 676 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 677 if (h < 32) 678 hashes[0] |= (1 << h); 679 else 680 hashes[1] |= (1 << (h - 32)); 681 mcnt++; 682 } 683 IF_ADDR_UNLOCK(ifp); 684 685 if (mcnt) 686 rxfilt |= RL_RXCFG_RX_MULTI; 687 else 688 rxfilt &= ~RL_RXCFG_RX_MULTI; 689 690 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 691 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 692 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 693} 694 695static void 696rl_reset(struct rl_softc *sc) 697{ 698 register int i; 699 700 RL_LOCK_ASSERT(sc); 701 702 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 703 704 for (i = 0; i < RL_TIMEOUT; i++) { 705 DELAY(10); 706 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 707 break; 708 } 709 if (i == RL_TIMEOUT) 710 device_printf(sc->rl_dev, "reset never completed!\n"); 711} 712 713/* 714 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 715 * IDs against our list and return a device name if we find a match. 716 */ 717static int 718rl_probe(device_t dev) 719{ 720 struct rl_type *t; 721 uint16_t devid, revid, vendor; 722 int i; 723 724 vendor = pci_get_vendor(dev); 725 devid = pci_get_device(dev); 726 revid = pci_get_revid(dev); 727 728 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 729 if (revid == 0x20) { 730 /* 8139C+, let re(4) take care of this device. */ 731 return (ENXIO); 732 } 733 } 734 t = rl_devs; 735 for (i = 0; i < sizeof(rl_devs) / sizeof(rl_devs[0]); i++, t++) { 736 if (vendor == t->rl_vid && devid == t->rl_did) { 737 device_set_desc(dev, t->rl_name); 738 return (BUS_PROBE_DEFAULT); 739 } 740 } 741 742 return (ENXIO); 743} 744 745struct rl_dmamap_arg { 746 bus_addr_t rl_busaddr; 747}; 748 749static void 750rl_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 751{ 752 struct rl_dmamap_arg *ctx; 753 754 if (error != 0) 755 return; 756 757 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 758 759 ctx = (struct rl_dmamap_arg *)arg; 760 ctx->rl_busaddr = segs[0].ds_addr; 761} 762 763/* 764 * Attach the interface. Allocate softc structures, do ifmedia 765 * setup and ethernet/BPF attach. 766 */ 767static int 768rl_attach(device_t dev) 769{ 770 uint8_t eaddr[ETHER_ADDR_LEN]; 771 uint16_t as[3]; 772 struct ifnet *ifp; 773 struct rl_softc *sc; 774 struct rl_type *t; 775 int error = 0, i, rid; 776 int unit; 777 uint16_t rl_did = 0; 778 779 sc = device_get_softc(dev); 780 unit = device_get_unit(dev); 781 sc->rl_dev = dev; 782 783 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 784 MTX_DEF); 785 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 786 787 pci_enable_busmaster(dev); 788 789 /* Map control/status registers. */ 790 rid = RL_RID; 791 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE); 792 793 if (sc->rl_res == NULL) { 794 device_printf(dev, "couldn't map ports/memory\n"); 795 error = ENXIO; 796 goto fail; 797 } 798 799#ifdef notdef 800 /* 801 * Detect the Realtek 8139B. For some reason, this chip is very 802 * unstable when left to autoselect the media 803 * The best workaround is to set the device to the required 804 * media type or to set it to the 10 Meg speed. 805 */ 806 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF) 807 device_printf(dev, 808"Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n"); 809#endif 810 811 sc->rl_btag = rman_get_bustag(sc->rl_res); 812 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 813 814 /* Allocate interrupt */ 815 rid = 0; 816 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 817 RF_SHAREABLE | RF_ACTIVE); 818 819 if (sc->rl_irq[0] == NULL) { 820 device_printf(dev, "couldn't map interrupt\n"); 821 error = ENXIO; 822 goto fail; 823 } 824 825 /* 826 * Reset the adapter. Only take the lock here as it's needed in 827 * order to call rl_reset(). 828 */ 829 RL_LOCK(sc); 830 rl_reset(sc); 831 RL_UNLOCK(sc); 832 833 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 834 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0); 835 if (rl_did != 0x8129) 836 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 837 838 /* 839 * Get station address from the EEPROM. 840 */ 841 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0); 842 for (i = 0; i < 3; i++) { 843 eaddr[(i * 2) + 0] = as[i] & 0xff; 844 eaddr[(i * 2) + 1] = as[i] >> 8; 845 } 846 847 /* 848 * Now read the exact device type from the EEPROM to find 849 * out if it's an 8129 or 8139. 850 */ 851 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0); 852 853 t = rl_devs; 854 sc->rl_type = 0; 855 while(t->rl_name != NULL) { 856 if (rl_did == t->rl_did) { 857 sc->rl_type = t->rl_basetype; 858 break; 859 } 860 t++; 861 } 862 863 if (sc->rl_type == 0) { 864 device_printf(dev, "unknown device ID: %x\n", rl_did); 865 error = ENXIO; 866 goto fail; 867 } 868 869 if ((error = rl_dma_alloc(sc)) != 0) 870 goto fail; 871 872 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 873 if (ifp == NULL) { 874 device_printf(dev, "can not if_alloc()\n"); 875 error = ENOSPC; 876 goto fail; 877 } 878 879 /* Do MII setup */ 880 if (mii_phy_probe(dev, &sc->rl_miibus, 881 rl_ifmedia_upd, rl_ifmedia_sts)) { 882 device_printf(dev, "MII without any phy!\n"); 883 error = ENXIO; 884 goto fail; 885 } 886 887 ifp->if_softc = sc; 888 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 889 ifp->if_mtu = ETHERMTU; 890 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 891 ifp->if_ioctl = rl_ioctl; 892 ifp->if_start = rl_start; 893 ifp->if_init = rl_init; 894 ifp->if_capabilities = IFCAP_VLAN_MTU; 895 ifp->if_capenable = ifp->if_capabilities; 896#ifdef DEVICE_POLLING 897 ifp->if_capabilities |= IFCAP_POLLING; 898#endif 899 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 900 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 901 IFQ_SET_READY(&ifp->if_snd); 902 903 /* 904 * Call MI attach routine. 905 */ 906 ether_ifattach(ifp, eaddr); 907 908 /* Hook interrupt last to avoid having to lock softc */ 909 error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE, 910 NULL, rl_intr, sc, &sc->rl_intrhand[0]); 911 if (error) { 912 device_printf(sc->rl_dev, "couldn't set up irq\n"); 913 ether_ifdetach(ifp); 914 } 915 916fail: 917 if (error) 918 rl_detach(dev); 919 920 return (error); 921} 922 923/* 924 * Shutdown hardware and free up resources. This can be called any 925 * time after the mutex has been initialized. It is called in both 926 * the error case in attach and the normal detach case so it needs 927 * to be careful about only freeing resources that have actually been 928 * allocated. 929 */ 930static int 931rl_detach(device_t dev) 932{ 933 struct rl_softc *sc; 934 struct ifnet *ifp; 935 936 sc = device_get_softc(dev); 937 ifp = sc->rl_ifp; 938 939 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 940 941#ifdef DEVICE_POLLING 942 if (ifp->if_capenable & IFCAP_POLLING) 943 ether_poll_deregister(ifp); 944#endif 945 /* These should only be active if attach succeeded */ 946 if (device_is_attached(dev)) { 947 RL_LOCK(sc); 948 rl_stop(sc); 949 RL_UNLOCK(sc); 950 callout_drain(&sc->rl_stat_callout); 951 ether_ifdetach(ifp); 952 } 953#if 0 954 sc->suspended = 1; 955#endif 956 if (sc->rl_miibus) 957 device_delete_child(dev, sc->rl_miibus); 958 bus_generic_detach(dev); 959 960 if (sc->rl_intrhand[0]) 961 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 962 if (sc->rl_irq[0]) 963 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]); 964 if (sc->rl_res) 965 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 966 967 if (ifp) 968 if_free(ifp); 969 970 rl_dma_free(sc); 971 972 mtx_destroy(&sc->rl_mtx); 973 974 return (0); 975} 976 977static int 978rl_dma_alloc(struct rl_softc *sc) 979{ 980 struct rl_dmamap_arg ctx; 981 int error, i; 982 983 /* 984 * Allocate the parent bus DMA tag appropriate for PCI. 985 */ 986 error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev), /* parent */ 987 1, 0, /* alignment, boundary */ 988 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 989 BUS_SPACE_MAXADDR, /* highaddr */ 990 NULL, NULL, /* filter, filterarg */ 991 BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */ 992 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 993 0, /* flags */ 994 NULL, NULL, /* lockfunc, lockarg */ 995 &sc->rl_parent_tag); 996 if (error) { 997 device_printf(sc->rl_dev, 998 "failed to create parent DMA tag.\n"); 999 goto fail; 1000 } 1001 /* Create DMA tag for Rx memory block. */ 1002 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 1003 RL_RX_8139_BUF_ALIGN, 0, /* alignment, boundary */ 1004 BUS_SPACE_MAXADDR, /* lowaddr */ 1005 BUS_SPACE_MAXADDR, /* highaddr */ 1006 NULL, NULL, /* filter, filterarg */ 1007 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, 1, /* maxsize,nsegments */ 1008 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, /* maxsegsize */ 1009 0, /* flags */ 1010 NULL, NULL, /* lockfunc, lockarg */ 1011 &sc->rl_cdata.rl_rx_tag); 1012 if (error) { 1013 device_printf(sc->rl_dev, 1014 "failed to create Rx memory block DMA tag.\n"); 1015 goto fail; 1016 } 1017 /* Create DMA tag for Tx buffer. */ 1018 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 1019 RL_TX_8139_BUF_ALIGN, 0, /* alignment, boundary */ 1020 BUS_SPACE_MAXADDR, /* lowaddr */ 1021 BUS_SPACE_MAXADDR, /* highaddr */ 1022 NULL, NULL, /* filter, filterarg */ 1023 MCLBYTES, 1, /* maxsize, nsegments */ 1024 MCLBYTES, /* maxsegsize */ 1025 0, /* flags */ 1026 NULL, NULL, /* lockfunc, lockarg */ 1027 &sc->rl_cdata.rl_tx_tag); 1028 if (error) { 1029 device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n"); 1030 goto fail; 1031 } 1032 1033 /* 1034 * Allocate DMA'able memory and load DMA map for Rx memory block. 1035 */ 1036 error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag, 1037 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK | 1038 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap); 1039 if (error != 0) { 1040 device_printf(sc->rl_dev, 1041 "failed to allocate Rx DMA memory block.\n"); 1042 goto fail; 1043 } 1044 ctx.rl_busaddr = 0; 1045 error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag, 1046 sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf, 1047 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, rl_dmamap_cb, &ctx, 1048 BUS_DMA_NOWAIT); 1049 if (error != 0 || ctx.rl_busaddr == 0) { 1050 device_printf(sc->rl_dev, 1051 "could not load Rx DMA memory block.\n"); 1052 goto fail; 1053 } 1054 sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr; 1055 1056 /* Create DMA maps for Tx buffers. */ 1057 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1058 sc->rl_cdata.rl_tx_chain[i] = NULL; 1059 sc->rl_cdata.rl_tx_dmamap[i] = NULL; 1060 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0, 1061 &sc->rl_cdata.rl_tx_dmamap[i]); 1062 if (error != 0) { 1063 device_printf(sc->rl_dev, 1064 "could not create Tx dmamap.\n"); 1065 goto fail; 1066 } 1067 } 1068 1069 /* Leave a few bytes before the start of the RX ring buffer. */ 1070 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1071 sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE; 1072 1073fail: 1074 return (error); 1075} 1076 1077static void 1078rl_dma_free(struct rl_softc *sc) 1079{ 1080 int i; 1081 1082 /* Rx memory block. */ 1083 if (sc->rl_cdata.rl_rx_tag != NULL) { 1084 if (sc->rl_cdata.rl_rx_dmamap != NULL) 1085 bus_dmamap_unload(sc->rl_cdata.rl_rx_tag, 1086 sc->rl_cdata.rl_rx_dmamap); 1087 if (sc->rl_cdata.rl_rx_dmamap != NULL && 1088 sc->rl_cdata.rl_rx_buf_ptr != NULL) 1089 bus_dmamem_free(sc->rl_cdata.rl_rx_tag, 1090 sc->rl_cdata.rl_rx_buf_ptr, 1091 sc->rl_cdata.rl_rx_dmamap); 1092 sc->rl_cdata.rl_rx_buf_ptr = NULL; 1093 sc->rl_cdata.rl_rx_buf = NULL; 1094 sc->rl_cdata.rl_rx_dmamap = NULL; 1095 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag); 1096 sc->rl_cdata.rl_tx_tag = NULL; 1097 } 1098 1099 /* Tx buffers. */ 1100 if (sc->rl_cdata.rl_tx_tag != NULL) { 1101 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1102 if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) { 1103 bus_dmamap_destroy( 1104 sc->rl_cdata.rl_tx_tag, 1105 sc->rl_cdata.rl_tx_dmamap[i]); 1106 sc->rl_cdata.rl_tx_dmamap[i] = NULL; 1107 } 1108 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag); 1109 sc->rl_cdata.rl_tx_tag = NULL; 1110 } 1111 } 1112 1113 if (sc->rl_parent_tag != NULL) { 1114 bus_dma_tag_destroy(sc->rl_parent_tag); 1115 sc->rl_parent_tag = NULL; 1116 } 1117} 1118 1119/* 1120 * Initialize the transmit descriptors. 1121 */ 1122static int 1123rl_list_tx_init(struct rl_softc *sc) 1124{ 1125 struct rl_chain_data *cd; 1126 int i; 1127 1128 RL_LOCK_ASSERT(sc); 1129 1130 cd = &sc->rl_cdata; 1131 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1132 cd->rl_tx_chain[i] = NULL; 1133 CSR_WRITE_4(sc, 1134 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000); 1135 } 1136 1137 sc->rl_cdata.cur_tx = 0; 1138 sc->rl_cdata.last_tx = 0; 1139 1140 return (0); 1141} 1142 1143static int 1144rl_list_rx_init(struct rl_softc *sc) 1145{ 1146 1147 RL_LOCK_ASSERT(sc); 1148 1149 bzero(sc->rl_cdata.rl_rx_buf_ptr, 1150 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ); 1151 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap, 1152 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1153 1154 return (0); 1155} 1156 1157/* 1158 * A frame has been uploaded: pass the resulting mbuf chain up to 1159 * the higher level protocols. 1160 * 1161 * You know there's something wrong with a PCI bus-master chip design 1162 * when you have to use m_devget(). 1163 * 1164 * The receive operation is badly documented in the datasheet, so I'll 1165 * attempt to document it here. The driver provides a buffer area and 1166 * places its base address in the RX buffer start address register. 1167 * The chip then begins copying frames into the RX buffer. Each frame 1168 * is preceded by a 32-bit RX status word which specifies the length 1169 * of the frame and certain other status bits. Each frame (starting with 1170 * the status word) is also 32-bit aligned. The frame length is in the 1171 * first 16 bits of the status word; the lower 15 bits correspond with 1172 * the 'rx status register' mentioned in the datasheet. 1173 * 1174 * Note: to make the Alpha happy, the frame payload needs to be aligned 1175 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1176 * as the offset argument to m_devget(). 1177 */ 1178static void 1179rl_rxeof(struct rl_softc *sc) 1180{ 1181 struct mbuf *m; 1182 struct ifnet *ifp = sc->rl_ifp; 1183 uint8_t *rxbufpos; 1184 int total_len = 0; 1185 int wrap = 0; 1186 uint32_t rxstat; 1187 uint16_t cur_rx; 1188 uint16_t limit; 1189 uint16_t max_bytes, rx_bytes = 0; 1190 1191 RL_LOCK_ASSERT(sc); 1192 1193 bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap, 1194 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1195 1196 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1197 1198 /* Do not try to read past this point. */ 1199 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1200 1201 if (limit < cur_rx) 1202 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1203 else 1204 max_bytes = limit - cur_rx; 1205 1206 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1207#ifdef DEVICE_POLLING 1208 if (ifp->if_capenable & IFCAP_POLLING) { 1209 if (sc->rxcycles <= 0) 1210 break; 1211 sc->rxcycles--; 1212 } 1213#endif 1214 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1215 rxstat = le32toh(*(uint32_t *)rxbufpos); 1216 1217 /* 1218 * Here's a totally undocumented fact for you. When the 1219 * RealTek chip is in the process of copying a packet into 1220 * RAM for you, the length will be 0xfff0. If you spot a 1221 * packet header with this value, you need to stop. The 1222 * datasheet makes absolutely no mention of this and 1223 * RealTek should be shot for this. 1224 */ 1225 total_len = rxstat >> 16; 1226 if (total_len == RL_RXSTAT_UNFINISHED) 1227 break; 1228 1229 if (!(rxstat & RL_RXSTAT_RXOK) || 1230 total_len < ETHER_MIN_LEN || 1231 total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 1232 ifp->if_ierrors++; 1233 rl_init_locked(sc); 1234 return; 1235 } 1236 1237 /* No errors; receive the packet. */ 1238 rx_bytes += total_len + 4; 1239 1240 /* 1241 * XXX The RealTek chip includes the CRC with every 1242 * received frame, and there's no way to turn this 1243 * behavior off (at least, I can't find anything in 1244 * the manual that explains how to do it) so we have 1245 * to trim off the CRC manually. 1246 */ 1247 total_len -= ETHER_CRC_LEN; 1248 1249 /* 1250 * Avoid trying to read more bytes than we know 1251 * the chip has prepared for us. 1252 */ 1253 if (rx_bytes > max_bytes) 1254 break; 1255 1256 rxbufpos = sc->rl_cdata.rl_rx_buf + 1257 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN); 1258 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1259 rxbufpos = sc->rl_cdata.rl_rx_buf; 1260 1261 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1262 if (total_len > wrap) { 1263 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1264 NULL); 1265 if (m == NULL) { 1266 ifp->if_ierrors++; 1267 } else { 1268 m_copyback(m, wrap, total_len - wrap, 1269 sc->rl_cdata.rl_rx_buf); 1270 } 1271 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1272 } else { 1273 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1274 NULL); 1275 if (m == NULL) 1276 ifp->if_ierrors++; 1277 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1278 } 1279 1280 /* Round up to 32-bit boundary. */ 1281 cur_rx = (cur_rx + 3) & ~3; 1282 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1283 1284 if (m == NULL) 1285 continue; 1286 1287 ifp->if_ipackets++; 1288 RL_UNLOCK(sc); 1289 (*ifp->if_input)(ifp, m); 1290 RL_LOCK(sc); 1291 } 1292 1293 /* No need to sync Rx memory block as we didn't mofify it. */ 1294} 1295 1296/* 1297 * A frame was downloaded to the chip. It's safe for us to clean up 1298 * the list buffers. 1299 */ 1300static void 1301rl_txeof(struct rl_softc *sc) 1302{ 1303 struct ifnet *ifp = sc->rl_ifp; 1304 uint32_t txstat; 1305 1306 RL_LOCK_ASSERT(sc); 1307 1308 /* 1309 * Go through our tx list and free mbufs for those 1310 * frames that have been uploaded. 1311 */ 1312 do { 1313 if (RL_LAST_TXMBUF(sc) == NULL) 1314 break; 1315 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1316 if (!(txstat & (RL_TXSTAT_TX_OK| 1317 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1318 break; 1319 1320 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1321 1322 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc), 1323 BUS_DMASYNC_POSTWRITE); 1324 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc)); 1325 m_freem(RL_LAST_TXMBUF(sc)); 1326 RL_LAST_TXMBUF(sc) = NULL; 1327 /* 1328 * If there was a transmit underrun, bump the TX threshold. 1329 * Make sure not to overflow the 63 * 32byte we can address 1330 * with the 6 available bit. 1331 */ 1332 if ((txstat & RL_TXSTAT_TX_UNDERRUN) && 1333 (sc->rl_txthresh < 2016)) 1334 sc->rl_txthresh += 32; 1335 if (txstat & RL_TXSTAT_TX_OK) 1336 ifp->if_opackets++; 1337 else { 1338 int oldthresh; 1339 ifp->if_oerrors++; 1340 if ((txstat & RL_TXSTAT_TXABRT) || 1341 (txstat & RL_TXSTAT_OUTOFWIN)) 1342 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1343 oldthresh = sc->rl_txthresh; 1344 /* error recovery */ 1345 rl_init_locked(sc); 1346 /* restore original threshold */ 1347 sc->rl_txthresh = oldthresh; 1348 return; 1349 } 1350 RL_INC(sc->rl_cdata.last_tx); 1351 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1352 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1353 1354 if (RL_LAST_TXMBUF(sc) == NULL) 1355 sc->rl_watchdog_timer = 0; 1356} 1357 1358static void 1359rl_tick(void *xsc) 1360{ 1361 struct rl_softc *sc = xsc; 1362 struct mii_data *mii; 1363 1364 RL_LOCK_ASSERT(sc); 1365 mii = device_get_softc(sc->rl_miibus); 1366 mii_tick(mii); 1367 1368 rl_watchdog(sc); 1369 1370 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc); 1371} 1372 1373#ifdef DEVICE_POLLING 1374static void 1375rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1376{ 1377 struct rl_softc *sc = ifp->if_softc; 1378 1379 RL_LOCK(sc); 1380 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1381 rl_poll_locked(ifp, cmd, count); 1382 RL_UNLOCK(sc); 1383} 1384 1385static void 1386rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1387{ 1388 struct rl_softc *sc = ifp->if_softc; 1389 1390 RL_LOCK_ASSERT(sc); 1391 1392 sc->rxcycles = count; 1393 rl_rxeof(sc); 1394 rl_txeof(sc); 1395 1396 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1397 rl_start_locked(ifp); 1398 1399 if (cmd == POLL_AND_CHECK_STATUS) { 1400 uint16_t status; 1401 1402 /* We should also check the status register. */ 1403 status = CSR_READ_2(sc, RL_ISR); 1404 if (status == 0xffff) 1405 return; 1406 if (status != 0) 1407 CSR_WRITE_2(sc, RL_ISR, status); 1408 1409 /* XXX We should check behaviour on receiver stalls. */ 1410 1411 if (status & RL_ISR_SYSTEM_ERR) 1412 rl_init_locked(sc); 1413 } 1414} 1415#endif /* DEVICE_POLLING */ 1416 1417static void 1418rl_intr(void *arg) 1419{ 1420 struct rl_softc *sc = arg; 1421 struct ifnet *ifp = sc->rl_ifp; 1422 uint16_t status; 1423 1424 RL_LOCK(sc); 1425 1426 if (sc->suspended) 1427 goto done_locked; 1428 1429#ifdef DEVICE_POLLING 1430 if (ifp->if_capenable & IFCAP_POLLING) 1431 goto done_locked; 1432#endif 1433 1434 for (;;) { 1435 status = CSR_READ_2(sc, RL_ISR); 1436 /* If the card has gone away, the read returns 0xffff. */ 1437 if (status == 0xffff) 1438 break; 1439 if (status != 0) 1440 CSR_WRITE_2(sc, RL_ISR, status); 1441 if ((status & RL_INTRS) == 0) 1442 break; 1443 if (status & RL_ISR_RX_OK) 1444 rl_rxeof(sc); 1445 if (status & RL_ISR_RX_ERR) 1446 rl_rxeof(sc); 1447 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1448 rl_txeof(sc); 1449 if (status & RL_ISR_SYSTEM_ERR) 1450 rl_init_locked(sc); 1451 } 1452 1453 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1454 rl_start_locked(ifp); 1455 1456done_locked: 1457 RL_UNLOCK(sc); 1458} 1459 1460/* 1461 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1462 * pointers to the fragment pointers. 1463 */ 1464static int 1465rl_encap(struct rl_softc *sc, struct mbuf **m_head) 1466{ 1467 struct mbuf *m; 1468 bus_dma_segment_t txsegs[1]; 1469 int error, nsegs, padlen; 1470 1471 RL_LOCK_ASSERT(sc); 1472 1473 m = *m_head; 1474 padlen = 0; 1475 /* 1476 * Hardware doesn't auto-pad, so we have to make sure 1477 * pad short frames out to the minimum frame length. 1478 */ 1479 if (m->m_pkthdr.len < RL_MIN_FRAMELEN) 1480 padlen = RL_MIN_FRAMELEN - m->m_pkthdr.len; 1481 /* 1482 * The RealTek is brain damaged and wants longword-aligned 1483 * TX buffers, plus we can only have one fragment buffer 1484 * per packet. We have to copy pretty much all the time. 1485 */ 1486 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0 || 1487 (padlen > 0 && M_TRAILINGSPACE(m) < padlen)) { 1488 m = m_defrag(*m_head, M_DONTWAIT); 1489 if (m == NULL) { 1490 m_freem(*m_head); 1491 *m_head = NULL; 1492 return (ENOMEM); 1493 } 1494 } 1495 *m_head = m; 1496 1497 if (padlen > 0) { 1498 /* 1499 * Make security concious people happy: zero out the 1500 * bytes in the pad area, since we don't know what 1501 * this mbuf cluster buffer's previous user might 1502 * have left in it. 1503 */ 1504 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1505 m->m_pkthdr.len += padlen; 1506 m->m_len = m->m_pkthdr.len; 1507 } 1508 1509 error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag, 1510 RL_CUR_DMAMAP(sc), m, txsegs, &nsegs, 0); 1511 if (error != 0) 1512 return (error); 1513 if (nsegs == 0) { 1514 m_freem(*m_head); 1515 *m_head = NULL; 1516 return (EIO); 1517 } 1518 1519 RL_CUR_TXMBUF(sc) = m; 1520 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc), 1521 BUS_DMASYNC_PREWRITE); 1522 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), RL_ADDR_LO(txsegs[0].ds_addr)); 1523 1524 return (0); 1525} 1526 1527/* 1528 * Main transmit routine. 1529 */ 1530static void 1531rl_start(struct ifnet *ifp) 1532{ 1533 struct rl_softc *sc = ifp->if_softc; 1534 1535 RL_LOCK(sc); 1536 rl_start_locked(ifp); 1537 RL_UNLOCK(sc); 1538} 1539 1540static void 1541rl_start_locked(struct ifnet *ifp) 1542{ 1543 struct rl_softc *sc = ifp->if_softc; 1544 struct mbuf *m_head = NULL; 1545 1546 RL_LOCK_ASSERT(sc); 1547 1548 while (RL_CUR_TXMBUF(sc) == NULL) { 1549 1550 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1551 1552 if (m_head == NULL) 1553 break; 1554 1555 if (rl_encap(sc, &m_head)) { 1556 if (m_head == NULL) 1557 break; 1558 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1559 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1560 break; 1561 } 1562 1563 /* Pass a copy of this mbuf chain to the bpf subsystem. */ 1564 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1565 1566 /* Transmit the frame. */ 1567 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1568 RL_TXTHRESH(sc->rl_txthresh) | 1569 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1570 1571 RL_INC(sc->rl_cdata.cur_tx); 1572 1573 /* Set a timeout in case the chip goes out to lunch. */ 1574 sc->rl_watchdog_timer = 5; 1575 } 1576 1577 /* 1578 * We broke out of the loop because all our TX slots are 1579 * full. Mark the NIC as busy until it drains some of the 1580 * packets from the queue. 1581 */ 1582 if (RL_CUR_TXMBUF(sc) != NULL) 1583 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1584} 1585 1586static void 1587rl_init(void *xsc) 1588{ 1589 struct rl_softc *sc = xsc; 1590 1591 RL_LOCK(sc); 1592 rl_init_locked(sc); 1593 RL_UNLOCK(sc); 1594} 1595 1596static void 1597rl_init_locked(struct rl_softc *sc) 1598{ 1599 struct ifnet *ifp = sc->rl_ifp; 1600 struct mii_data *mii; 1601 uint32_t rxcfg = 0; 1602 uint32_t eaddr[2]; 1603 1604 RL_LOCK_ASSERT(sc); 1605 1606 mii = device_get_softc(sc->rl_miibus); 1607 1608 /* 1609 * Cancel pending I/O and free all RX/TX buffers. 1610 */ 1611 rl_stop(sc); 1612 1613 rl_reset(sc); 1614 1615 /* 1616 * Init our MAC address. Even though the chipset 1617 * documentation doesn't mention it, we need to enter "Config 1618 * register write enable" mode to modify the ID registers. 1619 */ 1620 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1621 bzero(eaddr, sizeof(eaddr)); 1622 bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN); 1623 CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]); 1624 CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]); 1625 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1626 1627 /* Init the RX memory block pointer register. */ 1628 CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr + 1629 RL_RX_8139_BUF_RESERVE); 1630 /* Init TX descriptors. */ 1631 rl_list_tx_init(sc); 1632 /* Init Rx memory block. */ 1633 rl_list_rx_init(sc); 1634 1635 /* 1636 * Enable transmit and receive. 1637 */ 1638 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1639 1640 /* 1641 * Set the initial TX and RX configuration. 1642 */ 1643 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1644 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1645 1646 /* Set the individual bit to receive frames for this host only. */ 1647 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1648 rxcfg |= RL_RXCFG_RX_INDIV; 1649 1650 /* If we want promiscuous mode, set the allframes bit. */ 1651 if (ifp->if_flags & IFF_PROMISC) { 1652 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1653 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1654 } else { 1655 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1656 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1657 } 1658 1659 /* Set capture broadcast bit to capture broadcast frames. */ 1660 if (ifp->if_flags & IFF_BROADCAST) { 1661 rxcfg |= RL_RXCFG_RX_BROAD; 1662 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1663 } else { 1664 rxcfg &= ~RL_RXCFG_RX_BROAD; 1665 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1666 } 1667 1668 /* Program the multicast filter, if necessary. */ 1669 rl_setmulti(sc); 1670 1671#ifdef DEVICE_POLLING 1672 /* Disable interrupts if we are polling. */ 1673 if (ifp->if_capenable & IFCAP_POLLING) 1674 CSR_WRITE_2(sc, RL_IMR, 0); 1675 else 1676#endif 1677 /* Enable interrupts. */ 1678 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1679 1680 /* Set initial TX threshold */ 1681 sc->rl_txthresh = RL_TX_THRESH_INIT; 1682 1683 /* Start RX/TX process. */ 1684 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1685 1686 /* Enable receiver and transmitter. */ 1687 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1688 1689 mii_mediachg(mii); 1690 1691 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1692 1693 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1694 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1695 1696 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc); 1697} 1698 1699/* 1700 * Set media options. 1701 */ 1702static int 1703rl_ifmedia_upd(struct ifnet *ifp) 1704{ 1705 struct rl_softc *sc = ifp->if_softc; 1706 struct mii_data *mii; 1707 1708 mii = device_get_softc(sc->rl_miibus); 1709 1710 RL_LOCK(sc); 1711 mii_mediachg(mii); 1712 RL_UNLOCK(sc); 1713 1714 return (0); 1715} 1716 1717/* 1718 * Report current media status. 1719 */ 1720static void 1721rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1722{ 1723 struct rl_softc *sc = ifp->if_softc; 1724 struct mii_data *mii; 1725 1726 mii = device_get_softc(sc->rl_miibus); 1727 1728 RL_LOCK(sc); 1729 mii_pollstat(mii); 1730 RL_UNLOCK(sc); 1731 ifmr->ifm_active = mii->mii_media_active; 1732 ifmr->ifm_status = mii->mii_media_status; 1733} 1734 1735static int 1736rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1737{ 1738 struct ifreq *ifr = (struct ifreq *)data; 1739 struct mii_data *mii; 1740 struct rl_softc *sc = ifp->if_softc; 1741 int error = 0; 1742 1743 switch (command) { 1744 case SIOCSIFFLAGS: 1745 RL_LOCK(sc); 1746 if (ifp->if_flags & IFF_UP) { 1747 rl_init_locked(sc); 1748 } else { 1749 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1750 rl_stop(sc); 1751 } 1752 RL_UNLOCK(sc); 1753 error = 0; 1754 break; 1755 case SIOCADDMULTI: 1756 case SIOCDELMULTI: 1757 RL_LOCK(sc); 1758 rl_setmulti(sc); 1759 RL_UNLOCK(sc); 1760 error = 0; 1761 break; 1762 case SIOCGIFMEDIA: 1763 case SIOCSIFMEDIA: 1764 mii = device_get_softc(sc->rl_miibus); 1765 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1766 break; 1767 case SIOCSIFCAP: 1768#ifdef DEVICE_POLLING 1769 if (ifr->ifr_reqcap & IFCAP_POLLING && 1770 !(ifp->if_capenable & IFCAP_POLLING)) { 1771 error = ether_poll_register(rl_poll, ifp); 1772 if (error) 1773 return(error); 1774 RL_LOCK(sc); 1775 /* Disable interrupts */ 1776 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1777 ifp->if_capenable |= IFCAP_POLLING; 1778 RL_UNLOCK(sc); 1779 return (error); 1780 1781 } 1782 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1783 ifp->if_capenable & IFCAP_POLLING) { 1784 error = ether_poll_deregister(ifp); 1785 /* Enable interrupts. */ 1786 RL_LOCK(sc); 1787 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1788 ifp->if_capenable &= ~IFCAP_POLLING; 1789 RL_UNLOCK(sc); 1790 return (error); 1791 } 1792#endif /* DEVICE_POLLING */ 1793 break; 1794 default: 1795 error = ether_ioctl(ifp, command, data); 1796 break; 1797 } 1798 1799 return (error); 1800} 1801 1802static void 1803rl_watchdog(struct rl_softc *sc) 1804{ 1805 1806 RL_LOCK_ASSERT(sc); 1807 1808 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0) 1809 return; 1810 1811 device_printf(sc->rl_dev, "watchdog timeout\n"); 1812 sc->rl_ifp->if_oerrors++; 1813 1814 rl_txeof(sc); 1815 rl_rxeof(sc); 1816 rl_init_locked(sc); 1817} 1818 1819/* 1820 * Stop the adapter and free any mbufs allocated to the 1821 * RX and TX lists. 1822 */ 1823static void 1824rl_stop(struct rl_softc *sc) 1825{ 1826 register int i; 1827 struct ifnet *ifp = sc->rl_ifp; 1828 1829 RL_LOCK_ASSERT(sc); 1830 1831 sc->rl_watchdog_timer = 0; 1832 callout_stop(&sc->rl_stat_callout); 1833 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1834 1835 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1836 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1837 for (i = 0; i < RL_TIMEOUT; i++) { 1838 DELAY(10); 1839 if ((CSR_READ_1(sc, RL_COMMAND) & 1840 (RL_CMD_RX_ENB | RL_CMD_TX_ENB)) == 0) 1841 break; 1842 } 1843 if (i == RL_TIMEOUT) 1844 device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n"); 1845 1846 /* 1847 * Free the TX list buffers. 1848 */ 1849 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1850 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1851 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1852 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, 1853 sc->rl_cdata.rl_tx_dmamap[i], 1854 BUS_DMASYNC_POSTWRITE); 1855 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, 1856 sc->rl_cdata.rl_tx_dmamap[i]); 1857 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1858 sc->rl_cdata.rl_tx_chain[i] = NULL; 1859 } 1860 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 1861 0x0000000); 1862 } 1863 } 1864} 1865 1866/* 1867 * Device suspend routine. Stop the interface and save some PCI 1868 * settings in case the BIOS doesn't restore them properly on 1869 * resume. 1870 */ 1871static int 1872rl_suspend(device_t dev) 1873{ 1874 struct rl_softc *sc; 1875 1876 sc = device_get_softc(dev); 1877 1878 RL_LOCK(sc); 1879 rl_stop(sc); 1880 sc->suspended = 1; 1881 RL_UNLOCK(sc); 1882 1883 return (0); 1884} 1885 1886/* 1887 * Device resume routine. Restore some PCI settings in case the BIOS 1888 * doesn't, re-enable busmastering, and restart the interface if 1889 * appropriate. 1890 */ 1891static int 1892rl_resume(device_t dev) 1893{ 1894 struct rl_softc *sc; 1895 struct ifnet *ifp; 1896 1897 sc = device_get_softc(dev); 1898 ifp = sc->rl_ifp; 1899 1900 RL_LOCK(sc); 1901 1902 /* reinitialize interface if necessary */ 1903 if (ifp->if_flags & IFF_UP) 1904 rl_init_locked(sc); 1905 1906 sc->suspended = 0; 1907 1908 RL_UNLOCK(sc); 1909 1910 return (0); 1911} 1912 1913/* 1914 * Stop all chip I/O so that the kernel's probe routines don't 1915 * get confused by errant DMAs when rebooting. 1916 */ 1917static int 1918rl_shutdown(device_t dev) 1919{ 1920 struct rl_softc *sc; 1921 1922 sc = device_get_softc(dev); 1923 1924 RL_LOCK(sc); 1925 rl_stop(sc); 1926 RL_UNLOCK(sc); 1927 1928 return (0); 1929} 1930