if_rl.c revision 150968
1/*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 150968 2005-10-05 10:09:17Z glebius $"); 35 36/* 37 * RealTek 8129/8139 PCI NIC driver 38 * 39 * Supports several extremely cheap PCI 10/100 adapters based on 40 * the RealTek chipset. Datasheets can be obtained from 41 * www.realtek.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86#ifdef HAVE_KERNEL_OPTION_HEADERS 87#include "opt_device_polling.h" 88#endif 89 90#include <sys/param.h> 91#include <sys/endian.h> 92#include <sys/systm.h> 93#include <sys/sockio.h> 94#include <sys/mbuf.h> 95#include <sys/malloc.h> 96#include <sys/kernel.h> 97#include <sys/module.h> 98#include <sys/socket.h> 99 100#include <net/if.h> 101#include <net/if_arp.h> 102#include <net/ethernet.h> 103#include <net/if_dl.h> 104#include <net/if_media.h> 105#include <net/if_types.h> 106 107#include <net/bpf.h> 108 109#include <machine/bus.h> 110#include <machine/resource.h> 111#include <sys/bus.h> 112#include <sys/rman.h> 113 114#include <dev/mii/mii.h> 115#include <dev/mii/miivar.h> 116 117#include <dev/pci/pcireg.h> 118#include <dev/pci/pcivar.h> 119 120MODULE_DEPEND(rl, pci, 1, 1, 1); 121MODULE_DEPEND(rl, ether, 1, 1, 1); 122MODULE_DEPEND(rl, miibus, 1, 1, 1); 123 124/* "controller miibus0" required. See GENERIC if you get errors here. */ 125#include "miibus_if.h" 126 127/* 128 * Default to using PIO access for this driver. On SMP systems, 129 * there appear to be problems with memory mapped mode: it looks like 130 * doing too many memory mapped access back to back in rapid succession 131 * can hang the bus. I'm inclined to blame this on crummy design/construction 132 * on the part of RealTek. Memory mapped mode does appear to work on 133 * uniprocessor systems though. 134 */ 135#define RL_USEIOSPACE 136 137#include <pci/if_rlreg.h> 138 139/* 140 * Various supported device vendors/types and their names. 141 */ 142static struct rl_type rl_devs[] = { 143 { RT_VENDORID, RT_DEVICEID_8129, RL_8129, 144 "RealTek 8129 10/100BaseTX" }, 145 { RT_VENDORID, RT_DEVICEID_8139, RL_8139, 146 "RealTek 8139 10/100BaseTX" }, 147 { RT_VENDORID, RT_DEVICEID_8138, RL_8139, 148 "RealTek 8139 10/100BaseTX CardBus" }, 149 { RT_VENDORID, RT_DEVICEID_8100, RL_8139, 150 "RealTek 8100 10/100BaseTX" }, 151 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 152 "Accton MPX 5030/5038 10/100BaseTX" }, 153 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139, 154 "Delta Electronics 8139 10/100BaseTX" }, 155 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139, 156 "Addtron Technolgy 8139 10/100BaseTX" }, 157 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139, 158 "D-Link DFE-530TX+ 10/100BaseTX" }, 159 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139, 160 "D-Link DFE-690TXD 10/100BaseTX" }, 161 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 162 "Nortel Networks 10/100BaseTX" }, 163 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139, 164 "Corega FEther CB-TXD" }, 165 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139, 166 "Corega FEtherII CB-TXD" }, 167 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139, 168 "Peppercon AG ROL-F" }, 169 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139, 170 "Planex FNW-3800-TX" }, 171 { CP_VENDORID, RT_DEVICEID_8139, RL_8139, 172 "Compaq HNE-300" }, 173 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139, 174 "LevelOne FPC-0106TX" }, 175 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139, 176 "Edimax EP-4103DL CardBus" }, 177 { 0, 0, 0, NULL } 178}; 179 180static int rl_attach(device_t); 181static int rl_detach(device_t); 182static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int); 183static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int); 184static void rl_eeprom_putbyte(struct rl_softc *, int); 185static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *); 186static int rl_encap(struct rl_softc *, struct mbuf * ); 187static int rl_list_tx_init(struct rl_softc *); 188static int rl_ifmedia_upd(struct ifnet *); 189static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 190static int rl_ioctl(struct ifnet *, u_long, caddr_t); 191static void rl_intr(void *); 192static void rl_init(void *); 193static void rl_init_locked(struct rl_softc *sc); 194static void rl_mii_send(struct rl_softc *, uint32_t, int); 195static void rl_mii_sync(struct rl_softc *); 196static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *); 197static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *); 198static int rl_miibus_readreg(device_t, int, int); 199static void rl_miibus_statchg(device_t); 200static int rl_miibus_writereg(device_t, int, int, int); 201#ifdef DEVICE_POLLING 202static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 203static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); 204#endif 205static int rl_probe(device_t); 206static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int); 207static void rl_reset(struct rl_softc *); 208static int rl_resume(device_t); 209static void rl_rxeof(struct rl_softc *); 210static void rl_setmulti(struct rl_softc *); 211static void rl_shutdown(device_t); 212static void rl_start(struct ifnet *); 213static void rl_start_locked(struct ifnet *); 214static void rl_stop(struct rl_softc *); 215static int rl_suspend(device_t); 216static void rl_tick(void *); 217static void rl_txeof(struct rl_softc *); 218static void rl_watchdog(struct ifnet *); 219 220#ifdef RL_USEIOSPACE 221#define RL_RES SYS_RES_IOPORT 222#define RL_RID RL_PCI_LOIO 223#else 224#define RL_RES SYS_RES_MEMORY 225#define RL_RID RL_PCI_LOMEM 226#endif 227 228static device_method_t rl_methods[] = { 229 /* Device interface */ 230 DEVMETHOD(device_probe, rl_probe), 231 DEVMETHOD(device_attach, rl_attach), 232 DEVMETHOD(device_detach, rl_detach), 233 DEVMETHOD(device_suspend, rl_suspend), 234 DEVMETHOD(device_resume, rl_resume), 235 DEVMETHOD(device_shutdown, rl_shutdown), 236 237 /* bus interface */ 238 DEVMETHOD(bus_print_child, bus_generic_print_child), 239 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 240 241 /* MII interface */ 242 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 243 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 244 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 245 246 { 0, 0 } 247}; 248 249static driver_t rl_driver = { 250 "rl", 251 rl_methods, 252 sizeof(struct rl_softc) 253}; 254 255static devclass_t rl_devclass; 256 257DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0); 258DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0); 259DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 260 261#define EE_SET(x) \ 262 CSR_WRITE_1(sc, RL_EECMD, \ 263 CSR_READ_1(sc, RL_EECMD) | x) 264 265#define EE_CLR(x) \ 266 CSR_WRITE_1(sc, RL_EECMD, \ 267 CSR_READ_1(sc, RL_EECMD) & ~x) 268 269static void 270rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) 271{ 272 struct rl_softc *sc = arg; 273 274 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 275} 276 277static void 278rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) 279{ 280 struct rl_softc *sc = arg; 281 282 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 283} 284 285/* 286 * Send a read command and address to the EEPROM, check for ACK. 287 */ 288static void 289rl_eeprom_putbyte(struct rl_softc *sc, int addr) 290{ 291 register int d, i; 292 293 d = addr | sc->rl_eecmd_read; 294 295 /* 296 * Feed in each bit and strobe the clock. 297 */ 298 for (i = 0x400; i; i >>= 1) { 299 if (d & i) { 300 EE_SET(RL_EE_DATAIN); 301 } else { 302 EE_CLR(RL_EE_DATAIN); 303 } 304 DELAY(100); 305 EE_SET(RL_EE_CLK); 306 DELAY(150); 307 EE_CLR(RL_EE_CLK); 308 DELAY(100); 309 } 310} 311 312/* 313 * Read a word of data stored in the EEPROM at address 'addr.' 314 */ 315static void 316rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest) 317{ 318 register int i; 319 uint16_t word = 0; 320 321 /* Enter EEPROM access mode. */ 322 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 323 324 /* 325 * Send address of word we want to read. 326 */ 327 rl_eeprom_putbyte(sc, addr); 328 329 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 330 331 /* 332 * Start reading bits from EEPROM. 333 */ 334 for (i = 0x8000; i; i >>= 1) { 335 EE_SET(RL_EE_CLK); 336 DELAY(100); 337 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 338 word |= i; 339 EE_CLR(RL_EE_CLK); 340 DELAY(100); 341 } 342 343 /* Turn off EEPROM access mode. */ 344 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 345 346 *dest = word; 347} 348 349/* 350 * Read a sequence of words from the EEPROM. 351 */ 352static void 353rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap) 354{ 355 int i; 356 uint16_t word = 0, *ptr; 357 358 for (i = 0; i < cnt; i++) { 359 rl_eeprom_getword(sc, off + i, &word); 360 ptr = (uint16_t *)(dest + (i * 2)); 361 if (swap) 362 *ptr = ntohs(word); 363 else 364 *ptr = word; 365 } 366} 367 368/* 369 * MII access routines are provided for the 8129, which 370 * doesn't have a built-in PHY. For the 8139, we fake things 371 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 372 * direct access PHY registers. 373 */ 374#define MII_SET(x) \ 375 CSR_WRITE_1(sc, RL_MII, \ 376 CSR_READ_1(sc, RL_MII) | (x)) 377 378#define MII_CLR(x) \ 379 CSR_WRITE_1(sc, RL_MII, \ 380 CSR_READ_1(sc, RL_MII) & ~(x)) 381 382/* 383 * Sync the PHYs by setting data bit and strobing the clock 32 times. 384 */ 385static void 386rl_mii_sync(struct rl_softc *sc) 387{ 388 register int i; 389 390 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 391 392 for (i = 0; i < 32; i++) { 393 MII_SET(RL_MII_CLK); 394 DELAY(1); 395 MII_CLR(RL_MII_CLK); 396 DELAY(1); 397 } 398} 399 400/* 401 * Clock a series of bits through the MII. 402 */ 403static void 404rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt) 405{ 406 int i; 407 408 MII_CLR(RL_MII_CLK); 409 410 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 411 if (bits & i) { 412 MII_SET(RL_MII_DATAOUT); 413 } else { 414 MII_CLR(RL_MII_DATAOUT); 415 } 416 DELAY(1); 417 MII_CLR(RL_MII_CLK); 418 DELAY(1); 419 MII_SET(RL_MII_CLK); 420 } 421} 422 423/* 424 * Read an PHY register through the MII. 425 */ 426static int 427rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame) 428{ 429 int i, ack; 430 431 /* Set up frame for RX. */ 432 frame->mii_stdelim = RL_MII_STARTDELIM; 433 frame->mii_opcode = RL_MII_READOP; 434 frame->mii_turnaround = 0; 435 frame->mii_data = 0; 436 437 CSR_WRITE_2(sc, RL_MII, 0); 438 439 /* Turn on data xmit. */ 440 MII_SET(RL_MII_DIR); 441 442 rl_mii_sync(sc); 443 444 /* Send command/address info. */ 445 rl_mii_send(sc, frame->mii_stdelim, 2); 446 rl_mii_send(sc, frame->mii_opcode, 2); 447 rl_mii_send(sc, frame->mii_phyaddr, 5); 448 rl_mii_send(sc, frame->mii_regaddr, 5); 449 450 /* Idle bit */ 451 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 452 DELAY(1); 453 MII_SET(RL_MII_CLK); 454 DELAY(1); 455 456 /* Turn off xmit. */ 457 MII_CLR(RL_MII_DIR); 458 459 /* Check for ack */ 460 MII_CLR(RL_MII_CLK); 461 DELAY(1); 462 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 463 MII_SET(RL_MII_CLK); 464 DELAY(1); 465 466 /* 467 * Now try reading data bits. If the ack failed, we still 468 * need to clock through 16 cycles to keep the PHY(s) in sync. 469 */ 470 if (ack) { 471 for(i = 0; i < 16; i++) { 472 MII_CLR(RL_MII_CLK); 473 DELAY(1); 474 MII_SET(RL_MII_CLK); 475 DELAY(1); 476 } 477 goto fail; 478 } 479 480 for (i = 0x8000; i; i >>= 1) { 481 MII_CLR(RL_MII_CLK); 482 DELAY(1); 483 if (!ack) { 484 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 485 frame->mii_data |= i; 486 DELAY(1); 487 } 488 MII_SET(RL_MII_CLK); 489 DELAY(1); 490 } 491 492fail: 493 MII_CLR(RL_MII_CLK); 494 DELAY(1); 495 MII_SET(RL_MII_CLK); 496 DELAY(1); 497 498 return (ack ? 1 : 0); 499} 500 501/* 502 * Write to a PHY register through the MII. 503 */ 504static int 505rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame) 506{ 507 508 /* Set up frame for TX. */ 509 frame->mii_stdelim = RL_MII_STARTDELIM; 510 frame->mii_opcode = RL_MII_WRITEOP; 511 frame->mii_turnaround = RL_MII_TURNAROUND; 512 513 /* Turn on data output. */ 514 MII_SET(RL_MII_DIR); 515 516 rl_mii_sync(sc); 517 518 rl_mii_send(sc, frame->mii_stdelim, 2); 519 rl_mii_send(sc, frame->mii_opcode, 2); 520 rl_mii_send(sc, frame->mii_phyaddr, 5); 521 rl_mii_send(sc, frame->mii_regaddr, 5); 522 rl_mii_send(sc, frame->mii_turnaround, 2); 523 rl_mii_send(sc, frame->mii_data, 16); 524 525 /* Idle bit. */ 526 MII_SET(RL_MII_CLK); 527 DELAY(1); 528 MII_CLR(RL_MII_CLK); 529 DELAY(1); 530 531 /* Turn off xmit. */ 532 MII_CLR(RL_MII_DIR); 533 534 return (0); 535} 536 537static int 538rl_miibus_readreg(device_t dev, int phy, int reg) 539{ 540 struct rl_softc *sc; 541 struct rl_mii_frame frame; 542 uint16_t rval = 0; 543 uint16_t rl8139_reg = 0; 544 545 sc = device_get_softc(dev); 546 547 if (sc->rl_type == RL_8139) { 548 /* Pretend the internal PHY is only at address 0 */ 549 if (phy) { 550 return (0); 551 } 552 switch (reg) { 553 case MII_BMCR: 554 rl8139_reg = RL_BMCR; 555 break; 556 case MII_BMSR: 557 rl8139_reg = RL_BMSR; 558 break; 559 case MII_ANAR: 560 rl8139_reg = RL_ANAR; 561 break; 562 case MII_ANER: 563 rl8139_reg = RL_ANER; 564 break; 565 case MII_ANLPAR: 566 rl8139_reg = RL_LPAR; 567 break; 568 case MII_PHYIDR1: 569 case MII_PHYIDR2: 570 return (0); 571 /* 572 * Allow the rlphy driver to read the media status 573 * register. If we have a link partner which does not 574 * support NWAY, this is the register which will tell 575 * us the results of parallel detection. 576 */ 577 case RL_MEDIASTAT: 578 rval = CSR_READ_1(sc, RL_MEDIASTAT); 579 return (rval); 580 default: 581 if_printf(sc->rl_ifp, "bad phy register\n"); 582 return (0); 583 } 584 rval = CSR_READ_2(sc, rl8139_reg); 585 return (rval); 586 } 587 588 bzero((char *)&frame, sizeof(frame)); 589 frame.mii_phyaddr = phy; 590 frame.mii_regaddr = reg; 591 rl_mii_readreg(sc, &frame); 592 593 return (frame.mii_data); 594} 595 596static int 597rl_miibus_writereg(device_t dev, int phy, int reg, int data) 598{ 599 struct rl_softc *sc; 600 struct rl_mii_frame frame; 601 uint16_t rl8139_reg = 0; 602 603 sc = device_get_softc(dev); 604 605 if (sc->rl_type == RL_8139) { 606 /* Pretend the internal PHY is only at address 0 */ 607 if (phy) { 608 return (0); 609 } 610 switch (reg) { 611 case MII_BMCR: 612 rl8139_reg = RL_BMCR; 613 break; 614 case MII_BMSR: 615 rl8139_reg = RL_BMSR; 616 break; 617 case MII_ANAR: 618 rl8139_reg = RL_ANAR; 619 break; 620 case MII_ANER: 621 rl8139_reg = RL_ANER; 622 break; 623 case MII_ANLPAR: 624 rl8139_reg = RL_LPAR; 625 break; 626 case MII_PHYIDR1: 627 case MII_PHYIDR2: 628 return (0); 629 break; 630 default: 631 if_printf(sc->rl_ifp, "bad phy register\n"); 632 return (0); 633 } 634 CSR_WRITE_2(sc, rl8139_reg, data); 635 return (0); 636 } 637 638 bzero((char *)&frame, sizeof(frame)); 639 frame.mii_phyaddr = phy; 640 frame.mii_regaddr = reg; 641 frame.mii_data = data; 642 rl_mii_writereg(sc, &frame); 643 644 return (0); 645} 646 647static void 648rl_miibus_statchg(device_t dev) 649{ 650} 651 652/* 653 * Program the 64-bit multicast hash filter. 654 */ 655static void 656rl_setmulti(struct rl_softc *sc) 657{ 658 struct ifnet *ifp = sc->rl_ifp; 659 int h = 0; 660 uint32_t hashes[2] = { 0, 0 }; 661 struct ifmultiaddr *ifma; 662 uint32_t rxfilt; 663 int mcnt = 0; 664 665 RL_LOCK_ASSERT(sc); 666 667 rxfilt = CSR_READ_4(sc, RL_RXCFG); 668 669 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 670 rxfilt |= RL_RXCFG_RX_MULTI; 671 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 672 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 673 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 674 return; 675 } 676 677 /* first, zot all the existing hash bits */ 678 CSR_WRITE_4(sc, RL_MAR0, 0); 679 CSR_WRITE_4(sc, RL_MAR4, 0); 680 681 /* now program new ones */ 682 IF_ADDR_LOCK(ifp); 683 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 684 if (ifma->ifma_addr->sa_family != AF_LINK) 685 continue; 686 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 687 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 688 if (h < 32) 689 hashes[0] |= (1 << h); 690 else 691 hashes[1] |= (1 << (h - 32)); 692 mcnt++; 693 } 694 IF_ADDR_UNLOCK(ifp); 695 696 if (mcnt) 697 rxfilt |= RL_RXCFG_RX_MULTI; 698 else 699 rxfilt &= ~RL_RXCFG_RX_MULTI; 700 701 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 702 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 703 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 704} 705 706static void 707rl_reset(struct rl_softc *sc) 708{ 709 register int i; 710 711 RL_LOCK_ASSERT(sc); 712 713 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 714 715 for (i = 0; i < RL_TIMEOUT; i++) { 716 DELAY(10); 717 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 718 break; 719 } 720 if (i == RL_TIMEOUT) 721 if_printf(sc->rl_ifp, "reset never completed!\n"); 722} 723 724/* 725 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 726 * IDs against our list and return a device name if we find a match. 727 */ 728static int 729rl_probe(device_t dev) 730{ 731 struct rl_softc *sc; 732 struct rl_type *t = rl_devs; 733 int rid; 734 uint32_t hwrev; 735 736 sc = device_get_softc(dev); 737 738 while (t->rl_name != NULL) { 739 if ((pci_get_vendor(dev) == t->rl_vid) && 740 (pci_get_device(dev) == t->rl_did)) { 741 /* 742 * Temporarily map the I/O space 743 * so we can read the chip ID register. 744 */ 745 rid = RL_RID; 746 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 747 RF_ACTIVE); 748 if (sc->rl_res == NULL) { 749 device_printf(dev, 750 "couldn't map ports/memory\n"); 751 return (ENXIO); 752 } 753 sc->rl_btag = rman_get_bustag(sc->rl_res); 754 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 755 756 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 757 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 758 759 /* Don't attach to 8139C+ or 8169/8110 chips. */ 760 if (hwrev == RL_HWREV_8139CPLUS || 761 (hwrev == RL_HWREV_8169 && 762 t->rl_did == RT_DEVICEID_8169) || 763 hwrev == RL_HWREV_8169S || 764 hwrev == RL_HWREV_8110S) { 765 t++; 766 continue; 767 } 768 769 device_set_desc(dev, t->rl_name); 770 return (BUS_PROBE_DEFAULT); 771 } 772 t++; 773 } 774 775 return (ENXIO); 776} 777 778/* 779 * Attach the interface. Allocate softc structures, do ifmedia 780 * setup and ethernet/BPF attach. 781 */ 782static int 783rl_attach(device_t dev) 784{ 785 uint8_t eaddr[ETHER_ADDR_LEN]; 786 uint16_t as[3]; 787 struct ifnet *ifp; 788 struct rl_softc *sc; 789 struct rl_type *t; 790 int error = 0, i, rid; 791 int unit; 792 uint16_t rl_did = 0; 793 794 sc = device_get_softc(dev); 795 unit = device_get_unit(dev); 796 797 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 798 MTX_DEF); 799 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 800 801 pci_enable_busmaster(dev); 802 803 /* Map control/status registers. */ 804 rid = RL_RID; 805 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE); 806 807 if (sc->rl_res == NULL) { 808 device_printf(dev, "couldn't map ports/memory\n"); 809 error = ENXIO; 810 goto fail; 811 } 812 813#ifdef notdef 814 /* 815 * Detect the Realtek 8139B. For some reason, this chip is very 816 * unstable when left to autoselect the media 817 * The best workaround is to set the device to the required 818 * media type or to set it to the 10 Meg speed. 819 */ 820 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF) 821 device_printf(dev, 822"Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n"); 823#endif 824 825 sc->rl_btag = rman_get_bustag(sc->rl_res); 826 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 827 828 /* Allocate interrupt */ 829 rid = 0; 830 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 831 RF_SHAREABLE | RF_ACTIVE); 832 833 if (sc->rl_irq == NULL) { 834 device_printf(dev, "couldn't map interrupt\n"); 835 error = ENXIO; 836 goto fail; 837 } 838 839 /* 840 * Reset the adapter. Only take the lock here as it's needed in 841 * order to call rl_reset(). 842 */ 843 RL_LOCK(sc); 844 rl_reset(sc); 845 RL_UNLOCK(sc); 846 847 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 848 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0); 849 if (rl_did != 0x8129) 850 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 851 852 /* 853 * Get station address from the EEPROM. 854 */ 855 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0); 856 for (i = 0; i < 3; i++) { 857 eaddr[(i * 2) + 0] = as[i] & 0xff; 858 eaddr[(i * 2) + 1] = as[i] >> 8; 859 } 860 861 /* 862 * Now read the exact device type from the EEPROM to find 863 * out if it's an 8129 or 8139. 864 */ 865 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0); 866 867 t = rl_devs; 868 sc->rl_type = 0; 869 while(t->rl_name != NULL) { 870 if (rl_did == t->rl_did) { 871 sc->rl_type = t->rl_basetype; 872 break; 873 } 874 t++; 875 } 876 877 if (sc->rl_type == 0) { 878 device_printf(dev, "unknown device ID: %x\n", rl_did); 879 error = ENXIO; 880 goto fail; 881 } 882 883 /* 884 * Allocate the parent bus DMA tag appropriate for PCI. 885 */ 886#define RL_NSEG_NEW 32 887 error = bus_dma_tag_create(NULL, /* parent */ 888 1, 0, /* alignment, boundary */ 889 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 890 BUS_SPACE_MAXADDR, /* highaddr */ 891 NULL, NULL, /* filter, filterarg */ 892 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 893 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 894 BUS_DMA_ALLOCNOW, /* flags */ 895 NULL, NULL, /* lockfunc, lockarg */ 896 &sc->rl_parent_tag); 897 if (error) 898 goto fail; 899 900 /* 901 * Now allocate a tag for the DMA descriptor lists. 902 * All of our lists are allocated as a contiguous block 903 * of memory. 904 */ 905 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 906 1, 0, /* alignment, boundary */ 907 BUS_SPACE_MAXADDR, /* lowaddr */ 908 BUS_SPACE_MAXADDR, /* highaddr */ 909 NULL, NULL, /* filter, filterarg */ 910 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 911 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 912 BUS_DMA_ALLOCNOW, /* flags */ 913 NULL, NULL, /* lockfunc, lockarg */ 914 &sc->rl_tag); 915 if (error) 916 goto fail; 917 918 /* 919 * Now allocate a chunk of DMA-able memory based on the 920 * tag we just created. 921 */ 922 error = bus_dmamem_alloc(sc->rl_tag, 923 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 924 &sc->rl_cdata.rl_rx_dmamap); 925 if (error) { 926 device_printf(dev, "no memory for list buffers!\n"); 927 bus_dma_tag_destroy(sc->rl_tag); 928 sc->rl_tag = NULL; 929 goto fail; 930 } 931 932 /* Leave a few bytes before the start of the RX ring buffer. */ 933 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 934 sc->rl_cdata.rl_rx_buf += sizeof(uint64_t); 935 936 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 937 if (ifp == NULL) { 938 device_printf(dev, "can not if_alloc()\n"); 939 error = ENOSPC; 940 goto fail; 941 } 942 943 /* Do MII setup */ 944 if (mii_phy_probe(dev, &sc->rl_miibus, 945 rl_ifmedia_upd, rl_ifmedia_sts)) { 946 device_printf(dev, "MII without any phy!\n"); 947 error = ENXIO; 948 goto fail; 949 } 950 951 ifp->if_softc = sc; 952 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 953 ifp->if_mtu = ETHERMTU; 954 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 955 ifp->if_ioctl = rl_ioctl; 956 ifp->if_start = rl_start; 957 ifp->if_watchdog = rl_watchdog; 958 ifp->if_init = rl_init; 959 ifp->if_baudrate = 10000000; 960 ifp->if_capabilities = IFCAP_VLAN_MTU; 961 ifp->if_capenable = ifp->if_capabilities; 962#ifdef DEVICE_POLLING 963 ifp->if_capabilities |= IFCAP_POLLING; 964#endif 965 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 966 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 967 IFQ_SET_READY(&ifp->if_snd); 968 969 /* 970 * Call MI attach routine. 971 */ 972 ether_ifattach(ifp, eaddr); 973 974 /* Hook interrupt last to avoid having to lock softc */ 975 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE, 976 rl_intr, sc, &sc->rl_intrhand); 977 if (error) { 978 if_printf(ifp, "couldn't set up irq\n"); 979 ether_ifdetach(ifp); 980 } 981 982fail: 983 if (error) 984 rl_detach(dev); 985 986 return (error); 987} 988 989/* 990 * Shutdown hardware and free up resources. This can be called any 991 * time after the mutex has been initialized. It is called in both 992 * the error case in attach and the normal detach case so it needs 993 * to be careful about only freeing resources that have actually been 994 * allocated. 995 */ 996static int 997rl_detach(device_t dev) 998{ 999 struct rl_softc *sc; 1000 struct ifnet *ifp; 1001 1002 sc = device_get_softc(dev); 1003 ifp = sc->rl_ifp; 1004 1005 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 1006 1007#ifdef DEVICE_POLLING 1008 if (ifp->if_capenable & IFCAP_POLLING) 1009 ether_poll_deregister(ifp); 1010#endif 1011 /* These should only be active if attach succeeded */ 1012 if (device_is_attached(dev)) { 1013 RL_LOCK(sc); 1014 rl_stop(sc); 1015 RL_UNLOCK(sc); 1016 callout_drain(&sc->rl_stat_callout); 1017 ether_ifdetach(ifp); 1018 } 1019#if 0 1020 sc->suspended = 1; 1021#endif 1022 if (ifp) 1023 if_free(ifp); 1024 if (sc->rl_miibus) 1025 device_delete_child(dev, sc->rl_miibus); 1026 bus_generic_detach(dev); 1027 1028 if (sc->rl_intrhand) 1029 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1030 if (sc->rl_irq) 1031 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1032 if (sc->rl_res) 1033 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1034 1035 if (sc->rl_tag) { 1036 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1037 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1038 sc->rl_cdata.rl_rx_dmamap); 1039 bus_dma_tag_destroy(sc->rl_tag); 1040 } 1041 if (sc->rl_parent_tag) 1042 bus_dma_tag_destroy(sc->rl_parent_tag); 1043 1044 mtx_destroy(&sc->rl_mtx); 1045 1046 return (0); 1047} 1048 1049/* 1050 * Initialize the transmit descriptors. 1051 */ 1052static int 1053rl_list_tx_init(struct rl_softc *sc) 1054{ 1055 struct rl_chain_data *cd; 1056 int i; 1057 1058 RL_LOCK_ASSERT(sc); 1059 1060 cd = &sc->rl_cdata; 1061 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1062 cd->rl_tx_chain[i] = NULL; 1063 CSR_WRITE_4(sc, 1064 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000); 1065 } 1066 1067 sc->rl_cdata.cur_tx = 0; 1068 sc->rl_cdata.last_tx = 0; 1069 1070 return (0); 1071} 1072 1073/* 1074 * A frame has been uploaded: pass the resulting mbuf chain up to 1075 * the higher level protocols. 1076 * 1077 * You know there's something wrong with a PCI bus-master chip design 1078 * when you have to use m_devget(). 1079 * 1080 * The receive operation is badly documented in the datasheet, so I'll 1081 * attempt to document it here. The driver provides a buffer area and 1082 * places its base address in the RX buffer start address register. 1083 * The chip then begins copying frames into the RX buffer. Each frame 1084 * is preceded by a 32-bit RX status word which specifies the length 1085 * of the frame and certain other status bits. Each frame (starting with 1086 * the status word) is also 32-bit aligned. The frame length is in the 1087 * first 16 bits of the status word; the lower 15 bits correspond with 1088 * the 'rx status register' mentioned in the datasheet. 1089 * 1090 * Note: to make the Alpha happy, the frame payload needs to be aligned 1091 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1092 * as the offset argument to m_devget(). 1093 */ 1094static void 1095rl_rxeof(struct rl_softc *sc) 1096{ 1097 struct mbuf *m; 1098 struct ifnet *ifp = sc->rl_ifp; 1099 uint8_t *rxbufpos; 1100 int total_len = 0; 1101 int wrap = 0; 1102 uint32_t rxstat; 1103 uint16_t cur_rx; 1104 uint16_t limit; 1105 uint16_t max_bytes, rx_bytes = 0; 1106 1107 RL_LOCK_ASSERT(sc); 1108 1109 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1110 BUS_DMASYNC_POSTREAD); 1111 1112 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1113 1114 /* Do not try to read past this point. */ 1115 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1116 1117 if (limit < cur_rx) 1118 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1119 else 1120 max_bytes = limit - cur_rx; 1121 1122 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1123#ifdef DEVICE_POLLING 1124 if (ifp->if_capenable & IFCAP_POLLING) { 1125 if (sc->rxcycles <= 0) 1126 break; 1127 sc->rxcycles--; 1128 } 1129#endif 1130 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1131 rxstat = le32toh(*(uint32_t *)rxbufpos); 1132 1133 /* 1134 * Here's a totally undocumented fact for you. When the 1135 * RealTek chip is in the process of copying a packet into 1136 * RAM for you, the length will be 0xfff0. If you spot a 1137 * packet header with this value, you need to stop. The 1138 * datasheet makes absolutely no mention of this and 1139 * RealTek should be shot for this. 1140 */ 1141 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1142 break; 1143 1144 if (!(rxstat & RL_RXSTAT_RXOK)) { 1145 ifp->if_ierrors++; 1146 rl_init_locked(sc); 1147 return; 1148 } 1149 1150 /* No errors; receive the packet. */ 1151 total_len = rxstat >> 16; 1152 rx_bytes += total_len + 4; 1153 1154 /* 1155 * XXX The RealTek chip includes the CRC with every 1156 * received frame, and there's no way to turn this 1157 * behavior off (at least, I can't find anything in 1158 * the manual that explains how to do it) so we have 1159 * to trim off the CRC manually. 1160 */ 1161 total_len -= ETHER_CRC_LEN; 1162 1163 /* 1164 * Avoid trying to read more bytes than we know 1165 * the chip has prepared for us. 1166 */ 1167 if (rx_bytes > max_bytes) 1168 break; 1169 1170 rxbufpos = sc->rl_cdata.rl_rx_buf + 1171 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN); 1172 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1173 rxbufpos = sc->rl_cdata.rl_rx_buf; 1174 1175 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1176 if (total_len > wrap) { 1177 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1178 NULL); 1179 if (m == NULL) { 1180 ifp->if_ierrors++; 1181 } else { 1182 m_copyback(m, wrap, total_len - wrap, 1183 sc->rl_cdata.rl_rx_buf); 1184 } 1185 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1186 } else { 1187 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1188 NULL); 1189 if (m == NULL) 1190 ifp->if_ierrors++; 1191 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1192 } 1193 1194 /* Round up to 32-bit boundary. */ 1195 cur_rx = (cur_rx + 3) & ~3; 1196 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1197 1198 if (m == NULL) 1199 continue; 1200 1201 ifp->if_ipackets++; 1202 RL_UNLOCK(sc); 1203 (*ifp->if_input)(ifp, m); 1204 RL_LOCK(sc); 1205 } 1206} 1207 1208/* 1209 * A frame was downloaded to the chip. It's safe for us to clean up 1210 * the list buffers. 1211 */ 1212static void 1213rl_txeof(struct rl_softc *sc) 1214{ 1215 struct ifnet *ifp = sc->rl_ifp; 1216 uint32_t txstat; 1217 1218 RL_LOCK_ASSERT(sc); 1219 1220 /* 1221 * Go through our tx list and free mbufs for those 1222 * frames that have been uploaded. 1223 */ 1224 do { 1225 if (RL_LAST_TXMBUF(sc) == NULL) 1226 break; 1227 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1228 if (!(txstat & (RL_TXSTAT_TX_OK| 1229 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1230 break; 1231 1232 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1233 1234 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1235 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1236 m_freem(RL_LAST_TXMBUF(sc)); 1237 RL_LAST_TXMBUF(sc) = NULL; 1238 /* 1239 * If there was a transmit underrun, bump the TX threshold. 1240 * Make sure not to overflow the 63 * 32byte we can address 1241 * with the 6 available bit. 1242 */ 1243 if ((txstat & RL_TXSTAT_TX_UNDERRUN) && 1244 (sc->rl_txthresh < 2016)) 1245 sc->rl_txthresh += 32; 1246 if (txstat & RL_TXSTAT_TX_OK) 1247 ifp->if_opackets++; 1248 else { 1249 int oldthresh; 1250 ifp->if_oerrors++; 1251 if ((txstat & RL_TXSTAT_TXABRT) || 1252 (txstat & RL_TXSTAT_OUTOFWIN)) 1253 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1254 oldthresh = sc->rl_txthresh; 1255 /* error recovery */ 1256 rl_reset(sc); 1257 rl_init_locked(sc); 1258 /* restore original threshold */ 1259 sc->rl_txthresh = oldthresh; 1260 return; 1261 } 1262 RL_INC(sc->rl_cdata.last_tx); 1263 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1264 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1265 1266 if (RL_LAST_TXMBUF(sc) == NULL) 1267 ifp->if_timer = 0; 1268 else if (ifp->if_timer == 0) 1269 ifp->if_timer = 5; 1270} 1271 1272static void 1273rl_tick(void *xsc) 1274{ 1275 struct rl_softc *sc = xsc; 1276 struct mii_data *mii; 1277 1278 RL_LOCK_ASSERT(sc); 1279 mii = device_get_softc(sc->rl_miibus); 1280 mii_tick(mii); 1281 1282 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc); 1283} 1284 1285#ifdef DEVICE_POLLING 1286static void 1287rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1288{ 1289 struct rl_softc *sc = ifp->if_softc; 1290 1291 RL_LOCK(sc); 1292 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1293 rl_poll_locked(ifp, cmd, count); 1294 RL_UNLOCK(sc); 1295} 1296 1297static void 1298rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1299{ 1300 struct rl_softc *sc = ifp->if_softc; 1301 1302 RL_LOCK_ASSERT(sc); 1303 1304 sc->rxcycles = count; 1305 rl_rxeof(sc); 1306 rl_txeof(sc); 1307 1308 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1309 rl_start_locked(ifp); 1310 1311 if (cmd == POLL_AND_CHECK_STATUS) { 1312 uint16_t status; 1313 1314 /* We should also check the status register. */ 1315 status = CSR_READ_2(sc, RL_ISR); 1316 if (status == 0xffff) 1317 return; 1318 if (status != 0) 1319 CSR_WRITE_2(sc, RL_ISR, status); 1320 1321 /* XXX We should check behaviour on receiver stalls. */ 1322 1323 if (status & RL_ISR_SYSTEM_ERR) { 1324 rl_reset(sc); 1325 rl_init_locked(sc); 1326 } 1327 } 1328} 1329#endif /* DEVICE_POLLING */ 1330 1331static void 1332rl_intr(void *arg) 1333{ 1334 struct rl_softc *sc = arg; 1335 struct ifnet *ifp = sc->rl_ifp; 1336 uint16_t status; 1337 1338 RL_LOCK(sc); 1339 1340 if (sc->suspended) 1341 goto done_locked; 1342 1343#ifdef DEVICE_POLLING 1344 if (ifp->if_capenable & IFCAP_POLLING) 1345 goto done_locked; 1346#endif 1347 1348 for (;;) { 1349 status = CSR_READ_2(sc, RL_ISR); 1350 /* If the card has gone away, the read returns 0xffff. */ 1351 if (status == 0xffff) 1352 break; 1353 if (status != 0) 1354 CSR_WRITE_2(sc, RL_ISR, status); 1355 if ((status & RL_INTRS) == 0) 1356 break; 1357 if (status & RL_ISR_RX_OK) 1358 rl_rxeof(sc); 1359 if (status & RL_ISR_RX_ERR) 1360 rl_rxeof(sc); 1361 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1362 rl_txeof(sc); 1363 if (status & RL_ISR_SYSTEM_ERR) { 1364 rl_reset(sc); 1365 rl_init_locked(sc); 1366 } 1367 } 1368 1369 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1370 rl_start_locked(ifp); 1371 1372done_locked: 1373 RL_UNLOCK(sc); 1374} 1375 1376/* 1377 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1378 * pointers to the fragment pointers. 1379 */ 1380static int 1381rl_encap(struct rl_softc *sc, struct mbuf *m_head) 1382{ 1383 struct mbuf *m_new = NULL; 1384 1385 RL_LOCK_ASSERT(sc); 1386 1387 /* 1388 * The RealTek is brain damaged and wants longword-aligned 1389 * TX buffers, plus we can only have one fragment buffer 1390 * per packet. We have to copy pretty much all the time. 1391 */ 1392 m_new = m_defrag(m_head, M_DONTWAIT); 1393 1394 if (m_new == NULL) { 1395 m_freem(m_head); 1396 return (1); 1397 } 1398 m_head = m_new; 1399 1400 /* Pad frames to at least 60 bytes. */ 1401 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1402 /* 1403 * Make security concious people happy: zero out the 1404 * bytes in the pad area, since we don't know what 1405 * this mbuf cluster buffer's previous user might 1406 * have left in it. 1407 */ 1408 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1409 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1410 m_head->m_pkthdr.len += 1411 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1412 m_head->m_len = m_head->m_pkthdr.len; 1413 } 1414 1415 RL_CUR_TXMBUF(sc) = m_head; 1416 1417 return (0); 1418} 1419 1420/* 1421 * Main transmit routine. 1422 */ 1423static void 1424rl_start(struct ifnet *ifp) 1425{ 1426 struct rl_softc *sc = ifp->if_softc; 1427 1428 RL_LOCK(sc); 1429 rl_start_locked(ifp); 1430 RL_UNLOCK(sc); 1431} 1432 1433static void 1434rl_start_locked(struct ifnet *ifp) 1435{ 1436 struct rl_softc *sc = ifp->if_softc; 1437 struct mbuf *m_head = NULL; 1438 1439 RL_LOCK_ASSERT(sc); 1440 1441 while (RL_CUR_TXMBUF(sc) == NULL) { 1442 1443 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1444 1445 if (m_head == NULL) 1446 break; 1447 1448 if (rl_encap(sc, m_head)) 1449 break; 1450 1451 /* Pass a copy of this mbuf chain to the bpf subsystem. */ 1452 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1453 1454 /* Transmit the frame. */ 1455 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1456 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1457 mtod(RL_CUR_TXMBUF(sc), void *), 1458 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 1459 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1460 BUS_DMASYNC_PREREAD); 1461 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1462 RL_TXTHRESH(sc->rl_txthresh) | 1463 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1464 1465 RL_INC(sc->rl_cdata.cur_tx); 1466 1467 /* Set a timeout in case the chip goes out to lunch. */ 1468 ifp->if_timer = 5; 1469 } 1470 1471 /* 1472 * We broke out of the loop because all our TX slots are 1473 * full. Mark the NIC as busy until it drains some of the 1474 * packets from the queue. 1475 */ 1476 if (RL_CUR_TXMBUF(sc) != NULL) 1477 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1478} 1479 1480static void 1481rl_init(void *xsc) 1482{ 1483 struct rl_softc *sc = xsc; 1484 1485 RL_LOCK(sc); 1486 rl_init_locked(sc); 1487 RL_UNLOCK(sc); 1488} 1489 1490static void 1491rl_init_locked(struct rl_softc *sc) 1492{ 1493 struct ifnet *ifp = sc->rl_ifp; 1494 struct mii_data *mii; 1495 uint32_t rxcfg = 0; 1496 1497 RL_LOCK_ASSERT(sc); 1498 1499 mii = device_get_softc(sc->rl_miibus); 1500 1501 /* 1502 * Cancel pending I/O and free all RX/TX buffers. 1503 */ 1504 rl_stop(sc); 1505 1506 /* 1507 * Init our MAC address. Even though the chipset 1508 * documentation doesn't mention it, we need to enter "Config 1509 * register write enable" mode to modify the ID registers. 1510 */ 1511 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1512 CSR_WRITE_STREAM_4(sc, RL_IDR0, 1513 *(uint32_t *)(&IFP2ENADDR(sc->rl_ifp)[0])); 1514 CSR_WRITE_STREAM_4(sc, RL_IDR4, 1515 *(uint32_t *)(&IFP2ENADDR(sc->rl_ifp)[4])); 1516 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1517 1518 /* Init the RX buffer pointer register. */ 1519 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1520 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 1521 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1522 BUS_DMASYNC_PREWRITE); 1523 1524 /* Init TX descriptors. */ 1525 rl_list_tx_init(sc); 1526 1527 /* 1528 * Enable transmit and receive. 1529 */ 1530 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1531 1532 /* 1533 * Set the initial TX and RX configuration. 1534 */ 1535 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1536 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1537 1538 /* Set the individual bit to receive frames for this host only. */ 1539 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1540 rxcfg |= RL_RXCFG_RX_INDIV; 1541 1542 /* If we want promiscuous mode, set the allframes bit. */ 1543 if (ifp->if_flags & IFF_PROMISC) { 1544 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1545 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1546 } else { 1547 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1548 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1549 } 1550 1551 /* Set capture broadcast bit to capture broadcast frames. */ 1552 if (ifp->if_flags & IFF_BROADCAST) { 1553 rxcfg |= RL_RXCFG_RX_BROAD; 1554 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1555 } else { 1556 rxcfg &= ~RL_RXCFG_RX_BROAD; 1557 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1558 } 1559 1560 /* Program the multicast filter, if necessary. */ 1561 rl_setmulti(sc); 1562 1563#ifdef DEVICE_POLLING 1564 /* Disable interrupts if we are polling. */ 1565 if (ifp->if_capenable & IFCAP_POLLING) 1566 CSR_WRITE_2(sc, RL_IMR, 0); 1567 else 1568#endif 1569 /* Enable interrupts. */ 1570 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1571 1572 /* Set initial TX threshold */ 1573 sc->rl_txthresh = RL_TX_THRESH_INIT; 1574 1575 /* Start RX/TX process. */ 1576 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1577 1578 /* Enable receiver and transmitter. */ 1579 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1580 1581 mii_mediachg(mii); 1582 1583 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1584 1585 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1586 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1587 1588 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc); 1589} 1590 1591/* 1592 * Set media options. 1593 */ 1594static int 1595rl_ifmedia_upd(struct ifnet *ifp) 1596{ 1597 struct rl_softc *sc = ifp->if_softc; 1598 struct mii_data *mii; 1599 1600 mii = device_get_softc(sc->rl_miibus); 1601 1602 RL_LOCK(sc); 1603 mii_mediachg(mii); 1604 RL_UNLOCK(sc); 1605 1606 return (0); 1607} 1608 1609/* 1610 * Report current media status. 1611 */ 1612static void 1613rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1614{ 1615 struct rl_softc *sc = ifp->if_softc; 1616 struct mii_data *mii; 1617 1618 mii = device_get_softc(sc->rl_miibus); 1619 1620 RL_LOCK(sc); 1621 mii_pollstat(mii); 1622 RL_UNLOCK(sc); 1623 ifmr->ifm_active = mii->mii_media_active; 1624 ifmr->ifm_status = mii->mii_media_status; 1625} 1626 1627static int 1628rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1629{ 1630 struct ifreq *ifr = (struct ifreq *)data; 1631 struct mii_data *mii; 1632 struct rl_softc *sc = ifp->if_softc; 1633 int error = 0; 1634 1635 switch (command) { 1636 case SIOCSIFFLAGS: 1637 RL_LOCK(sc); 1638 if (ifp->if_flags & IFF_UP) { 1639 rl_init_locked(sc); 1640 } else { 1641 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1642 rl_stop(sc); 1643 } 1644 RL_UNLOCK(sc); 1645 error = 0; 1646 break; 1647 case SIOCADDMULTI: 1648 case SIOCDELMULTI: 1649 RL_LOCK(sc); 1650 rl_setmulti(sc); 1651 RL_UNLOCK(sc); 1652 error = 0; 1653 break; 1654 case SIOCGIFMEDIA: 1655 case SIOCSIFMEDIA: 1656 mii = device_get_softc(sc->rl_miibus); 1657 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1658 break; 1659 case SIOCSIFCAP: 1660#ifdef DEVICE_POLLING 1661 if (ifr->ifr_reqcap & IFCAP_POLLING && 1662 !(ifp->if_capenable & IFCAP_POLLING)) { 1663 error = ether_poll_register(rl_poll, ifp); 1664 if (error) 1665 return(error); 1666 RL_LOCK(sc); 1667 /* Disable interrupts */ 1668 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1669 ifp->if_capenable |= IFCAP_POLLING; 1670 RL_UNLOCK(sc); 1671 return (error); 1672 1673 } 1674 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1675 ifp->if_capenable & IFCAP_POLLING) { 1676 error = ether_poll_deregister(ifp); 1677 /* Enable interrupts. */ 1678 RL_LOCK(sc); 1679 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1680 ifp->if_capenable &= ~IFCAP_POLLING; 1681 RL_UNLOCK(sc); 1682 return (error); 1683 } 1684#endif /* DEVICE_POLLING */ 1685 break; 1686 default: 1687 error = ether_ioctl(ifp, command, data); 1688 break; 1689 } 1690 1691 return (error); 1692} 1693 1694static void 1695rl_watchdog(struct ifnet *ifp) 1696{ 1697 struct rl_softc *sc = ifp->if_softc; 1698 1699 RL_LOCK(sc); 1700 1701 if_printf(ifp, "watchdog timeout\n"); 1702 ifp->if_oerrors++; 1703 1704 rl_txeof(sc); 1705 rl_rxeof(sc); 1706 rl_init_locked(sc); 1707 1708 RL_UNLOCK(sc); 1709} 1710 1711/* 1712 * Stop the adapter and free any mbufs allocated to the 1713 * RX and TX lists. 1714 */ 1715static void 1716rl_stop(struct rl_softc *sc) 1717{ 1718 register int i; 1719 struct ifnet *ifp = sc->rl_ifp; 1720 1721 RL_LOCK_ASSERT(sc); 1722 1723 ifp->if_timer = 0; 1724 callout_stop(&sc->rl_stat_callout); 1725 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1726 1727 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1728 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1729 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1730 1731 /* 1732 * Free the TX list buffers. 1733 */ 1734 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1735 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1736 bus_dmamap_unload(sc->rl_tag, 1737 sc->rl_cdata.rl_tx_dmamap[i]); 1738 bus_dmamap_destroy(sc->rl_tag, 1739 sc->rl_cdata.rl_tx_dmamap[i]); 1740 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1741 sc->rl_cdata.rl_tx_chain[i] = NULL; 1742 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 1743 0x0000000); 1744 } 1745 } 1746} 1747 1748/* 1749 * Device suspend routine. Stop the interface and save some PCI 1750 * settings in case the BIOS doesn't restore them properly on 1751 * resume. 1752 */ 1753static int 1754rl_suspend(device_t dev) 1755{ 1756 struct rl_softc *sc; 1757 1758 sc = device_get_softc(dev); 1759 1760 RL_LOCK(sc); 1761 rl_stop(sc); 1762 sc->suspended = 1; 1763 RL_UNLOCK(sc); 1764 1765 return (0); 1766} 1767 1768/* 1769 * Device resume routine. Restore some PCI settings in case the BIOS 1770 * doesn't, re-enable busmastering, and restart the interface if 1771 * appropriate. 1772 */ 1773static int 1774rl_resume(device_t dev) 1775{ 1776 struct rl_softc *sc; 1777 struct ifnet *ifp; 1778 1779 sc = device_get_softc(dev); 1780 ifp = sc->rl_ifp; 1781 1782 RL_LOCK(sc); 1783 1784 /* reinitialize interface if necessary */ 1785 if (ifp->if_flags & IFF_UP) 1786 rl_init_locked(sc); 1787 1788 sc->suspended = 0; 1789 1790 RL_UNLOCK(sc); 1791 1792 return (0); 1793} 1794 1795/* 1796 * Stop all chip I/O so that the kernel's probe routines don't 1797 * get confused by errant DMAs when rebooting. 1798 */ 1799static void 1800rl_shutdown(device_t dev) 1801{ 1802 struct rl_softc *sc; 1803 1804 sc = device_get_softc(dev); 1805 1806 RL_LOCK(sc); 1807 rl_stop(sc); 1808 RL_UNLOCK(sc); 1809} 1810