if_rl.c revision 150789
1/*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 150789 2005-10-01 18:56:19Z glebius $"); 35 36/* 37 * RealTek 8129/8139 PCI NIC driver 38 * 39 * Supports several extremely cheap PCI 10/100 adapters based on 40 * the RealTek chipset. Datasheets can be obtained from 41 * www.realtek.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86#include <sys/param.h> 87#include <sys/endian.h> 88#include <sys/systm.h> 89#include <sys/sockio.h> 90#include <sys/mbuf.h> 91#include <sys/malloc.h> 92#include <sys/kernel.h> 93#include <sys/module.h> 94#include <sys/socket.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> 98#include <net/ethernet.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101#include <net/if_types.h> 102 103#include <net/bpf.h> 104 105#include <machine/bus.h> 106#include <machine/resource.h> 107#include <sys/bus.h> 108#include <sys/rman.h> 109 110#include <dev/mii/mii.h> 111#include <dev/mii/miivar.h> 112 113#include <dev/pci/pcireg.h> 114#include <dev/pci/pcivar.h> 115 116MODULE_DEPEND(rl, pci, 1, 1, 1); 117MODULE_DEPEND(rl, ether, 1, 1, 1); 118MODULE_DEPEND(rl, miibus, 1, 1, 1); 119 120/* "controller miibus0" required. See GENERIC if you get errors here. */ 121#include "miibus_if.h" 122 123/* 124 * Default to using PIO access for this driver. On SMP systems, 125 * there appear to be problems with memory mapped mode: it looks like 126 * doing too many memory mapped access back to back in rapid succession 127 * can hang the bus. I'm inclined to blame this on crummy design/construction 128 * on the part of RealTek. Memory mapped mode does appear to work on 129 * uniprocessor systems though. 130 */ 131#define RL_USEIOSPACE 132 133#include <pci/if_rlreg.h> 134 135/* 136 * Various supported device vendors/types and their names. 137 */ 138static struct rl_type rl_devs[] = { 139 { RT_VENDORID, RT_DEVICEID_8129, RL_8129, 140 "RealTek 8129 10/100BaseTX" }, 141 { RT_VENDORID, RT_DEVICEID_8139, RL_8139, 142 "RealTek 8139 10/100BaseTX" }, 143 { RT_VENDORID, RT_DEVICEID_8138, RL_8139, 144 "RealTek 8139 10/100BaseTX CardBus" }, 145 { RT_VENDORID, RT_DEVICEID_8100, RL_8139, 146 "RealTek 8100 10/100BaseTX" }, 147 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 148 "Accton MPX 5030/5038 10/100BaseTX" }, 149 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139, 150 "Delta Electronics 8139 10/100BaseTX" }, 151 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139, 152 "Addtron Technolgy 8139 10/100BaseTX" }, 153 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139, 154 "D-Link DFE-530TX+ 10/100BaseTX" }, 155 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139, 156 "D-Link DFE-690TXD 10/100BaseTX" }, 157 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 158 "Nortel Networks 10/100BaseTX" }, 159 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139, 160 "Corega FEther CB-TXD" }, 161 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139, 162 "Corega FEtherII CB-TXD" }, 163 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139, 164 "Peppercon AG ROL-F" }, 165 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139, 166 "Planex FNW-3800-TX" }, 167 { CP_VENDORID, RT_DEVICEID_8139, RL_8139, 168 "Compaq HNE-300" }, 169 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139, 170 "LevelOne FPC-0106TX" }, 171 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139, 172 "Edimax EP-4103DL CardBus" }, 173 { 0, 0, 0, NULL } 174}; 175 176static int rl_attach(device_t); 177static int rl_detach(device_t); 178static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int); 179static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int); 180static void rl_eeprom_putbyte(struct rl_softc *, int); 181static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *); 182static int rl_encap(struct rl_softc *, struct mbuf * ); 183static int rl_list_tx_init(struct rl_softc *); 184static int rl_ifmedia_upd(struct ifnet *); 185static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 186static int rl_ioctl(struct ifnet *, u_long, caddr_t); 187static void rl_intr(void *); 188static void rl_init(void *); 189static void rl_init_locked(struct rl_softc *sc); 190static void rl_mii_send(struct rl_softc *, uint32_t, int); 191static void rl_mii_sync(struct rl_softc *); 192static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *); 193static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *); 194static int rl_miibus_readreg(device_t, int, int); 195static void rl_miibus_statchg(device_t); 196static int rl_miibus_writereg(device_t, int, int, int); 197#ifdef DEVICE_POLLING 198static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 199static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); 200#endif 201static int rl_probe(device_t); 202static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int); 203static void rl_reset(struct rl_softc *); 204static int rl_resume(device_t); 205static void rl_rxeof(struct rl_softc *); 206static void rl_setmulti(struct rl_softc *); 207static void rl_shutdown(device_t); 208static void rl_start(struct ifnet *); 209static void rl_start_locked(struct ifnet *); 210static void rl_stop(struct rl_softc *); 211static int rl_suspend(device_t); 212static void rl_tick(void *); 213static void rl_txeof(struct rl_softc *); 214static void rl_watchdog(struct ifnet *); 215 216#ifdef RL_USEIOSPACE 217#define RL_RES SYS_RES_IOPORT 218#define RL_RID RL_PCI_LOIO 219#else 220#define RL_RES SYS_RES_MEMORY 221#define RL_RID RL_PCI_LOMEM 222#endif 223 224static device_method_t rl_methods[] = { 225 /* Device interface */ 226 DEVMETHOD(device_probe, rl_probe), 227 DEVMETHOD(device_attach, rl_attach), 228 DEVMETHOD(device_detach, rl_detach), 229 DEVMETHOD(device_suspend, rl_suspend), 230 DEVMETHOD(device_resume, rl_resume), 231 DEVMETHOD(device_shutdown, rl_shutdown), 232 233 /* bus interface */ 234 DEVMETHOD(bus_print_child, bus_generic_print_child), 235 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 236 237 /* MII interface */ 238 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 239 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 240 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 241 242 { 0, 0 } 243}; 244 245static driver_t rl_driver = { 246 "rl", 247 rl_methods, 248 sizeof(struct rl_softc) 249}; 250 251static devclass_t rl_devclass; 252 253DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0); 254DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0); 255DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 256 257#define EE_SET(x) \ 258 CSR_WRITE_1(sc, RL_EECMD, \ 259 CSR_READ_1(sc, RL_EECMD) | x) 260 261#define EE_CLR(x) \ 262 CSR_WRITE_1(sc, RL_EECMD, \ 263 CSR_READ_1(sc, RL_EECMD) & ~x) 264 265static void 266rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) 267{ 268 struct rl_softc *sc = arg; 269 270 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 271} 272 273static void 274rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) 275{ 276 struct rl_softc *sc = arg; 277 278 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 279} 280 281/* 282 * Send a read command and address to the EEPROM, check for ACK. 283 */ 284static void 285rl_eeprom_putbyte(struct rl_softc *sc, int addr) 286{ 287 register int d, i; 288 289 d = addr | sc->rl_eecmd_read; 290 291 /* 292 * Feed in each bit and strobe the clock. 293 */ 294 for (i = 0x400; i; i >>= 1) { 295 if (d & i) { 296 EE_SET(RL_EE_DATAIN); 297 } else { 298 EE_CLR(RL_EE_DATAIN); 299 } 300 DELAY(100); 301 EE_SET(RL_EE_CLK); 302 DELAY(150); 303 EE_CLR(RL_EE_CLK); 304 DELAY(100); 305 } 306} 307 308/* 309 * Read a word of data stored in the EEPROM at address 'addr.' 310 */ 311static void 312rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest) 313{ 314 register int i; 315 uint16_t word = 0; 316 317 /* Enter EEPROM access mode. */ 318 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 319 320 /* 321 * Send address of word we want to read. 322 */ 323 rl_eeprom_putbyte(sc, addr); 324 325 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 326 327 /* 328 * Start reading bits from EEPROM. 329 */ 330 for (i = 0x8000; i; i >>= 1) { 331 EE_SET(RL_EE_CLK); 332 DELAY(100); 333 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 334 word |= i; 335 EE_CLR(RL_EE_CLK); 336 DELAY(100); 337 } 338 339 /* Turn off EEPROM access mode. */ 340 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 341 342 *dest = word; 343} 344 345/* 346 * Read a sequence of words from the EEPROM. 347 */ 348static void 349rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap) 350{ 351 int i; 352 uint16_t word = 0, *ptr; 353 354 for (i = 0; i < cnt; i++) { 355 rl_eeprom_getword(sc, off + i, &word); 356 ptr = (uint16_t *)(dest + (i * 2)); 357 if (swap) 358 *ptr = ntohs(word); 359 else 360 *ptr = word; 361 } 362} 363 364/* 365 * MII access routines are provided for the 8129, which 366 * doesn't have a built-in PHY. For the 8139, we fake things 367 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 368 * direct access PHY registers. 369 */ 370#define MII_SET(x) \ 371 CSR_WRITE_1(sc, RL_MII, \ 372 CSR_READ_1(sc, RL_MII) | (x)) 373 374#define MII_CLR(x) \ 375 CSR_WRITE_1(sc, RL_MII, \ 376 CSR_READ_1(sc, RL_MII) & ~(x)) 377 378/* 379 * Sync the PHYs by setting data bit and strobing the clock 32 times. 380 */ 381static void 382rl_mii_sync(struct rl_softc *sc) 383{ 384 register int i; 385 386 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 387 388 for (i = 0; i < 32; i++) { 389 MII_SET(RL_MII_CLK); 390 DELAY(1); 391 MII_CLR(RL_MII_CLK); 392 DELAY(1); 393 } 394} 395 396/* 397 * Clock a series of bits through the MII. 398 */ 399static void 400rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt) 401{ 402 int i; 403 404 MII_CLR(RL_MII_CLK); 405 406 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 407 if (bits & i) { 408 MII_SET(RL_MII_DATAOUT); 409 } else { 410 MII_CLR(RL_MII_DATAOUT); 411 } 412 DELAY(1); 413 MII_CLR(RL_MII_CLK); 414 DELAY(1); 415 MII_SET(RL_MII_CLK); 416 } 417} 418 419/* 420 * Read an PHY register through the MII. 421 */ 422static int 423rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame) 424{ 425 int i, ack; 426 427 /* Set up frame for RX. */ 428 frame->mii_stdelim = RL_MII_STARTDELIM; 429 frame->mii_opcode = RL_MII_READOP; 430 frame->mii_turnaround = 0; 431 frame->mii_data = 0; 432 433 CSR_WRITE_2(sc, RL_MII, 0); 434 435 /* Turn on data xmit. */ 436 MII_SET(RL_MII_DIR); 437 438 rl_mii_sync(sc); 439 440 /* Send command/address info. */ 441 rl_mii_send(sc, frame->mii_stdelim, 2); 442 rl_mii_send(sc, frame->mii_opcode, 2); 443 rl_mii_send(sc, frame->mii_phyaddr, 5); 444 rl_mii_send(sc, frame->mii_regaddr, 5); 445 446 /* Idle bit */ 447 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 448 DELAY(1); 449 MII_SET(RL_MII_CLK); 450 DELAY(1); 451 452 /* Turn off xmit. */ 453 MII_CLR(RL_MII_DIR); 454 455 /* Check for ack */ 456 MII_CLR(RL_MII_CLK); 457 DELAY(1); 458 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 459 MII_SET(RL_MII_CLK); 460 DELAY(1); 461 462 /* 463 * Now try reading data bits. If the ack failed, we still 464 * need to clock through 16 cycles to keep the PHY(s) in sync. 465 */ 466 if (ack) { 467 for(i = 0; i < 16; i++) { 468 MII_CLR(RL_MII_CLK); 469 DELAY(1); 470 MII_SET(RL_MII_CLK); 471 DELAY(1); 472 } 473 goto fail; 474 } 475 476 for (i = 0x8000; i; i >>= 1) { 477 MII_CLR(RL_MII_CLK); 478 DELAY(1); 479 if (!ack) { 480 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 481 frame->mii_data |= i; 482 DELAY(1); 483 } 484 MII_SET(RL_MII_CLK); 485 DELAY(1); 486 } 487 488fail: 489 MII_CLR(RL_MII_CLK); 490 DELAY(1); 491 MII_SET(RL_MII_CLK); 492 DELAY(1); 493 494 return (ack ? 1 : 0); 495} 496 497/* 498 * Write to a PHY register through the MII. 499 */ 500static int 501rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame) 502{ 503 504 /* Set up frame for TX. */ 505 frame->mii_stdelim = RL_MII_STARTDELIM; 506 frame->mii_opcode = RL_MII_WRITEOP; 507 frame->mii_turnaround = RL_MII_TURNAROUND; 508 509 /* Turn on data output. */ 510 MII_SET(RL_MII_DIR); 511 512 rl_mii_sync(sc); 513 514 rl_mii_send(sc, frame->mii_stdelim, 2); 515 rl_mii_send(sc, frame->mii_opcode, 2); 516 rl_mii_send(sc, frame->mii_phyaddr, 5); 517 rl_mii_send(sc, frame->mii_regaddr, 5); 518 rl_mii_send(sc, frame->mii_turnaround, 2); 519 rl_mii_send(sc, frame->mii_data, 16); 520 521 /* Idle bit. */ 522 MII_SET(RL_MII_CLK); 523 DELAY(1); 524 MII_CLR(RL_MII_CLK); 525 DELAY(1); 526 527 /* Turn off xmit. */ 528 MII_CLR(RL_MII_DIR); 529 530 return (0); 531} 532 533static int 534rl_miibus_readreg(device_t dev, int phy, int reg) 535{ 536 struct rl_softc *sc; 537 struct rl_mii_frame frame; 538 uint16_t rval = 0; 539 uint16_t rl8139_reg = 0; 540 541 sc = device_get_softc(dev); 542 543 if (sc->rl_type == RL_8139) { 544 /* Pretend the internal PHY is only at address 0 */ 545 if (phy) { 546 return (0); 547 } 548 switch (reg) { 549 case MII_BMCR: 550 rl8139_reg = RL_BMCR; 551 break; 552 case MII_BMSR: 553 rl8139_reg = RL_BMSR; 554 break; 555 case MII_ANAR: 556 rl8139_reg = RL_ANAR; 557 break; 558 case MII_ANER: 559 rl8139_reg = RL_ANER; 560 break; 561 case MII_ANLPAR: 562 rl8139_reg = RL_LPAR; 563 break; 564 case MII_PHYIDR1: 565 case MII_PHYIDR2: 566 return (0); 567 /* 568 * Allow the rlphy driver to read the media status 569 * register. If we have a link partner which does not 570 * support NWAY, this is the register which will tell 571 * us the results of parallel detection. 572 */ 573 case RL_MEDIASTAT: 574 rval = CSR_READ_1(sc, RL_MEDIASTAT); 575 return (rval); 576 default: 577 if_printf(sc->rl_ifp, "bad phy register\n"); 578 return (0); 579 } 580 rval = CSR_READ_2(sc, rl8139_reg); 581 return (rval); 582 } 583 584 bzero((char *)&frame, sizeof(frame)); 585 frame.mii_phyaddr = phy; 586 frame.mii_regaddr = reg; 587 rl_mii_readreg(sc, &frame); 588 589 return (frame.mii_data); 590} 591 592static int 593rl_miibus_writereg(device_t dev, int phy, int reg, int data) 594{ 595 struct rl_softc *sc; 596 struct rl_mii_frame frame; 597 uint16_t rl8139_reg = 0; 598 599 sc = device_get_softc(dev); 600 601 if (sc->rl_type == RL_8139) { 602 /* Pretend the internal PHY is only at address 0 */ 603 if (phy) { 604 return (0); 605 } 606 switch (reg) { 607 case MII_BMCR: 608 rl8139_reg = RL_BMCR; 609 break; 610 case MII_BMSR: 611 rl8139_reg = RL_BMSR; 612 break; 613 case MII_ANAR: 614 rl8139_reg = RL_ANAR; 615 break; 616 case MII_ANER: 617 rl8139_reg = RL_ANER; 618 break; 619 case MII_ANLPAR: 620 rl8139_reg = RL_LPAR; 621 break; 622 case MII_PHYIDR1: 623 case MII_PHYIDR2: 624 return (0); 625 break; 626 default: 627 if_printf(sc->rl_ifp, "bad phy register\n"); 628 return (0); 629 } 630 CSR_WRITE_2(sc, rl8139_reg, data); 631 return (0); 632 } 633 634 bzero((char *)&frame, sizeof(frame)); 635 frame.mii_phyaddr = phy; 636 frame.mii_regaddr = reg; 637 frame.mii_data = data; 638 rl_mii_writereg(sc, &frame); 639 640 return (0); 641} 642 643static void 644rl_miibus_statchg(device_t dev) 645{ 646} 647 648/* 649 * Program the 64-bit multicast hash filter. 650 */ 651static void 652rl_setmulti(struct rl_softc *sc) 653{ 654 struct ifnet *ifp = sc->rl_ifp; 655 int h = 0; 656 uint32_t hashes[2] = { 0, 0 }; 657 struct ifmultiaddr *ifma; 658 uint32_t rxfilt; 659 int mcnt = 0; 660 661 RL_LOCK_ASSERT(sc); 662 663 rxfilt = CSR_READ_4(sc, RL_RXCFG); 664 665 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 666 rxfilt |= RL_RXCFG_RX_MULTI; 667 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 668 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 669 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 670 return; 671 } 672 673 /* first, zot all the existing hash bits */ 674 CSR_WRITE_4(sc, RL_MAR0, 0); 675 CSR_WRITE_4(sc, RL_MAR4, 0); 676 677 /* now program new ones */ 678 IF_ADDR_LOCK(ifp); 679 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 680 if (ifma->ifma_addr->sa_family != AF_LINK) 681 continue; 682 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 683 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 684 if (h < 32) 685 hashes[0] |= (1 << h); 686 else 687 hashes[1] |= (1 << (h - 32)); 688 mcnt++; 689 } 690 IF_ADDR_UNLOCK(ifp); 691 692 if (mcnt) 693 rxfilt |= RL_RXCFG_RX_MULTI; 694 else 695 rxfilt &= ~RL_RXCFG_RX_MULTI; 696 697 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 698 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 699 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 700} 701 702static void 703rl_reset(struct rl_softc *sc) 704{ 705 register int i; 706 707 RL_LOCK_ASSERT(sc); 708 709 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 710 711 for (i = 0; i < RL_TIMEOUT; i++) { 712 DELAY(10); 713 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 714 break; 715 } 716 if (i == RL_TIMEOUT) 717 if_printf(sc->rl_ifp, "reset never completed!\n"); 718} 719 720/* 721 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 722 * IDs against our list and return a device name if we find a match. 723 */ 724static int 725rl_probe(device_t dev) 726{ 727 struct rl_softc *sc; 728 struct rl_type *t = rl_devs; 729 int rid; 730 uint32_t hwrev; 731 732 sc = device_get_softc(dev); 733 734 while (t->rl_name != NULL) { 735 if ((pci_get_vendor(dev) == t->rl_vid) && 736 (pci_get_device(dev) == t->rl_did)) { 737 /* 738 * Temporarily map the I/O space 739 * so we can read the chip ID register. 740 */ 741 rid = RL_RID; 742 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 743 RF_ACTIVE); 744 if (sc->rl_res == NULL) { 745 device_printf(dev, 746 "couldn't map ports/memory\n"); 747 return (ENXIO); 748 } 749 sc->rl_btag = rman_get_bustag(sc->rl_res); 750 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 751 752 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 753 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 754 755 /* Don't attach to 8139C+ or 8169/8110 chips. */ 756 if (hwrev == RL_HWREV_8139CPLUS || 757 (hwrev == RL_HWREV_8169 && 758 t->rl_did == RT_DEVICEID_8169) || 759 hwrev == RL_HWREV_8169S || 760 hwrev == RL_HWREV_8110S) { 761 t++; 762 continue; 763 } 764 765 device_set_desc(dev, t->rl_name); 766 return (BUS_PROBE_DEFAULT); 767 } 768 t++; 769 } 770 771 return (ENXIO); 772} 773 774/* 775 * Attach the interface. Allocate softc structures, do ifmedia 776 * setup and ethernet/BPF attach. 777 */ 778static int 779rl_attach(device_t dev) 780{ 781 uint8_t eaddr[ETHER_ADDR_LEN]; 782 uint16_t as[3]; 783 struct ifnet *ifp; 784 struct rl_softc *sc; 785 struct rl_type *t; 786 int error = 0, i, rid; 787 int unit; 788 uint16_t rl_did = 0; 789 790 sc = device_get_softc(dev); 791 unit = device_get_unit(dev); 792 793 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 794 MTX_DEF); 795 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 796 797 pci_enable_busmaster(dev); 798 799 /* Map control/status registers. */ 800 rid = RL_RID; 801 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE); 802 803 if (sc->rl_res == NULL) { 804 device_printf(dev, "couldn't map ports/memory\n"); 805 error = ENXIO; 806 goto fail; 807 } 808 809#ifdef notdef 810 /* 811 * Detect the Realtek 8139B. For some reason, this chip is very 812 * unstable when left to autoselect the media 813 * The best workaround is to set the device to the required 814 * media type or to set it to the 10 Meg speed. 815 */ 816 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF) 817 device_printf(dev, 818"Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n"); 819#endif 820 821 sc->rl_btag = rman_get_bustag(sc->rl_res); 822 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 823 824 /* Allocate interrupt */ 825 rid = 0; 826 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 827 RF_SHAREABLE | RF_ACTIVE); 828 829 if (sc->rl_irq == NULL) { 830 device_printf(dev, "couldn't map interrupt\n"); 831 error = ENXIO; 832 goto fail; 833 } 834 835 /* 836 * Reset the adapter. Only take the lock here as it's needed in 837 * order to call rl_reset(). 838 */ 839 RL_LOCK(sc); 840 rl_reset(sc); 841 RL_UNLOCK(sc); 842 843 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 844 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0); 845 if (rl_did != 0x8129) 846 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 847 848 /* 849 * Get station address from the EEPROM. 850 */ 851 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0); 852 for (i = 0; i < 3; i++) { 853 eaddr[(i * 2) + 0] = as[i] & 0xff; 854 eaddr[(i * 2) + 1] = as[i] >> 8; 855 } 856 857 /* 858 * Now read the exact device type from the EEPROM to find 859 * out if it's an 8129 or 8139. 860 */ 861 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0); 862 863 t = rl_devs; 864 sc->rl_type = 0; 865 while(t->rl_name != NULL) { 866 if (rl_did == t->rl_did) { 867 sc->rl_type = t->rl_basetype; 868 break; 869 } 870 t++; 871 } 872 873 if (sc->rl_type == 0) { 874 device_printf(dev, "unknown device ID: %x\n", rl_did); 875 error = ENXIO; 876 goto fail; 877 } 878 879 /* 880 * Allocate the parent bus DMA tag appropriate for PCI. 881 */ 882#define RL_NSEG_NEW 32 883 error = bus_dma_tag_create(NULL, /* parent */ 884 1, 0, /* alignment, boundary */ 885 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 886 BUS_SPACE_MAXADDR, /* highaddr */ 887 NULL, NULL, /* filter, filterarg */ 888 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 889 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 890 BUS_DMA_ALLOCNOW, /* flags */ 891 NULL, NULL, /* lockfunc, lockarg */ 892 &sc->rl_parent_tag); 893 if (error) 894 goto fail; 895 896 /* 897 * Now allocate a tag for the DMA descriptor lists. 898 * All of our lists are allocated as a contiguous block 899 * of memory. 900 */ 901 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 902 1, 0, /* alignment, boundary */ 903 BUS_SPACE_MAXADDR, /* lowaddr */ 904 BUS_SPACE_MAXADDR, /* highaddr */ 905 NULL, NULL, /* filter, filterarg */ 906 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 907 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 908 BUS_DMA_ALLOCNOW, /* flags */ 909 NULL, NULL, /* lockfunc, lockarg */ 910 &sc->rl_tag); 911 if (error) 912 goto fail; 913 914 /* 915 * Now allocate a chunk of DMA-able memory based on the 916 * tag we just created. 917 */ 918 error = bus_dmamem_alloc(sc->rl_tag, 919 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 920 &sc->rl_cdata.rl_rx_dmamap); 921 if (error) { 922 device_printf(dev, "no memory for list buffers!\n"); 923 bus_dma_tag_destroy(sc->rl_tag); 924 sc->rl_tag = NULL; 925 goto fail; 926 } 927 928 /* Leave a few bytes before the start of the RX ring buffer. */ 929 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 930 sc->rl_cdata.rl_rx_buf += sizeof(uint64_t); 931 932 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 933 if (ifp == NULL) { 934 device_printf(dev, "can not if_alloc()\n"); 935 error = ENOSPC; 936 goto fail; 937 } 938 939 /* Do MII setup */ 940 if (mii_phy_probe(dev, &sc->rl_miibus, 941 rl_ifmedia_upd, rl_ifmedia_sts)) { 942 device_printf(dev, "MII without any phy!\n"); 943 error = ENXIO; 944 goto fail; 945 } 946 947 ifp->if_softc = sc; 948 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 949 ifp->if_mtu = ETHERMTU; 950 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 951 ifp->if_ioctl = rl_ioctl; 952 ifp->if_start = rl_start; 953 ifp->if_watchdog = rl_watchdog; 954 ifp->if_init = rl_init; 955 ifp->if_baudrate = 10000000; 956 ifp->if_capabilities = IFCAP_VLAN_MTU; 957 ifp->if_capenable = ifp->if_capabilities; 958#ifdef DEVICE_POLLING 959 ifp->if_capabilities |= IFCAP_POLLING; 960#endif 961 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 962 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 963 IFQ_SET_READY(&ifp->if_snd); 964 965 /* 966 * Call MI attach routine. 967 */ 968 ether_ifattach(ifp, eaddr); 969 970 /* Hook interrupt last to avoid having to lock softc */ 971 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE, 972 rl_intr, sc, &sc->rl_intrhand); 973 if (error) { 974 if_printf(ifp, "couldn't set up irq\n"); 975 ether_ifdetach(ifp); 976 } 977 978fail: 979 if (error) 980 rl_detach(dev); 981 982 return (error); 983} 984 985/* 986 * Shutdown hardware and free up resources. This can be called any 987 * time after the mutex has been initialized. It is called in both 988 * the error case in attach and the normal detach case so it needs 989 * to be careful about only freeing resources that have actually been 990 * allocated. 991 */ 992static int 993rl_detach(device_t dev) 994{ 995 struct rl_softc *sc; 996 struct ifnet *ifp; 997 998 sc = device_get_softc(dev); 999 ifp = sc->rl_ifp; 1000 1001 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 1002 1003#ifdef DEVICE_POLLING 1004 if (ifp->if_capenable & IFCAP_POLLING) 1005 ether_poll_deregister(ifp); 1006#endif 1007 /* These should only be active if attach succeeded */ 1008 if (device_is_attached(dev)) { 1009 RL_LOCK(sc); 1010 rl_stop(sc); 1011 RL_UNLOCK(sc); 1012 callout_drain(&sc->rl_stat_callout); 1013 ether_ifdetach(ifp); 1014 } 1015#if 0 1016 sc->suspended = 1; 1017#endif 1018 if (ifp) 1019 if_free(ifp); 1020 if (sc->rl_miibus) 1021 device_delete_child(dev, sc->rl_miibus); 1022 bus_generic_detach(dev); 1023 1024 if (sc->rl_intrhand) 1025 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1026 if (sc->rl_irq) 1027 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1028 if (sc->rl_res) 1029 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1030 1031 if (sc->rl_tag) { 1032 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1033 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1034 sc->rl_cdata.rl_rx_dmamap); 1035 bus_dma_tag_destroy(sc->rl_tag); 1036 } 1037 if (sc->rl_parent_tag) 1038 bus_dma_tag_destroy(sc->rl_parent_tag); 1039 1040 mtx_destroy(&sc->rl_mtx); 1041 1042 return (0); 1043} 1044 1045/* 1046 * Initialize the transmit descriptors. 1047 */ 1048static int 1049rl_list_tx_init(struct rl_softc *sc) 1050{ 1051 struct rl_chain_data *cd; 1052 int i; 1053 1054 RL_LOCK_ASSERT(sc); 1055 1056 cd = &sc->rl_cdata; 1057 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1058 cd->rl_tx_chain[i] = NULL; 1059 CSR_WRITE_4(sc, 1060 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000); 1061 } 1062 1063 sc->rl_cdata.cur_tx = 0; 1064 sc->rl_cdata.last_tx = 0; 1065 1066 return (0); 1067} 1068 1069/* 1070 * A frame has been uploaded: pass the resulting mbuf chain up to 1071 * the higher level protocols. 1072 * 1073 * You know there's something wrong with a PCI bus-master chip design 1074 * when you have to use m_devget(). 1075 * 1076 * The receive operation is badly documented in the datasheet, so I'll 1077 * attempt to document it here. The driver provides a buffer area and 1078 * places its base address in the RX buffer start address register. 1079 * The chip then begins copying frames into the RX buffer. Each frame 1080 * is preceded by a 32-bit RX status word which specifies the length 1081 * of the frame and certain other status bits. Each frame (starting with 1082 * the status word) is also 32-bit aligned. The frame length is in the 1083 * first 16 bits of the status word; the lower 15 bits correspond with 1084 * the 'rx status register' mentioned in the datasheet. 1085 * 1086 * Note: to make the Alpha happy, the frame payload needs to be aligned 1087 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1088 * as the offset argument to m_devget(). 1089 */ 1090static void 1091rl_rxeof(struct rl_softc *sc) 1092{ 1093 struct mbuf *m; 1094 struct ifnet *ifp = sc->rl_ifp; 1095 uint8_t *rxbufpos; 1096 int total_len = 0; 1097 int wrap = 0; 1098 uint32_t rxstat; 1099 uint16_t cur_rx; 1100 uint16_t limit; 1101 uint16_t max_bytes, rx_bytes = 0; 1102 1103 RL_LOCK_ASSERT(sc); 1104 1105 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1106 BUS_DMASYNC_POSTREAD); 1107 1108 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1109 1110 /* Do not try to read past this point. */ 1111 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1112 1113 if (limit < cur_rx) 1114 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1115 else 1116 max_bytes = limit - cur_rx; 1117 1118 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1119#ifdef DEVICE_POLLING 1120 if (ifp->if_capenable & IFCAP_POLLING) { 1121 if (sc->rxcycles <= 0) 1122 break; 1123 sc->rxcycles--; 1124 } 1125#endif 1126 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1127 rxstat = le32toh(*(uint32_t *)rxbufpos); 1128 1129 /* 1130 * Here's a totally undocumented fact for you. When the 1131 * RealTek chip is in the process of copying a packet into 1132 * RAM for you, the length will be 0xfff0. If you spot a 1133 * packet header with this value, you need to stop. The 1134 * datasheet makes absolutely no mention of this and 1135 * RealTek should be shot for this. 1136 */ 1137 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1138 break; 1139 1140 if (!(rxstat & RL_RXSTAT_RXOK)) { 1141 ifp->if_ierrors++; 1142 rl_init_locked(sc); 1143 return; 1144 } 1145 1146 /* No errors; receive the packet. */ 1147 total_len = rxstat >> 16; 1148 rx_bytes += total_len + 4; 1149 1150 /* 1151 * XXX The RealTek chip includes the CRC with every 1152 * received frame, and there's no way to turn this 1153 * behavior off (at least, I can't find anything in 1154 * the manual that explains how to do it) so we have 1155 * to trim off the CRC manually. 1156 */ 1157 total_len -= ETHER_CRC_LEN; 1158 1159 /* 1160 * Avoid trying to read more bytes than we know 1161 * the chip has prepared for us. 1162 */ 1163 if (rx_bytes > max_bytes) 1164 break; 1165 1166 rxbufpos = sc->rl_cdata.rl_rx_buf + 1167 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN); 1168 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1169 rxbufpos = sc->rl_cdata.rl_rx_buf; 1170 1171 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1172 if (total_len > wrap) { 1173 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1174 NULL); 1175 if (m == NULL) { 1176 ifp->if_ierrors++; 1177 } else { 1178 m_copyback(m, wrap, total_len - wrap, 1179 sc->rl_cdata.rl_rx_buf); 1180 } 1181 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1182 } else { 1183 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1184 NULL); 1185 if (m == NULL) 1186 ifp->if_ierrors++; 1187 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1188 } 1189 1190 /* Round up to 32-bit boundary. */ 1191 cur_rx = (cur_rx + 3) & ~3; 1192 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1193 1194 if (m == NULL) 1195 continue; 1196 1197 ifp->if_ipackets++; 1198 RL_UNLOCK(sc); 1199 (*ifp->if_input)(ifp, m); 1200 RL_LOCK(sc); 1201 } 1202} 1203 1204/* 1205 * A frame was downloaded to the chip. It's safe for us to clean up 1206 * the list buffers. 1207 */ 1208static void 1209rl_txeof(struct rl_softc *sc) 1210{ 1211 struct ifnet *ifp = sc->rl_ifp; 1212 uint32_t txstat; 1213 1214 RL_LOCK_ASSERT(sc); 1215 1216 /* 1217 * Go through our tx list and free mbufs for those 1218 * frames that have been uploaded. 1219 */ 1220 do { 1221 if (RL_LAST_TXMBUF(sc) == NULL) 1222 break; 1223 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1224 if (!(txstat & (RL_TXSTAT_TX_OK| 1225 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1226 break; 1227 1228 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1229 1230 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1231 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1232 m_freem(RL_LAST_TXMBUF(sc)); 1233 RL_LAST_TXMBUF(sc) = NULL; 1234 /* 1235 * If there was a transmit underrun, bump the TX threshold. 1236 * Make sure not to overflow the 63 * 32byte we can address 1237 * with the 6 available bit. 1238 */ 1239 if ((txstat & RL_TXSTAT_TX_UNDERRUN) && 1240 (sc->rl_txthresh < 2016)) 1241 sc->rl_txthresh += 32; 1242 if (txstat & RL_TXSTAT_TX_OK) 1243 ifp->if_opackets++; 1244 else { 1245 int oldthresh; 1246 ifp->if_oerrors++; 1247 if ((txstat & RL_TXSTAT_TXABRT) || 1248 (txstat & RL_TXSTAT_OUTOFWIN)) 1249 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1250 oldthresh = sc->rl_txthresh; 1251 /* error recovery */ 1252 rl_reset(sc); 1253 rl_init_locked(sc); 1254 /* restore original threshold */ 1255 sc->rl_txthresh = oldthresh; 1256 return; 1257 } 1258 RL_INC(sc->rl_cdata.last_tx); 1259 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1260 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1261 1262 if (RL_LAST_TXMBUF(sc) == NULL) 1263 ifp->if_timer = 0; 1264 else if (ifp->if_timer == 0) 1265 ifp->if_timer = 5; 1266} 1267 1268static void 1269rl_tick(void *xsc) 1270{ 1271 struct rl_softc *sc = xsc; 1272 struct mii_data *mii; 1273 1274 RL_LOCK_ASSERT(sc); 1275 mii = device_get_softc(sc->rl_miibus); 1276 mii_tick(mii); 1277 1278 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc); 1279} 1280 1281#ifdef DEVICE_POLLING 1282static void 1283rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1284{ 1285 struct rl_softc *sc = ifp->if_softc; 1286 1287 RL_LOCK(sc); 1288 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1289 rl_poll_locked(ifp, cmd, count); 1290 RL_UNLOCK(sc); 1291} 1292 1293static void 1294rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1295{ 1296 struct rl_softc *sc = ifp->if_softc; 1297 1298 RL_LOCK_ASSERT(sc); 1299 1300 sc->rxcycles = count; 1301 rl_rxeof(sc); 1302 rl_txeof(sc); 1303 1304 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1305 rl_start_locked(ifp); 1306 1307 if (cmd == POLL_AND_CHECK_STATUS) { 1308 uint16_t status; 1309 1310 /* We should also check the status register. */ 1311 status = CSR_READ_2(sc, RL_ISR); 1312 if (status == 0xffff) 1313 return; 1314 if (status != 0) 1315 CSR_WRITE_2(sc, RL_ISR, status); 1316 1317 /* XXX We should check behaviour on receiver stalls. */ 1318 1319 if (status & RL_ISR_SYSTEM_ERR) { 1320 rl_reset(sc); 1321 rl_init_locked(sc); 1322 } 1323 } 1324} 1325#endif /* DEVICE_POLLING */ 1326 1327static void 1328rl_intr(void *arg) 1329{ 1330 struct rl_softc *sc = arg; 1331 struct ifnet *ifp = sc->rl_ifp; 1332 uint16_t status; 1333 1334 RL_LOCK(sc); 1335 1336 if (sc->suspended) 1337 goto done_locked; 1338 1339#ifdef DEVICE_POLLING 1340 if (ifp->if_capenable & IFCAP_POLLING) 1341 goto done_locked; 1342#endif 1343 1344 for (;;) { 1345 status = CSR_READ_2(sc, RL_ISR); 1346 /* If the card has gone away, the read returns 0xffff. */ 1347 if (status == 0xffff) 1348 break; 1349 if (status != 0) 1350 CSR_WRITE_2(sc, RL_ISR, status); 1351 if ((status & RL_INTRS) == 0) 1352 break; 1353 if (status & RL_ISR_RX_OK) 1354 rl_rxeof(sc); 1355 if (status & RL_ISR_RX_ERR) 1356 rl_rxeof(sc); 1357 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1358 rl_txeof(sc); 1359 if (status & RL_ISR_SYSTEM_ERR) { 1360 rl_reset(sc); 1361 rl_init_locked(sc); 1362 } 1363 } 1364 1365 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1366 rl_start_locked(ifp); 1367 1368done_locked: 1369 RL_UNLOCK(sc); 1370} 1371 1372/* 1373 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1374 * pointers to the fragment pointers. 1375 */ 1376static int 1377rl_encap(struct rl_softc *sc, struct mbuf *m_head) 1378{ 1379 struct mbuf *m_new = NULL; 1380 1381 RL_LOCK_ASSERT(sc); 1382 1383 /* 1384 * The RealTek is brain damaged and wants longword-aligned 1385 * TX buffers, plus we can only have one fragment buffer 1386 * per packet. We have to copy pretty much all the time. 1387 */ 1388 m_new = m_defrag(m_head, M_DONTWAIT); 1389 1390 if (m_new == NULL) { 1391 m_freem(m_head); 1392 return (1); 1393 } 1394 m_head = m_new; 1395 1396 /* Pad frames to at least 60 bytes. */ 1397 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1398 /* 1399 * Make security concious people happy: zero out the 1400 * bytes in the pad area, since we don't know what 1401 * this mbuf cluster buffer's previous user might 1402 * have left in it. 1403 */ 1404 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1405 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1406 m_head->m_pkthdr.len += 1407 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1408 m_head->m_len = m_head->m_pkthdr.len; 1409 } 1410 1411 RL_CUR_TXMBUF(sc) = m_head; 1412 1413 return (0); 1414} 1415 1416/* 1417 * Main transmit routine. 1418 */ 1419static void 1420rl_start(struct ifnet *ifp) 1421{ 1422 struct rl_softc *sc = ifp->if_softc; 1423 1424 RL_LOCK(sc); 1425 rl_start_locked(ifp); 1426 RL_UNLOCK(sc); 1427} 1428 1429static void 1430rl_start_locked(struct ifnet *ifp) 1431{ 1432 struct rl_softc *sc = ifp->if_softc; 1433 struct mbuf *m_head = NULL; 1434 1435 RL_LOCK_ASSERT(sc); 1436 1437 while (RL_CUR_TXMBUF(sc) == NULL) { 1438 1439 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1440 1441 if (m_head == NULL) 1442 break; 1443 1444 if (rl_encap(sc, m_head)) 1445 break; 1446 1447 /* Pass a copy of this mbuf chain to the bpf subsystem. */ 1448 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1449 1450 /* Transmit the frame. */ 1451 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1452 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1453 mtod(RL_CUR_TXMBUF(sc), void *), 1454 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 1455 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1456 BUS_DMASYNC_PREREAD); 1457 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1458 RL_TXTHRESH(sc->rl_txthresh) | 1459 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1460 1461 RL_INC(sc->rl_cdata.cur_tx); 1462 1463 /* Set a timeout in case the chip goes out to lunch. */ 1464 ifp->if_timer = 5; 1465 } 1466 1467 /* 1468 * We broke out of the loop because all our TX slots are 1469 * full. Mark the NIC as busy until it drains some of the 1470 * packets from the queue. 1471 */ 1472 if (RL_CUR_TXMBUF(sc) != NULL) 1473 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1474} 1475 1476static void 1477rl_init(void *xsc) 1478{ 1479 struct rl_softc *sc = xsc; 1480 1481 RL_LOCK(sc); 1482 rl_init_locked(sc); 1483 RL_UNLOCK(sc); 1484} 1485 1486static void 1487rl_init_locked(struct rl_softc *sc) 1488{ 1489 struct ifnet *ifp = sc->rl_ifp; 1490 struct mii_data *mii; 1491 uint32_t rxcfg = 0; 1492 1493 RL_LOCK_ASSERT(sc); 1494 1495 mii = device_get_softc(sc->rl_miibus); 1496 1497 /* 1498 * Cancel pending I/O and free all RX/TX buffers. 1499 */ 1500 rl_stop(sc); 1501 1502 /* 1503 * Init our MAC address. Even though the chipset 1504 * documentation doesn't mention it, we need to enter "Config 1505 * register write enable" mode to modify the ID registers. 1506 */ 1507 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1508 CSR_WRITE_STREAM_4(sc, RL_IDR0, 1509 *(uint32_t *)(&IFP2ENADDR(sc->rl_ifp)[0])); 1510 CSR_WRITE_STREAM_4(sc, RL_IDR4, 1511 *(uint32_t *)(&IFP2ENADDR(sc->rl_ifp)[4])); 1512 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1513 1514 /* Init the RX buffer pointer register. */ 1515 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1516 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 1517 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1518 BUS_DMASYNC_PREWRITE); 1519 1520 /* Init TX descriptors. */ 1521 rl_list_tx_init(sc); 1522 1523 /* 1524 * Enable transmit and receive. 1525 */ 1526 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1527 1528 /* 1529 * Set the initial TX and RX configuration. 1530 */ 1531 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1532 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1533 1534 /* Set the individual bit to receive frames for this host only. */ 1535 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1536 rxcfg |= RL_RXCFG_RX_INDIV; 1537 1538 /* If we want promiscuous mode, set the allframes bit. */ 1539 if (ifp->if_flags & IFF_PROMISC) { 1540 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1541 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1542 } else { 1543 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1544 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1545 } 1546 1547 /* Set capture broadcast bit to capture broadcast frames. */ 1548 if (ifp->if_flags & IFF_BROADCAST) { 1549 rxcfg |= RL_RXCFG_RX_BROAD; 1550 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1551 } else { 1552 rxcfg &= ~RL_RXCFG_RX_BROAD; 1553 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1554 } 1555 1556 /* Program the multicast filter, if necessary. */ 1557 rl_setmulti(sc); 1558 1559#ifdef DEVICE_POLLING 1560 /* Disable interrupts if we are polling. */ 1561 if (ifp->if_capenable & IFCAP_POLLING) 1562 CSR_WRITE_2(sc, RL_IMR, 0); 1563 else 1564#endif 1565 /* Enable interrupts. */ 1566 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1567 1568 /* Set initial TX threshold */ 1569 sc->rl_txthresh = RL_TX_THRESH_INIT; 1570 1571 /* Start RX/TX process. */ 1572 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1573 1574 /* Enable receiver and transmitter. */ 1575 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1576 1577 mii_mediachg(mii); 1578 1579 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1580 1581 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1582 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1583 1584 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc); 1585} 1586 1587/* 1588 * Set media options. 1589 */ 1590static int 1591rl_ifmedia_upd(struct ifnet *ifp) 1592{ 1593 struct rl_softc *sc = ifp->if_softc; 1594 struct mii_data *mii; 1595 1596 mii = device_get_softc(sc->rl_miibus); 1597 1598 RL_LOCK(sc); 1599 mii_mediachg(mii); 1600 RL_UNLOCK(sc); 1601 1602 return (0); 1603} 1604 1605/* 1606 * Report current media status. 1607 */ 1608static void 1609rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1610{ 1611 struct rl_softc *sc = ifp->if_softc; 1612 struct mii_data *mii; 1613 1614 mii = device_get_softc(sc->rl_miibus); 1615 1616 RL_LOCK(sc); 1617 mii_pollstat(mii); 1618 RL_UNLOCK(sc); 1619 ifmr->ifm_active = mii->mii_media_active; 1620 ifmr->ifm_status = mii->mii_media_status; 1621} 1622 1623static int 1624rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1625{ 1626 struct ifreq *ifr = (struct ifreq *)data; 1627 struct mii_data *mii; 1628 struct rl_softc *sc = ifp->if_softc; 1629 int error = 0; 1630 1631 switch (command) { 1632 case SIOCSIFFLAGS: 1633 RL_LOCK(sc); 1634 if (ifp->if_flags & IFF_UP) { 1635 rl_init_locked(sc); 1636 } else { 1637 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1638 rl_stop(sc); 1639 } 1640 RL_UNLOCK(sc); 1641 error = 0; 1642 break; 1643 case SIOCADDMULTI: 1644 case SIOCDELMULTI: 1645 RL_LOCK(sc); 1646 rl_setmulti(sc); 1647 RL_UNLOCK(sc); 1648 error = 0; 1649 break; 1650 case SIOCGIFMEDIA: 1651 case SIOCSIFMEDIA: 1652 mii = device_get_softc(sc->rl_miibus); 1653 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1654 break; 1655 case SIOCSIFCAP: 1656#ifdef DEVICE_POLLING 1657 if (ifr->ifr_reqcap & IFCAP_POLLING && 1658 !(ifp->if_capenable & IFCAP_POLLING)) { 1659 error = ether_poll_register(rl_poll, ifp); 1660 if (error) 1661 return(error); 1662 RL_LOCK(sc); 1663 /* Disable interrupts */ 1664 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1665 ifp->if_capenable |= IFCAP_POLLING; 1666 RL_UNLOCK(sc); 1667 return (error); 1668 1669 } 1670 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1671 ifp->if_capenable & IFCAP_POLLING) { 1672 error = ether_poll_deregister(ifp); 1673 /* Enable interrupts. */ 1674 RL_LOCK(sc); 1675 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1676 ifp->if_capenable &= ~IFCAP_POLLING; 1677 RL_UNLOCK(sc); 1678 return (error); 1679 } 1680#endif /* DEVICE_POLLING */ 1681 break; 1682 default: 1683 error = ether_ioctl(ifp, command, data); 1684 break; 1685 } 1686 1687 return (error); 1688} 1689 1690static void 1691rl_watchdog(struct ifnet *ifp) 1692{ 1693 struct rl_softc *sc = ifp->if_softc; 1694 1695 RL_LOCK(sc); 1696 1697 if_printf(ifp, "watchdog timeout\n"); 1698 ifp->if_oerrors++; 1699 1700 rl_txeof(sc); 1701 rl_rxeof(sc); 1702 rl_init_locked(sc); 1703 1704 RL_UNLOCK(sc); 1705} 1706 1707/* 1708 * Stop the adapter and free any mbufs allocated to the 1709 * RX and TX lists. 1710 */ 1711static void 1712rl_stop(struct rl_softc *sc) 1713{ 1714 register int i; 1715 struct ifnet *ifp = sc->rl_ifp; 1716 1717 RL_LOCK_ASSERT(sc); 1718 1719 ifp->if_timer = 0; 1720 callout_stop(&sc->rl_stat_callout); 1721 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1722 1723 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1724 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1725 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1726 1727 /* 1728 * Free the TX list buffers. 1729 */ 1730 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1731 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1732 bus_dmamap_unload(sc->rl_tag, 1733 sc->rl_cdata.rl_tx_dmamap[i]); 1734 bus_dmamap_destroy(sc->rl_tag, 1735 sc->rl_cdata.rl_tx_dmamap[i]); 1736 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1737 sc->rl_cdata.rl_tx_chain[i] = NULL; 1738 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 1739 0x0000000); 1740 } 1741 } 1742} 1743 1744/* 1745 * Device suspend routine. Stop the interface and save some PCI 1746 * settings in case the BIOS doesn't restore them properly on 1747 * resume. 1748 */ 1749static int 1750rl_suspend(device_t dev) 1751{ 1752 struct rl_softc *sc; 1753 1754 sc = device_get_softc(dev); 1755 1756 RL_LOCK(sc); 1757 rl_stop(sc); 1758 sc->suspended = 1; 1759 RL_UNLOCK(sc); 1760 1761 return (0); 1762} 1763 1764/* 1765 * Device resume routine. Restore some PCI settings in case the BIOS 1766 * doesn't, re-enable busmastering, and restart the interface if 1767 * appropriate. 1768 */ 1769static int 1770rl_resume(device_t dev) 1771{ 1772 struct rl_softc *sc; 1773 struct ifnet *ifp; 1774 1775 sc = device_get_softc(dev); 1776 ifp = sc->rl_ifp; 1777 1778 RL_LOCK(sc); 1779 1780 /* reinitialize interface if necessary */ 1781 if (ifp->if_flags & IFF_UP) 1782 rl_init_locked(sc); 1783 1784 sc->suspended = 0; 1785 1786 RL_UNLOCK(sc); 1787 1788 return (0); 1789} 1790 1791/* 1792 * Stop all chip I/O so that the kernel's probe routines don't 1793 * get confused by errant DMAs when rebooting. 1794 */ 1795static void 1796rl_shutdown(device_t dev) 1797{ 1798 struct rl_softc *sc; 1799 1800 sc = device_get_softc(dev); 1801 1802 RL_LOCK(sc); 1803 rl_stop(sc); 1804 RL_UNLOCK(sc); 1805} 1806