if_rl.c revision 147256
1/*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 147256 2005-06-10 16:49:24Z brooks $"); 35 36/* 37 * RealTek 8129/8139 PCI NIC driver 38 * 39 * Supports several extremely cheap PCI 10/100 adapters based on 40 * the RealTek chipset. Datasheets can be obtained from 41 * www.realtek.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86#include <sys/param.h> 87#include <sys/endian.h> 88#include <sys/systm.h> 89#include <sys/sockio.h> 90#include <sys/mbuf.h> 91#include <sys/malloc.h> 92#include <sys/kernel.h> 93#include <sys/module.h> 94#include <sys/socket.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> 98#include <net/ethernet.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101#include <net/if_types.h> 102 103#include <net/bpf.h> 104 105#include <machine/bus.h> 106#include <machine/resource.h> 107#include <sys/bus.h> 108#include <sys/rman.h> 109 110#include <dev/mii/mii.h> 111#include <dev/mii/miivar.h> 112 113#include <dev/pci/pcireg.h> 114#include <dev/pci/pcivar.h> 115 116MODULE_DEPEND(rl, pci, 1, 1, 1); 117MODULE_DEPEND(rl, ether, 1, 1, 1); 118MODULE_DEPEND(rl, miibus, 1, 1, 1); 119 120/* "controller miibus0" required. See GENERIC if you get errors here. */ 121#include "miibus_if.h" 122 123/* 124 * Default to using PIO access for this driver. On SMP systems, 125 * there appear to be problems with memory mapped mode: it looks like 126 * doing too many memory mapped access back to back in rapid succession 127 * can hang the bus. I'm inclined to blame this on crummy design/construction 128 * on the part of RealTek. Memory mapped mode does appear to work on 129 * uniprocessor systems though. 130 */ 131#define RL_USEIOSPACE 132 133#include <pci/if_rlreg.h> 134 135/* 136 * Various supported device vendors/types and their names. 137 */ 138static struct rl_type rl_devs[] = { 139 { RT_VENDORID, RT_DEVICEID_8129, RL_8129, 140 "RealTek 8129 10/100BaseTX" }, 141 { RT_VENDORID, RT_DEVICEID_8139, RL_8139, 142 "RealTek 8139 10/100BaseTX" }, 143 { RT_VENDORID, RT_DEVICEID_8138, RL_8139, 144 "RealTek 8139 10/100BaseTX CardBus" }, 145 { RT_VENDORID, RT_DEVICEID_8100, RL_8139, 146 "RealTek 8100 10/100BaseTX" }, 147 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 148 "Accton MPX 5030/5038 10/100BaseTX" }, 149 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139, 150 "Delta Electronics 8139 10/100BaseTX" }, 151 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139, 152 "Addtron Technolgy 8139 10/100BaseTX" }, 153 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139, 154 "D-Link DFE-530TX+ 10/100BaseTX" }, 155 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139, 156 "D-Link DFE-690TXD 10/100BaseTX" }, 157 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 158 "Nortel Networks 10/100BaseTX" }, 159 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139, 160 "Corega FEther CB-TXD" }, 161 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139, 162 "Corega FEtherII CB-TXD" }, 163 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139, 164 "Peppercon AG ROL-F" }, 165 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139, 166 "Planex FNW-3800-TX" }, 167 { CP_VENDORID, RT_DEVICEID_8139, RL_8139, 168 "Compaq HNE-300" }, 169 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139, 170 "LevelOne FPC-0106TX" }, 171 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139, 172 "Edimax EP-4103DL CardBus" }, 173 { 0, 0, 0, NULL } 174}; 175 176static int rl_attach(device_t); 177static int rl_detach(device_t); 178static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int); 179static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int); 180static void rl_eeprom_putbyte(struct rl_softc *, int); 181static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *); 182static int rl_encap(struct rl_softc *, struct mbuf * ); 183static int rl_list_tx_init(struct rl_softc *); 184static int rl_ifmedia_upd(struct ifnet *); 185static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 186static int rl_ioctl(struct ifnet *, u_long, caddr_t); 187static void rl_intr(void *); 188static void rl_init(void *); 189static void rl_init_locked(struct rl_softc *sc); 190static void rl_mii_send(struct rl_softc *, uint32_t, int); 191static void rl_mii_sync(struct rl_softc *); 192static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *); 193static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *); 194static int rl_miibus_readreg(device_t, int, int); 195static void rl_miibus_statchg(device_t); 196static int rl_miibus_writereg(device_t, int, int, int); 197#ifdef DEVICE_POLLING 198static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd, 199 int count); 200static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, 201 int count); 202#endif 203static int rl_probe(device_t); 204static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int); 205static void rl_reset(struct rl_softc *); 206static int rl_resume(device_t); 207static void rl_rxeof(struct rl_softc *); 208static void rl_setmulti(struct rl_softc *); 209static void rl_shutdown(device_t); 210static void rl_start(struct ifnet *); 211static void rl_start_locked(struct ifnet *); 212static void rl_stop(struct rl_softc *); 213static int rl_suspend(device_t); 214static void rl_tick(void *); 215static void rl_txeof(struct rl_softc *); 216static void rl_watchdog(struct ifnet *); 217 218#ifdef RL_USEIOSPACE 219#define RL_RES SYS_RES_IOPORT 220#define RL_RID RL_PCI_LOIO 221#else 222#define RL_RES SYS_RES_MEMORY 223#define RL_RID RL_PCI_LOMEM 224#endif 225 226static device_method_t rl_methods[] = { 227 /* Device interface */ 228 DEVMETHOD(device_probe, rl_probe), 229 DEVMETHOD(device_attach, rl_attach), 230 DEVMETHOD(device_detach, rl_detach), 231 DEVMETHOD(device_suspend, rl_suspend), 232 DEVMETHOD(device_resume, rl_resume), 233 DEVMETHOD(device_shutdown, rl_shutdown), 234 235 /* bus interface */ 236 DEVMETHOD(bus_print_child, bus_generic_print_child), 237 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 238 239 /* MII interface */ 240 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 241 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 242 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 243 244 { 0, 0 } 245}; 246 247static driver_t rl_driver = { 248 "rl", 249 rl_methods, 250 sizeof(struct rl_softc) 251}; 252 253static devclass_t rl_devclass; 254 255DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0); 256DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0); 257DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 258 259#define EE_SET(x) \ 260 CSR_WRITE_1(sc, RL_EECMD, \ 261 CSR_READ_1(sc, RL_EECMD) | x) 262 263#define EE_CLR(x) \ 264 CSR_WRITE_1(sc, RL_EECMD, \ 265 CSR_READ_1(sc, RL_EECMD) & ~x) 266 267static void 268rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) 269{ 270 struct rl_softc *sc = arg; 271 272 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 273} 274 275static void 276rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error) 277{ 278 struct rl_softc *sc = arg; 279 280 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 281} 282 283/* 284 * Send a read command and address to the EEPROM, check for ACK. 285 */ 286static void 287rl_eeprom_putbyte(struct rl_softc *sc, int addr) 288{ 289 register int d, i; 290 291 d = addr | sc->rl_eecmd_read; 292 293 /* 294 * Feed in each bit and strobe the clock. 295 */ 296 for (i = 0x400; i; i >>= 1) { 297 if (d & i) { 298 EE_SET(RL_EE_DATAIN); 299 } else { 300 EE_CLR(RL_EE_DATAIN); 301 } 302 DELAY(100); 303 EE_SET(RL_EE_CLK); 304 DELAY(150); 305 EE_CLR(RL_EE_CLK); 306 DELAY(100); 307 } 308} 309 310/* 311 * Read a word of data stored in the EEPROM at address 'addr.' 312 */ 313static void 314rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest) 315{ 316 register int i; 317 uint16_t word = 0; 318 319 /* Enter EEPROM access mode. */ 320 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 321 322 /* 323 * Send address of word we want to read. 324 */ 325 rl_eeprom_putbyte(sc, addr); 326 327 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 328 329 /* 330 * Start reading bits from EEPROM. 331 */ 332 for (i = 0x8000; i; i >>= 1) { 333 EE_SET(RL_EE_CLK); 334 DELAY(100); 335 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 336 word |= i; 337 EE_CLR(RL_EE_CLK); 338 DELAY(100); 339 } 340 341 /* Turn off EEPROM access mode. */ 342 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 343 344 *dest = word; 345} 346 347/* 348 * Read a sequence of words from the EEPROM. 349 */ 350static void 351rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap) 352{ 353 int i; 354 uint16_t word = 0, *ptr; 355 356 for (i = 0; i < cnt; i++) { 357 rl_eeprom_getword(sc, off + i, &word); 358 ptr = (uint16_t *)(dest + (i * 2)); 359 if (swap) 360 *ptr = ntohs(word); 361 else 362 *ptr = word; 363 } 364} 365 366/* 367 * MII access routines are provided for the 8129, which 368 * doesn't have a built-in PHY. For the 8139, we fake things 369 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 370 * direct access PHY registers. 371 */ 372#define MII_SET(x) \ 373 CSR_WRITE_1(sc, RL_MII, \ 374 CSR_READ_1(sc, RL_MII) | (x)) 375 376#define MII_CLR(x) \ 377 CSR_WRITE_1(sc, RL_MII, \ 378 CSR_READ_1(sc, RL_MII) & ~(x)) 379 380/* 381 * Sync the PHYs by setting data bit and strobing the clock 32 times. 382 */ 383static void 384rl_mii_sync(struct rl_softc *sc) 385{ 386 register int i; 387 388 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 389 390 for (i = 0; i < 32; i++) { 391 MII_SET(RL_MII_CLK); 392 DELAY(1); 393 MII_CLR(RL_MII_CLK); 394 DELAY(1); 395 } 396} 397 398/* 399 * Clock a series of bits through the MII. 400 */ 401static void 402rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt) 403{ 404 int i; 405 406 MII_CLR(RL_MII_CLK); 407 408 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 409 if (bits & i) { 410 MII_SET(RL_MII_DATAOUT); 411 } else { 412 MII_CLR(RL_MII_DATAOUT); 413 } 414 DELAY(1); 415 MII_CLR(RL_MII_CLK); 416 DELAY(1); 417 MII_SET(RL_MII_CLK); 418 } 419} 420 421/* 422 * Read an PHY register through the MII. 423 */ 424static int 425rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame) 426{ 427 int i, ack; 428 429 RL_LOCK(sc); 430 431 /* Set up frame for RX. */ 432 frame->mii_stdelim = RL_MII_STARTDELIM; 433 frame->mii_opcode = RL_MII_READOP; 434 frame->mii_turnaround = 0; 435 frame->mii_data = 0; 436 437 CSR_WRITE_2(sc, RL_MII, 0); 438 439 /* Turn on data xmit. */ 440 MII_SET(RL_MII_DIR); 441 442 rl_mii_sync(sc); 443 444 /* Send command/address info. */ 445 rl_mii_send(sc, frame->mii_stdelim, 2); 446 rl_mii_send(sc, frame->mii_opcode, 2); 447 rl_mii_send(sc, frame->mii_phyaddr, 5); 448 rl_mii_send(sc, frame->mii_regaddr, 5); 449 450 /* Idle bit */ 451 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 452 DELAY(1); 453 MII_SET(RL_MII_CLK); 454 DELAY(1); 455 456 /* Turn off xmit. */ 457 MII_CLR(RL_MII_DIR); 458 459 /* Check for ack */ 460 MII_CLR(RL_MII_CLK); 461 DELAY(1); 462 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 463 MII_SET(RL_MII_CLK); 464 DELAY(1); 465 466 /* 467 * Now try reading data bits. If the ack failed, we still 468 * need to clock through 16 cycles to keep the PHY(s) in sync. 469 */ 470 if (ack) { 471 for(i = 0; i < 16; i++) { 472 MII_CLR(RL_MII_CLK); 473 DELAY(1); 474 MII_SET(RL_MII_CLK); 475 DELAY(1); 476 } 477 goto fail; 478 } 479 480 for (i = 0x8000; i; i >>= 1) { 481 MII_CLR(RL_MII_CLK); 482 DELAY(1); 483 if (!ack) { 484 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 485 frame->mii_data |= i; 486 DELAY(1); 487 } 488 MII_SET(RL_MII_CLK); 489 DELAY(1); 490 } 491 492fail: 493 MII_CLR(RL_MII_CLK); 494 DELAY(1); 495 MII_SET(RL_MII_CLK); 496 DELAY(1); 497 498 RL_UNLOCK(sc); 499 500 return (ack ? 1 : 0); 501} 502 503/* 504 * Write to a PHY register through the MII. 505 */ 506static int 507rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame) 508{ 509 510 RL_LOCK(sc); 511 512 /* Set up frame for TX. */ 513 frame->mii_stdelim = RL_MII_STARTDELIM; 514 frame->mii_opcode = RL_MII_WRITEOP; 515 frame->mii_turnaround = RL_MII_TURNAROUND; 516 517 /* Turn on data output. */ 518 MII_SET(RL_MII_DIR); 519 520 rl_mii_sync(sc); 521 522 rl_mii_send(sc, frame->mii_stdelim, 2); 523 rl_mii_send(sc, frame->mii_opcode, 2); 524 rl_mii_send(sc, frame->mii_phyaddr, 5); 525 rl_mii_send(sc, frame->mii_regaddr, 5); 526 rl_mii_send(sc, frame->mii_turnaround, 2); 527 rl_mii_send(sc, frame->mii_data, 16); 528 529 /* Idle bit. */ 530 MII_SET(RL_MII_CLK); 531 DELAY(1); 532 MII_CLR(RL_MII_CLK); 533 DELAY(1); 534 535 /* Turn off xmit. */ 536 MII_CLR(RL_MII_DIR); 537 538 RL_UNLOCK(sc); 539 540 return (0); 541} 542 543static int 544rl_miibus_readreg(device_t dev, int phy, int reg) 545{ 546 struct rl_softc *sc; 547 struct rl_mii_frame frame; 548 uint16_t rval = 0; 549 uint16_t rl8139_reg = 0; 550 551 sc = device_get_softc(dev); 552 553 if (sc->rl_type == RL_8139) { 554 /* Pretend the internal PHY is only at address 0 */ 555 if (phy) { 556 return (0); 557 } 558 switch (reg) { 559 case MII_BMCR: 560 rl8139_reg = RL_BMCR; 561 break; 562 case MII_BMSR: 563 rl8139_reg = RL_BMSR; 564 break; 565 case MII_ANAR: 566 rl8139_reg = RL_ANAR; 567 break; 568 case MII_ANER: 569 rl8139_reg = RL_ANER; 570 break; 571 case MII_ANLPAR: 572 rl8139_reg = RL_LPAR; 573 break; 574 case MII_PHYIDR1: 575 case MII_PHYIDR2: 576 return (0); 577 /* 578 * Allow the rlphy driver to read the media status 579 * register. If we have a link partner which does not 580 * support NWAY, this is the register which will tell 581 * us the results of parallel detection. 582 */ 583 case RL_MEDIASTAT: 584 rval = CSR_READ_1(sc, RL_MEDIASTAT); 585 return (rval); 586 default: 587 if_printf(sc->rl_ifp, "bad phy register\n"); 588 return (0); 589 } 590 rval = CSR_READ_2(sc, rl8139_reg); 591 return (rval); 592 } 593 594 bzero((char *)&frame, sizeof(frame)); 595 frame.mii_phyaddr = phy; 596 frame.mii_regaddr = reg; 597 rl_mii_readreg(sc, &frame); 598 599 return (frame.mii_data); 600} 601 602static int 603rl_miibus_writereg(device_t dev, int phy, int reg, int data) 604{ 605 struct rl_softc *sc; 606 struct rl_mii_frame frame; 607 uint16_t rl8139_reg = 0; 608 609 sc = device_get_softc(dev); 610 611 if (sc->rl_type == RL_8139) { 612 /* Pretend the internal PHY is only at address 0 */ 613 if (phy) { 614 return (0); 615 } 616 switch (reg) { 617 case MII_BMCR: 618 rl8139_reg = RL_BMCR; 619 break; 620 case MII_BMSR: 621 rl8139_reg = RL_BMSR; 622 break; 623 case MII_ANAR: 624 rl8139_reg = RL_ANAR; 625 break; 626 case MII_ANER: 627 rl8139_reg = RL_ANER; 628 break; 629 case MII_ANLPAR: 630 rl8139_reg = RL_LPAR; 631 break; 632 case MII_PHYIDR1: 633 case MII_PHYIDR2: 634 return (0); 635 break; 636 default: 637 if_printf(sc->rl_ifp, "bad phy register\n"); 638 return (0); 639 } 640 CSR_WRITE_2(sc, rl8139_reg, data); 641 return (0); 642 } 643 644 bzero((char *)&frame, sizeof(frame)); 645 frame.mii_phyaddr = phy; 646 frame.mii_regaddr = reg; 647 frame.mii_data = data; 648 rl_mii_writereg(sc, &frame); 649 650 return (0); 651} 652 653static void 654rl_miibus_statchg(device_t dev) 655{ 656} 657 658/* 659 * Program the 64-bit multicast hash filter. 660 */ 661static void 662rl_setmulti(struct rl_softc *sc) 663{ 664 struct ifnet *ifp = sc->rl_ifp; 665 int h = 0; 666 uint32_t hashes[2] = { 0, 0 }; 667 struct ifmultiaddr *ifma; 668 uint32_t rxfilt; 669 int mcnt = 0; 670 671 RL_LOCK_ASSERT(sc); 672 673 rxfilt = CSR_READ_4(sc, RL_RXCFG); 674 675 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 676 rxfilt |= RL_RXCFG_RX_MULTI; 677 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 678 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 679 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 680 return; 681 } 682 683 /* first, zot all the existing hash bits */ 684 CSR_WRITE_4(sc, RL_MAR0, 0); 685 CSR_WRITE_4(sc, RL_MAR4, 0); 686 687 /* now program new ones */ 688 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 689 if (ifma->ifma_addr->sa_family != AF_LINK) 690 continue; 691 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 692 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 693 if (h < 32) 694 hashes[0] |= (1 << h); 695 else 696 hashes[1] |= (1 << (h - 32)); 697 mcnt++; 698 } 699 700 if (mcnt) 701 rxfilt |= RL_RXCFG_RX_MULTI; 702 else 703 rxfilt &= ~RL_RXCFG_RX_MULTI; 704 705 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 706 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 707 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 708} 709 710static void 711rl_reset(struct rl_softc *sc) 712{ 713 register int i; 714 715 RL_LOCK_ASSERT(sc); 716 717 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 718 719 for (i = 0; i < RL_TIMEOUT; i++) { 720 DELAY(10); 721 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 722 break; 723 } 724 if (i == RL_TIMEOUT) 725 if_printf(sc->rl_ifp, "reset never completed!\n"); 726} 727 728/* 729 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 730 * IDs against our list and return a device name if we find a match. 731 */ 732static int 733rl_probe(device_t dev) 734{ 735 struct rl_softc *sc; 736 struct rl_type *t = rl_devs; 737 int rid; 738 uint32_t hwrev; 739 740 sc = device_get_softc(dev); 741 742 while (t->rl_name != NULL) { 743 if ((pci_get_vendor(dev) == t->rl_vid) && 744 (pci_get_device(dev) == t->rl_did)) { 745 /* 746 * Temporarily map the I/O space 747 * so we can read the chip ID register. 748 */ 749 rid = RL_RID; 750 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 751 RF_ACTIVE); 752 if (sc->rl_res == NULL) { 753 device_printf(dev, 754 "couldn't map ports/memory\n"); 755 return (ENXIO); 756 } 757 sc->rl_btag = rman_get_bustag(sc->rl_res); 758 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 759 760 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 761 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 762 763 /* Don't attach to 8139C+ or 8169/8110 chips. */ 764 if (hwrev == RL_HWREV_8139CPLUS || 765 (hwrev == RL_HWREV_8169 && 766 t->rl_did == RT_DEVICEID_8169) || 767 hwrev == RL_HWREV_8169S || 768 hwrev == RL_HWREV_8110S) { 769 t++; 770 continue; 771 } 772 773 device_set_desc(dev, t->rl_name); 774 return (BUS_PROBE_DEFAULT); 775 } 776 t++; 777 } 778 779 return (ENXIO); 780} 781 782/* 783 * Attach the interface. Allocate softc structures, do ifmedia 784 * setup and ethernet/BPF attach. 785 */ 786static int 787rl_attach(device_t dev) 788{ 789 uint8_t eaddr[ETHER_ADDR_LEN]; 790 uint16_t as[3]; 791 struct ifnet *ifp; 792 struct rl_softc *sc; 793 struct rl_type *t; 794 int error = 0, i, rid; 795 int unit; 796 uint16_t rl_did = 0; 797 798 sc = device_get_softc(dev); 799 unit = device_get_unit(dev); 800 801 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 802 MTX_DEF); 803 804 pci_enable_busmaster(dev); 805 806 /* Map control/status registers. */ 807 rid = RL_RID; 808 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE); 809 810 if (sc->rl_res == NULL) { 811 device_printf(dev, "couldn't map ports/memory\n"); 812 error = ENXIO; 813 goto fail; 814 } 815 816#ifdef notdef 817 /* 818 * Detect the Realtek 8139B. For some reason, this chip is very 819 * unstable when left to autoselect the media 820 * The best workaround is to set the device to the required 821 * media type or to set it to the 10 Meg speed. 822 */ 823 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF) 824 device_printf(dev, 825"Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n"); 826#endif 827 828 sc->rl_btag = rman_get_bustag(sc->rl_res); 829 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 830 831 /* Allocate interrupt */ 832 rid = 0; 833 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 834 RF_SHAREABLE | RF_ACTIVE); 835 836 if (sc->rl_irq == NULL) { 837 device_printf(dev, "couldn't map interrupt\n"); 838 error = ENXIO; 839 goto fail; 840 } 841 842 /* 843 * Reset the adapter. Only take the lock here as it's needed in 844 * order to call rl_reset(). 845 */ 846 RL_LOCK(sc); 847 rl_reset(sc); 848 RL_UNLOCK(sc); 849 850 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 851 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0); 852 if (rl_did != 0x8129) 853 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 854 855 /* 856 * Get station address from the EEPROM. 857 */ 858 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0); 859 for (i = 0; i < 3; i++) { 860 eaddr[(i * 2) + 0] = as[i] & 0xff; 861 eaddr[(i * 2) + 1] = as[i] >> 8; 862 } 863 864 sc->rl_unit = unit; 865 866 /* 867 * Now read the exact device type from the EEPROM to find 868 * out if it's an 8129 or 8139. 869 */ 870 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0); 871 872 t = rl_devs; 873 sc->rl_type = 0; 874 while(t->rl_name != NULL) { 875 if (rl_did == t->rl_did) { 876 sc->rl_type = t->rl_basetype; 877 break; 878 } 879 t++; 880 } 881 882 if (sc->rl_type == 0) { 883 device_printf(dev, "unknown device ID: %x\n", rl_did); 884 error = ENXIO; 885 goto fail; 886 } 887 888 /* 889 * Allocate the parent bus DMA tag appropriate for PCI. 890 */ 891#define RL_NSEG_NEW 32 892 error = bus_dma_tag_create(NULL, /* parent */ 893 1, 0, /* alignment, boundary */ 894 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 895 BUS_SPACE_MAXADDR, /* highaddr */ 896 NULL, NULL, /* filter, filterarg */ 897 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 898 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 899 BUS_DMA_ALLOCNOW, /* flags */ 900 NULL, NULL, /* lockfunc, lockarg */ 901 &sc->rl_parent_tag); 902 if (error) 903 goto fail; 904 905 /* 906 * Now allocate a tag for the DMA descriptor lists. 907 * All of our lists are allocated as a contiguous block 908 * of memory. 909 */ 910 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 911 1, 0, /* alignment, boundary */ 912 BUS_SPACE_MAXADDR, /* lowaddr */ 913 BUS_SPACE_MAXADDR, /* highaddr */ 914 NULL, NULL, /* filter, filterarg */ 915 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 916 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 917 BUS_DMA_ALLOCNOW, /* flags */ 918 NULL, NULL, /* lockfunc, lockarg */ 919 &sc->rl_tag); 920 if (error) 921 goto fail; 922 923 /* 924 * Now allocate a chunk of DMA-able memory based on the 925 * tag we just created. 926 */ 927 error = bus_dmamem_alloc(sc->rl_tag, 928 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 929 &sc->rl_cdata.rl_rx_dmamap); 930 if (error) { 931 device_printf(dev, "no memory for list buffers!\n"); 932 bus_dma_tag_destroy(sc->rl_tag); 933 sc->rl_tag = NULL; 934 goto fail; 935 } 936 937 /* Leave a few bytes before the start of the RX ring buffer. */ 938 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 939 sc->rl_cdata.rl_rx_buf += sizeof(uint64_t); 940 941 /* Do MII setup */ 942 if (mii_phy_probe(dev, &sc->rl_miibus, 943 rl_ifmedia_upd, rl_ifmedia_sts)) { 944 device_printf(dev, "MII without any phy!\n"); 945 error = ENXIO; 946 goto fail; 947 } 948 949 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 950 if (ifp == NULL) { 951 device_printf(dev, "can not if_alloc()\n"); 952 error = ENOSPC; 953 goto fail; 954 } 955 ifp->if_softc = sc; 956 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 957 ifp->if_mtu = ETHERMTU; 958 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 959 ifp->if_ioctl = rl_ioctl; 960 ifp->if_start = rl_start; 961 ifp->if_watchdog = rl_watchdog; 962 ifp->if_init = rl_init; 963 ifp->if_baudrate = 10000000; 964 ifp->if_capabilities = IFCAP_VLAN_MTU; 965#ifdef DEVICE_POLLING 966 ifp->if_capabilities |= IFCAP_POLLING; 967#endif 968 ifp->if_capenable = ifp->if_capabilities; 969 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 970 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 971 IFQ_SET_READY(&ifp->if_snd); 972 973 callout_handle_init(&sc->rl_stat_ch); 974 975 /* 976 * Call MI attach routine. 977 */ 978 ether_ifattach(ifp, eaddr); 979 980 /* Hook interrupt last to avoid having to lock softc */ 981 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE, 982 rl_intr, sc, &sc->rl_intrhand); 983 if (error) { 984 if_printf(ifp, "couldn't set up irq\n"); 985 ether_ifdetach(ifp); 986 if_free(ifp); 987 } 988 989fail: 990 if (error) 991 rl_detach(dev); 992 993 return (error); 994} 995 996/* 997 * Shutdown hardware and free up resources. This can be called any 998 * time after the mutex has been initialized. It is called in both 999 * the error case in attach and the normal detach case so it needs 1000 * to be careful about only freeing resources that have actually been 1001 * allocated. 1002 */ 1003static int 1004rl_detach(device_t dev) 1005{ 1006 struct rl_softc *sc; 1007 struct ifnet *ifp; 1008 int attached; 1009 1010 sc = device_get_softc(dev); 1011 ifp = sc->rl_ifp; 1012 1013 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 1014 attached = device_is_attached(dev); 1015 /* These should only be active if attach succeeded */ 1016 if (attached) { 1017 ether_ifdetach(ifp); 1018 if_free(ifp); 1019 } 1020 RL_LOCK(sc); 1021#if 0 1022 sc->suspended = 1; 1023#endif 1024 if (attached) 1025 rl_stop(sc); 1026 if (sc->rl_miibus) 1027 device_delete_child(dev, sc->rl_miibus); 1028 bus_generic_detach(dev); 1029 1030 if (sc->rl_intrhand) 1031 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1032 if (sc->rl_irq) 1033 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1034 if (sc->rl_res) 1035 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1036 1037 if (sc->rl_tag) { 1038 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1039 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1040 sc->rl_cdata.rl_rx_dmamap); 1041 bus_dma_tag_destroy(sc->rl_tag); 1042 } 1043 if (sc->rl_parent_tag) 1044 bus_dma_tag_destroy(sc->rl_parent_tag); 1045 1046 RL_UNLOCK(sc); 1047 mtx_destroy(&sc->rl_mtx); 1048 1049 return (0); 1050} 1051 1052/* 1053 * Initialize the transmit descriptors. 1054 */ 1055static int 1056rl_list_tx_init(struct rl_softc *sc) 1057{ 1058 struct rl_chain_data *cd; 1059 int i; 1060 1061 RL_LOCK_ASSERT(sc); 1062 1063 cd = &sc->rl_cdata; 1064 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1065 cd->rl_tx_chain[i] = NULL; 1066 CSR_WRITE_4(sc, 1067 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000); 1068 } 1069 1070 sc->rl_cdata.cur_tx = 0; 1071 sc->rl_cdata.last_tx = 0; 1072 1073 return (0); 1074} 1075 1076/* 1077 * A frame has been uploaded: pass the resulting mbuf chain up to 1078 * the higher level protocols. 1079 * 1080 * You know there's something wrong with a PCI bus-master chip design 1081 * when you have to use m_devget(). 1082 * 1083 * The receive operation is badly documented in the datasheet, so I'll 1084 * attempt to document it here. The driver provides a buffer area and 1085 * places its base address in the RX buffer start address register. 1086 * The chip then begins copying frames into the RX buffer. Each frame 1087 * is preceded by a 32-bit RX status word which specifies the length 1088 * of the frame and certain other status bits. Each frame (starting with 1089 * the status word) is also 32-bit aligned. The frame length is in the 1090 * first 16 bits of the status word; the lower 15 bits correspond with 1091 * the 'rx status register' mentioned in the datasheet. 1092 * 1093 * Note: to make the Alpha happy, the frame payload needs to be aligned 1094 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1095 * as the offset argument to m_devget(). 1096 */ 1097static void 1098rl_rxeof(struct rl_softc *sc) 1099{ 1100 struct mbuf *m; 1101 struct ifnet *ifp = sc->rl_ifp; 1102 uint8_t *rxbufpos; 1103 int total_len = 0; 1104 int wrap = 0; 1105 uint32_t rxstat; 1106 uint16_t cur_rx; 1107 uint16_t limit; 1108 uint16_t max_bytes, rx_bytes = 0; 1109 1110 RL_LOCK_ASSERT(sc); 1111 1112 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1113 BUS_DMASYNC_POSTREAD); 1114 1115 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1116 1117 /* Do not try to read past this point. */ 1118 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1119 1120 if (limit < cur_rx) 1121 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1122 else 1123 max_bytes = limit - cur_rx; 1124 1125 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1126#ifdef DEVICE_POLLING 1127 if (ifp->if_flags & IFF_POLLING) { 1128 if (sc->rxcycles <= 0) 1129 break; 1130 sc->rxcycles--; 1131 } 1132#endif /* DEVICE_POLLING */ 1133 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1134 rxstat = le32toh(*(uint32_t *)rxbufpos); 1135 1136 /* 1137 * Here's a totally undocumented fact for you. When the 1138 * RealTek chip is in the process of copying a packet into 1139 * RAM for you, the length will be 0xfff0. If you spot a 1140 * packet header with this value, you need to stop. The 1141 * datasheet makes absolutely no mention of this and 1142 * RealTek should be shot for this. 1143 */ 1144 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1145 break; 1146 1147 if (!(rxstat & RL_RXSTAT_RXOK)) { 1148 ifp->if_ierrors++; 1149 rl_init_locked(sc); 1150 return; 1151 } 1152 1153 /* No errors; receive the packet. */ 1154 total_len = rxstat >> 16; 1155 rx_bytes += total_len + 4; 1156 1157 /* 1158 * XXX The RealTek chip includes the CRC with every 1159 * received frame, and there's no way to turn this 1160 * behavior off (at least, I can't find anything in 1161 * the manual that explains how to do it) so we have 1162 * to trim off the CRC manually. 1163 */ 1164 total_len -= ETHER_CRC_LEN; 1165 1166 /* 1167 * Avoid trying to read more bytes than we know 1168 * the chip has prepared for us. 1169 */ 1170 if (rx_bytes > max_bytes) 1171 break; 1172 1173 rxbufpos = sc->rl_cdata.rl_rx_buf + 1174 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN); 1175 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1176 rxbufpos = sc->rl_cdata.rl_rx_buf; 1177 1178 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1179 if (total_len > wrap) { 1180 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1181 NULL); 1182 if (m == NULL) { 1183 ifp->if_ierrors++; 1184 } else { 1185 m_copyback(m, wrap, total_len - wrap, 1186 sc->rl_cdata.rl_rx_buf); 1187 } 1188 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1189 } else { 1190 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1191 NULL); 1192 if (m == NULL) 1193 ifp->if_ierrors++; 1194 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1195 } 1196 1197 /* Round up to 32-bit boundary. */ 1198 cur_rx = (cur_rx + 3) & ~3; 1199 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1200 1201 if (m == NULL) 1202 continue; 1203 1204 ifp->if_ipackets++; 1205 RL_UNLOCK(sc); 1206 (*ifp->if_input)(ifp, m); 1207 RL_LOCK(sc); 1208 } 1209} 1210 1211/* 1212 * A frame was downloaded to the chip. It's safe for us to clean up 1213 * the list buffers. 1214 */ 1215static void 1216rl_txeof(struct rl_softc *sc) 1217{ 1218 struct ifnet *ifp = sc->rl_ifp; 1219 uint32_t txstat; 1220 1221 RL_LOCK_ASSERT(sc); 1222 1223 /* 1224 * Go through our tx list and free mbufs for those 1225 * frames that have been uploaded. 1226 */ 1227 do { 1228 if (RL_LAST_TXMBUF(sc) == NULL) 1229 break; 1230 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1231 if (!(txstat & (RL_TXSTAT_TX_OK| 1232 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1233 break; 1234 1235 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1236 1237 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1238 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1239 m_freem(RL_LAST_TXMBUF(sc)); 1240 RL_LAST_TXMBUF(sc) = NULL; 1241 /* 1242 * If there was a transmit underrun, bump the TX threshold. 1243 * Make sure not to overflow the 63 * 32byte we can address 1244 * with the 6 available bit. 1245 */ 1246 if ((txstat & RL_TXSTAT_TX_UNDERRUN) && 1247 (sc->rl_txthresh < 2016)) 1248 sc->rl_txthresh += 32; 1249 if (txstat & RL_TXSTAT_TX_OK) 1250 ifp->if_opackets++; 1251 else { 1252 int oldthresh; 1253 ifp->if_oerrors++; 1254 if ((txstat & RL_TXSTAT_TXABRT) || 1255 (txstat & RL_TXSTAT_OUTOFWIN)) 1256 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1257 oldthresh = sc->rl_txthresh; 1258 /* error recovery */ 1259 rl_reset(sc); 1260 rl_init_locked(sc); 1261 /* restore original threshold */ 1262 sc->rl_txthresh = oldthresh; 1263 return; 1264 } 1265 RL_INC(sc->rl_cdata.last_tx); 1266 ifp->if_flags &= ~IFF_OACTIVE; 1267 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1268 1269 if (RL_LAST_TXMBUF(sc) == NULL) 1270 ifp->if_timer = 0; 1271 else if (ifp->if_timer == 0) 1272 ifp->if_timer = 5; 1273} 1274 1275static void 1276rl_tick(void *xsc) 1277{ 1278 struct rl_softc *sc = xsc; 1279 struct mii_data *mii; 1280 1281 RL_LOCK(sc); 1282 mii = device_get_softc(sc->rl_miibus); 1283 mii_tick(mii); 1284 1285 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1286 RL_UNLOCK(sc); 1287} 1288 1289#ifdef DEVICE_POLLING 1290static void 1291rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1292{ 1293 struct rl_softc *sc = ifp->if_softc; 1294 1295 RL_LOCK(sc); 1296 rl_poll_locked(ifp, cmd, count); 1297 RL_UNLOCK(sc); 1298} 1299 1300static void 1301rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1302{ 1303 struct rl_softc *sc = ifp->if_softc; 1304 1305 RL_LOCK_ASSERT(sc); 1306 1307 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1308 ether_poll_deregister(ifp); 1309 cmd = POLL_DEREGISTER; 1310 } 1311 1312 if (cmd == POLL_DEREGISTER) { 1313 /* Final call; enable interrupts. */ 1314 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1315 return; 1316 } 1317 1318 sc->rxcycles = count; 1319 rl_rxeof(sc); 1320 rl_txeof(sc); 1321 1322 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1323 rl_start_locked(ifp); 1324 1325 if (cmd == POLL_AND_CHECK_STATUS) { 1326 uint16_t status; 1327 1328 /* We should also check the status register. */ 1329 status = CSR_READ_2(sc, RL_ISR); 1330 if (status == 0xffff) 1331 return; 1332 if (status != 0) 1333 CSR_WRITE_2(sc, RL_ISR, status); 1334 1335 /* XXX We should check behaviour on receiver stalls. */ 1336 1337 if (status & RL_ISR_SYSTEM_ERR) { 1338 rl_reset(sc); 1339 rl_init_locked(sc); 1340 } 1341 } 1342} 1343#endif /* DEVICE_POLLING */ 1344 1345static void 1346rl_intr(void *arg) 1347{ 1348 struct rl_softc *sc = arg; 1349 struct ifnet *ifp = sc->rl_ifp; 1350 uint16_t status; 1351 1352 RL_LOCK(sc); 1353 1354 if (sc->suspended) 1355 goto done_locked; 1356 1357#ifdef DEVICE_POLLING 1358 if (ifp->if_flags & IFF_POLLING) 1359 goto done_locked; 1360 1361 if ((ifp->if_capenable & IFCAP_POLLING) && 1362 ether_poll_register(rl_poll, ifp)) { 1363 /* Disable interrupts. */ 1364 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1365 rl_poll_locked(ifp, 0, 1); 1366 goto done_locked; 1367 } 1368#endif /* DEVICE_POLLING */ 1369 1370 for (;;) { 1371 status = CSR_READ_2(sc, RL_ISR); 1372 /* If the card has gone away, the read returns 0xffff. */ 1373 if (status == 0xffff) 1374 break; 1375 if (status != 0) 1376 CSR_WRITE_2(sc, RL_ISR, status); 1377 if ((status & RL_INTRS) == 0) 1378 break; 1379 if (status & RL_ISR_RX_OK) 1380 rl_rxeof(sc); 1381 if (status & RL_ISR_RX_ERR) 1382 rl_rxeof(sc); 1383 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1384 rl_txeof(sc); 1385 if (status & RL_ISR_SYSTEM_ERR) { 1386 rl_reset(sc); 1387 rl_init_locked(sc); 1388 } 1389 } 1390 1391 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1392 rl_start_locked(ifp); 1393 1394done_locked: 1395 RL_UNLOCK(sc); 1396} 1397 1398/* 1399 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1400 * pointers to the fragment pointers. 1401 */ 1402static int 1403rl_encap(struct rl_softc *sc, struct mbuf *m_head) 1404{ 1405 struct mbuf *m_new = NULL; 1406 1407 RL_LOCK_ASSERT(sc); 1408 1409 /* 1410 * The RealTek is brain damaged and wants longword-aligned 1411 * TX buffers, plus we can only have one fragment buffer 1412 * per packet. We have to copy pretty much all the time. 1413 */ 1414 m_new = m_defrag(m_head, M_DONTWAIT); 1415 1416 if (m_new == NULL) { 1417 m_freem(m_head); 1418 return (1); 1419 } 1420 m_head = m_new; 1421 1422 /* Pad frames to at least 60 bytes. */ 1423 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1424 /* 1425 * Make security concious people happy: zero out the 1426 * bytes in the pad area, since we don't know what 1427 * this mbuf cluster buffer's previous user might 1428 * have left in it. 1429 */ 1430 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1431 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1432 m_head->m_pkthdr.len += 1433 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1434 m_head->m_len = m_head->m_pkthdr.len; 1435 } 1436 1437 RL_CUR_TXMBUF(sc) = m_head; 1438 1439 return (0); 1440} 1441 1442/* 1443 * Main transmit routine. 1444 */ 1445static void 1446rl_start(struct ifnet *ifp) 1447{ 1448 struct rl_softc *sc = ifp->if_softc; 1449 1450 RL_LOCK(sc); 1451 rl_start_locked(ifp); 1452 RL_UNLOCK(sc); 1453} 1454 1455static void 1456rl_start_locked(struct ifnet *ifp) 1457{ 1458 struct rl_softc *sc = ifp->if_softc; 1459 struct mbuf *m_head = NULL; 1460 1461 RL_LOCK_ASSERT(sc); 1462 1463 while (RL_CUR_TXMBUF(sc) == NULL) { 1464 1465 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1466 1467 if (m_head == NULL) 1468 break; 1469 1470 if (rl_encap(sc, m_head)) 1471 break; 1472 1473 /* Pass a copy of this mbuf chain to the bpf subsystem. */ 1474 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1475 1476 /* Transmit the frame. */ 1477 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1478 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1479 mtod(RL_CUR_TXMBUF(sc), void *), 1480 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 1481 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1482 BUS_DMASYNC_PREREAD); 1483 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1484 RL_TXTHRESH(sc->rl_txthresh) | 1485 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1486 1487 RL_INC(sc->rl_cdata.cur_tx); 1488 1489 /* Set a timeout in case the chip goes out to lunch. */ 1490 ifp->if_timer = 5; 1491 } 1492 1493 /* 1494 * We broke out of the loop because all our TX slots are 1495 * full. Mark the NIC as busy until it drains some of the 1496 * packets from the queue. 1497 */ 1498 if (RL_CUR_TXMBUF(sc) != NULL) 1499 ifp->if_flags |= IFF_OACTIVE; 1500} 1501 1502static void 1503rl_init(void *xsc) 1504{ 1505 struct rl_softc *sc = xsc; 1506 1507 RL_LOCK(sc); 1508 rl_init_locked(sc); 1509 RL_UNLOCK(sc); 1510} 1511 1512static void 1513rl_init_locked(struct rl_softc *sc) 1514{ 1515 struct ifnet *ifp = sc->rl_ifp; 1516 struct mii_data *mii; 1517 uint32_t rxcfg = 0; 1518 1519 RL_LOCK_ASSERT(sc); 1520 1521 mii = device_get_softc(sc->rl_miibus); 1522 1523 /* 1524 * Cancel pending I/O and free all RX/TX buffers. 1525 */ 1526 rl_stop(sc); 1527 1528 /* 1529 * Init our MAC address. Even though the chipset 1530 * documentation doesn't mention it, we need to enter "Config 1531 * register write enable" mode to modify the ID registers. 1532 */ 1533 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1534 CSR_WRITE_STREAM_4(sc, RL_IDR0, 1535 *(uint32_t *)(&IFP2ENADDR(sc->rl_ifp)[0])); 1536 CSR_WRITE_STREAM_4(sc, RL_IDR4, 1537 *(uint32_t *)(&IFP2ENADDR(sc->rl_ifp)[4])); 1538 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1539 1540 /* Init the RX buffer pointer register. */ 1541 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1542 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 1543 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1544 BUS_DMASYNC_PREWRITE); 1545 1546 /* Init TX descriptors. */ 1547 rl_list_tx_init(sc); 1548 1549 /* 1550 * Enable transmit and receive. 1551 */ 1552 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1553 1554 /* 1555 * Set the initial TX and RX configuration. 1556 */ 1557 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1558 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1559 1560 /* Set the individual bit to receive frames for this host only. */ 1561 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1562 rxcfg |= RL_RXCFG_RX_INDIV; 1563 1564 /* If we want promiscuous mode, set the allframes bit. */ 1565 if (ifp->if_flags & IFF_PROMISC) { 1566 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1567 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1568 } else { 1569 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1570 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1571 } 1572 1573 /* Set capture broadcast bit to capture broadcast frames. */ 1574 if (ifp->if_flags & IFF_BROADCAST) { 1575 rxcfg |= RL_RXCFG_RX_BROAD; 1576 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1577 } else { 1578 rxcfg &= ~RL_RXCFG_RX_BROAD; 1579 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1580 } 1581 1582 /* Program the multicast filter, if necessary. */ 1583 rl_setmulti(sc); 1584 1585#ifdef DEVICE_POLLING 1586 /* Disable interrupts if we are polling. */ 1587 if (ifp->if_flags & IFF_POLLING) 1588 CSR_WRITE_2(sc, RL_IMR, 0); 1589 else 1590#endif /* DEVICE_POLLING */ 1591 /* Enable interrupts. */ 1592 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1593 1594 /* Set initial TX threshold */ 1595 sc->rl_txthresh = RL_TX_THRESH_INIT; 1596 1597 /* Start RX/TX process. */ 1598 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1599 1600 /* Enable receiver and transmitter. */ 1601 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1602 1603 mii_mediachg(mii); 1604 1605 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1606 1607 ifp->if_flags |= IFF_RUNNING; 1608 ifp->if_flags &= ~IFF_OACTIVE; 1609 1610 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1611} 1612 1613/* 1614 * Set media options. 1615 */ 1616static int 1617rl_ifmedia_upd(struct ifnet *ifp) 1618{ 1619 struct rl_softc *sc = ifp->if_softc; 1620 struct mii_data *mii; 1621 1622 mii = device_get_softc(sc->rl_miibus); 1623 1624 mii_mediachg(mii); 1625 1626 return (0); 1627} 1628 1629/* 1630 * Report current media status. 1631 */ 1632static void 1633rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1634{ 1635 struct rl_softc *sc = ifp->if_softc; 1636 struct mii_data *mii; 1637 1638 mii = device_get_softc(sc->rl_miibus); 1639 1640 mii_pollstat(mii); 1641 ifmr->ifm_active = mii->mii_media_active; 1642 ifmr->ifm_status = mii->mii_media_status; 1643} 1644 1645static int 1646rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1647{ 1648 struct ifreq *ifr = (struct ifreq *)data; 1649 struct mii_data *mii; 1650 struct rl_softc *sc = ifp->if_softc; 1651 int error = 0; 1652 1653 switch (command) { 1654 case SIOCSIFFLAGS: 1655 RL_LOCK(sc); 1656 if (ifp->if_flags & IFF_UP) { 1657 rl_init_locked(sc); 1658 } else { 1659 if (ifp->if_flags & IFF_RUNNING) 1660 rl_stop(sc); 1661 } 1662 RL_UNLOCK(sc); 1663 error = 0; 1664 break; 1665 case SIOCADDMULTI: 1666 case SIOCDELMULTI: 1667 RL_LOCK(sc); 1668 rl_setmulti(sc); 1669 RL_UNLOCK(sc); 1670 error = 0; 1671 break; 1672 case SIOCGIFMEDIA: 1673 case SIOCSIFMEDIA: 1674 mii = device_get_softc(sc->rl_miibus); 1675 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1676 break; 1677 case SIOCSIFCAP: 1678 ifp->if_capenable &= ~IFCAP_POLLING; 1679 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 1680 break; 1681 default: 1682 error = ether_ioctl(ifp, command, data); 1683 break; 1684 } 1685 1686 return (error); 1687} 1688 1689static void 1690rl_watchdog(struct ifnet *ifp) 1691{ 1692 struct rl_softc *sc = ifp->if_softc; 1693 1694 RL_LOCK(sc); 1695 1696 if_printf(ifp, "watchdog timeout\n"); 1697 ifp->if_oerrors++; 1698 1699 rl_txeof(sc); 1700 rl_rxeof(sc); 1701 rl_init_locked(sc); 1702 1703 RL_UNLOCK(sc); 1704} 1705 1706/* 1707 * Stop the adapter and free any mbufs allocated to the 1708 * RX and TX lists. 1709 */ 1710static void 1711rl_stop(struct rl_softc *sc) 1712{ 1713 register int i; 1714 struct ifnet *ifp = sc->rl_ifp; 1715 1716 RL_LOCK_ASSERT(sc); 1717 1718 ifp->if_timer = 0; 1719 untimeout(rl_tick, sc, sc->rl_stat_ch); 1720 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1721#ifdef DEVICE_POLLING 1722 ether_poll_deregister(ifp); 1723#endif /* DEVICE_POLLING */ 1724 1725 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1726 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1727 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1728 1729 /* 1730 * Free the TX list buffers. 1731 */ 1732 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1733 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1734 bus_dmamap_unload(sc->rl_tag, 1735 sc->rl_cdata.rl_tx_dmamap[i]); 1736 bus_dmamap_destroy(sc->rl_tag, 1737 sc->rl_cdata.rl_tx_dmamap[i]); 1738 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1739 sc->rl_cdata.rl_tx_chain[i] = NULL; 1740 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 1741 0x0000000); 1742 } 1743 } 1744} 1745 1746/* 1747 * Device suspend routine. Stop the interface and save some PCI 1748 * settings in case the BIOS doesn't restore them properly on 1749 * resume. 1750 */ 1751static int 1752rl_suspend(device_t dev) 1753{ 1754 struct rl_softc *sc; 1755 1756 sc = device_get_softc(dev); 1757 1758 RL_LOCK(sc); 1759 rl_stop(sc); 1760 sc->suspended = 1; 1761 RL_UNLOCK(sc); 1762 1763 return (0); 1764} 1765 1766/* 1767 * Device resume routine. Restore some PCI settings in case the BIOS 1768 * doesn't, re-enable busmastering, and restart the interface if 1769 * appropriate. 1770 */ 1771static int 1772rl_resume(device_t dev) 1773{ 1774 struct rl_softc *sc; 1775 struct ifnet *ifp; 1776 1777 sc = device_get_softc(dev); 1778 ifp = sc->rl_ifp; 1779 1780 RL_LOCK(sc); 1781 1782 /* reinitialize interface if necessary */ 1783 if (ifp->if_flags & IFF_UP) 1784 rl_init_locked(sc); 1785 1786 sc->suspended = 0; 1787 1788 RL_UNLOCK(sc); 1789 1790 return (0); 1791} 1792 1793/* 1794 * Stop all chip I/O so that the kernel's probe routines don't 1795 * get confused by errant DMAs when rebooting. 1796 */ 1797static void 1798rl_shutdown(device_t dev) 1799{ 1800 struct rl_softc *sc; 1801 1802 sc = device_get_softc(dev); 1803 1804 RL_LOCK(sc); 1805 rl_stop(sc); 1806 RL_UNLOCK(sc); 1807} 1808