if_rl.c revision 131253
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 131253 2004-06-28 20:07:03Z imp $"); 35 36/* 37 * RealTek 8129/8139 PCI NIC driver 38 * 39 * Supports several extremely cheap PCI 10/100 adapters based on 40 * the RealTek chipset. Datasheets can be obtained from 41 * www.realtek.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86#include <sys/param.h> 87#include <sys/endian.h> 88#include <sys/systm.h> 89#include <sys/sockio.h> 90#include <sys/mbuf.h> 91#include <sys/malloc.h> 92#include <sys/kernel.h> 93#include <sys/module.h> 94#include <sys/socket.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> 98#include <net/ethernet.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101 102#include <net/bpf.h> 103 104#include <machine/bus_pio.h> 105#include <machine/bus_memio.h> 106#include <machine/bus.h> 107#include <machine/resource.h> 108#include <sys/bus.h> 109#include <sys/rman.h> 110 111#include <dev/mii/mii.h> 112#include <dev/mii/miivar.h> 113 114#include <dev/pci/pcireg.h> 115#include <dev/pci/pcivar.h> 116 117MODULE_DEPEND(rl, pci, 1, 1, 1); 118MODULE_DEPEND(rl, ether, 1, 1, 1); 119MODULE_DEPEND(rl, miibus, 1, 1, 1); 120 121/* "controller miibus0" required. See GENERIC if you get errors here. */ 122#include "miibus_if.h" 123 124/* 125 * Default to using PIO access for this driver. On SMP systems, 126 * there appear to be problems with memory mapped mode: it looks like 127 * doing too many memory mapped access back to back in rapid succession 128 * can hang the bus. I'm inclined to blame this on crummy design/construction 129 * on the part of RealTek. Memory mapped mode does appear to work on 130 * uniprocessor systems though. 131 */ 132#define RL_USEIOSPACE 133 134#include <pci/if_rlreg.h> 135 136/* 137 * Various supported device vendors/types and their names. 138 */ 139static struct rl_type rl_devs[] = { 140 { RT_VENDORID, RT_DEVICEID_8129, RL_8129, 141 "RealTek 8129 10/100BaseTX" }, 142 { RT_VENDORID, RT_DEVICEID_8139, RL_8139, 143 "RealTek 8139 10/100BaseTX" }, 144 { RT_VENDORID, RT_DEVICEID_8138, RL_8139, 145 "RealTek 8139 10/100BaseTX CardBus" }, 146 { RT_VENDORID, RT_DEVICEID_8100, RL_8139, 147 "RealTek 8100 10/100BaseTX" }, 148 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 149 "Accton MPX 5030/5038 10/100BaseTX" }, 150 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139, 151 "Delta Electronics 8139 10/100BaseTX" }, 152 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139, 153 "Addtron Technolgy 8139 10/100BaseTX" }, 154 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139, 155 "D-Link DFE-530TX+ 10/100BaseTX" }, 156 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139, 157 "D-Link DFE-690TXD 10/100BaseTX" }, 158 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 159 "Nortel Networks 10/100BaseTX" }, 160 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139, 161 "Corega FEther CB-TXD" }, 162 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139, 163 "Corega FEtherII CB-TXD" }, 164 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139, 165 "Peppercon AG ROL-F" }, 166 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139, 167 "Planex FNW-3800-TX" }, 168 { CP_VENDORID, RT_DEVICEID_8139, RL_8139, 169 "Compaq HNE-300" }, 170 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139, 171 "LevelOne FPC-0106TX" }, 172 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139, 173 "Edimax EP-4103DL CardBus" }, 174 { 0, 0, 0, NULL } 175}; 176 177static int rl_probe (device_t); 178static int rl_attach (device_t); 179static int rl_detach (device_t); 180 181static int rl_encap (struct rl_softc *, struct mbuf * ); 182 183static void rl_rxeof (struct rl_softc *); 184static void rl_txeof (struct rl_softc *); 185static void rl_intr (void *); 186static void rl_tick (void *); 187static void rl_start (struct ifnet *); 188static int rl_ioctl (struct ifnet *, u_long, caddr_t); 189static void rl_init (void *); 190static void rl_stop (struct rl_softc *); 191static void rl_watchdog (struct ifnet *); 192static int rl_suspend (device_t); 193static int rl_resume (device_t); 194static void rl_shutdown (device_t); 195static int rl_ifmedia_upd (struct ifnet *); 196static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 197 198static void rl_eeprom_putbyte (struct rl_softc *, int); 199static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 200static void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 201static void rl_mii_sync (struct rl_softc *); 202static void rl_mii_send (struct rl_softc *, u_int32_t, int); 203static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 204static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 205 206static int rl_miibus_readreg (device_t, int, int); 207static int rl_miibus_writereg (device_t, int, int, int); 208static void rl_miibus_statchg (device_t); 209 210static void rl_setmulti (struct rl_softc *); 211static void rl_reset (struct rl_softc *); 212static int rl_list_tx_init (struct rl_softc *); 213 214static void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 215static void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 216 217#ifdef RL_USEIOSPACE 218#define RL_RES SYS_RES_IOPORT 219#define RL_RID RL_PCI_LOIO 220#else 221#define RL_RES SYS_RES_MEMORY 222#define RL_RID RL_PCI_LOMEM 223#endif 224 225static device_method_t rl_methods[] = { 226 /* Device interface */ 227 DEVMETHOD(device_probe, rl_probe), 228 DEVMETHOD(device_attach, rl_attach), 229 DEVMETHOD(device_detach, rl_detach), 230 DEVMETHOD(device_suspend, rl_suspend), 231 DEVMETHOD(device_resume, rl_resume), 232 DEVMETHOD(device_shutdown, rl_shutdown), 233 234 /* bus interface */ 235 DEVMETHOD(bus_print_child, bus_generic_print_child), 236 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 237 238 /* MII interface */ 239 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 240 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 241 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 242 243 { 0, 0 } 244}; 245 246static driver_t rl_driver = { 247 "rl", 248 rl_methods, 249 sizeof(struct rl_softc) 250}; 251 252static devclass_t rl_devclass; 253 254DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0); 255DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0); 256DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 257 258#define EE_SET(x) \ 259 CSR_WRITE_1(sc, RL_EECMD, \ 260 CSR_READ_1(sc, RL_EECMD) | x) 261 262#define EE_CLR(x) \ 263 CSR_WRITE_1(sc, RL_EECMD, \ 264 CSR_READ_1(sc, RL_EECMD) & ~x) 265 266static void 267rl_dma_map_rxbuf(arg, segs, nseg, error) 268 void *arg; 269 bus_dma_segment_t *segs; 270 int nseg, error; 271{ 272 struct rl_softc *sc; 273 274 sc = arg; 275 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 276 277 return; 278} 279 280static void 281rl_dma_map_txbuf(arg, segs, nseg, error) 282 void *arg; 283 bus_dma_segment_t *segs; 284 int nseg, error; 285{ 286 struct rl_softc *sc; 287 288 sc = arg; 289 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 290 291 return; 292} 293 294/* 295 * Send a read command and address to the EEPROM, check for ACK. 296 */ 297static void 298rl_eeprom_putbyte(sc, addr) 299 struct rl_softc *sc; 300 int addr; 301{ 302 register int d, i; 303 304 d = addr | sc->rl_eecmd_read; 305 306 /* 307 * Feed in each bit and strobe the clock. 308 */ 309 for (i = 0x400; i; i >>= 1) { 310 if (d & i) { 311 EE_SET(RL_EE_DATAIN); 312 } else { 313 EE_CLR(RL_EE_DATAIN); 314 } 315 DELAY(100); 316 EE_SET(RL_EE_CLK); 317 DELAY(150); 318 EE_CLR(RL_EE_CLK); 319 DELAY(100); 320 } 321 322 return; 323} 324 325/* 326 * Read a word of data stored in the EEPROM at address 'addr.' 327 */ 328static void 329rl_eeprom_getword(sc, addr, dest) 330 struct rl_softc *sc; 331 int addr; 332 u_int16_t *dest; 333{ 334 register int i; 335 u_int16_t word = 0; 336 337 /* Enter EEPROM access mode. */ 338 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 339 340 /* 341 * Send address of word we want to read. 342 */ 343 rl_eeprom_putbyte(sc, addr); 344 345 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 346 347 /* 348 * Start reading bits from EEPROM. 349 */ 350 for (i = 0x8000; i; i >>= 1) { 351 EE_SET(RL_EE_CLK); 352 DELAY(100); 353 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 354 word |= i; 355 EE_CLR(RL_EE_CLK); 356 DELAY(100); 357 } 358 359 /* Turn off EEPROM access mode. */ 360 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 361 362 *dest = word; 363 364 return; 365} 366 367/* 368 * Read a sequence of words from the EEPROM. 369 */ 370static void 371rl_read_eeprom(sc, dest, off, cnt, swap) 372 struct rl_softc *sc; 373 caddr_t dest; 374 int off; 375 int cnt; 376 int swap; 377{ 378 int i; 379 u_int16_t word = 0, *ptr; 380 381 for (i = 0; i < cnt; i++) { 382 rl_eeprom_getword(sc, off + i, &word); 383 ptr = (u_int16_t *)(dest + (i * 2)); 384 if (swap) 385 *ptr = ntohs(word); 386 else 387 *ptr = word; 388 } 389 390 return; 391} 392 393 394/* 395 * MII access routines are provided for the 8129, which 396 * doesn't have a built-in PHY. For the 8139, we fake things 397 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 398 * direct access PHY registers. 399 */ 400#define MII_SET(x) \ 401 CSR_WRITE_1(sc, RL_MII, \ 402 CSR_READ_1(sc, RL_MII) | (x)) 403 404#define MII_CLR(x) \ 405 CSR_WRITE_1(sc, RL_MII, \ 406 CSR_READ_1(sc, RL_MII) & ~(x)) 407 408/* 409 * Sync the PHYs by setting data bit and strobing the clock 32 times. 410 */ 411static void 412rl_mii_sync(sc) 413 struct rl_softc *sc; 414{ 415 register int i; 416 417 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 418 419 for (i = 0; i < 32; i++) { 420 MII_SET(RL_MII_CLK); 421 DELAY(1); 422 MII_CLR(RL_MII_CLK); 423 DELAY(1); 424 } 425 426 return; 427} 428 429/* 430 * Clock a series of bits through the MII. 431 */ 432static void 433rl_mii_send(sc, bits, cnt) 434 struct rl_softc *sc; 435 u_int32_t bits; 436 int cnt; 437{ 438 int i; 439 440 MII_CLR(RL_MII_CLK); 441 442 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 443 if (bits & i) { 444 MII_SET(RL_MII_DATAOUT); 445 } else { 446 MII_CLR(RL_MII_DATAOUT); 447 } 448 DELAY(1); 449 MII_CLR(RL_MII_CLK); 450 DELAY(1); 451 MII_SET(RL_MII_CLK); 452 } 453} 454 455/* 456 * Read an PHY register through the MII. 457 */ 458static int 459rl_mii_readreg(sc, frame) 460 struct rl_softc *sc; 461 struct rl_mii_frame *frame; 462 463{ 464 int i, ack; 465 466 RL_LOCK(sc); 467 468 /* 469 * Set up frame for RX. 470 */ 471 frame->mii_stdelim = RL_MII_STARTDELIM; 472 frame->mii_opcode = RL_MII_READOP; 473 frame->mii_turnaround = 0; 474 frame->mii_data = 0; 475 476 CSR_WRITE_2(sc, RL_MII, 0); 477 478 /* 479 * Turn on data xmit. 480 */ 481 MII_SET(RL_MII_DIR); 482 483 rl_mii_sync(sc); 484 485 /* 486 * Send command/address info. 487 */ 488 rl_mii_send(sc, frame->mii_stdelim, 2); 489 rl_mii_send(sc, frame->mii_opcode, 2); 490 rl_mii_send(sc, frame->mii_phyaddr, 5); 491 rl_mii_send(sc, frame->mii_regaddr, 5); 492 493 /* Idle bit */ 494 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 495 DELAY(1); 496 MII_SET(RL_MII_CLK); 497 DELAY(1); 498 499 /* Turn off xmit. */ 500 MII_CLR(RL_MII_DIR); 501 502 /* Check for ack */ 503 MII_CLR(RL_MII_CLK); 504 DELAY(1); 505 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 506 MII_SET(RL_MII_CLK); 507 DELAY(1); 508 509 /* 510 * Now try reading data bits. If the ack failed, we still 511 * need to clock through 16 cycles to keep the PHY(s) in sync. 512 */ 513 if (ack) { 514 for(i = 0; i < 16; i++) { 515 MII_CLR(RL_MII_CLK); 516 DELAY(1); 517 MII_SET(RL_MII_CLK); 518 DELAY(1); 519 } 520 goto fail; 521 } 522 523 for (i = 0x8000; i; i >>= 1) { 524 MII_CLR(RL_MII_CLK); 525 DELAY(1); 526 if (!ack) { 527 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 528 frame->mii_data |= i; 529 DELAY(1); 530 } 531 MII_SET(RL_MII_CLK); 532 DELAY(1); 533 } 534 535fail: 536 537 MII_CLR(RL_MII_CLK); 538 DELAY(1); 539 MII_SET(RL_MII_CLK); 540 DELAY(1); 541 542 RL_UNLOCK(sc); 543 544 if (ack) 545 return(1); 546 return(0); 547} 548 549/* 550 * Write to a PHY register through the MII. 551 */ 552static int 553rl_mii_writereg(sc, frame) 554 struct rl_softc *sc; 555 struct rl_mii_frame *frame; 556 557{ 558 RL_LOCK(sc); 559 560 /* 561 * Set up frame for TX. 562 */ 563 564 frame->mii_stdelim = RL_MII_STARTDELIM; 565 frame->mii_opcode = RL_MII_WRITEOP; 566 frame->mii_turnaround = RL_MII_TURNAROUND; 567 568 /* 569 * Turn on data output. 570 */ 571 MII_SET(RL_MII_DIR); 572 573 rl_mii_sync(sc); 574 575 rl_mii_send(sc, frame->mii_stdelim, 2); 576 rl_mii_send(sc, frame->mii_opcode, 2); 577 rl_mii_send(sc, frame->mii_phyaddr, 5); 578 rl_mii_send(sc, frame->mii_regaddr, 5); 579 rl_mii_send(sc, frame->mii_turnaround, 2); 580 rl_mii_send(sc, frame->mii_data, 16); 581 582 /* Idle bit. */ 583 MII_SET(RL_MII_CLK); 584 DELAY(1); 585 MII_CLR(RL_MII_CLK); 586 DELAY(1); 587 588 /* 589 * Turn off xmit. 590 */ 591 MII_CLR(RL_MII_DIR); 592 593 RL_UNLOCK(sc); 594 595 return(0); 596} 597 598static int 599rl_miibus_readreg(dev, phy, reg) 600 device_t dev; 601 int phy, reg; 602{ 603 struct rl_softc *sc; 604 struct rl_mii_frame frame; 605 u_int16_t rval = 0; 606 u_int16_t rl8139_reg = 0; 607 608 sc = device_get_softc(dev); 609 RL_LOCK(sc); 610 611 if (sc->rl_type == RL_8139) { 612 /* Pretend the internal PHY is only at address 0 */ 613 if (phy) { 614 RL_UNLOCK(sc); 615 return(0); 616 } 617 switch(reg) { 618 case MII_BMCR: 619 rl8139_reg = RL_BMCR; 620 break; 621 case MII_BMSR: 622 rl8139_reg = RL_BMSR; 623 break; 624 case MII_ANAR: 625 rl8139_reg = RL_ANAR; 626 break; 627 case MII_ANER: 628 rl8139_reg = RL_ANER; 629 break; 630 case MII_ANLPAR: 631 rl8139_reg = RL_LPAR; 632 break; 633 case MII_PHYIDR1: 634 case MII_PHYIDR2: 635 RL_UNLOCK(sc); 636 return(0); 637 /* 638 * Allow the rlphy driver to read the media status 639 * register. If we have a link partner which does not 640 * support NWAY, this is the register which will tell 641 * us the results of parallel detection. 642 */ 643 case RL_MEDIASTAT: 644 rval = CSR_READ_1(sc, RL_MEDIASTAT); 645 RL_UNLOCK(sc); 646 return(rval); 647 default: 648 printf("rl%d: bad phy register\n", sc->rl_unit); 649 RL_UNLOCK(sc); 650 return(0); 651 } 652 rval = CSR_READ_2(sc, rl8139_reg); 653 RL_UNLOCK(sc); 654 return(rval); 655 } 656 657 bzero((char *)&frame, sizeof(frame)); 658 659 frame.mii_phyaddr = phy; 660 frame.mii_regaddr = reg; 661 rl_mii_readreg(sc, &frame); 662 RL_UNLOCK(sc); 663 664 return(frame.mii_data); 665} 666 667static int 668rl_miibus_writereg(dev, phy, reg, data) 669 device_t dev; 670 int phy, reg, data; 671{ 672 struct rl_softc *sc; 673 struct rl_mii_frame frame; 674 u_int16_t rl8139_reg = 0; 675 676 sc = device_get_softc(dev); 677 RL_LOCK(sc); 678 679 if (sc->rl_type == RL_8139) { 680 /* Pretend the internal PHY is only at address 0 */ 681 if (phy) { 682 RL_UNLOCK(sc); 683 return(0); 684 } 685 switch(reg) { 686 case MII_BMCR: 687 rl8139_reg = RL_BMCR; 688 break; 689 case MII_BMSR: 690 rl8139_reg = RL_BMSR; 691 break; 692 case MII_ANAR: 693 rl8139_reg = RL_ANAR; 694 break; 695 case MII_ANER: 696 rl8139_reg = RL_ANER; 697 break; 698 case MII_ANLPAR: 699 rl8139_reg = RL_LPAR; 700 break; 701 case MII_PHYIDR1: 702 case MII_PHYIDR2: 703 RL_UNLOCK(sc); 704 return(0); 705 break; 706 default: 707 printf("rl%d: bad phy register\n", sc->rl_unit); 708 RL_UNLOCK(sc); 709 return(0); 710 } 711 CSR_WRITE_2(sc, rl8139_reg, data); 712 RL_UNLOCK(sc); 713 return(0); 714 } 715 716 bzero((char *)&frame, sizeof(frame)); 717 718 frame.mii_phyaddr = phy; 719 frame.mii_regaddr = reg; 720 frame.mii_data = data; 721 722 rl_mii_writereg(sc, &frame); 723 724 RL_UNLOCK(sc); 725 return(0); 726} 727 728static void 729rl_miibus_statchg(dev) 730 device_t dev; 731{ 732 return; 733} 734 735/* 736 * Program the 64-bit multicast hash filter. 737 */ 738static void 739rl_setmulti(sc) 740 struct rl_softc *sc; 741{ 742 struct ifnet *ifp; 743 int h = 0; 744 u_int32_t hashes[2] = { 0, 0 }; 745 struct ifmultiaddr *ifma; 746 u_int32_t rxfilt; 747 int mcnt = 0; 748 749 ifp = &sc->arpcom.ac_if; 750 751 rxfilt = CSR_READ_4(sc, RL_RXCFG); 752 753 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 754 rxfilt |= RL_RXCFG_RX_MULTI; 755 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 756 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 757 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 758 return; 759 } 760 761 /* first, zot all the existing hash bits */ 762 CSR_WRITE_4(sc, RL_MAR0, 0); 763 CSR_WRITE_4(sc, RL_MAR4, 0); 764 765 /* now program new ones */ 766 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 767 if (ifma->ifma_addr->sa_family != AF_LINK) 768 continue; 769 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 770 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 771 if (h < 32) 772 hashes[0] |= (1 << h); 773 else 774 hashes[1] |= (1 << (h - 32)); 775 mcnt++; 776 } 777 778 if (mcnt) 779 rxfilt |= RL_RXCFG_RX_MULTI; 780 else 781 rxfilt &= ~RL_RXCFG_RX_MULTI; 782 783 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 784 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 785 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 786 787 return; 788} 789 790static void 791rl_reset(sc) 792 struct rl_softc *sc; 793{ 794 register int i; 795 796 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 797 798 for (i = 0; i < RL_TIMEOUT; i++) { 799 DELAY(10); 800 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 801 break; 802 } 803 if (i == RL_TIMEOUT) 804 printf("rl%d: reset never completed!\n", sc->rl_unit); 805 806 return; 807} 808 809/* 810 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 811 * IDs against our list and return a device name if we find a match. 812 */ 813static int 814rl_probe(dev) 815 device_t dev; 816{ 817 struct rl_type *t; 818 struct rl_softc *sc; 819 int rid; 820 u_int32_t hwrev; 821 822 t = rl_devs; 823 sc = device_get_softc(dev); 824 825 while(t->rl_name != NULL) { 826 if ((pci_get_vendor(dev) == t->rl_vid) && 827 (pci_get_device(dev) == t->rl_did)) { 828 829 /* 830 * Temporarily map the I/O space 831 * so we can read the chip ID register. 832 */ 833 rid = RL_RID; 834 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 835 RF_ACTIVE); 836 if (sc->rl_res == NULL) { 837 device_printf(dev, 838 "couldn't map ports/memory\n"); 839 return(ENXIO); 840 } 841 sc->rl_btag = rman_get_bustag(sc->rl_res); 842 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 843 mtx_init(&sc->rl_mtx, 844 device_get_nameunit(dev), 845 MTX_NETWORK_LOCK, MTX_DEF); 846 RL_LOCK(sc); 847 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 848 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 849 RL_UNLOCK(sc); 850 mtx_destroy(&sc->rl_mtx); 851 852 /* Don't attach to 8139C+ or 8169/8110 chips. */ 853 if (hwrev == RL_HWREV_8139CPLUS || 854 (hwrev == RL_HWREV_8169 && 855 t->rl_did == RT_DEVICEID_8169) || 856 hwrev == RL_HWREV_8169S || 857 hwrev == RL_HWREV_8110S) { 858 t++; 859 continue; 860 } 861 862 device_set_desc(dev, t->rl_name); 863 return(0); 864 } 865 t++; 866 } 867 868 return(ENXIO); 869} 870 871/* 872 * Attach the interface. Allocate softc structures, do ifmedia 873 * setup and ethernet/BPF attach. 874 */ 875static int 876rl_attach(dev) 877 device_t dev; 878{ 879 u_char eaddr[ETHER_ADDR_LEN]; 880 u_int16_t as[3]; 881 struct rl_softc *sc; 882 struct ifnet *ifp; 883 u_int16_t rl_did = 0; 884 struct rl_type *t; 885 int unit, error = 0, rid, i; 886 887 sc = device_get_softc(dev); 888 unit = device_get_unit(dev); 889 890 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 891 MTX_DEF | MTX_RECURSE); 892 /* 893 * Map control/status registers. 894 */ 895 pci_enable_busmaster(dev); 896 897 rid = RL_RID; 898 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE); 899 900 if (sc->rl_res == NULL) { 901 printf ("rl%d: couldn't map ports/memory\n", unit); 902 error = ENXIO; 903 goto fail; 904 } 905 906#ifdef notdef 907 /* Detect the Realtek 8139B. For some reason, this chip is very 908 * unstable when left to autoselect the media 909 * The best workaround is to set the device to the required 910 * media type or to set it to the 10 Meg speed. 911 */ 912 913 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 914 printf("rl%d: Realtek 8139B detected. Warning, " 915 "this may be unstable in autoselect mode\n", unit); 916 } 917#endif 918 919 sc->rl_btag = rman_get_bustag(sc->rl_res); 920 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 921 922 /* Allocate interrupt */ 923 rid = 0; 924 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 925 RF_SHAREABLE | RF_ACTIVE); 926 927 if (sc->rl_irq == NULL) { 928 printf("rl%d: couldn't map interrupt\n", unit); 929 error = ENXIO; 930 goto fail; 931 } 932 933 /* Reset the adapter. */ 934 rl_reset(sc); 935 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 936 rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 937 if (rl_did != 0x8129) 938 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 939 940 /* 941 * Get station address from the EEPROM. 942 */ 943 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 944 for (i = 0; i < 3; i++) { 945 eaddr[(i * 2) + 0] = as[i] & 0xff; 946 eaddr[(i * 2) + 1] = as[i] >> 8; 947 } 948 949 sc->rl_unit = unit; 950 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 951 952 /* 953 * Now read the exact device type from the EEPROM to find 954 * out if it's an 8129 or 8139. 955 */ 956 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 957 958 t = rl_devs; 959 sc->rl_type = 0; 960 while(t->rl_name != NULL) { 961 if (rl_did == t->rl_did) { 962 sc->rl_type = t->rl_basetype; 963 break; 964 } 965 t++; 966 } 967 968 if (sc->rl_type == 0) { 969 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 970 error = ENXIO; 971 goto fail; 972 } 973 974 /* 975 * Allocate the parent bus DMA tag appropriate for PCI. 976 */ 977#define RL_NSEG_NEW 32 978 error = bus_dma_tag_create(NULL, /* parent */ 979 1, 0, /* alignment, boundary */ 980 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 981 BUS_SPACE_MAXADDR, /* highaddr */ 982 NULL, NULL, /* filter, filterarg */ 983 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 984 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 985 BUS_DMA_ALLOCNOW, /* flags */ 986 NULL, NULL, /* lockfunc, lockarg */ 987 &sc->rl_parent_tag); 988 if (error) 989 goto fail; 990 991 /* 992 * Now allocate a tag for the DMA descriptor lists. 993 * All of our lists are allocated as a contiguous block 994 * of memory. 995 */ 996 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 997 1, 0, /* alignment, boundary */ 998 BUS_SPACE_MAXADDR, /* lowaddr */ 999 BUS_SPACE_MAXADDR, /* highaddr */ 1000 NULL, NULL, /* filter, filterarg */ 1001 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 1002 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1003 BUS_DMA_ALLOCNOW, /* flags */ 1004 NULL, NULL, /* lockfunc, lockarg */ 1005 &sc->rl_tag); 1006 if (error) 1007 goto fail; 1008 1009 /* 1010 * Now allocate a chunk of DMA-able memory based on the 1011 * tag we just created. 1012 */ 1013 error = bus_dmamem_alloc(sc->rl_tag, 1014 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1015 &sc->rl_cdata.rl_rx_dmamap); 1016 1017 if (error) { 1018 printf("rl%d: no memory for list buffers!\n", unit); 1019 bus_dma_tag_destroy(sc->rl_tag); 1020 sc->rl_tag = NULL; 1021 goto fail; 1022 } 1023 1024 /* Leave a few bytes before the start of the RX ring buffer. */ 1025 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1026 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1027 1028 /* Do MII setup */ 1029 if (mii_phy_probe(dev, &sc->rl_miibus, 1030 rl_ifmedia_upd, rl_ifmedia_sts)) { 1031 printf("rl%d: MII without any phy!\n", sc->rl_unit); 1032 error = ENXIO; 1033 goto fail; 1034 } 1035 1036 ifp = &sc->arpcom.ac_if; 1037 ifp->if_softc = sc; 1038 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1039 ifp->if_mtu = ETHERMTU; 1040 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1041 ifp->if_ioctl = rl_ioctl; 1042 ifp->if_start = rl_start; 1043 ifp->if_watchdog = rl_watchdog; 1044 ifp->if_init = rl_init; 1045 ifp->if_baudrate = 10000000; 1046 ifp->if_capabilities = IFCAP_VLAN_MTU; 1047#ifdef DEVICE_POLLING 1048 ifp->if_capabilities |= IFCAP_POLLING; 1049#endif 1050 ifp->if_capenable = ifp->if_capabilities; 1051 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1052 1053 callout_handle_init(&sc->rl_stat_ch); 1054 1055 /* 1056 * Call MI attach routine. 1057 */ 1058 ether_ifattach(ifp, eaddr); 1059 1060 /* Hook interrupt last to avoid having to lock softc */ 1061 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1062 rl_intr, sc, &sc->rl_intrhand); 1063 1064 if (error) { 1065 printf("rl%d: couldn't set up irq\n", unit); 1066 ether_ifdetach(ifp); 1067 goto fail; 1068 } 1069 1070fail: 1071 if (error) 1072 rl_detach(dev); 1073 1074 return (error); 1075} 1076 1077/* 1078 * Shutdown hardware and free up resources. This can be called any 1079 * time after the mutex has been initialized. It is called in both 1080 * the error case in attach and the normal detach case so it needs 1081 * to be careful about only freeing resources that have actually been 1082 * allocated. 1083 */ 1084static int 1085rl_detach(dev) 1086 device_t dev; 1087{ 1088 struct rl_softc *sc; 1089 struct ifnet *ifp; 1090 1091 sc = device_get_softc(dev); 1092 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 1093 RL_LOCK(sc); 1094 ifp = &sc->arpcom.ac_if; 1095 1096 /* These should only be active if attach succeeded */ 1097 if (device_is_attached(dev)) { 1098 rl_stop(sc); 1099 ether_ifdetach(ifp); 1100 } 1101 if (sc->rl_miibus) 1102 device_delete_child(dev, sc->rl_miibus); 1103 bus_generic_detach(dev); 1104 1105 if (sc->rl_intrhand) 1106 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1107 if (sc->rl_irq) 1108 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1109 if (sc->rl_res) 1110 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1111 1112 if (sc->rl_tag) { 1113 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1114 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1115 sc->rl_cdata.rl_rx_dmamap); 1116 bus_dma_tag_destroy(sc->rl_tag); 1117 } 1118 if (sc->rl_parent_tag) 1119 bus_dma_tag_destroy(sc->rl_parent_tag); 1120 1121 RL_UNLOCK(sc); 1122 mtx_destroy(&sc->rl_mtx); 1123 1124 return(0); 1125} 1126 1127/* 1128 * Initialize the transmit descriptors. 1129 */ 1130static int 1131rl_list_tx_init(sc) 1132 struct rl_softc *sc; 1133{ 1134 struct rl_chain_data *cd; 1135 int i; 1136 1137 cd = &sc->rl_cdata; 1138 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1139 cd->rl_tx_chain[i] = NULL; 1140 CSR_WRITE_4(sc, 1141 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1142 } 1143 1144 sc->rl_cdata.cur_tx = 0; 1145 sc->rl_cdata.last_tx = 0; 1146 1147 return(0); 1148} 1149 1150/* 1151 * A frame has been uploaded: pass the resulting mbuf chain up to 1152 * the higher level protocols. 1153 * 1154 * You know there's something wrong with a PCI bus-master chip design 1155 * when you have to use m_devget(). 1156 * 1157 * The receive operation is badly documented in the datasheet, so I'll 1158 * attempt to document it here. The driver provides a buffer area and 1159 * places its base address in the RX buffer start address register. 1160 * The chip then begins copying frames into the RX buffer. Each frame 1161 * is preceded by a 32-bit RX status word which specifies the length 1162 * of the frame and certain other status bits. Each frame (starting with 1163 * the status word) is also 32-bit aligned. The frame length is in the 1164 * first 16 bits of the status word; the lower 15 bits correspond with 1165 * the 'rx status register' mentioned in the datasheet. 1166 * 1167 * Note: to make the Alpha happy, the frame payload needs to be aligned 1168 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1169 * as the offset argument to m_devget(). 1170 */ 1171static void 1172rl_rxeof(sc) 1173 struct rl_softc *sc; 1174{ 1175 struct mbuf *m; 1176 struct ifnet *ifp; 1177 int total_len = 0; 1178 u_int32_t rxstat; 1179 caddr_t rxbufpos; 1180 int wrap = 0; 1181 u_int16_t cur_rx; 1182 u_int16_t limit; 1183 u_int16_t rx_bytes = 0, max_bytes; 1184 1185 RL_LOCK_ASSERT(sc); 1186 1187 ifp = &sc->arpcom.ac_if; 1188 1189 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1190 BUS_DMASYNC_POSTREAD); 1191 1192 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1193 1194 /* Do not try to read past this point. */ 1195 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1196 1197 if (limit < cur_rx) 1198 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1199 else 1200 max_bytes = limit - cur_rx; 1201 1202 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1203#ifdef DEVICE_POLLING 1204 if (ifp->if_flags & IFF_POLLING) { 1205 if (sc->rxcycles <= 0) 1206 break; 1207 sc->rxcycles--; 1208 } 1209#endif /* DEVICE_POLLING */ 1210 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1211 rxstat = le32toh(*(u_int32_t *)rxbufpos); 1212 1213 /* 1214 * Here's a totally undocumented fact for you. When the 1215 * RealTek chip is in the process of copying a packet into 1216 * RAM for you, the length will be 0xfff0. If you spot a 1217 * packet header with this value, you need to stop. The 1218 * datasheet makes absolutely no mention of this and 1219 * RealTek should be shot for this. 1220 */ 1221 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1222 break; 1223 1224 if (!(rxstat & RL_RXSTAT_RXOK)) { 1225 ifp->if_ierrors++; 1226 rl_init(sc); 1227 return; 1228 } 1229 1230 /* No errors; receive the packet. */ 1231 total_len = rxstat >> 16; 1232 rx_bytes += total_len + 4; 1233 1234 /* 1235 * XXX The RealTek chip includes the CRC with every 1236 * received frame, and there's no way to turn this 1237 * behavior off (at least, I can't find anything in 1238 * the manual that explains how to do it) so we have 1239 * to trim off the CRC manually. 1240 */ 1241 total_len -= ETHER_CRC_LEN; 1242 1243 /* 1244 * Avoid trying to read more bytes than we know 1245 * the chip has prepared for us. 1246 */ 1247 if (rx_bytes > max_bytes) 1248 break; 1249 1250 rxbufpos = sc->rl_cdata.rl_rx_buf + 1251 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1252 1253 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1254 rxbufpos = sc->rl_cdata.rl_rx_buf; 1255 1256 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1257 1258 if (total_len > wrap) { 1259 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1260 NULL); 1261 if (m == NULL) { 1262 ifp->if_ierrors++; 1263 } else { 1264 m_copyback(m, wrap, total_len - wrap, 1265 sc->rl_cdata.rl_rx_buf); 1266 } 1267 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1268 } else { 1269 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1270 NULL); 1271 if (m == NULL) { 1272 ifp->if_ierrors++; 1273 } 1274 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1275 } 1276 1277 /* 1278 * Round up to 32-bit boundary. 1279 */ 1280 cur_rx = (cur_rx + 3) & ~3; 1281 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1282 1283 if (m == NULL) 1284 continue; 1285 1286 ifp->if_ipackets++; 1287 RL_UNLOCK(sc); 1288 (*ifp->if_input)(ifp, m); 1289 RL_LOCK(sc); 1290 } 1291 1292 return; 1293} 1294 1295/* 1296 * A frame was downloaded to the chip. It's safe for us to clean up 1297 * the list buffers. 1298 */ 1299static void 1300rl_txeof(sc) 1301 struct rl_softc *sc; 1302{ 1303 struct ifnet *ifp; 1304 u_int32_t txstat; 1305 1306 ifp = &sc->arpcom.ac_if; 1307 1308 /* 1309 * Go through our tx list and free mbufs for those 1310 * frames that have been uploaded. 1311 */ 1312 do { 1313 if (RL_LAST_TXMBUF(sc) == NULL) 1314 break; 1315 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1316 if (!(txstat & (RL_TXSTAT_TX_OK| 1317 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1318 break; 1319 1320 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1321 1322 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1323 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1324 m_freem(RL_LAST_TXMBUF(sc)); 1325 RL_LAST_TXMBUF(sc) = NULL; 1326 if (txstat & RL_TXSTAT_TX_OK) 1327 ifp->if_opackets++; 1328 else { 1329 int oldthresh; 1330 ifp->if_oerrors++; 1331 if ((txstat & RL_TXSTAT_TXABRT) || 1332 (txstat & RL_TXSTAT_OUTOFWIN)) 1333 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1334 oldthresh = sc->rl_txthresh; 1335 /* error recovery */ 1336 rl_reset(sc); 1337 rl_init(sc); 1338 /* 1339 * If there was a transmit underrun, 1340 * bump the TX threshold. 1341 */ 1342 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1343 sc->rl_txthresh = oldthresh + 32; 1344 return; 1345 } 1346 RL_INC(sc->rl_cdata.last_tx); 1347 ifp->if_flags &= ~IFF_OACTIVE; 1348 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1349 1350 if (RL_LAST_TXMBUF(sc) == NULL) 1351 ifp->if_timer = 0; 1352 else if (ifp->if_timer == 0) 1353 ifp->if_timer = 5; 1354 1355 return; 1356} 1357 1358static void 1359rl_tick(xsc) 1360 void *xsc; 1361{ 1362 struct rl_softc *sc; 1363 struct mii_data *mii; 1364 1365 sc = xsc; 1366 RL_LOCK(sc); 1367 mii = device_get_softc(sc->rl_miibus); 1368 1369 mii_tick(mii); 1370 1371 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1372 RL_UNLOCK(sc); 1373 1374 return; 1375} 1376 1377#ifdef DEVICE_POLLING 1378static void 1379rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1380{ 1381 struct rl_softc *sc = ifp->if_softc; 1382 1383 RL_LOCK(sc); 1384 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1385 ether_poll_deregister(ifp); 1386 cmd = POLL_DEREGISTER; 1387 } 1388 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1389 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1390 goto done; 1391 } 1392 1393 sc->rxcycles = count; 1394 rl_rxeof(sc); 1395 rl_txeof(sc); 1396 if (ifp->if_snd.ifq_head != NULL) 1397 rl_start(ifp); 1398 1399 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1400 u_int16_t status; 1401 1402 status = CSR_READ_2(sc, RL_ISR); 1403 if (status == 0xffff) 1404 goto done; 1405 if (status) 1406 CSR_WRITE_2(sc, RL_ISR, status); 1407 1408 /* 1409 * XXX check behaviour on receiver stalls. 1410 */ 1411 1412 if (status & RL_ISR_SYSTEM_ERR) { 1413 rl_reset(sc); 1414 rl_init(sc); 1415 } 1416 } 1417done: 1418 RL_UNLOCK(sc); 1419} 1420#endif /* DEVICE_POLLING */ 1421 1422static void 1423rl_intr(arg) 1424 void *arg; 1425{ 1426 struct rl_softc *sc; 1427 struct ifnet *ifp; 1428 u_int16_t status; 1429 1430 sc = arg; 1431 1432 if (sc->suspended) { 1433 return; 1434 } 1435 1436 RL_LOCK(sc); 1437 ifp = &sc->arpcom.ac_if; 1438 1439#ifdef DEVICE_POLLING 1440 if (ifp->if_flags & IFF_POLLING) 1441 goto done; 1442 if ((ifp->if_capenable & IFCAP_POLLING) && 1443 ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 1444 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1445 rl_poll(ifp, 0, 1); 1446 goto done; 1447 } 1448#endif /* DEVICE_POLLING */ 1449 1450 for (;;) { 1451 1452 status = CSR_READ_2(sc, RL_ISR); 1453 /* If the card has gone away the read returns 0xffff. */ 1454 if (status == 0xffff) 1455 break; 1456 if (status) 1457 CSR_WRITE_2(sc, RL_ISR, status); 1458 1459 if ((status & RL_INTRS) == 0) 1460 break; 1461 1462 if (status & RL_ISR_RX_OK) 1463 rl_rxeof(sc); 1464 1465 if (status & RL_ISR_RX_ERR) 1466 rl_rxeof(sc); 1467 1468 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1469 rl_txeof(sc); 1470 1471 if (status & RL_ISR_SYSTEM_ERR) { 1472 rl_reset(sc); 1473 rl_init(sc); 1474 } 1475 1476 } 1477 1478 if (ifp->if_snd.ifq_head != NULL) 1479 rl_start(ifp); 1480 1481#ifdef DEVICE_POLLING 1482done: 1483#endif 1484 RL_UNLOCK(sc); 1485 1486 return; 1487} 1488 1489/* 1490 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1491 * pointers to the fragment pointers. 1492 */ 1493static int 1494rl_encap(sc, m_head) 1495 struct rl_softc *sc; 1496 struct mbuf *m_head; 1497{ 1498 struct mbuf *m_new = NULL; 1499 1500 /* 1501 * The RealTek is brain damaged and wants longword-aligned 1502 * TX buffers, plus we can only have one fragment buffer 1503 * per packet. We have to copy pretty much all the time. 1504 */ 1505 m_new = m_defrag(m_head, M_DONTWAIT); 1506 1507 if (m_new == NULL) { 1508 m_freem(m_head); 1509 return(1); 1510 } 1511 m_head = m_new; 1512 1513 /* Pad frames to at least 60 bytes. */ 1514 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1515 /* 1516 * Make security concious people happy: zero out the 1517 * bytes in the pad area, since we don't know what 1518 * this mbuf cluster buffer's previous user might 1519 * have left in it. 1520 */ 1521 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1522 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1523 m_head->m_pkthdr.len += 1524 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1525 m_head->m_len = m_head->m_pkthdr.len; 1526 } 1527 1528 RL_CUR_TXMBUF(sc) = m_head; 1529 1530 return(0); 1531} 1532 1533/* 1534 * Main transmit routine. 1535 */ 1536 1537static void 1538rl_start(ifp) 1539 struct ifnet *ifp; 1540{ 1541 struct rl_softc *sc; 1542 struct mbuf *m_head = NULL; 1543 1544 sc = ifp->if_softc; 1545 RL_LOCK(sc); 1546 1547 while(RL_CUR_TXMBUF(sc) == NULL) { 1548 IF_DEQUEUE(&ifp->if_snd, m_head); 1549 if (m_head == NULL) 1550 break; 1551 1552 if (rl_encap(sc, m_head)) { 1553 break; 1554 } 1555 1556 /* 1557 * If there's a BPF listener, bounce a copy of this frame 1558 * to him. 1559 */ 1560 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1561 1562 /* 1563 * Transmit the frame. 1564 */ 1565 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1566 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1567 mtod(RL_CUR_TXMBUF(sc), void *), 1568 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 1569 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1570 BUS_DMASYNC_PREREAD); 1571 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1572 RL_TXTHRESH(sc->rl_txthresh) | 1573 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1574 1575 RL_INC(sc->rl_cdata.cur_tx); 1576 1577 /* 1578 * Set a timeout in case the chip goes out to lunch. 1579 */ 1580 ifp->if_timer = 5; 1581 } 1582 1583 /* 1584 * We broke out of the loop because all our TX slots are 1585 * full. Mark the NIC as busy until it drains some of the 1586 * packets from the queue. 1587 */ 1588 if (RL_CUR_TXMBUF(sc) != NULL) 1589 ifp->if_flags |= IFF_OACTIVE; 1590 1591 RL_UNLOCK(sc); 1592 1593 return; 1594} 1595 1596static void 1597rl_init(xsc) 1598 void *xsc; 1599{ 1600 struct rl_softc *sc = xsc; 1601 struct ifnet *ifp = &sc->arpcom.ac_if; 1602 struct mii_data *mii; 1603 u_int32_t rxcfg = 0; 1604 1605 RL_LOCK(sc); 1606 mii = device_get_softc(sc->rl_miibus); 1607 1608 /* 1609 * Cancel pending I/O and free all RX/TX buffers. 1610 */ 1611 rl_stop(sc); 1612 1613 /* 1614 * Init our MAC address. Even though the chipset 1615 * documentation doesn't mention it, we need to enter "Config 1616 * register write enable" mode to modify the ID registers. 1617 */ 1618 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1619 CSR_WRITE_STREAM_4(sc, RL_IDR0, 1620 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1621 CSR_WRITE_STREAM_4(sc, RL_IDR4, 1622 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1623 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1624 1625 /* Init the RX buffer pointer register. */ 1626 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1627 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 1628 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1629 BUS_DMASYNC_PREWRITE); 1630 1631 /* Init TX descriptors. */ 1632 rl_list_tx_init(sc); 1633 1634 /* 1635 * Enable transmit and receive. 1636 */ 1637 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1638 1639 /* 1640 * Set the initial TX and RX configuration. 1641 */ 1642 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1643 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1644 1645 /* Set the individual bit to receive frames for this host only. */ 1646 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1647 rxcfg |= RL_RXCFG_RX_INDIV; 1648 1649 /* If we want promiscuous mode, set the allframes bit. */ 1650 if (ifp->if_flags & IFF_PROMISC) { 1651 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1652 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1653 } else { 1654 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1655 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1656 } 1657 1658 /* 1659 * Set capture broadcast bit to capture broadcast frames. 1660 */ 1661 if (ifp->if_flags & IFF_BROADCAST) { 1662 rxcfg |= RL_RXCFG_RX_BROAD; 1663 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1664 } else { 1665 rxcfg &= ~RL_RXCFG_RX_BROAD; 1666 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1667 } 1668 1669 /* 1670 * Program the multicast filter, if necessary. 1671 */ 1672 rl_setmulti(sc); 1673 1674#ifdef DEVICE_POLLING 1675 /* 1676 * Disable interrupts if we are polling. 1677 */ 1678 if (ifp->if_flags & IFF_POLLING) 1679 CSR_WRITE_2(sc, RL_IMR, 0); 1680 else /* otherwise ... */ 1681#endif /* DEVICE_POLLING */ 1682 /* 1683 * Enable interrupts. 1684 */ 1685 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1686 1687 /* Set initial TX threshold */ 1688 sc->rl_txthresh = RL_TX_THRESH_INIT; 1689 1690 /* Start RX/TX process. */ 1691 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1692 1693 /* Enable receiver and transmitter. */ 1694 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1695 1696 mii_mediachg(mii); 1697 1698 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1699 1700 ifp->if_flags |= IFF_RUNNING; 1701 ifp->if_flags &= ~IFF_OACTIVE; 1702 1703 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1704 RL_UNLOCK(sc); 1705 1706 return; 1707} 1708 1709/* 1710 * Set media options. 1711 */ 1712static int 1713rl_ifmedia_upd(ifp) 1714 struct ifnet *ifp; 1715{ 1716 struct rl_softc *sc; 1717 struct mii_data *mii; 1718 1719 sc = ifp->if_softc; 1720 mii = device_get_softc(sc->rl_miibus); 1721 mii_mediachg(mii); 1722 1723 return(0); 1724} 1725 1726/* 1727 * Report current media status. 1728 */ 1729static void 1730rl_ifmedia_sts(ifp, ifmr) 1731 struct ifnet *ifp; 1732 struct ifmediareq *ifmr; 1733{ 1734 struct rl_softc *sc; 1735 struct mii_data *mii; 1736 1737 sc = ifp->if_softc; 1738 mii = device_get_softc(sc->rl_miibus); 1739 1740 mii_pollstat(mii); 1741 ifmr->ifm_active = mii->mii_media_active; 1742 ifmr->ifm_status = mii->mii_media_status; 1743 1744 return; 1745} 1746 1747static int 1748rl_ioctl(ifp, command, data) 1749 struct ifnet *ifp; 1750 u_long command; 1751 caddr_t data; 1752{ 1753 struct rl_softc *sc = ifp->if_softc; 1754 struct ifreq *ifr = (struct ifreq *) data; 1755 struct mii_data *mii; 1756 int error = 0; 1757 1758 RL_LOCK(sc); 1759 1760 switch(command) { 1761 case SIOCSIFFLAGS: 1762 if (ifp->if_flags & IFF_UP) { 1763 rl_init(sc); 1764 } else { 1765 if (ifp->if_flags & IFF_RUNNING) 1766 rl_stop(sc); 1767 } 1768 error = 0; 1769 break; 1770 case SIOCADDMULTI: 1771 case SIOCDELMULTI: 1772 rl_setmulti(sc); 1773 error = 0; 1774 break; 1775 case SIOCGIFMEDIA: 1776 case SIOCSIFMEDIA: 1777 mii = device_get_softc(sc->rl_miibus); 1778 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1779 break; 1780 case SIOCSIFCAP: 1781 ifp->if_capenable &= ~IFCAP_POLLING; 1782 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 1783 break; 1784 default: 1785 error = ether_ioctl(ifp, command, data); 1786 break; 1787 } 1788 1789 RL_UNLOCK(sc); 1790 1791 return(error); 1792} 1793 1794static void 1795rl_watchdog(ifp) 1796 struct ifnet *ifp; 1797{ 1798 struct rl_softc *sc; 1799 1800 sc = ifp->if_softc; 1801 RL_LOCK(sc); 1802 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1803 ifp->if_oerrors++; 1804 1805 rl_txeof(sc); 1806 rl_rxeof(sc); 1807 rl_init(sc); 1808 RL_UNLOCK(sc); 1809 1810 return; 1811} 1812 1813/* 1814 * Stop the adapter and free any mbufs allocated to the 1815 * RX and TX lists. 1816 */ 1817static void 1818rl_stop(sc) 1819 struct rl_softc *sc; 1820{ 1821 register int i; 1822 struct ifnet *ifp; 1823 1824 RL_LOCK(sc); 1825 ifp = &sc->arpcom.ac_if; 1826 ifp->if_timer = 0; 1827 1828 untimeout(rl_tick, sc, sc->rl_stat_ch); 1829 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1830#ifdef DEVICE_POLLING 1831 ether_poll_deregister(ifp); 1832#endif /* DEVICE_POLLING */ 1833 1834 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1835 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1836 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1837 1838 /* 1839 * Free the TX list buffers. 1840 */ 1841 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1842 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1843 bus_dmamap_unload(sc->rl_tag, 1844 sc->rl_cdata.rl_tx_dmamap[i]); 1845 bus_dmamap_destroy(sc->rl_tag, 1846 sc->rl_cdata.rl_tx_dmamap[i]); 1847 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1848 sc->rl_cdata.rl_tx_chain[i] = NULL; 1849 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(u_int32_t)), 1850 0x0000000); 1851 } 1852 } 1853 1854 RL_UNLOCK(sc); 1855 return; 1856} 1857 1858/* 1859 * Device suspend routine. Stop the interface and save some PCI 1860 * settings in case the BIOS doesn't restore them properly on 1861 * resume. 1862 */ 1863static int 1864rl_suspend(dev) 1865 device_t dev; 1866{ 1867 struct rl_softc *sc; 1868 1869 sc = device_get_softc(dev); 1870 rl_stop(sc); 1871 sc->suspended = 1; 1872 1873 return (0); 1874} 1875 1876/* 1877 * Device resume routine. Restore some PCI settings in case the BIOS 1878 * doesn't, re-enable busmastering, and restart the interface if 1879 * appropriate. 1880 */ 1881static int 1882rl_resume(dev) 1883 device_t dev; 1884{ 1885 struct rl_softc *sc; 1886 struct ifnet *ifp; 1887 1888 sc = device_get_softc(dev); 1889 ifp = &sc->arpcom.ac_if; 1890 1891 /* reinitialize interface if necessary */ 1892 if (ifp->if_flags & IFF_UP) 1893 rl_init(sc); 1894 1895 sc->suspended = 0; 1896 1897 return (0); 1898} 1899 1900/* 1901 * Stop all chip I/O so that the kernel's probe routines don't 1902 * get confused by errant DMAs when rebooting. 1903 */ 1904static void 1905rl_shutdown(dev) 1906 device_t dev; 1907{ 1908 struct rl_softc *sc; 1909 1910 sc = device_get_softc(dev); 1911 1912 rl_stop(sc); 1913 1914 return; 1915} 1916