if_rl.c revision 129878
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 129878 2004-05-30 20:00:41Z phk $"); 35 36/* 37 * RealTek 8129/8139 PCI NIC driver 38 * 39 * Supports several extremely cheap PCI 10/100 adapters based on 40 * the RealTek chipset. Datasheets can be obtained from 41 * www.realtek.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86#include <sys/param.h> 87#include <sys/endian.h> 88#include <sys/systm.h> 89#include <sys/sockio.h> 90#include <sys/mbuf.h> 91#include <sys/malloc.h> 92#include <sys/kernel.h> 93#include <sys/module.h> 94#include <sys/socket.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> 98#include <net/ethernet.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101 102#include <net/bpf.h> 103 104#include <machine/bus_pio.h> 105#include <machine/bus_memio.h> 106#include <machine/bus.h> 107#include <machine/resource.h> 108#include <sys/bus.h> 109#include <sys/rman.h> 110 111#include <dev/mii/mii.h> 112#include <dev/mii/miivar.h> 113 114#include <dev/pci/pcireg.h> 115#include <dev/pci/pcivar.h> 116 117MODULE_DEPEND(rl, pci, 1, 1, 1); 118MODULE_DEPEND(rl, ether, 1, 1, 1); 119MODULE_DEPEND(rl, miibus, 1, 1, 1); 120 121/* "controller miibus0" required. See GENERIC if you get errors here. */ 122#include "miibus_if.h" 123 124/* 125 * Default to using PIO access for this driver. On SMP systems, 126 * there appear to be problems with memory mapped mode: it looks like 127 * doing too many memory mapped access back to back in rapid succession 128 * can hang the bus. I'm inclined to blame this on crummy design/construction 129 * on the part of RealTek. Memory mapped mode does appear to work on 130 * uniprocessor systems though. 131 */ 132#define RL_USEIOSPACE 133 134#include <pci/if_rlreg.h> 135 136/* 137 * Various supported device vendors/types and their names. 138 */ 139static struct rl_type rl_devs[] = { 140 { RT_VENDORID, RT_DEVICEID_8129, RL_8129, 141 "RealTek 8129 10/100BaseTX" }, 142 { RT_VENDORID, RT_DEVICEID_8139, RL_8139, 143 "RealTek 8139 10/100BaseTX" }, 144 { RT_VENDORID, RT_DEVICEID_8138, RL_8139, 145 "RealTek 8139 10/100BaseTX CardBus" }, 146 { RT_VENDORID, RT_DEVICEID_8100, RL_8139, 147 "RealTek 8100 10/100BaseTX" }, 148 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 149 "Accton MPX 5030/5038 10/100BaseTX" }, 150 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139, 151 "Delta Electronics 8139 10/100BaseTX" }, 152 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139, 153 "Addtron Technolgy 8139 10/100BaseTX" }, 154 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139, 155 "D-Link DFE-530TX+ 10/100BaseTX" }, 156 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139, 157 "D-Link DFE-690TXD 10/100BaseTX" }, 158 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 159 "Nortel Networks 10/100BaseTX" }, 160 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139, 161 "Corega FEther CB-TXD" }, 162 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139, 163 "Corega FEtherII CB-TXD" }, 164 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139, 165 "Peppercon AG ROL-F" }, 166 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139, 167 "Planex FNW-3800-TX" }, 168 { CP_VENDORID, RT_DEVICEID_8139, RL_8139, 169 "Compaq HNE-300" }, 170 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139, 171 "LevelOne FPC-0106TX" }, 172 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139, 173 "Edimax EP-4103DL CardBus" }, 174 { 0, 0, 0, NULL } 175}; 176 177static int rl_probe (device_t); 178static int rl_attach (device_t); 179static int rl_detach (device_t); 180 181static int rl_encap (struct rl_softc *, struct mbuf * ); 182 183static void rl_rxeof (struct rl_softc *); 184static void rl_txeof (struct rl_softc *); 185static void rl_intr (void *); 186static void rl_tick (void *); 187static void rl_start (struct ifnet *); 188static int rl_ioctl (struct ifnet *, u_long, caddr_t); 189static void rl_init (void *); 190static void rl_stop (struct rl_softc *); 191static void rl_watchdog (struct ifnet *); 192static int rl_suspend (device_t); 193static int rl_resume (device_t); 194static void rl_shutdown (device_t); 195static int rl_ifmedia_upd (struct ifnet *); 196static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 197 198static void rl_eeprom_putbyte (struct rl_softc *, int); 199static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 200static void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 201static void rl_mii_sync (struct rl_softc *); 202static void rl_mii_send (struct rl_softc *, u_int32_t, int); 203static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 204static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 205 206static int rl_miibus_readreg (device_t, int, int); 207static int rl_miibus_writereg (device_t, int, int, int); 208static void rl_miibus_statchg (device_t); 209 210static uint32_t rl_mchash (const uint8_t *); 211static void rl_setmulti (struct rl_softc *); 212static void rl_reset (struct rl_softc *); 213static int rl_list_tx_init (struct rl_softc *); 214 215static void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 216static void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 217 218#ifdef RL_USEIOSPACE 219#define RL_RES SYS_RES_IOPORT 220#define RL_RID RL_PCI_LOIO 221#else 222#define RL_RES SYS_RES_MEMORY 223#define RL_RID RL_PCI_LOMEM 224#endif 225 226static device_method_t rl_methods[] = { 227 /* Device interface */ 228 DEVMETHOD(device_probe, rl_probe), 229 DEVMETHOD(device_attach, rl_attach), 230 DEVMETHOD(device_detach, rl_detach), 231 DEVMETHOD(device_suspend, rl_suspend), 232 DEVMETHOD(device_resume, rl_resume), 233 DEVMETHOD(device_shutdown, rl_shutdown), 234 235 /* bus interface */ 236 DEVMETHOD(bus_print_child, bus_generic_print_child), 237 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 238 239 /* MII interface */ 240 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 241 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 242 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 243 244 { 0, 0 } 245}; 246 247static driver_t rl_driver = { 248 "rl", 249 rl_methods, 250 sizeof(struct rl_softc) 251}; 252 253static devclass_t rl_devclass; 254 255DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0); 256DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0); 257DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 258 259#define EE_SET(x) \ 260 CSR_WRITE_1(sc, RL_EECMD, \ 261 CSR_READ_1(sc, RL_EECMD) | x) 262 263#define EE_CLR(x) \ 264 CSR_WRITE_1(sc, RL_EECMD, \ 265 CSR_READ_1(sc, RL_EECMD) & ~x) 266 267static void 268rl_dma_map_rxbuf(arg, segs, nseg, error) 269 void *arg; 270 bus_dma_segment_t *segs; 271 int nseg, error; 272{ 273 struct rl_softc *sc; 274 275 sc = arg; 276 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 277 278 return; 279} 280 281static void 282rl_dma_map_txbuf(arg, segs, nseg, error) 283 void *arg; 284 bus_dma_segment_t *segs; 285 int nseg, error; 286{ 287 struct rl_softc *sc; 288 289 sc = arg; 290 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 291 292 return; 293} 294 295/* 296 * Send a read command and address to the EEPROM, check for ACK. 297 */ 298static void 299rl_eeprom_putbyte(sc, addr) 300 struct rl_softc *sc; 301 int addr; 302{ 303 register int d, i; 304 305 d = addr | sc->rl_eecmd_read; 306 307 /* 308 * Feed in each bit and strobe the clock. 309 */ 310 for (i = 0x400; i; i >>= 1) { 311 if (d & i) { 312 EE_SET(RL_EE_DATAIN); 313 } else { 314 EE_CLR(RL_EE_DATAIN); 315 } 316 DELAY(100); 317 EE_SET(RL_EE_CLK); 318 DELAY(150); 319 EE_CLR(RL_EE_CLK); 320 DELAY(100); 321 } 322 323 return; 324} 325 326/* 327 * Read a word of data stored in the EEPROM at address 'addr.' 328 */ 329static void 330rl_eeprom_getword(sc, addr, dest) 331 struct rl_softc *sc; 332 int addr; 333 u_int16_t *dest; 334{ 335 register int i; 336 u_int16_t word = 0; 337 338 /* Enter EEPROM access mode. */ 339 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 340 341 /* 342 * Send address of word we want to read. 343 */ 344 rl_eeprom_putbyte(sc, addr); 345 346 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 347 348 /* 349 * Start reading bits from EEPROM. 350 */ 351 for (i = 0x8000; i; i >>= 1) { 352 EE_SET(RL_EE_CLK); 353 DELAY(100); 354 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 355 word |= i; 356 EE_CLR(RL_EE_CLK); 357 DELAY(100); 358 } 359 360 /* Turn off EEPROM access mode. */ 361 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 362 363 *dest = word; 364 365 return; 366} 367 368/* 369 * Read a sequence of words from the EEPROM. 370 */ 371static void 372rl_read_eeprom(sc, dest, off, cnt, swap) 373 struct rl_softc *sc; 374 caddr_t dest; 375 int off; 376 int cnt; 377 int swap; 378{ 379 int i; 380 u_int16_t word = 0, *ptr; 381 382 for (i = 0; i < cnt; i++) { 383 rl_eeprom_getword(sc, off + i, &word); 384 ptr = (u_int16_t *)(dest + (i * 2)); 385 if (swap) 386 *ptr = ntohs(word); 387 else 388 *ptr = word; 389 } 390 391 return; 392} 393 394 395/* 396 * MII access routines are provided for the 8129, which 397 * doesn't have a built-in PHY. For the 8139, we fake things 398 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 399 * direct access PHY registers. 400 */ 401#define MII_SET(x) \ 402 CSR_WRITE_1(sc, RL_MII, \ 403 CSR_READ_1(sc, RL_MII) | (x)) 404 405#define MII_CLR(x) \ 406 CSR_WRITE_1(sc, RL_MII, \ 407 CSR_READ_1(sc, RL_MII) & ~(x)) 408 409/* 410 * Sync the PHYs by setting data bit and strobing the clock 32 times. 411 */ 412static void 413rl_mii_sync(sc) 414 struct rl_softc *sc; 415{ 416 register int i; 417 418 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 419 420 for (i = 0; i < 32; i++) { 421 MII_SET(RL_MII_CLK); 422 DELAY(1); 423 MII_CLR(RL_MII_CLK); 424 DELAY(1); 425 } 426 427 return; 428} 429 430/* 431 * Clock a series of bits through the MII. 432 */ 433static void 434rl_mii_send(sc, bits, cnt) 435 struct rl_softc *sc; 436 u_int32_t bits; 437 int cnt; 438{ 439 int i; 440 441 MII_CLR(RL_MII_CLK); 442 443 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 444 if (bits & i) { 445 MII_SET(RL_MII_DATAOUT); 446 } else { 447 MII_CLR(RL_MII_DATAOUT); 448 } 449 DELAY(1); 450 MII_CLR(RL_MII_CLK); 451 DELAY(1); 452 MII_SET(RL_MII_CLK); 453 } 454} 455 456/* 457 * Read an PHY register through the MII. 458 */ 459static int 460rl_mii_readreg(sc, frame) 461 struct rl_softc *sc; 462 struct rl_mii_frame *frame; 463 464{ 465 int i, ack; 466 467 RL_LOCK(sc); 468 469 /* 470 * Set up frame for RX. 471 */ 472 frame->mii_stdelim = RL_MII_STARTDELIM; 473 frame->mii_opcode = RL_MII_READOP; 474 frame->mii_turnaround = 0; 475 frame->mii_data = 0; 476 477 CSR_WRITE_2(sc, RL_MII, 0); 478 479 /* 480 * Turn on data xmit. 481 */ 482 MII_SET(RL_MII_DIR); 483 484 rl_mii_sync(sc); 485 486 /* 487 * Send command/address info. 488 */ 489 rl_mii_send(sc, frame->mii_stdelim, 2); 490 rl_mii_send(sc, frame->mii_opcode, 2); 491 rl_mii_send(sc, frame->mii_phyaddr, 5); 492 rl_mii_send(sc, frame->mii_regaddr, 5); 493 494 /* Idle bit */ 495 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 496 DELAY(1); 497 MII_SET(RL_MII_CLK); 498 DELAY(1); 499 500 /* Turn off xmit. */ 501 MII_CLR(RL_MII_DIR); 502 503 /* Check for ack */ 504 MII_CLR(RL_MII_CLK); 505 DELAY(1); 506 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 507 MII_SET(RL_MII_CLK); 508 DELAY(1); 509 510 /* 511 * Now try reading data bits. If the ack failed, we still 512 * need to clock through 16 cycles to keep the PHY(s) in sync. 513 */ 514 if (ack) { 515 for(i = 0; i < 16; i++) { 516 MII_CLR(RL_MII_CLK); 517 DELAY(1); 518 MII_SET(RL_MII_CLK); 519 DELAY(1); 520 } 521 goto fail; 522 } 523 524 for (i = 0x8000; i; i >>= 1) { 525 MII_CLR(RL_MII_CLK); 526 DELAY(1); 527 if (!ack) { 528 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 529 frame->mii_data |= i; 530 DELAY(1); 531 } 532 MII_SET(RL_MII_CLK); 533 DELAY(1); 534 } 535 536fail: 537 538 MII_CLR(RL_MII_CLK); 539 DELAY(1); 540 MII_SET(RL_MII_CLK); 541 DELAY(1); 542 543 RL_UNLOCK(sc); 544 545 if (ack) 546 return(1); 547 return(0); 548} 549 550/* 551 * Write to a PHY register through the MII. 552 */ 553static int 554rl_mii_writereg(sc, frame) 555 struct rl_softc *sc; 556 struct rl_mii_frame *frame; 557 558{ 559 RL_LOCK(sc); 560 561 /* 562 * Set up frame for TX. 563 */ 564 565 frame->mii_stdelim = RL_MII_STARTDELIM; 566 frame->mii_opcode = RL_MII_WRITEOP; 567 frame->mii_turnaround = RL_MII_TURNAROUND; 568 569 /* 570 * Turn on data output. 571 */ 572 MII_SET(RL_MII_DIR); 573 574 rl_mii_sync(sc); 575 576 rl_mii_send(sc, frame->mii_stdelim, 2); 577 rl_mii_send(sc, frame->mii_opcode, 2); 578 rl_mii_send(sc, frame->mii_phyaddr, 5); 579 rl_mii_send(sc, frame->mii_regaddr, 5); 580 rl_mii_send(sc, frame->mii_turnaround, 2); 581 rl_mii_send(sc, frame->mii_data, 16); 582 583 /* Idle bit. */ 584 MII_SET(RL_MII_CLK); 585 DELAY(1); 586 MII_CLR(RL_MII_CLK); 587 DELAY(1); 588 589 /* 590 * Turn off xmit. 591 */ 592 MII_CLR(RL_MII_DIR); 593 594 RL_UNLOCK(sc); 595 596 return(0); 597} 598 599static int 600rl_miibus_readreg(dev, phy, reg) 601 device_t dev; 602 int phy, reg; 603{ 604 struct rl_softc *sc; 605 struct rl_mii_frame frame; 606 u_int16_t rval = 0; 607 u_int16_t rl8139_reg = 0; 608 609 sc = device_get_softc(dev); 610 RL_LOCK(sc); 611 612 if (sc->rl_type == RL_8139) { 613 /* Pretend the internal PHY is only at address 0 */ 614 if (phy) { 615 RL_UNLOCK(sc); 616 return(0); 617 } 618 switch(reg) { 619 case MII_BMCR: 620 rl8139_reg = RL_BMCR; 621 break; 622 case MII_BMSR: 623 rl8139_reg = RL_BMSR; 624 break; 625 case MII_ANAR: 626 rl8139_reg = RL_ANAR; 627 break; 628 case MII_ANER: 629 rl8139_reg = RL_ANER; 630 break; 631 case MII_ANLPAR: 632 rl8139_reg = RL_LPAR; 633 break; 634 case MII_PHYIDR1: 635 case MII_PHYIDR2: 636 RL_UNLOCK(sc); 637 return(0); 638 /* 639 * Allow the rlphy driver to read the media status 640 * register. If we have a link partner which does not 641 * support NWAY, this is the register which will tell 642 * us the results of parallel detection. 643 */ 644 case RL_MEDIASTAT: 645 rval = CSR_READ_1(sc, RL_MEDIASTAT); 646 RL_UNLOCK(sc); 647 return(rval); 648 default: 649 printf("rl%d: bad phy register\n", sc->rl_unit); 650 RL_UNLOCK(sc); 651 return(0); 652 } 653 rval = CSR_READ_2(sc, rl8139_reg); 654 RL_UNLOCK(sc); 655 return(rval); 656 } 657 658 bzero((char *)&frame, sizeof(frame)); 659 660 frame.mii_phyaddr = phy; 661 frame.mii_regaddr = reg; 662 rl_mii_readreg(sc, &frame); 663 RL_UNLOCK(sc); 664 665 return(frame.mii_data); 666} 667 668static int 669rl_miibus_writereg(dev, phy, reg, data) 670 device_t dev; 671 int phy, reg, data; 672{ 673 struct rl_softc *sc; 674 struct rl_mii_frame frame; 675 u_int16_t rl8139_reg = 0; 676 677 sc = device_get_softc(dev); 678 RL_LOCK(sc); 679 680 if (sc->rl_type == RL_8139) { 681 /* Pretend the internal PHY is only at address 0 */ 682 if (phy) { 683 RL_UNLOCK(sc); 684 return(0); 685 } 686 switch(reg) { 687 case MII_BMCR: 688 rl8139_reg = RL_BMCR; 689 break; 690 case MII_BMSR: 691 rl8139_reg = RL_BMSR; 692 break; 693 case MII_ANAR: 694 rl8139_reg = RL_ANAR; 695 break; 696 case MII_ANER: 697 rl8139_reg = RL_ANER; 698 break; 699 case MII_ANLPAR: 700 rl8139_reg = RL_LPAR; 701 break; 702 case MII_PHYIDR1: 703 case MII_PHYIDR2: 704 RL_UNLOCK(sc); 705 return(0); 706 break; 707 default: 708 printf("rl%d: bad phy register\n", sc->rl_unit); 709 RL_UNLOCK(sc); 710 return(0); 711 } 712 CSR_WRITE_2(sc, rl8139_reg, data); 713 RL_UNLOCK(sc); 714 return(0); 715 } 716 717 bzero((char *)&frame, sizeof(frame)); 718 719 frame.mii_phyaddr = phy; 720 frame.mii_regaddr = reg; 721 frame.mii_data = data; 722 723 rl_mii_writereg(sc, &frame); 724 725 RL_UNLOCK(sc); 726 return(0); 727} 728 729static void 730rl_miibus_statchg(dev) 731 device_t dev; 732{ 733 return; 734} 735 736/* 737 * Calculate CRC of a multicast group address, return the upper 6 bits. 738 */ 739static u_int32_t 740rl_mchash(addr) 741 const uint8_t *addr; 742{ 743 uint32_t crc, carry; 744 int idx, bit; 745 uint8_t data; 746 747 /* Compute CRC for the address value. */ 748 crc = 0xFFFFFFFF; /* initial value */ 749 750 for (idx = 0; idx < 6; idx++) { 751 for (data = *addr++, bit = 0; bit < 8; bit++, data >>=1 ) { 752 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 753 crc <<= 1; 754 if (carry) 755 crc = (crc ^ 0x04c11db6) | carry; 756 } 757 } 758 759 /* return the filter bit position */ 760 return(crc >> 26); 761} 762 763/* 764 * Program the 64-bit multicast hash filter. 765 */ 766static void 767rl_setmulti(sc) 768 struct rl_softc *sc; 769{ 770 struct ifnet *ifp; 771 int h = 0; 772 u_int32_t hashes[2] = { 0, 0 }; 773 struct ifmultiaddr *ifma; 774 u_int32_t rxfilt; 775 int mcnt = 0; 776 777 ifp = &sc->arpcom.ac_if; 778 779 rxfilt = CSR_READ_4(sc, RL_RXCFG); 780 781 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 782 rxfilt |= RL_RXCFG_RX_MULTI; 783 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 784 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 785 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 786 return; 787 } 788 789 /* first, zot all the existing hash bits */ 790 CSR_WRITE_4(sc, RL_MAR0, 0); 791 CSR_WRITE_4(sc, RL_MAR4, 0); 792 793 /* now program new ones */ 794 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 795 if (ifma->ifma_addr->sa_family != AF_LINK) 796 continue; 797 h = rl_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 798 if (h < 32) 799 hashes[0] |= (1 << h); 800 else 801 hashes[1] |= (1 << (h - 32)); 802 mcnt++; 803 } 804 805 if (mcnt) 806 rxfilt |= RL_RXCFG_RX_MULTI; 807 else 808 rxfilt &= ~RL_RXCFG_RX_MULTI; 809 810 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 811 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 812 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 813 814 return; 815} 816 817static void 818rl_reset(sc) 819 struct rl_softc *sc; 820{ 821 register int i; 822 823 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 824 825 for (i = 0; i < RL_TIMEOUT; i++) { 826 DELAY(10); 827 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 828 break; 829 } 830 if (i == RL_TIMEOUT) 831 printf("rl%d: reset never completed!\n", sc->rl_unit); 832 833 return; 834} 835 836/* 837 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 838 * IDs against our list and return a device name if we find a match. 839 */ 840static int 841rl_probe(dev) 842 device_t dev; 843{ 844 struct rl_type *t; 845 struct rl_softc *sc; 846 int rid; 847 u_int32_t hwrev; 848 849 t = rl_devs; 850 sc = device_get_softc(dev); 851 852 while(t->rl_name != NULL) { 853 if ((pci_get_vendor(dev) == t->rl_vid) && 854 (pci_get_device(dev) == t->rl_did)) { 855 856 /* 857 * Temporarily map the I/O space 858 * so we can read the chip ID register. 859 */ 860 rid = RL_RID; 861 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 862 RF_ACTIVE); 863 if (sc->rl_res == NULL) { 864 device_printf(dev, 865 "couldn't map ports/memory\n"); 866 return(ENXIO); 867 } 868 sc->rl_btag = rman_get_bustag(sc->rl_res); 869 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 870 mtx_init(&sc->rl_mtx, 871 device_get_nameunit(dev), 872 MTX_NETWORK_LOCK, MTX_DEF); 873 RL_LOCK(sc); 874 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 875 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 876 RL_UNLOCK(sc); 877 mtx_destroy(&sc->rl_mtx); 878 879 /* Don't attach to 8139C+ or 8169/8110 chips. */ 880 if (hwrev == RL_HWREV_8139CPLUS || 881 (hwrev == RL_HWREV_8169 && 882 t->rl_did == RT_DEVICEID_8169) || 883 hwrev == RL_HWREV_8169S || 884 hwrev == RL_HWREV_8110S) { 885 t++; 886 continue; 887 } 888 889 device_set_desc(dev, t->rl_name); 890 return(0); 891 } 892 t++; 893 } 894 895 return(ENXIO); 896} 897 898/* 899 * Attach the interface. Allocate softc structures, do ifmedia 900 * setup and ethernet/BPF attach. 901 */ 902static int 903rl_attach(dev) 904 device_t dev; 905{ 906 u_char eaddr[ETHER_ADDR_LEN]; 907 u_int16_t as[3]; 908 struct rl_softc *sc; 909 struct ifnet *ifp; 910 u_int16_t rl_did = 0; 911 struct rl_type *t; 912 int unit, error = 0, rid, i; 913 914 sc = device_get_softc(dev); 915 unit = device_get_unit(dev); 916 917 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 918 MTX_DEF | MTX_RECURSE); 919#ifndef BURN_BRIDGES 920 /* 921 * Handle power management nonsense. 922 */ 923 924 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 925 u_int32_t iobase, membase, irq; 926 927 /* Save important PCI config data. */ 928 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 929 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 930 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 931 932 /* Reset the power state. */ 933 printf("rl%d: chip is is in D%d power mode " 934 "-- setting to D0\n", unit, 935 pci_get_powerstate(dev)); 936 937 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 938 939 /* Restore PCI config data. */ 940 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 941 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 942 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 943 } 944#endif 945 /* 946 * Map control/status registers. 947 */ 948 pci_enable_busmaster(dev); 949 950 rid = RL_RID; 951 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE); 952 953 if (sc->rl_res == NULL) { 954 printf ("rl%d: couldn't map ports/memory\n", unit); 955 error = ENXIO; 956 goto fail; 957 } 958 959#ifdef notdef 960 /* Detect the Realtek 8139B. For some reason, this chip is very 961 * unstable when left to autoselect the media 962 * The best workaround is to set the device to the required 963 * media type or to set it to the 10 Meg speed. 964 */ 965 966 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 967 printf("rl%d: Realtek 8139B detected. Warning, " 968 "this may be unstable in autoselect mode\n", unit); 969 } 970#endif 971 972 sc->rl_btag = rman_get_bustag(sc->rl_res); 973 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 974 975 /* Allocate interrupt */ 976 rid = 0; 977 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 978 RF_SHAREABLE | RF_ACTIVE); 979 980 if (sc->rl_irq == NULL) { 981 printf("rl%d: couldn't map interrupt\n", unit); 982 error = ENXIO; 983 goto fail; 984 } 985 986 /* Reset the adapter. */ 987 rl_reset(sc); 988 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 989 rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 990 if (rl_did != 0x8129) 991 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 992 993 /* 994 * Get station address from the EEPROM. 995 */ 996 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 997 for (i = 0; i < 3; i++) { 998 eaddr[(i * 2) + 0] = as[i] & 0xff; 999 eaddr[(i * 2) + 1] = as[i] >> 8; 1000 } 1001 1002 sc->rl_unit = unit; 1003 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1004 1005 /* 1006 * Now read the exact device type from the EEPROM to find 1007 * out if it's an 8129 or 8139. 1008 */ 1009 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 1010 1011 t = rl_devs; 1012 sc->rl_type = 0; 1013 while(t->rl_name != NULL) { 1014 if (rl_did == t->rl_did) { 1015 sc->rl_type = t->rl_basetype; 1016 break; 1017 } 1018 t++; 1019 } 1020 1021 if (sc->rl_type == 0) { 1022 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 1023 error = ENXIO; 1024 goto fail; 1025 } 1026 1027 /* 1028 * Allocate the parent bus DMA tag appropriate for PCI. 1029 */ 1030#define RL_NSEG_NEW 32 1031 error = bus_dma_tag_create(NULL, /* parent */ 1032 1, 0, /* alignment, boundary */ 1033 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1034 BUS_SPACE_MAXADDR, /* highaddr */ 1035 NULL, NULL, /* filter, filterarg */ 1036 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1037 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1038 BUS_DMA_ALLOCNOW, /* flags */ 1039 NULL, NULL, /* lockfunc, lockarg */ 1040 &sc->rl_parent_tag); 1041 if (error) 1042 goto fail; 1043 1044 /* 1045 * Now allocate a tag for the DMA descriptor lists. 1046 * All of our lists are allocated as a contiguous block 1047 * of memory. 1048 */ 1049 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 1050 1, 0, /* alignment, boundary */ 1051 BUS_SPACE_MAXADDR, /* lowaddr */ 1052 BUS_SPACE_MAXADDR, /* highaddr */ 1053 NULL, NULL, /* filter, filterarg */ 1054 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 1055 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1056 BUS_DMA_ALLOCNOW, /* flags */ 1057 NULL, NULL, /* lockfunc, lockarg */ 1058 &sc->rl_tag); 1059 if (error) 1060 goto fail; 1061 1062 /* 1063 * Now allocate a chunk of DMA-able memory based on the 1064 * tag we just created. 1065 */ 1066 error = bus_dmamem_alloc(sc->rl_tag, 1067 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1068 &sc->rl_cdata.rl_rx_dmamap); 1069 1070 if (error) { 1071 printf("rl%d: no memory for list buffers!\n", unit); 1072 bus_dma_tag_destroy(sc->rl_tag); 1073 sc->rl_tag = NULL; 1074 goto fail; 1075 } 1076 1077 /* Leave a few bytes before the start of the RX ring buffer. */ 1078 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1079 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1080 1081 /* Do MII setup */ 1082 if (mii_phy_probe(dev, &sc->rl_miibus, 1083 rl_ifmedia_upd, rl_ifmedia_sts)) { 1084 printf("rl%d: MII without any phy!\n", sc->rl_unit); 1085 error = ENXIO; 1086 goto fail; 1087 } 1088 1089 ifp = &sc->arpcom.ac_if; 1090 ifp->if_softc = sc; 1091 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1092 ifp->if_mtu = ETHERMTU; 1093 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1094 ifp->if_ioctl = rl_ioctl; 1095 ifp->if_start = rl_start; 1096 ifp->if_watchdog = rl_watchdog; 1097 ifp->if_init = rl_init; 1098 ifp->if_baudrate = 10000000; 1099 ifp->if_capabilities = IFCAP_VLAN_MTU; 1100#ifdef DEVICE_POLLING 1101 ifp->if_capabilities |= IFCAP_POLLING; 1102#endif 1103 ifp->if_capenable = ifp->if_capabilities; 1104 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1105 1106 callout_handle_init(&sc->rl_stat_ch); 1107 1108 /* 1109 * Call MI attach routine. 1110 */ 1111 ether_ifattach(ifp, eaddr); 1112 1113 /* Hook interrupt last to avoid having to lock softc */ 1114 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1115 rl_intr, sc, &sc->rl_intrhand); 1116 1117 if (error) { 1118 printf("rl%d: couldn't set up irq\n", unit); 1119 ether_ifdetach(ifp); 1120 goto fail; 1121 } 1122 1123fail: 1124 if (error) 1125 rl_detach(dev); 1126 1127 return (error); 1128} 1129 1130/* 1131 * Shutdown hardware and free up resources. This can be called any 1132 * time after the mutex has been initialized. It is called in both 1133 * the error case in attach and the normal detach case so it needs 1134 * to be careful about only freeing resources that have actually been 1135 * allocated. 1136 */ 1137static int 1138rl_detach(dev) 1139 device_t dev; 1140{ 1141 struct rl_softc *sc; 1142 struct ifnet *ifp; 1143 1144 sc = device_get_softc(dev); 1145 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 1146 RL_LOCK(sc); 1147 ifp = &sc->arpcom.ac_if; 1148 1149 /* These should only be active if attach succeeded */ 1150 if (device_is_attached(dev)) { 1151 rl_stop(sc); 1152 ether_ifdetach(ifp); 1153 } 1154 if (sc->rl_miibus) 1155 device_delete_child(dev, sc->rl_miibus); 1156 bus_generic_detach(dev); 1157 1158 if (sc->rl_intrhand) 1159 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1160 if (sc->rl_irq) 1161 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1162 if (sc->rl_res) 1163 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1164 1165 if (sc->rl_tag) { 1166 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1167 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1168 sc->rl_cdata.rl_rx_dmamap); 1169 bus_dma_tag_destroy(sc->rl_tag); 1170 } 1171 if (sc->rl_parent_tag) 1172 bus_dma_tag_destroy(sc->rl_parent_tag); 1173 1174 RL_UNLOCK(sc); 1175 mtx_destroy(&sc->rl_mtx); 1176 1177 return(0); 1178} 1179 1180/* 1181 * Initialize the transmit descriptors. 1182 */ 1183static int 1184rl_list_tx_init(sc) 1185 struct rl_softc *sc; 1186{ 1187 struct rl_chain_data *cd; 1188 int i; 1189 1190 cd = &sc->rl_cdata; 1191 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1192 cd->rl_tx_chain[i] = NULL; 1193 CSR_WRITE_4(sc, 1194 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1195 } 1196 1197 sc->rl_cdata.cur_tx = 0; 1198 sc->rl_cdata.last_tx = 0; 1199 1200 return(0); 1201} 1202 1203/* 1204 * A frame has been uploaded: pass the resulting mbuf chain up to 1205 * the higher level protocols. 1206 * 1207 * You know there's something wrong with a PCI bus-master chip design 1208 * when you have to use m_devget(). 1209 * 1210 * The receive operation is badly documented in the datasheet, so I'll 1211 * attempt to document it here. The driver provides a buffer area and 1212 * places its base address in the RX buffer start address register. 1213 * The chip then begins copying frames into the RX buffer. Each frame 1214 * is preceded by a 32-bit RX status word which specifies the length 1215 * of the frame and certain other status bits. Each frame (starting with 1216 * the status word) is also 32-bit aligned. The frame length is in the 1217 * first 16 bits of the status word; the lower 15 bits correspond with 1218 * the 'rx status register' mentioned in the datasheet. 1219 * 1220 * Note: to make the Alpha happy, the frame payload needs to be aligned 1221 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1222 * as the offset argument to m_devget(). 1223 */ 1224static void 1225rl_rxeof(sc) 1226 struct rl_softc *sc; 1227{ 1228 struct mbuf *m; 1229 struct ifnet *ifp; 1230 int total_len = 0; 1231 u_int32_t rxstat; 1232 caddr_t rxbufpos; 1233 int wrap = 0; 1234 u_int16_t cur_rx; 1235 u_int16_t limit; 1236 u_int16_t rx_bytes = 0, max_bytes; 1237 1238 RL_LOCK_ASSERT(sc); 1239 1240 ifp = &sc->arpcom.ac_if; 1241 1242 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1243 BUS_DMASYNC_POSTREAD); 1244 1245 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1246 1247 /* Do not try to read past this point. */ 1248 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1249 1250 if (limit < cur_rx) 1251 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1252 else 1253 max_bytes = limit - cur_rx; 1254 1255 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1256#ifdef DEVICE_POLLING 1257 if (ifp->if_flags & IFF_POLLING) { 1258 if (sc->rxcycles <= 0) 1259 break; 1260 sc->rxcycles--; 1261 } 1262#endif /* DEVICE_POLLING */ 1263 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1264 rxstat = le32toh(*(u_int32_t *)rxbufpos); 1265 1266 /* 1267 * Here's a totally undocumented fact for you. When the 1268 * RealTek chip is in the process of copying a packet into 1269 * RAM for you, the length will be 0xfff0. If you spot a 1270 * packet header with this value, you need to stop. The 1271 * datasheet makes absolutely no mention of this and 1272 * RealTek should be shot for this. 1273 */ 1274 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1275 break; 1276 1277 if (!(rxstat & RL_RXSTAT_RXOK)) { 1278 ifp->if_ierrors++; 1279 rl_init(sc); 1280 return; 1281 } 1282 1283 /* No errors; receive the packet. */ 1284 total_len = rxstat >> 16; 1285 rx_bytes += total_len + 4; 1286 1287 /* 1288 * XXX The RealTek chip includes the CRC with every 1289 * received frame, and there's no way to turn this 1290 * behavior off (at least, I can't find anything in 1291 * the manual that explains how to do it) so we have 1292 * to trim off the CRC manually. 1293 */ 1294 total_len -= ETHER_CRC_LEN; 1295 1296 /* 1297 * Avoid trying to read more bytes than we know 1298 * the chip has prepared for us. 1299 */ 1300 if (rx_bytes > max_bytes) 1301 break; 1302 1303 rxbufpos = sc->rl_cdata.rl_rx_buf + 1304 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1305 1306 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1307 rxbufpos = sc->rl_cdata.rl_rx_buf; 1308 1309 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1310 1311 if (total_len > wrap) { 1312 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1313 NULL); 1314 if (m == NULL) { 1315 ifp->if_ierrors++; 1316 } else { 1317 m_copyback(m, wrap, total_len - wrap, 1318 sc->rl_cdata.rl_rx_buf); 1319 } 1320 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1321 } else { 1322 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1323 NULL); 1324 if (m == NULL) { 1325 ifp->if_ierrors++; 1326 } 1327 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1328 } 1329 1330 /* 1331 * Round up to 32-bit boundary. 1332 */ 1333 cur_rx = (cur_rx + 3) & ~3; 1334 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1335 1336 if (m == NULL) 1337 continue; 1338 1339 ifp->if_ipackets++; 1340 RL_UNLOCK(sc); 1341 (*ifp->if_input)(ifp, m); 1342 RL_LOCK(sc); 1343 } 1344 1345 return; 1346} 1347 1348/* 1349 * A frame was downloaded to the chip. It's safe for us to clean up 1350 * the list buffers. 1351 */ 1352static void 1353rl_txeof(sc) 1354 struct rl_softc *sc; 1355{ 1356 struct ifnet *ifp; 1357 u_int32_t txstat; 1358 1359 ifp = &sc->arpcom.ac_if; 1360 1361 /* 1362 * Go through our tx list and free mbufs for those 1363 * frames that have been uploaded. 1364 */ 1365 do { 1366 if (RL_LAST_TXMBUF(sc) == NULL) 1367 break; 1368 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1369 if (!(txstat & (RL_TXSTAT_TX_OK| 1370 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1371 break; 1372 1373 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1374 1375 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1376 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1377 m_freem(RL_LAST_TXMBUF(sc)); 1378 RL_LAST_TXMBUF(sc) = NULL; 1379 if (txstat & RL_TXSTAT_TX_OK) 1380 ifp->if_opackets++; 1381 else { 1382 int oldthresh; 1383 ifp->if_oerrors++; 1384 if ((txstat & RL_TXSTAT_TXABRT) || 1385 (txstat & RL_TXSTAT_OUTOFWIN)) 1386 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1387 oldthresh = sc->rl_txthresh; 1388 /* error recovery */ 1389 rl_reset(sc); 1390 rl_init(sc); 1391 /* 1392 * If there was a transmit underrun, 1393 * bump the TX threshold. 1394 */ 1395 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1396 sc->rl_txthresh = oldthresh + 32; 1397 return; 1398 } 1399 RL_INC(sc->rl_cdata.last_tx); 1400 ifp->if_flags &= ~IFF_OACTIVE; 1401 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1402 1403 if (RL_LAST_TXMBUF(sc) == NULL) 1404 ifp->if_timer = 0; 1405 else if (ifp->if_timer == 0) 1406 ifp->if_timer = 5; 1407 1408 return; 1409} 1410 1411static void 1412rl_tick(xsc) 1413 void *xsc; 1414{ 1415 struct rl_softc *sc; 1416 struct mii_data *mii; 1417 1418 sc = xsc; 1419 RL_LOCK(sc); 1420 mii = device_get_softc(sc->rl_miibus); 1421 1422 mii_tick(mii); 1423 1424 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1425 RL_UNLOCK(sc); 1426 1427 return; 1428} 1429 1430#ifdef DEVICE_POLLING 1431static void 1432rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1433{ 1434 struct rl_softc *sc = ifp->if_softc; 1435 1436 RL_LOCK(sc); 1437 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1438 ether_poll_deregister(ifp); 1439 cmd = POLL_DEREGISTER; 1440 } 1441 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1442 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1443 goto done; 1444 } 1445 1446 sc->rxcycles = count; 1447 rl_rxeof(sc); 1448 rl_txeof(sc); 1449 if (ifp->if_snd.ifq_head != NULL) 1450 rl_start(ifp); 1451 1452 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1453 u_int16_t status; 1454 1455 status = CSR_READ_2(sc, RL_ISR); 1456 if (status == 0xffff) 1457 goto done; 1458 if (status) 1459 CSR_WRITE_2(sc, RL_ISR, status); 1460 1461 /* 1462 * XXX check behaviour on receiver stalls. 1463 */ 1464 1465 if (status & RL_ISR_SYSTEM_ERR) { 1466 rl_reset(sc); 1467 rl_init(sc); 1468 } 1469 } 1470done: 1471 RL_UNLOCK(sc); 1472} 1473#endif /* DEVICE_POLLING */ 1474 1475static void 1476rl_intr(arg) 1477 void *arg; 1478{ 1479 struct rl_softc *sc; 1480 struct ifnet *ifp; 1481 u_int16_t status; 1482 1483 sc = arg; 1484 1485 if (sc->suspended) { 1486 return; 1487 } 1488 1489 RL_LOCK(sc); 1490 ifp = &sc->arpcom.ac_if; 1491 1492#ifdef DEVICE_POLLING 1493 if (ifp->if_flags & IFF_POLLING) 1494 goto done; 1495 if ((ifp->if_capenable & IFCAP_POLLING) && 1496 ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 1497 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1498 rl_poll(ifp, 0, 1); 1499 goto done; 1500 } 1501#endif /* DEVICE_POLLING */ 1502 1503 for (;;) { 1504 1505 status = CSR_READ_2(sc, RL_ISR); 1506 /* If the card has gone away the read returns 0xffff. */ 1507 if (status == 0xffff) 1508 break; 1509 if (status) 1510 CSR_WRITE_2(sc, RL_ISR, status); 1511 1512 if ((status & RL_INTRS) == 0) 1513 break; 1514 1515 if (status & RL_ISR_RX_OK) 1516 rl_rxeof(sc); 1517 1518 if (status & RL_ISR_RX_ERR) 1519 rl_rxeof(sc); 1520 1521 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1522 rl_txeof(sc); 1523 1524 if (status & RL_ISR_SYSTEM_ERR) { 1525 rl_reset(sc); 1526 rl_init(sc); 1527 } 1528 1529 } 1530 1531 if (ifp->if_snd.ifq_head != NULL) 1532 rl_start(ifp); 1533 1534#ifdef DEVICE_POLLING 1535done: 1536#endif 1537 RL_UNLOCK(sc); 1538 1539 return; 1540} 1541 1542/* 1543 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1544 * pointers to the fragment pointers. 1545 */ 1546static int 1547rl_encap(sc, m_head) 1548 struct rl_softc *sc; 1549 struct mbuf *m_head; 1550{ 1551 struct mbuf *m_new = NULL; 1552 1553 /* 1554 * The RealTek is brain damaged and wants longword-aligned 1555 * TX buffers, plus we can only have one fragment buffer 1556 * per packet. We have to copy pretty much all the time. 1557 */ 1558 m_new = m_defrag(m_head, M_DONTWAIT); 1559 1560 if (m_new == NULL) { 1561 m_freem(m_head); 1562 return(1); 1563 } 1564 m_head = m_new; 1565 1566 /* Pad frames to at least 60 bytes. */ 1567 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1568 /* 1569 * Make security concious people happy: zero out the 1570 * bytes in the pad area, since we don't know what 1571 * this mbuf cluster buffer's previous user might 1572 * have left in it. 1573 */ 1574 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1575 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1576 m_head->m_pkthdr.len += 1577 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1578 m_head->m_len = m_head->m_pkthdr.len; 1579 } 1580 1581 RL_CUR_TXMBUF(sc) = m_head; 1582 1583 return(0); 1584} 1585 1586/* 1587 * Main transmit routine. 1588 */ 1589 1590static void 1591rl_start(ifp) 1592 struct ifnet *ifp; 1593{ 1594 struct rl_softc *sc; 1595 struct mbuf *m_head = NULL; 1596 1597 sc = ifp->if_softc; 1598 RL_LOCK(sc); 1599 1600 while(RL_CUR_TXMBUF(sc) == NULL) { 1601 IF_DEQUEUE(&ifp->if_snd, m_head); 1602 if (m_head == NULL) 1603 break; 1604 1605 if (rl_encap(sc, m_head)) { 1606 break; 1607 } 1608 1609 /* 1610 * If there's a BPF listener, bounce a copy of this frame 1611 * to him. 1612 */ 1613 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1614 1615 /* 1616 * Transmit the frame. 1617 */ 1618 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1619 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1620 mtod(RL_CUR_TXMBUF(sc), void *), 1621 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 1622 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1623 BUS_DMASYNC_PREREAD); 1624 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1625 RL_TXTHRESH(sc->rl_txthresh) | 1626 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1627 1628 RL_INC(sc->rl_cdata.cur_tx); 1629 1630 /* 1631 * Set a timeout in case the chip goes out to lunch. 1632 */ 1633 ifp->if_timer = 5; 1634 } 1635 1636 /* 1637 * We broke out of the loop because all our TX slots are 1638 * full. Mark the NIC as busy until it drains some of the 1639 * packets from the queue. 1640 */ 1641 if (RL_CUR_TXMBUF(sc) != NULL) 1642 ifp->if_flags |= IFF_OACTIVE; 1643 1644 RL_UNLOCK(sc); 1645 1646 return; 1647} 1648 1649static void 1650rl_init(xsc) 1651 void *xsc; 1652{ 1653 struct rl_softc *sc = xsc; 1654 struct ifnet *ifp = &sc->arpcom.ac_if; 1655 struct mii_data *mii; 1656 u_int32_t rxcfg = 0; 1657 1658 RL_LOCK(sc); 1659 mii = device_get_softc(sc->rl_miibus); 1660 1661 /* 1662 * Cancel pending I/O and free all RX/TX buffers. 1663 */ 1664 rl_stop(sc); 1665 1666 /* 1667 * Init our MAC address. Even though the chipset 1668 * documentation doesn't mention it, we need to enter "Config 1669 * register write enable" mode to modify the ID registers. 1670 */ 1671 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1672 CSR_WRITE_STREAM_4(sc, RL_IDR0, 1673 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1674 CSR_WRITE_STREAM_4(sc, RL_IDR4, 1675 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1676 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1677 1678 /* Init the RX buffer pointer register. */ 1679 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1680 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 1681 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1682 BUS_DMASYNC_PREWRITE); 1683 1684 /* Init TX descriptors. */ 1685 rl_list_tx_init(sc); 1686 1687 /* 1688 * Enable transmit and receive. 1689 */ 1690 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1691 1692 /* 1693 * Set the initial TX and RX configuration. 1694 */ 1695 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1696 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1697 1698 /* Set the individual bit to receive frames for this host only. */ 1699 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1700 rxcfg |= RL_RXCFG_RX_INDIV; 1701 1702 /* If we want promiscuous mode, set the allframes bit. */ 1703 if (ifp->if_flags & IFF_PROMISC) { 1704 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1705 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1706 } else { 1707 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1708 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1709 } 1710 1711 /* 1712 * Set capture broadcast bit to capture broadcast frames. 1713 */ 1714 if (ifp->if_flags & IFF_BROADCAST) { 1715 rxcfg |= RL_RXCFG_RX_BROAD; 1716 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1717 } else { 1718 rxcfg &= ~RL_RXCFG_RX_BROAD; 1719 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1720 } 1721 1722 /* 1723 * Program the multicast filter, if necessary. 1724 */ 1725 rl_setmulti(sc); 1726 1727#ifdef DEVICE_POLLING 1728 /* 1729 * Disable interrupts if we are polling. 1730 */ 1731 if (ifp->if_flags & IFF_POLLING) 1732 CSR_WRITE_2(sc, RL_IMR, 0); 1733 else /* otherwise ... */ 1734#endif /* DEVICE_POLLING */ 1735 /* 1736 * Enable interrupts. 1737 */ 1738 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1739 1740 /* Set initial TX threshold */ 1741 sc->rl_txthresh = RL_TX_THRESH_INIT; 1742 1743 /* Start RX/TX process. */ 1744 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1745 1746 /* Enable receiver and transmitter. */ 1747 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1748 1749 mii_mediachg(mii); 1750 1751 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1752 1753 ifp->if_flags |= IFF_RUNNING; 1754 ifp->if_flags &= ~IFF_OACTIVE; 1755 1756 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1757 RL_UNLOCK(sc); 1758 1759 return; 1760} 1761 1762/* 1763 * Set media options. 1764 */ 1765static int 1766rl_ifmedia_upd(ifp) 1767 struct ifnet *ifp; 1768{ 1769 struct rl_softc *sc; 1770 struct mii_data *mii; 1771 1772 sc = ifp->if_softc; 1773 mii = device_get_softc(sc->rl_miibus); 1774 mii_mediachg(mii); 1775 1776 return(0); 1777} 1778 1779/* 1780 * Report current media status. 1781 */ 1782static void 1783rl_ifmedia_sts(ifp, ifmr) 1784 struct ifnet *ifp; 1785 struct ifmediareq *ifmr; 1786{ 1787 struct rl_softc *sc; 1788 struct mii_data *mii; 1789 1790 sc = ifp->if_softc; 1791 mii = device_get_softc(sc->rl_miibus); 1792 1793 mii_pollstat(mii); 1794 ifmr->ifm_active = mii->mii_media_active; 1795 ifmr->ifm_status = mii->mii_media_status; 1796 1797 return; 1798} 1799 1800static int 1801rl_ioctl(ifp, command, data) 1802 struct ifnet *ifp; 1803 u_long command; 1804 caddr_t data; 1805{ 1806 struct rl_softc *sc = ifp->if_softc; 1807 struct ifreq *ifr = (struct ifreq *) data; 1808 struct mii_data *mii; 1809 int error = 0; 1810 1811 RL_LOCK(sc); 1812 1813 switch(command) { 1814 case SIOCSIFFLAGS: 1815 if (ifp->if_flags & IFF_UP) { 1816 rl_init(sc); 1817 } else { 1818 if (ifp->if_flags & IFF_RUNNING) 1819 rl_stop(sc); 1820 } 1821 error = 0; 1822 break; 1823 case SIOCADDMULTI: 1824 case SIOCDELMULTI: 1825 rl_setmulti(sc); 1826 error = 0; 1827 break; 1828 case SIOCGIFMEDIA: 1829 case SIOCSIFMEDIA: 1830 mii = device_get_softc(sc->rl_miibus); 1831 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1832 break; 1833 case SIOCSIFCAP: 1834 ifp->if_capenable &= ~IFCAP_POLLING; 1835 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 1836 break; 1837 default: 1838 error = ether_ioctl(ifp, command, data); 1839 break; 1840 } 1841 1842 RL_UNLOCK(sc); 1843 1844 return(error); 1845} 1846 1847static void 1848rl_watchdog(ifp) 1849 struct ifnet *ifp; 1850{ 1851 struct rl_softc *sc; 1852 1853 sc = ifp->if_softc; 1854 RL_LOCK(sc); 1855 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1856 ifp->if_oerrors++; 1857 1858 rl_txeof(sc); 1859 rl_rxeof(sc); 1860 rl_init(sc); 1861 RL_UNLOCK(sc); 1862 1863 return; 1864} 1865 1866/* 1867 * Stop the adapter and free any mbufs allocated to the 1868 * RX and TX lists. 1869 */ 1870static void 1871rl_stop(sc) 1872 struct rl_softc *sc; 1873{ 1874 register int i; 1875 struct ifnet *ifp; 1876 1877 RL_LOCK(sc); 1878 ifp = &sc->arpcom.ac_if; 1879 ifp->if_timer = 0; 1880 1881 untimeout(rl_tick, sc, sc->rl_stat_ch); 1882 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1883#ifdef DEVICE_POLLING 1884 ether_poll_deregister(ifp); 1885#endif /* DEVICE_POLLING */ 1886 1887 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1888 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1889 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1890 1891 /* 1892 * Free the TX list buffers. 1893 */ 1894 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1895 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1896 bus_dmamap_unload(sc->rl_tag, 1897 sc->rl_cdata.rl_tx_dmamap[i]); 1898 bus_dmamap_destroy(sc->rl_tag, 1899 sc->rl_cdata.rl_tx_dmamap[i]); 1900 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1901 sc->rl_cdata.rl_tx_chain[i] = NULL; 1902 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(u_int32_t)), 1903 0x0000000); 1904 } 1905 } 1906 1907 RL_UNLOCK(sc); 1908 return; 1909} 1910 1911/* 1912 * Device suspend routine. Stop the interface and save some PCI 1913 * settings in case the BIOS doesn't restore them properly on 1914 * resume. 1915 */ 1916static int 1917rl_suspend(dev) 1918 device_t dev; 1919{ 1920#ifndef BURN_BRIDGES 1921 register int i; 1922#endif 1923 struct rl_softc *sc; 1924 1925 sc = device_get_softc(dev); 1926 1927 rl_stop(sc); 1928 1929#ifndef BURN_BRIDGES 1930 for (i = 0; i < 5; i++) 1931 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 1932 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1933 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1934 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1935 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1936#endif 1937 1938 sc->suspended = 1; 1939 1940 return (0); 1941} 1942 1943/* 1944 * Device resume routine. Restore some PCI settings in case the BIOS 1945 * doesn't, re-enable busmastering, and restart the interface if 1946 * appropriate. 1947 */ 1948static int 1949rl_resume(dev) 1950 device_t dev; 1951{ 1952#ifndef BURN_BRIDGES 1953 register int i; 1954#endif 1955 struct rl_softc *sc; 1956 struct ifnet *ifp; 1957 1958 sc = device_get_softc(dev); 1959 ifp = &sc->arpcom.ac_if; 1960 1961#ifndef BURN_BRIDGES 1962 /* better way to do this? */ 1963 for (i = 0; i < 5; i++) 1964 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 1965 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1966 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1967 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1968 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1969 1970 /* reenable busmastering */ 1971 pci_enable_busmaster(dev); 1972 pci_enable_io(dev, RL_RES); 1973#endif 1974 1975 /* reinitialize interface if necessary */ 1976 if (ifp->if_flags & IFF_UP) 1977 rl_init(sc); 1978 1979 sc->suspended = 0; 1980 1981 return (0); 1982} 1983 1984/* 1985 * Stop all chip I/O so that the kernel's probe routines don't 1986 * get confused by errant DMAs when rebooting. 1987 */ 1988static void 1989rl_shutdown(dev) 1990 device_t dev; 1991{ 1992 struct rl_softc *sc; 1993 1994 sc = device_get_softc(dev); 1995 1996 rl_stop(sc); 1997 1998 return; 1999} 2000