if_rl.c revision 122625
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * RealTek 8129/8139 PCI NIC driver 35 * 36 * Supports several extremely cheap PCI 10/100 adapters based on 37 * the RealTek chipset. Datasheets can be obtained from 38 * www.realtek.com.tw. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 47 * probably the worst PCI ethernet controller ever made, with the possible 48 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 49 * DMA, but it has a terrible interface that nullifies any performance 50 * gains that bus-master DMA usually offers. 51 * 52 * For transmission, the chip offers a series of four TX descriptor 53 * registers. Each transmit frame must be in a contiguous buffer, aligned 54 * on a longword (32-bit) boundary. This means we almost always have to 55 * do mbuf copies in order to transmit a frame, except in the unlikely 56 * case where a) the packet fits into a single mbuf, and b) the packet 57 * is 32-bit aligned within the mbuf's data area. The presence of only 58 * four descriptor registers means that we can never have more than four 59 * packets queued for transmission at any one time. 60 * 61 * Reception is not much better. The driver has to allocate a single large 62 * buffer area (up to 64K in size) into which the chip will DMA received 63 * frames. Because we don't know where within this region received packets 64 * will begin or end, we have no choice but to copy data from the buffer 65 * area into mbufs in order to pass the packets up to the higher protocol 66 * levels. 67 * 68 * It's impossible given this rotten design to really achieve decent 69 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 70 * some equally overmuscled CPU to drive it. 71 * 72 * On the bright side, the 8139 does have a built-in PHY, although 73 * rather than using an MDIO serial interface like most other NICs, the 74 * PHY registers are directly accessible through the 8139's register 75 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 76 * filter. 77 * 78 * The 8129 chip is an older version of the 8139 that uses an external PHY 79 * chip. The 8129 has a serial MDIO interface for accessing the MII where 80 * the 8139 lets you directly access the on-board PHY registers. We need 81 * to select which interface to use depending on the chip type. 82 */ 83 84#include <sys/cdefs.h> 85__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 122625 2003-11-13 20:55:53Z obrien $"); 86 87#include <sys/param.h> 88#include <sys/endian.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/socket.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> 98#include <net/ethernet.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101 102#include <net/bpf.h> 103 104#include <machine/bus_pio.h> 105#include <machine/bus_memio.h> 106#include <machine/bus.h> 107#include <machine/resource.h> 108#include <sys/bus.h> 109#include <sys/rman.h> 110 111#include <dev/mii/mii.h> 112#include <dev/mii/miivar.h> 113 114#include <dev/pci/pcireg.h> 115#include <dev/pci/pcivar.h> 116 117MODULE_DEPEND(rl, pci, 1, 1, 1); 118MODULE_DEPEND(rl, ether, 1, 1, 1); 119MODULE_DEPEND(rl, miibus, 1, 1, 1); 120 121/* "controller miibus0" required. See GENERIC if you get errors here. */ 122#include "miibus_if.h" 123 124/* 125 * Default to using PIO access for this driver. On SMP systems, 126 * there appear to be problems with memory mapped mode: it looks like 127 * doing too many memory mapped access back to back in rapid succession 128 * can hang the bus. I'm inclined to blame this on crummy design/construction 129 * on the part of RealTek. Memory mapped mode does appear to work on 130 * uniprocessor systems though. 131 */ 132#define RL_USEIOSPACE 133 134#include <pci/if_rlreg.h> 135 136/* 137 * Various supported device vendors/types and their names. 138 */ 139static struct rl_type rl_devs[] = { 140 { RT_VENDORID, RT_DEVICEID_8129, RL_8129, 141 "RealTek 8129 10/100BaseTX" }, 142 { RT_VENDORID, RT_DEVICEID_8139, RL_8139, 143 "RealTek 8139 10/100BaseTX" }, 144 { RT_VENDORID, RT_DEVICEID_8138, RL_8139, 145 "RealTek 8139 10/100BaseTX CardBus" }, 146 { RT_VENDORID, RT_DEVICEID_8100, RL_8139, 147 "RealTek 8100 10/100BaseTX" }, 148 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 149 "Accton MPX 5030/5038 10/100BaseTX" }, 150 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139, 151 "Delta Electronics 8139 10/100BaseTX" }, 152 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139, 153 "Addtron Technolgy 8139 10/100BaseTX" }, 154 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139, 155 "D-Link DFE-530TX+ 10/100BaseTX" }, 156 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139, 157 "D-Link DFE-690TXD 10/100BaseTX" }, 158 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 159 "Nortel Networks 10/100BaseTX" }, 160 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139, 161 "Corega FEther CB-TXD" }, 162 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139, 163 "Corega FEtherII CB-TXD" }, 164 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139, 165 "Peppercon AG ROL-F" }, 166 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139, 167 "Planex FNW-3800-TX" }, 168 { CP_VENDORID, RT_DEVICEID_8139, RL_8139, 169 "Compaq HNE-300" }, 170 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139, 171 "LevelOne FPC-0106TX" }, 172 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139, 173 "Edimax EP-4103DL CardBus" }, 174 { 0, 0, NULL } 175}; 176 177static int rl_probe (device_t); 178static int rl_attach (device_t); 179static int rl_detach (device_t); 180 181static int rl_encap (struct rl_softc *, struct mbuf * ); 182 183static void rl_rxeof (struct rl_softc *); 184static void rl_txeof (struct rl_softc *); 185static void rl_intr (void *); 186static void rl_tick (void *); 187static void rl_start (struct ifnet *); 188static int rl_ioctl (struct ifnet *, u_long, caddr_t); 189static void rl_init (void *); 190static void rl_stop (struct rl_softc *); 191static void rl_watchdog (struct ifnet *); 192static int rl_suspend (device_t); 193static int rl_resume (device_t); 194static void rl_shutdown (device_t); 195static int rl_ifmedia_upd (struct ifnet *); 196static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 197 198static void rl_eeprom_putbyte (struct rl_softc *, int); 199static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 200static void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 201static void rl_mii_sync (struct rl_softc *); 202static void rl_mii_send (struct rl_softc *, u_int32_t, int); 203static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 204static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 205 206static int rl_miibus_readreg (device_t, int, int); 207static int rl_miibus_writereg (device_t, int, int, int); 208static void rl_miibus_statchg (device_t); 209 210static u_int32_t rl_mchash (caddr_t); 211static void rl_setmulti (struct rl_softc *); 212static void rl_reset (struct rl_softc *); 213static int rl_list_tx_init (struct rl_softc *); 214 215static void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 216static void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 217 218#ifdef RL_USEIOSPACE 219#define RL_RES SYS_RES_IOPORT 220#define RL_RID RL_PCI_LOIO 221#else 222#define RL_RES SYS_RES_MEMORY 223#define RL_RID RL_PCI_LOMEM 224#endif 225 226static device_method_t rl_methods[] = { 227 /* Device interface */ 228 DEVMETHOD(device_probe, rl_probe), 229 DEVMETHOD(device_attach, rl_attach), 230 DEVMETHOD(device_detach, rl_detach), 231 DEVMETHOD(device_suspend, rl_suspend), 232 DEVMETHOD(device_resume, rl_resume), 233 DEVMETHOD(device_shutdown, rl_shutdown), 234 235 /* bus interface */ 236 DEVMETHOD(bus_print_child, bus_generic_print_child), 237 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 238 239 /* MII interface */ 240 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 241 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 242 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 243 244 { 0, 0 } 245}; 246 247static driver_t rl_driver = { 248 "rl", 249 rl_methods, 250 sizeof(struct rl_softc) 251}; 252 253static devclass_t rl_devclass; 254 255DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0); 256DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 257 258#define EE_SET(x) \ 259 CSR_WRITE_1(sc, RL_EECMD, \ 260 CSR_READ_1(sc, RL_EECMD) | x) 261 262#define EE_CLR(x) \ 263 CSR_WRITE_1(sc, RL_EECMD, \ 264 CSR_READ_1(sc, RL_EECMD) & ~x) 265 266static void 267rl_dma_map_rxbuf(arg, segs, nseg, error) 268 void *arg; 269 bus_dma_segment_t *segs; 270 int nseg, error; 271{ 272 struct rl_softc *sc; 273 274 sc = arg; 275 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 276 277 return; 278} 279 280static void 281rl_dma_map_txbuf(arg, segs, nseg, error) 282 void *arg; 283 bus_dma_segment_t *segs; 284 int nseg, error; 285{ 286 struct rl_softc *sc; 287 288 sc = arg; 289 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 290 291 return; 292} 293 294/* 295 * Send a read command and address to the EEPROM, check for ACK. 296 */ 297static void 298rl_eeprom_putbyte(sc, addr) 299 struct rl_softc *sc; 300 int addr; 301{ 302 register int d, i; 303 304 d = addr | sc->rl_eecmd_read; 305 306 /* 307 * Feed in each bit and strobe the clock. 308 */ 309 for (i = 0x400; i; i >>= 1) { 310 if (d & i) { 311 EE_SET(RL_EE_DATAIN); 312 } else { 313 EE_CLR(RL_EE_DATAIN); 314 } 315 DELAY(100); 316 EE_SET(RL_EE_CLK); 317 DELAY(150); 318 EE_CLR(RL_EE_CLK); 319 DELAY(100); 320 } 321 322 return; 323} 324 325/* 326 * Read a word of data stored in the EEPROM at address 'addr.' 327 */ 328static void 329rl_eeprom_getword(sc, addr, dest) 330 struct rl_softc *sc; 331 int addr; 332 u_int16_t *dest; 333{ 334 register int i; 335 u_int16_t word = 0; 336 337 /* Enter EEPROM access mode. */ 338 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 339 340 /* 341 * Send address of word we want to read. 342 */ 343 rl_eeprom_putbyte(sc, addr); 344 345 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 346 347 /* 348 * Start reading bits from EEPROM. 349 */ 350 for (i = 0x8000; i; i >>= 1) { 351 EE_SET(RL_EE_CLK); 352 DELAY(100); 353 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 354 word |= i; 355 EE_CLR(RL_EE_CLK); 356 DELAY(100); 357 } 358 359 /* Turn off EEPROM access mode. */ 360 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 361 362 *dest = word; 363 364 return; 365} 366 367/* 368 * Read a sequence of words from the EEPROM. 369 */ 370static void 371rl_read_eeprom(sc, dest, off, cnt, swap) 372 struct rl_softc *sc; 373 caddr_t dest; 374 int off; 375 int cnt; 376 int swap; 377{ 378 int i; 379 u_int16_t word = 0, *ptr; 380 381 for (i = 0; i < cnt; i++) { 382 rl_eeprom_getword(sc, off + i, &word); 383 ptr = (u_int16_t *)(dest + (i * 2)); 384 if (swap) 385 *ptr = ntohs(word); 386 else 387 *ptr = word; 388 } 389 390 return; 391} 392 393 394/* 395 * MII access routines are provided for the 8129, which 396 * doesn't have a built-in PHY. For the 8139, we fake things 397 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 398 * direct access PHY registers. 399 */ 400#define MII_SET(x) \ 401 CSR_WRITE_1(sc, RL_MII, \ 402 CSR_READ_1(sc, RL_MII) | (x)) 403 404#define MII_CLR(x) \ 405 CSR_WRITE_1(sc, RL_MII, \ 406 CSR_READ_1(sc, RL_MII) & ~(x)) 407 408/* 409 * Sync the PHYs by setting data bit and strobing the clock 32 times. 410 */ 411static void 412rl_mii_sync(sc) 413 struct rl_softc *sc; 414{ 415 register int i; 416 417 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 418 419 for (i = 0; i < 32; i++) { 420 MII_SET(RL_MII_CLK); 421 DELAY(1); 422 MII_CLR(RL_MII_CLK); 423 DELAY(1); 424 } 425 426 return; 427} 428 429/* 430 * Clock a series of bits through the MII. 431 */ 432static void 433rl_mii_send(sc, bits, cnt) 434 struct rl_softc *sc; 435 u_int32_t bits; 436 int cnt; 437{ 438 int i; 439 440 MII_CLR(RL_MII_CLK); 441 442 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 443 if (bits & i) { 444 MII_SET(RL_MII_DATAOUT); 445 } else { 446 MII_CLR(RL_MII_DATAOUT); 447 } 448 DELAY(1); 449 MII_CLR(RL_MII_CLK); 450 DELAY(1); 451 MII_SET(RL_MII_CLK); 452 } 453} 454 455/* 456 * Read an PHY register through the MII. 457 */ 458static int 459rl_mii_readreg(sc, frame) 460 struct rl_softc *sc; 461 struct rl_mii_frame *frame; 462 463{ 464 int i, ack; 465 466 RL_LOCK(sc); 467 468 /* 469 * Set up frame for RX. 470 */ 471 frame->mii_stdelim = RL_MII_STARTDELIM; 472 frame->mii_opcode = RL_MII_READOP; 473 frame->mii_turnaround = 0; 474 frame->mii_data = 0; 475 476 CSR_WRITE_2(sc, RL_MII, 0); 477 478 /* 479 * Turn on data xmit. 480 */ 481 MII_SET(RL_MII_DIR); 482 483 rl_mii_sync(sc); 484 485 /* 486 * Send command/address info. 487 */ 488 rl_mii_send(sc, frame->mii_stdelim, 2); 489 rl_mii_send(sc, frame->mii_opcode, 2); 490 rl_mii_send(sc, frame->mii_phyaddr, 5); 491 rl_mii_send(sc, frame->mii_regaddr, 5); 492 493 /* Idle bit */ 494 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 495 DELAY(1); 496 MII_SET(RL_MII_CLK); 497 DELAY(1); 498 499 /* Turn off xmit. */ 500 MII_CLR(RL_MII_DIR); 501 502 /* Check for ack */ 503 MII_CLR(RL_MII_CLK); 504 DELAY(1); 505 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 506 MII_SET(RL_MII_CLK); 507 DELAY(1); 508 509 /* 510 * Now try reading data bits. If the ack failed, we still 511 * need to clock through 16 cycles to keep the PHY(s) in sync. 512 */ 513 if (ack) { 514 for(i = 0; i < 16; i++) { 515 MII_CLR(RL_MII_CLK); 516 DELAY(1); 517 MII_SET(RL_MII_CLK); 518 DELAY(1); 519 } 520 goto fail; 521 } 522 523 for (i = 0x8000; i; i >>= 1) { 524 MII_CLR(RL_MII_CLK); 525 DELAY(1); 526 if (!ack) { 527 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 528 frame->mii_data |= i; 529 DELAY(1); 530 } 531 MII_SET(RL_MII_CLK); 532 DELAY(1); 533 } 534 535fail: 536 537 MII_CLR(RL_MII_CLK); 538 DELAY(1); 539 MII_SET(RL_MII_CLK); 540 DELAY(1); 541 542 RL_UNLOCK(sc); 543 544 if (ack) 545 return(1); 546 return(0); 547} 548 549/* 550 * Write to a PHY register through the MII. 551 */ 552static int 553rl_mii_writereg(sc, frame) 554 struct rl_softc *sc; 555 struct rl_mii_frame *frame; 556 557{ 558 RL_LOCK(sc); 559 560 /* 561 * Set up frame for TX. 562 */ 563 564 frame->mii_stdelim = RL_MII_STARTDELIM; 565 frame->mii_opcode = RL_MII_WRITEOP; 566 frame->mii_turnaround = RL_MII_TURNAROUND; 567 568 /* 569 * Turn on data output. 570 */ 571 MII_SET(RL_MII_DIR); 572 573 rl_mii_sync(sc); 574 575 rl_mii_send(sc, frame->mii_stdelim, 2); 576 rl_mii_send(sc, frame->mii_opcode, 2); 577 rl_mii_send(sc, frame->mii_phyaddr, 5); 578 rl_mii_send(sc, frame->mii_regaddr, 5); 579 rl_mii_send(sc, frame->mii_turnaround, 2); 580 rl_mii_send(sc, frame->mii_data, 16); 581 582 /* Idle bit. */ 583 MII_SET(RL_MII_CLK); 584 DELAY(1); 585 MII_CLR(RL_MII_CLK); 586 DELAY(1); 587 588 /* 589 * Turn off xmit. 590 */ 591 MII_CLR(RL_MII_DIR); 592 593 RL_UNLOCK(sc); 594 595 return(0); 596} 597 598static int 599rl_miibus_readreg(dev, phy, reg) 600 device_t dev; 601 int phy, reg; 602{ 603 struct rl_softc *sc; 604 struct rl_mii_frame frame; 605 u_int16_t rval = 0; 606 u_int16_t rl8139_reg = 0; 607 608 sc = device_get_softc(dev); 609 RL_LOCK(sc); 610 611 if (sc->rl_type == RL_8139) { 612 /* Pretend the internal PHY is only at address 0 */ 613 if (phy) { 614 RL_UNLOCK(sc); 615 return(0); 616 } 617 switch(reg) { 618 case MII_BMCR: 619 rl8139_reg = RL_BMCR; 620 break; 621 case MII_BMSR: 622 rl8139_reg = RL_BMSR; 623 break; 624 case MII_ANAR: 625 rl8139_reg = RL_ANAR; 626 break; 627 case MII_ANER: 628 rl8139_reg = RL_ANER; 629 break; 630 case MII_ANLPAR: 631 rl8139_reg = RL_LPAR; 632 break; 633 case MII_PHYIDR1: 634 case MII_PHYIDR2: 635 RL_UNLOCK(sc); 636 return(0); 637 /* 638 * Allow the rlphy driver to read the media status 639 * register. If we have a link partner which does not 640 * support NWAY, this is the register which will tell 641 * us the results of parallel detection. 642 */ 643 case RL_MEDIASTAT: 644 rval = CSR_READ_1(sc, RL_MEDIASTAT); 645 RL_UNLOCK(sc); 646 return(rval); 647 default: 648 printf("rl%d: bad phy register\n", sc->rl_unit); 649 RL_UNLOCK(sc); 650 return(0); 651 } 652 rval = CSR_READ_2(sc, rl8139_reg); 653 RL_UNLOCK(sc); 654 return(rval); 655 } 656 657 bzero((char *)&frame, sizeof(frame)); 658 659 frame.mii_phyaddr = phy; 660 frame.mii_regaddr = reg; 661 rl_mii_readreg(sc, &frame); 662 RL_UNLOCK(sc); 663 664 return(frame.mii_data); 665} 666 667static int 668rl_miibus_writereg(dev, phy, reg, data) 669 device_t dev; 670 int phy, reg, data; 671{ 672 struct rl_softc *sc; 673 struct rl_mii_frame frame; 674 u_int16_t rl8139_reg = 0; 675 676 sc = device_get_softc(dev); 677 RL_LOCK(sc); 678 679 if (sc->rl_type == RL_8139) { 680 /* Pretend the internal PHY is only at address 0 */ 681 if (phy) { 682 RL_UNLOCK(sc); 683 return(0); 684 } 685 switch(reg) { 686 case MII_BMCR: 687 rl8139_reg = RL_BMCR; 688 break; 689 case MII_BMSR: 690 rl8139_reg = RL_BMSR; 691 break; 692 case MII_ANAR: 693 rl8139_reg = RL_ANAR; 694 break; 695 case MII_ANER: 696 rl8139_reg = RL_ANER; 697 break; 698 case MII_ANLPAR: 699 rl8139_reg = RL_LPAR; 700 break; 701 case MII_PHYIDR1: 702 case MII_PHYIDR2: 703 RL_UNLOCK(sc); 704 return(0); 705 break; 706 default: 707 printf("rl%d: bad phy register\n", sc->rl_unit); 708 RL_UNLOCK(sc); 709 return(0); 710 } 711 CSR_WRITE_2(sc, rl8139_reg, data); 712 RL_UNLOCK(sc); 713 return(0); 714 } 715 716 bzero((char *)&frame, sizeof(frame)); 717 718 frame.mii_phyaddr = phy; 719 frame.mii_regaddr = reg; 720 frame.mii_data = data; 721 722 rl_mii_writereg(sc, &frame); 723 724 RL_UNLOCK(sc); 725 return(0); 726} 727 728static void 729rl_miibus_statchg(dev) 730 device_t dev; 731{ 732 return; 733} 734 735/* 736 * Calculate CRC of a multicast group address, return the upper 6 bits. 737 */ 738static u_int32_t 739rl_mchash(addr) 740 caddr_t addr; 741{ 742 u_int32_t crc, carry; 743 int idx, bit; 744 u_int8_t data; 745 746 /* Compute CRC for the address value. */ 747 crc = 0xFFFFFFFF; /* initial value */ 748 749 for (idx = 0; idx < 6; idx++) { 750 for (data = *addr++, bit = 0; bit < 8; bit++, data >>=1 ) { 751 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 752 crc <<= 1; 753 if (carry) 754 crc = (crc ^ 0x04c11db6) | carry; 755 } 756 } 757 758 /* return the filter bit position */ 759 return(crc >> 26); 760} 761 762/* 763 * Program the 64-bit multicast hash filter. 764 */ 765static void 766rl_setmulti(sc) 767 struct rl_softc *sc; 768{ 769 struct ifnet *ifp; 770 int h = 0; 771 u_int32_t hashes[2] = { 0, 0 }; 772 struct ifmultiaddr *ifma; 773 u_int32_t rxfilt; 774 int mcnt = 0; 775 776 ifp = &sc->arpcom.ac_if; 777 778 rxfilt = CSR_READ_4(sc, RL_RXCFG); 779 780 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 781 rxfilt |= RL_RXCFG_RX_MULTI; 782 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 783 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 784 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 785 return; 786 } 787 788 /* first, zot all the existing hash bits */ 789 CSR_WRITE_4(sc, RL_MAR0, 0); 790 CSR_WRITE_4(sc, RL_MAR4, 0); 791 792 /* now program new ones */ 793 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 794 if (ifma->ifma_addr->sa_family != AF_LINK) 795 continue; 796 h = rl_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 797 if (h < 32) 798 hashes[0] |= (1 << h); 799 else 800 hashes[1] |= (1 << (h - 32)); 801 mcnt++; 802 } 803 804 if (mcnt) 805 rxfilt |= RL_RXCFG_RX_MULTI; 806 else 807 rxfilt &= ~RL_RXCFG_RX_MULTI; 808 809 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 810 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 811 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 812 813 return; 814} 815 816static void 817rl_reset(sc) 818 struct rl_softc *sc; 819{ 820 register int i; 821 822 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 823 824 for (i = 0; i < RL_TIMEOUT; i++) { 825 DELAY(10); 826 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 827 break; 828 } 829 if (i == RL_TIMEOUT) 830 printf("rl%d: reset never completed!\n", sc->rl_unit); 831 832 return; 833} 834 835/* 836 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 837 * IDs against our list and return a device name if we find a match. 838 */ 839static int 840rl_probe(dev) 841 device_t dev; 842{ 843 struct rl_type *t; 844 struct rl_softc *sc; 845 int rid; 846 u_int32_t hwrev; 847 848 t = rl_devs; 849 sc = device_get_softc(dev); 850 851 while(t->rl_name != NULL) { 852 if ((pci_get_vendor(dev) == t->rl_vid) && 853 (pci_get_device(dev) == t->rl_did)) { 854 855 /* 856 * Temporarily map the I/O space 857 * so we can read the chip ID register. 858 */ 859 rid = RL_RID; 860 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 861 0, ~0, 1, RF_ACTIVE); 862 if (sc->rl_res == NULL) { 863 device_printf(dev, 864 "couldn't map ports/memory\n"); 865 return(ENXIO); 866 } 867 sc->rl_btag = rman_get_bustag(sc->rl_res); 868 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 869 mtx_init(&sc->rl_mtx, 870 device_get_nameunit(dev), 871 MTX_NETWORK_LOCK, MTX_DEF); 872 RL_LOCK(sc); 873 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 874 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 875 RL_UNLOCK(sc); 876 mtx_destroy(&sc->rl_mtx); 877 878 /* Don't attach to 8139C+ or 8169/8110 chips. */ 879 if (hwrev == RL_HWREV_8139CPLUS || 880 hwrev == RL_HWREV_8169 || 881 hwrev == RL_HWREV_8169S || 882 hwrev == RL_HWREV_8110S) { 883 t++; 884 continue; 885 } 886 887 device_set_desc(dev, t->rl_name); 888 return(0); 889 } 890 t++; 891 } 892 893 return(ENXIO); 894} 895 896/* 897 * Attach the interface. Allocate softc structures, do ifmedia 898 * setup and ethernet/BPF attach. 899 */ 900static int 901rl_attach(dev) 902 device_t dev; 903{ 904 u_char eaddr[ETHER_ADDR_LEN]; 905 u_int16_t as[3]; 906 struct rl_softc *sc; 907 struct ifnet *ifp; 908 u_int16_t rl_did = 0; 909 struct rl_type *t; 910 int unit, error = 0, rid, i; 911 912 sc = device_get_softc(dev); 913 unit = device_get_unit(dev); 914 915 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 916 MTX_DEF | MTX_RECURSE); 917#ifndef BURN_BRIDGES 918 /* 919 * Handle power management nonsense. 920 */ 921 922 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 923 u_int32_t iobase, membase, irq; 924 925 /* Save important PCI config data. */ 926 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 927 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 928 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 929 930 /* Reset the power state. */ 931 printf("rl%d: chip is is in D%d power mode " 932 "-- setting to D0\n", unit, 933 pci_get_powerstate(dev)); 934 935 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 936 937 /* Restore PCI config data. */ 938 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 939 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 940 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 941 } 942#endif 943 /* 944 * Map control/status registers. 945 */ 946 pci_enable_busmaster(dev); 947 948 rid = RL_RID; 949 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 950 0, ~0, 1, RF_ACTIVE); 951 952 if (sc->rl_res == NULL) { 953 printf ("rl%d: couldn't map ports/memory\n", unit); 954 error = ENXIO; 955 goto fail; 956 } 957 958#ifdef notdef 959 /* Detect the Realtek 8139B. For some reason, this chip is very 960 * unstable when left to autoselect the media 961 * The best workaround is to set the device to the required 962 * media type or to set it to the 10 Meg speed. 963 */ 964 965 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 966 printf("rl%d: Realtek 8139B detected. Warning, " 967 "this may be unstable in autoselect mode\n", unit); 968 } 969#endif 970 971 sc->rl_btag = rman_get_bustag(sc->rl_res); 972 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 973 974 /* Allocate interrupt */ 975 rid = 0; 976 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 977 RF_SHAREABLE | RF_ACTIVE); 978 979 if (sc->rl_irq == NULL) { 980 printf("rl%d: couldn't map interrupt\n", unit); 981 error = ENXIO; 982 goto fail; 983 } 984 985 /* Reset the adapter. */ 986 rl_reset(sc); 987 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 988 rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 989 if (rl_did != 0x8129) 990 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 991 992 /* 993 * Get station address from the EEPROM. 994 */ 995 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 996 for (i = 0; i < 3; i++) { 997 eaddr[(i * 2) + 0] = as[i] & 0xff; 998 eaddr[(i * 2) + 1] = as[i] >> 8; 999 } 1000 1001 /* 1002 * A RealTek chip was detected. Inform the world. 1003 */ 1004 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1005 1006 sc->rl_unit = unit; 1007 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1008 1009 /* 1010 * Now read the exact device type from the EEPROM to find 1011 * out if it's an 8129 or 8139. 1012 */ 1013 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 1014 1015 t = rl_devs; 1016 sc->rl_type = 0; 1017 while(t->rl_name != NULL) { 1018 if (rl_did == t->rl_did) { 1019 sc->rl_type = t->rl_basetype; 1020 break; 1021 } 1022 t++; 1023 } 1024 1025 if (sc->rl_type == 0) { 1026 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 1027 error = ENXIO; 1028 goto fail; 1029 } 1030 1031 /* 1032 * Allocate the parent bus DMA tag appropriate for PCI. 1033 */ 1034#define RL_NSEG_NEW 32 1035 error = bus_dma_tag_create(NULL, /* parent */ 1036 1, 0, /* alignment, boundary */ 1037 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1038 BUS_SPACE_MAXADDR, /* highaddr */ 1039 NULL, NULL, /* filter, filterarg */ 1040 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1041 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1042 BUS_DMA_ALLOCNOW, /* flags */ 1043 NULL, NULL, /* lockfunc, lockarg */ 1044 &sc->rl_parent_tag); 1045 if (error) 1046 goto fail; 1047 1048 /* 1049 * Now allocate a tag for the DMA descriptor lists. 1050 * All of our lists are allocated as a contiguous block 1051 * of memory. 1052 */ 1053 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 1054 1, 0, /* alignment, boundary */ 1055 BUS_SPACE_MAXADDR, /* lowaddr */ 1056 BUS_SPACE_MAXADDR, /* highaddr */ 1057 NULL, NULL, /* filter, filterarg */ 1058 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 1059 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1060 BUS_DMA_ALLOCNOW, /* flags */ 1061 NULL, NULL, /* lockfunc, lockarg */ 1062 &sc->rl_tag); 1063 if (error) 1064 goto fail; 1065 1066 /* 1067 * Now allocate a chunk of DMA-able memory based on the 1068 * tag we just created. 1069 */ 1070 error = bus_dmamem_alloc(sc->rl_tag, 1071 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1072 &sc->rl_cdata.rl_rx_dmamap); 1073 1074 if (error) { 1075 printf("rl%d: no memory for list buffers!\n", unit); 1076 bus_dma_tag_destroy(sc->rl_tag); 1077 sc->rl_tag = NULL; 1078 goto fail; 1079 } 1080 1081 /* Leave a few bytes before the start of the RX ring buffer. */ 1082 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1083 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1084 1085 /* Do MII setup */ 1086 if (mii_phy_probe(dev, &sc->rl_miibus, 1087 rl_ifmedia_upd, rl_ifmedia_sts)) { 1088 printf("rl%d: MII without any phy!\n", sc->rl_unit); 1089 error = ENXIO; 1090 goto fail; 1091 } 1092 1093 ifp = &sc->arpcom.ac_if; 1094 ifp->if_softc = sc; 1095 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1096 ifp->if_mtu = ETHERMTU; 1097 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1098 ifp->if_ioctl = rl_ioctl; 1099 ifp->if_output = ether_output; 1100 ifp->if_start = rl_start; 1101 ifp->if_watchdog = rl_watchdog; 1102 ifp->if_init = rl_init; 1103 ifp->if_baudrate = 10000000; 1104 ifp->if_capabilities = IFCAP_VLAN_MTU; 1105 ifp->if_capenable = ifp->if_capabilities; 1106 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1107 1108 callout_handle_init(&sc->rl_stat_ch); 1109 1110 /* 1111 * Call MI attach routine. 1112 */ 1113 ether_ifattach(ifp, eaddr); 1114 1115 /* Hook interrupt last to avoid having to lock softc */ 1116 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1117 rl_intr, sc, &sc->rl_intrhand); 1118 1119 if (error) { 1120 printf("rl%d: couldn't set up irq\n", unit); 1121 ether_ifdetach(ifp); 1122 goto fail; 1123 } 1124 1125fail: 1126 if (error) 1127 rl_detach(dev); 1128 1129 return (error); 1130} 1131 1132/* 1133 * Shutdown hardware and free up resources. This can be called any 1134 * time after the mutex has been initialized. It is called in both 1135 * the error case in attach and the normal detach case so it needs 1136 * to be careful about only freeing resources that have actually been 1137 * allocated. 1138 */ 1139static int 1140rl_detach(dev) 1141 device_t dev; 1142{ 1143 struct rl_softc *sc; 1144 struct ifnet *ifp; 1145 1146 sc = device_get_softc(dev); 1147 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 1148 RL_LOCK(sc); 1149 ifp = &sc->arpcom.ac_if; 1150 1151 /* These should only be active if attach succeeded */ 1152 if (device_is_attached(dev)) { 1153 rl_stop(sc); 1154 ether_ifdetach(ifp); 1155 } 1156 if (sc->rl_miibus) 1157 device_delete_child(dev, sc->rl_miibus); 1158 bus_generic_detach(dev); 1159 1160 if (sc->rl_intrhand) 1161 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1162 if (sc->rl_irq) 1163 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1164 if (sc->rl_res) 1165 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1166 1167 if (sc->rl_tag) { 1168 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1169 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1170 sc->rl_cdata.rl_rx_dmamap); 1171 bus_dma_tag_destroy(sc->rl_tag); 1172 } 1173 if (sc->rl_parent_tag) 1174 bus_dma_tag_destroy(sc->rl_parent_tag); 1175 1176 RL_UNLOCK(sc); 1177 mtx_destroy(&sc->rl_mtx); 1178 1179 return(0); 1180} 1181 1182/* 1183 * Initialize the transmit descriptors. 1184 */ 1185static int 1186rl_list_tx_init(sc) 1187 struct rl_softc *sc; 1188{ 1189 struct rl_chain_data *cd; 1190 int i; 1191 1192 cd = &sc->rl_cdata; 1193 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1194 cd->rl_tx_chain[i] = NULL; 1195 CSR_WRITE_4(sc, 1196 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1197 } 1198 1199 sc->rl_cdata.cur_tx = 0; 1200 sc->rl_cdata.last_tx = 0; 1201 1202 return(0); 1203} 1204 1205/* 1206 * A frame has been uploaded: pass the resulting mbuf chain up to 1207 * the higher level protocols. 1208 * 1209 * You know there's something wrong with a PCI bus-master chip design 1210 * when you have to use m_devget(). 1211 * 1212 * The receive operation is badly documented in the datasheet, so I'll 1213 * attempt to document it here. The driver provides a buffer area and 1214 * places its base address in the RX buffer start address register. 1215 * The chip then begins copying frames into the RX buffer. Each frame 1216 * is preceded by a 32-bit RX status word which specifies the length 1217 * of the frame and certain other status bits. Each frame (starting with 1218 * the status word) is also 32-bit aligned. The frame length is in the 1219 * first 16 bits of the status word; the lower 15 bits correspond with 1220 * the 'rx status register' mentioned in the datasheet. 1221 * 1222 * Note: to make the Alpha happy, the frame payload needs to be aligned 1223 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1224 * as the offset argument to m_devget(). 1225 */ 1226static void 1227rl_rxeof(sc) 1228 struct rl_softc *sc; 1229{ 1230 struct mbuf *m; 1231 struct ifnet *ifp; 1232 int total_len = 0; 1233 u_int32_t rxstat; 1234 caddr_t rxbufpos; 1235 int wrap = 0; 1236 u_int16_t cur_rx; 1237 u_int16_t limit; 1238 u_int16_t rx_bytes = 0, max_bytes; 1239 1240 ifp = &sc->arpcom.ac_if; 1241 1242 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1243 BUS_DMASYNC_POSTREAD); 1244 1245 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1246 1247 /* Do not try to read past this point. */ 1248 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1249 1250 if (limit < cur_rx) 1251 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1252 else 1253 max_bytes = limit - cur_rx; 1254 1255 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1256#ifdef DEVICE_POLLING 1257 if (ifp->if_flags & IFF_POLLING) { 1258 if (sc->rxcycles <= 0) 1259 break; 1260 sc->rxcycles--; 1261 } 1262#endif /* DEVICE_POLLING */ 1263 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1264 rxstat = le32toh(*(u_int32_t *)rxbufpos); 1265 1266 /* 1267 * Here's a totally undocumented fact for you. When the 1268 * RealTek chip is in the process of copying a packet into 1269 * RAM for you, the length will be 0xfff0. If you spot a 1270 * packet header with this value, you need to stop. The 1271 * datasheet makes absolutely no mention of this and 1272 * RealTek should be shot for this. 1273 */ 1274 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1275 break; 1276 1277 if (!(rxstat & RL_RXSTAT_RXOK)) { 1278 ifp->if_ierrors++; 1279 rl_init(sc); 1280 return; 1281 } 1282 1283 /* No errors; receive the packet. */ 1284 total_len = rxstat >> 16; 1285 rx_bytes += total_len + 4; 1286 1287 /* 1288 * XXX The RealTek chip includes the CRC with every 1289 * received frame, and there's no way to turn this 1290 * behavior off (at least, I can't find anything in 1291 * the manual that explains how to do it) so we have 1292 * to trim off the CRC manually. 1293 */ 1294 total_len -= ETHER_CRC_LEN; 1295 1296 /* 1297 * Avoid trying to read more bytes than we know 1298 * the chip has prepared for us. 1299 */ 1300 if (rx_bytes > max_bytes) 1301 break; 1302 1303 rxbufpos = sc->rl_cdata.rl_rx_buf + 1304 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1305 1306 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1307 rxbufpos = sc->rl_cdata.rl_rx_buf; 1308 1309 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1310 1311 if (total_len > wrap) { 1312 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1313 NULL); 1314 if (m == NULL) { 1315 ifp->if_ierrors++; 1316 } else { 1317 m_copyback(m, wrap, total_len - wrap, 1318 sc->rl_cdata.rl_rx_buf); 1319 } 1320 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1321 } else { 1322 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1323 NULL); 1324 if (m == NULL) { 1325 ifp->if_ierrors++; 1326 } 1327 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1328 } 1329 1330 /* 1331 * Round up to 32-bit boundary. 1332 */ 1333 cur_rx = (cur_rx + 3) & ~3; 1334 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1335 1336 if (m == NULL) 1337 continue; 1338 1339 ifp->if_ipackets++; 1340 (*ifp->if_input)(ifp, m); 1341 } 1342 1343 return; 1344} 1345 1346/* 1347 * A frame was downloaded to the chip. It's safe for us to clean up 1348 * the list buffers. 1349 */ 1350static void 1351rl_txeof(sc) 1352 struct rl_softc *sc; 1353{ 1354 struct ifnet *ifp; 1355 u_int32_t txstat; 1356 1357 ifp = &sc->arpcom.ac_if; 1358 1359 /* 1360 * Go through our tx list and free mbufs for those 1361 * frames that have been uploaded. 1362 */ 1363 do { 1364 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1365 if (!(txstat & (RL_TXSTAT_TX_OK| 1366 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1367 break; 1368 1369 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1370 1371 if (RL_LAST_TXMBUF(sc) != NULL) { 1372 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1373 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1374 m_freem(RL_LAST_TXMBUF(sc)); 1375 RL_LAST_TXMBUF(sc) = NULL; 1376 } 1377 if (txstat & RL_TXSTAT_TX_OK) 1378 ifp->if_opackets++; 1379 else { 1380 int oldthresh; 1381 ifp->if_oerrors++; 1382 if ((txstat & RL_TXSTAT_TXABRT) || 1383 (txstat & RL_TXSTAT_OUTOFWIN)) 1384 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1385 oldthresh = sc->rl_txthresh; 1386 /* error recovery */ 1387 rl_reset(sc); 1388 rl_init(sc); 1389 /* 1390 * If there was a transmit underrun, 1391 * bump the TX threshold. 1392 */ 1393 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1394 sc->rl_txthresh = oldthresh + 32; 1395 return; 1396 } 1397 RL_INC(sc->rl_cdata.last_tx); 1398 ifp->if_flags &= ~IFF_OACTIVE; 1399 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1400 1401 ifp->if_timer = 1402 (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5; 1403 1404 return; 1405} 1406 1407static void 1408rl_tick(xsc) 1409 void *xsc; 1410{ 1411 struct rl_softc *sc; 1412 struct mii_data *mii; 1413 1414 sc = xsc; 1415 RL_LOCK(sc); 1416 mii = device_get_softc(sc->rl_miibus); 1417 1418 mii_tick(mii); 1419 1420 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1421 RL_UNLOCK(sc); 1422 1423 return; 1424} 1425 1426#ifdef DEVICE_POLLING 1427static void 1428rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1429{ 1430 struct rl_softc *sc = ifp->if_softc; 1431 1432 RL_LOCK(sc); 1433 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1434 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1435 goto done; 1436 } 1437 1438 sc->rxcycles = count; 1439 rl_rxeof(sc); 1440 rl_txeof(sc); 1441 if (ifp->if_snd.ifq_head != NULL) 1442 rl_start(ifp); 1443 1444 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1445 u_int16_t status; 1446 1447 status = CSR_READ_2(sc, RL_ISR); 1448 if (status == 0xffff) 1449 goto done; 1450 if (status) 1451 CSR_WRITE_2(sc, RL_ISR, status); 1452 1453 /* 1454 * XXX check behaviour on receiver stalls. 1455 */ 1456 1457 if (status & RL_ISR_SYSTEM_ERR) { 1458 rl_reset(sc); 1459 rl_init(sc); 1460 } 1461 } 1462done: 1463 RL_UNLOCK(sc); 1464} 1465#endif /* DEVICE_POLLING */ 1466 1467static void 1468rl_intr(arg) 1469 void *arg; 1470{ 1471 struct rl_softc *sc; 1472 struct ifnet *ifp; 1473 u_int16_t status; 1474 1475 sc = arg; 1476 1477 if (sc->suspended) { 1478 return; 1479 } 1480 1481 RL_LOCK(sc); 1482 ifp = &sc->arpcom.ac_if; 1483 1484#ifdef DEVICE_POLLING 1485 if (ifp->if_flags & IFF_POLLING) 1486 goto done; 1487 if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 1488 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1489 rl_poll(ifp, 0, 1); 1490 goto done; 1491 } 1492#endif /* DEVICE_POLLING */ 1493 1494 for (;;) { 1495 1496 status = CSR_READ_2(sc, RL_ISR); 1497 /* If the card has gone away the read returns 0xffff. */ 1498 if (status == 0xffff) 1499 break; 1500 if (status) 1501 CSR_WRITE_2(sc, RL_ISR, status); 1502 1503 if ((status & RL_INTRS) == 0) 1504 break; 1505 1506 if (status & RL_ISR_RX_OK) 1507 rl_rxeof(sc); 1508 1509 if (status & RL_ISR_RX_ERR) 1510 rl_rxeof(sc); 1511 1512 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1513 rl_txeof(sc); 1514 1515 if (status & RL_ISR_SYSTEM_ERR) { 1516 rl_reset(sc); 1517 rl_init(sc); 1518 } 1519 1520 } 1521 1522 if (ifp->if_snd.ifq_head != NULL) 1523 rl_start(ifp); 1524 1525#ifdef DEVICE_POLLING 1526done: 1527#endif 1528 RL_UNLOCK(sc); 1529 1530 return; 1531} 1532 1533/* 1534 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1535 * pointers to the fragment pointers. 1536 */ 1537static int 1538rl_encap(sc, m_head) 1539 struct rl_softc *sc; 1540 struct mbuf *m_head; 1541{ 1542 struct mbuf *m_new = NULL; 1543 1544 /* 1545 * The RealTek is brain damaged and wants longword-aligned 1546 * TX buffers, plus we can only have one fragment buffer 1547 * per packet. We have to copy pretty much all the time. 1548 */ 1549 m_new = m_defrag(m_head, M_DONTWAIT); 1550 1551 if (m_new == NULL) { 1552 m_freem(m_head); 1553 return(1); 1554 } 1555 m_head = m_new; 1556 1557 /* Pad frames to at least 60 bytes. */ 1558 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1559 /* 1560 * Make security concious people happy: zero out the 1561 * bytes in the pad area, since we don't know what 1562 * this mbuf cluster buffer's previous user might 1563 * have left in it. 1564 */ 1565 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1566 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1567 m_head->m_pkthdr.len += 1568 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1569 m_head->m_len = m_head->m_pkthdr.len; 1570 } 1571 1572 RL_CUR_TXMBUF(sc) = m_head; 1573 1574 return(0); 1575} 1576 1577/* 1578 * Main transmit routine. 1579 */ 1580 1581static void 1582rl_start(ifp) 1583 struct ifnet *ifp; 1584{ 1585 struct rl_softc *sc; 1586 struct mbuf *m_head = NULL; 1587 1588 sc = ifp->if_softc; 1589 RL_LOCK(sc); 1590 1591 while(RL_CUR_TXMBUF(sc) == NULL) { 1592 IF_DEQUEUE(&ifp->if_snd, m_head); 1593 if (m_head == NULL) 1594 break; 1595 1596 if (rl_encap(sc, m_head)) { 1597 break; 1598 } 1599 1600 /* 1601 * If there's a BPF listener, bounce a copy of this frame 1602 * to him. 1603 */ 1604 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1605 1606 /* 1607 * Transmit the frame. 1608 */ 1609 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1610 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1611 mtod(RL_CUR_TXMBUF(sc), void *), 1612 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 1613 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1614 BUS_DMASYNC_PREREAD); 1615 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1616 RL_TXTHRESH(sc->rl_txthresh) | 1617 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1618 1619 RL_INC(sc->rl_cdata.cur_tx); 1620 1621 /* 1622 * Set a timeout in case the chip goes out to lunch. 1623 */ 1624 ifp->if_timer = 5; 1625 } 1626 1627 /* 1628 * We broke out of the loop because all our TX slots are 1629 * full. Mark the NIC as busy until it drains some of the 1630 * packets from the queue. 1631 */ 1632 if (RL_CUR_TXMBUF(sc) != NULL) 1633 ifp->if_flags |= IFF_OACTIVE; 1634 1635 RL_UNLOCK(sc); 1636 1637 return; 1638} 1639 1640static void 1641rl_init(xsc) 1642 void *xsc; 1643{ 1644 struct rl_softc *sc = xsc; 1645 struct ifnet *ifp = &sc->arpcom.ac_if; 1646 struct mii_data *mii; 1647 u_int32_t rxcfg = 0; 1648 1649 RL_LOCK(sc); 1650 mii = device_get_softc(sc->rl_miibus); 1651 1652 /* 1653 * Cancel pending I/O and free all RX/TX buffers. 1654 */ 1655 rl_stop(sc); 1656 1657 /* 1658 * Init our MAC address. Even though the chipset 1659 * documentation doesn't mention it, we need to enter "Config 1660 * register write enable" mode to modify the ID registers. 1661 */ 1662 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1663 CSR_WRITE_STREAM_4(sc, RL_IDR0, 1664 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1665 CSR_WRITE_STREAM_4(sc, RL_IDR4, 1666 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1667 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1668 1669 /* Init the RX buffer pointer register. */ 1670 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1671 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 1672 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1673 BUS_DMASYNC_PREWRITE); 1674 1675 /* Init TX descriptors. */ 1676 rl_list_tx_init(sc); 1677 1678 /* 1679 * Enable transmit and receive. 1680 */ 1681 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1682 1683 /* 1684 * Set the initial TX and RX configuration. 1685 */ 1686 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1687 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1688 1689 /* Set the individual bit to receive frames for this host only. */ 1690 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1691 rxcfg |= RL_RXCFG_RX_INDIV; 1692 1693 /* If we want promiscuous mode, set the allframes bit. */ 1694 if (ifp->if_flags & IFF_PROMISC) { 1695 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1696 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1697 } else { 1698 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1699 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1700 } 1701 1702 /* 1703 * Set capture broadcast bit to capture broadcast frames. 1704 */ 1705 if (ifp->if_flags & IFF_BROADCAST) { 1706 rxcfg |= RL_RXCFG_RX_BROAD; 1707 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1708 } else { 1709 rxcfg &= ~RL_RXCFG_RX_BROAD; 1710 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1711 } 1712 1713 /* 1714 * Program the multicast filter, if necessary. 1715 */ 1716 rl_setmulti(sc); 1717 1718#ifdef DEVICE_POLLING 1719 /* 1720 * Disable interrupts if we are polling. 1721 */ 1722 if (ifp->if_flags & IFF_POLLING) 1723 CSR_WRITE_2(sc, RL_IMR, 0); 1724 else /* otherwise ... */ 1725#endif /* DEVICE_POLLING */ 1726 /* 1727 * Enable interrupts. 1728 */ 1729 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1730 1731 /* Set initial TX threshold */ 1732 sc->rl_txthresh = RL_TX_THRESH_INIT; 1733 1734 /* Start RX/TX process. */ 1735 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1736 1737 /* Enable receiver and transmitter. */ 1738 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1739 1740 mii_mediachg(mii); 1741 1742 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1743 1744 ifp->if_flags |= IFF_RUNNING; 1745 ifp->if_flags &= ~IFF_OACTIVE; 1746 1747 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1748 RL_UNLOCK(sc); 1749 1750 return; 1751} 1752 1753/* 1754 * Set media options. 1755 */ 1756static int 1757rl_ifmedia_upd(ifp) 1758 struct ifnet *ifp; 1759{ 1760 struct rl_softc *sc; 1761 struct mii_data *mii; 1762 1763 sc = ifp->if_softc; 1764 mii = device_get_softc(sc->rl_miibus); 1765 mii_mediachg(mii); 1766 1767 return(0); 1768} 1769 1770/* 1771 * Report current media status. 1772 */ 1773static void 1774rl_ifmedia_sts(ifp, ifmr) 1775 struct ifnet *ifp; 1776 struct ifmediareq *ifmr; 1777{ 1778 struct rl_softc *sc; 1779 struct mii_data *mii; 1780 1781 sc = ifp->if_softc; 1782 mii = device_get_softc(sc->rl_miibus); 1783 1784 mii_pollstat(mii); 1785 ifmr->ifm_active = mii->mii_media_active; 1786 ifmr->ifm_status = mii->mii_media_status; 1787 1788 return; 1789} 1790 1791static int 1792rl_ioctl(ifp, command, data) 1793 struct ifnet *ifp; 1794 u_long command; 1795 caddr_t data; 1796{ 1797 struct rl_softc *sc = ifp->if_softc; 1798 struct ifreq *ifr = (struct ifreq *) data; 1799 struct mii_data *mii; 1800 int error = 0; 1801 1802 RL_LOCK(sc); 1803 1804 switch(command) { 1805 case SIOCSIFFLAGS: 1806 if (ifp->if_flags & IFF_UP) { 1807 rl_init(sc); 1808 } else { 1809 if (ifp->if_flags & IFF_RUNNING) 1810 rl_stop(sc); 1811 } 1812 error = 0; 1813 break; 1814 case SIOCADDMULTI: 1815 case SIOCDELMULTI: 1816 rl_setmulti(sc); 1817 error = 0; 1818 break; 1819 case SIOCGIFMEDIA: 1820 case SIOCSIFMEDIA: 1821 mii = device_get_softc(sc->rl_miibus); 1822 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1823 break; 1824 default: 1825 error = ether_ioctl(ifp, command, data); 1826 break; 1827 } 1828 1829 RL_UNLOCK(sc); 1830 1831 return(error); 1832} 1833 1834static void 1835rl_watchdog(ifp) 1836 struct ifnet *ifp; 1837{ 1838 struct rl_softc *sc; 1839 1840 sc = ifp->if_softc; 1841 RL_LOCK(sc); 1842 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1843 ifp->if_oerrors++; 1844 1845 rl_txeof(sc); 1846 rl_rxeof(sc); 1847 rl_init(sc); 1848 RL_UNLOCK(sc); 1849 1850 return; 1851} 1852 1853/* 1854 * Stop the adapter and free any mbufs allocated to the 1855 * RX and TX lists. 1856 */ 1857static void 1858rl_stop(sc) 1859 struct rl_softc *sc; 1860{ 1861 register int i; 1862 struct ifnet *ifp; 1863 1864 RL_LOCK(sc); 1865 ifp = &sc->arpcom.ac_if; 1866 ifp->if_timer = 0; 1867 1868 untimeout(rl_tick, sc, sc->rl_stat_ch); 1869 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1870#ifdef DEVICE_POLLING 1871 ether_poll_deregister(ifp); 1872#endif /* DEVICE_POLLING */ 1873 1874 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1875 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1876 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1877 1878 /* 1879 * Free the TX list buffers. 1880 */ 1881 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1882 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1883 bus_dmamap_unload(sc->rl_tag, 1884 sc->rl_cdata.rl_tx_dmamap[i]); 1885 bus_dmamap_destroy(sc->rl_tag, 1886 sc->rl_cdata.rl_tx_dmamap[i]); 1887 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1888 sc->rl_cdata.rl_tx_chain[i] = NULL; 1889 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1890 } 1891 } 1892 1893 RL_UNLOCK(sc); 1894 return; 1895} 1896 1897/* 1898 * Device suspend routine. Stop the interface and save some PCI 1899 * settings in case the BIOS doesn't restore them properly on 1900 * resume. 1901 */ 1902static int 1903rl_suspend(dev) 1904 device_t dev; 1905{ 1906 register int i; 1907 struct rl_softc *sc; 1908 1909 sc = device_get_softc(dev); 1910 1911 rl_stop(sc); 1912 1913 for (i = 0; i < 5; i++) 1914 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 1915 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1916 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1917 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1918 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1919 1920 sc->suspended = 1; 1921 1922 return (0); 1923} 1924 1925/* 1926 * Device resume routine. Restore some PCI settings in case the BIOS 1927 * doesn't, re-enable busmastering, and restart the interface if 1928 * appropriate. 1929 */ 1930static int 1931rl_resume(dev) 1932 device_t dev; 1933{ 1934 register int i; 1935 struct rl_softc *sc; 1936 struct ifnet *ifp; 1937 1938 sc = device_get_softc(dev); 1939 ifp = &sc->arpcom.ac_if; 1940 1941 /* better way to do this? */ 1942 for (i = 0; i < 5; i++) 1943 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 1944 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1945 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1946 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1947 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1948 1949 /* reenable busmastering */ 1950 pci_enable_busmaster(dev); 1951 pci_enable_io(dev, RL_RES); 1952 1953 /* reinitialize interface if necessary */ 1954 if (ifp->if_flags & IFF_UP) 1955 rl_init(sc); 1956 1957 sc->suspended = 0; 1958 1959 return (0); 1960} 1961 1962/* 1963 * Stop all chip I/O so that the kernel's probe routines don't 1964 * get confused by errant DMAs when rebooting. 1965 */ 1966static void 1967rl_shutdown(dev) 1968 device_t dev; 1969{ 1970 struct rl_softc *sc; 1971 1972 sc = device_get_softc(dev); 1973 1974 rl_stop(sc); 1975 1976 return; 1977} 1978