if_rl.c revision 112379
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * RealTek 8129/8139 PCI NIC driver 35 * 36 * Supports several extremely cheap PCI 10/100 adapters based on 37 * the RealTek chipset. Datasheets can be obtained from 38 * www.realtek.com.tw. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 47 * probably the worst PCI ethernet controller ever made, with the possible 48 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 49 * DMA, but it has a terrible interface that nullifies any performance 50 * gains that bus-master DMA usually offers. 51 * 52 * For transmission, the chip offers a series of four TX descriptor 53 * registers. Each transmit frame must be in a contiguous buffer, aligned 54 * on a longword (32-bit) boundary. This means we almost always have to 55 * do mbuf copies in order to transmit a frame, except in the unlikely 56 * case where a) the packet fits into a single mbuf, and b) the packet 57 * is 32-bit aligned within the mbuf's data area. The presence of only 58 * four descriptor registers means that we can never have more than four 59 * packets queued for transmission at any one time. 60 * 61 * Reception is not much better. The driver has to allocate a single large 62 * buffer area (up to 64K in size) into which the chip will DMA received 63 * frames. Because we don't know where within this region received packets 64 * will begin or end, we have no choice but to copy data from the buffer 65 * area into mbufs in order to pass the packets up to the higher protocol 66 * levels. 67 * 68 * It's impossible given this rotten design to really achieve decent 69 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 70 * some equally overmuscled CPU to drive it. 71 * 72 * On the bright side, the 8139 does have a built-in PHY, although 73 * rather than using an MDIO serial interface like most other NICs, the 74 * PHY registers are directly accessible through the 8139's register 75 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 76 * filter. 77 * 78 * The 8129 chip is an older version of the 8139 that uses an external PHY 79 * chip. The 8129 has a serial MDIO interface for accessing the MII where 80 * the 8139 lets you directly access the on-board PHY registers. We need 81 * to select which interface to use depending on the chip type. 82 */ 83 84#include <sys/param.h> 85#include <sys/endian.h> 86#include <sys/systm.h> 87#include <sys/sockio.h> 88#include <sys/mbuf.h> 89#include <sys/malloc.h> 90#include <sys/kernel.h> 91#include <sys/socket.h> 92 93#include <net/if.h> 94#include <net/if_arp.h> 95#include <net/ethernet.h> 96#include <net/if_dl.h> 97#include <net/if_media.h> 98 99#include <net/bpf.h> 100 101#include <machine/bus_pio.h> 102#include <machine/bus_memio.h> 103#include <machine/bus.h> 104#include <machine/resource.h> 105#include <sys/bus.h> 106#include <sys/rman.h> 107 108#include <dev/mii/mii.h> 109#include <dev/mii/miivar.h> 110 111#include <pci/pcireg.h> 112#include <pci/pcivar.h> 113 114MODULE_DEPEND(rl, miibus, 1, 1, 1); 115 116/* "controller miibus0" required. See GENERIC if you get errors here. */ 117#include "miibus_if.h" 118 119/* 120 * Default to using PIO access for this driver. On SMP systems, 121 * there appear to be problems with memory mapped mode: it looks like 122 * doing too many memory mapped access back to back in rapid succession 123 * can hang the bus. I'm inclined to blame this on crummy design/construction 124 * on the part of RealTek. Memory mapped mode does appear to work on 125 * uniprocessor systems though. 126 */ 127#define RL_USEIOSPACE 128 129#include <pci/if_rlreg.h> 130 131__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 112379 2003-03-18 14:57:09Z sanpei $"); 132 133/* 134 * Various supported device vendors/types and their names. 135 */ 136static struct rl_type rl_devs[] = { 137 { RT_VENDORID, RT_DEVICEID_8129, 138 "RealTek 8129 10/100BaseTX" }, 139 { RT_VENDORID, RT_DEVICEID_8139, 140 "RealTek 8139 10/100BaseTX" }, 141 { RT_VENDORID, RT_DEVICEID_8138, 142 "RealTek 8139 10/100BaseTX CardBus" }, 143 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 144 "Accton MPX 5030/5038 10/100BaseTX" }, 145 { DELTA_VENDORID, DELTA_DEVICEID_8139, 146 "Delta Electronics 8139 10/100BaseTX" }, 147 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 148 "Addtron Technolgy 8139 10/100BaseTX" }, 149 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 150 "D-Link DFE-530TX+ 10/100BaseTX" }, 151 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, 152 "D-Link DFE-690TXD 10/100BaseTX" }, 153 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, 154 "Nortel Networks 10/100BaseTX" }, 155 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, 156 "Corega FEther CB-TXD" }, 157 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, 158 "Corega FEtherII CB-TXD" }, 159 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, 160 "Peppercon AG ROL-F" }, 161 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, 162 "Planex FNW-3800-TX" }, 163 { 0, 0, NULL } 164}; 165 166static int rl_probe (device_t); 167static int rl_attach (device_t); 168static int rl_detach (device_t); 169 170static int rl_encap (struct rl_softc *, struct mbuf * ); 171 172static void rl_rxeof (struct rl_softc *); 173static void rl_txeof (struct rl_softc *); 174static void rl_intr (void *); 175static void rl_tick (void *); 176static void rl_start (struct ifnet *); 177static int rl_ioctl (struct ifnet *, u_long, caddr_t); 178static void rl_init (void *); 179static void rl_stop (struct rl_softc *); 180static void rl_watchdog (struct ifnet *); 181static int rl_suspend (device_t); 182static int rl_resume (device_t); 183static void rl_shutdown (device_t); 184static int rl_ifmedia_upd (struct ifnet *); 185static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 186 187static void rl_eeprom_putbyte (struct rl_softc *, int); 188static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 189static void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 190static void rl_mii_sync (struct rl_softc *); 191static void rl_mii_send (struct rl_softc *, u_int32_t, int); 192static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 193static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 194 195static int rl_miibus_readreg (device_t, int, int); 196static int rl_miibus_writereg (device_t, int, int, int); 197static void rl_miibus_statchg (device_t); 198 199static u_int8_t rl_calchash (caddr_t); 200static void rl_setmulti (struct rl_softc *); 201static void rl_reset (struct rl_softc *); 202static int rl_list_tx_init (struct rl_softc *); 203 204static void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 205static void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 206 207#ifdef RL_USEIOSPACE 208#define RL_RES SYS_RES_IOPORT 209#define RL_RID RL_PCI_LOIO 210#else 211#define RL_RES SYS_RES_MEMORY 212#define RL_RID RL_PCI_LOMEM 213#endif 214 215static device_method_t rl_methods[] = { 216 /* Device interface */ 217 DEVMETHOD(device_probe, rl_probe), 218 DEVMETHOD(device_attach, rl_attach), 219 DEVMETHOD(device_detach, rl_detach), 220 DEVMETHOD(device_suspend, rl_suspend), 221 DEVMETHOD(device_resume, rl_resume), 222 DEVMETHOD(device_shutdown, rl_shutdown), 223 224 /* bus interface */ 225 DEVMETHOD(bus_print_child, bus_generic_print_child), 226 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 227 228 /* MII interface */ 229 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 230 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 231 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 232 233 { 0, 0 } 234}; 235 236static driver_t rl_driver = { 237 "rl", 238 rl_methods, 239 sizeof(struct rl_softc) 240}; 241 242static devclass_t rl_devclass; 243 244DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 245DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 246DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 247 248#define EE_SET(x) \ 249 CSR_WRITE_1(sc, RL_EECMD, \ 250 CSR_READ_1(sc, RL_EECMD) | x) 251 252#define EE_CLR(x) \ 253 CSR_WRITE_1(sc, RL_EECMD, \ 254 CSR_READ_1(sc, RL_EECMD) & ~x) 255 256static void 257rl_dma_map_rxbuf(arg, segs, nseg, error) 258 void *arg; 259 bus_dma_segment_t *segs; 260 int nseg, error; 261{ 262 struct rl_softc *sc; 263 264 sc = arg; 265 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 266 267 return; 268} 269 270static void 271rl_dma_map_txbuf(arg, segs, nseg, error) 272 void *arg; 273 bus_dma_segment_t *segs; 274 int nseg, error; 275{ 276 struct rl_softc *sc; 277 278 sc = arg; 279 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 280 281 return; 282} 283 284/* 285 * Send a read command and address to the EEPROM, check for ACK. 286 */ 287static void 288rl_eeprom_putbyte(sc, addr) 289 struct rl_softc *sc; 290 int addr; 291{ 292 register int d, i; 293 294 d = addr | sc->rl_eecmd_read; 295 296 /* 297 * Feed in each bit and strobe the clock. 298 */ 299 for (i = 0x400; i; i >>= 1) { 300 if (d & i) { 301 EE_SET(RL_EE_DATAIN); 302 } else { 303 EE_CLR(RL_EE_DATAIN); 304 } 305 DELAY(100); 306 EE_SET(RL_EE_CLK); 307 DELAY(150); 308 EE_CLR(RL_EE_CLK); 309 DELAY(100); 310 } 311 312 return; 313} 314 315/* 316 * Read a word of data stored in the EEPROM at address 'addr.' 317 */ 318static void 319rl_eeprom_getword(sc, addr, dest) 320 struct rl_softc *sc; 321 int addr; 322 u_int16_t *dest; 323{ 324 register int i; 325 u_int16_t word = 0; 326 327 /* Enter EEPROM access mode. */ 328 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 329 330 /* 331 * Send address of word we want to read. 332 */ 333 rl_eeprom_putbyte(sc, addr); 334 335 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 336 337 /* 338 * Start reading bits from EEPROM. 339 */ 340 for (i = 0x8000; i; i >>= 1) { 341 EE_SET(RL_EE_CLK); 342 DELAY(100); 343 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 344 word |= i; 345 EE_CLR(RL_EE_CLK); 346 DELAY(100); 347 } 348 349 /* Turn off EEPROM access mode. */ 350 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 351 352 *dest = word; 353 354 return; 355} 356 357/* 358 * Read a sequence of words from the EEPROM. 359 */ 360static void 361rl_read_eeprom(sc, dest, off, cnt, swap) 362 struct rl_softc *sc; 363 caddr_t dest; 364 int off; 365 int cnt; 366 int swap; 367{ 368 int i; 369 u_int16_t word = 0, *ptr; 370 371 for (i = 0; i < cnt; i++) { 372 rl_eeprom_getword(sc, off + i, &word); 373 ptr = (u_int16_t *)(dest + (i * 2)); 374 if (swap) 375 *ptr = ntohs(word); 376 else 377 *ptr = word; 378 } 379 380 return; 381} 382 383 384/* 385 * MII access routines are provided for the 8129, which 386 * doesn't have a built-in PHY. For the 8139, we fake things 387 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 388 * direct access PHY registers. 389 */ 390#define MII_SET(x) \ 391 CSR_WRITE_1(sc, RL_MII, \ 392 CSR_READ_1(sc, RL_MII) | (x)) 393 394#define MII_CLR(x) \ 395 CSR_WRITE_1(sc, RL_MII, \ 396 CSR_READ_1(sc, RL_MII) & ~(x)) 397 398/* 399 * Sync the PHYs by setting data bit and strobing the clock 32 times. 400 */ 401static void 402rl_mii_sync(sc) 403 struct rl_softc *sc; 404{ 405 register int i; 406 407 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 408 409 for (i = 0; i < 32; i++) { 410 MII_SET(RL_MII_CLK); 411 DELAY(1); 412 MII_CLR(RL_MII_CLK); 413 DELAY(1); 414 } 415 416 return; 417} 418 419/* 420 * Clock a series of bits through the MII. 421 */ 422static void 423rl_mii_send(sc, bits, cnt) 424 struct rl_softc *sc; 425 u_int32_t bits; 426 int cnt; 427{ 428 int i; 429 430 MII_CLR(RL_MII_CLK); 431 432 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 433 if (bits & i) { 434 MII_SET(RL_MII_DATAOUT); 435 } else { 436 MII_CLR(RL_MII_DATAOUT); 437 } 438 DELAY(1); 439 MII_CLR(RL_MII_CLK); 440 DELAY(1); 441 MII_SET(RL_MII_CLK); 442 } 443} 444 445/* 446 * Read an PHY register through the MII. 447 */ 448static int 449rl_mii_readreg(sc, frame) 450 struct rl_softc *sc; 451 struct rl_mii_frame *frame; 452 453{ 454 int i, ack; 455 456 RL_LOCK(sc); 457 458 /* 459 * Set up frame for RX. 460 */ 461 frame->mii_stdelim = RL_MII_STARTDELIM; 462 frame->mii_opcode = RL_MII_READOP; 463 frame->mii_turnaround = 0; 464 frame->mii_data = 0; 465 466 CSR_WRITE_2(sc, RL_MII, 0); 467 468 /* 469 * Turn on data xmit. 470 */ 471 MII_SET(RL_MII_DIR); 472 473 rl_mii_sync(sc); 474 475 /* 476 * Send command/address info. 477 */ 478 rl_mii_send(sc, frame->mii_stdelim, 2); 479 rl_mii_send(sc, frame->mii_opcode, 2); 480 rl_mii_send(sc, frame->mii_phyaddr, 5); 481 rl_mii_send(sc, frame->mii_regaddr, 5); 482 483 /* Idle bit */ 484 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 485 DELAY(1); 486 MII_SET(RL_MII_CLK); 487 DELAY(1); 488 489 /* Turn off xmit. */ 490 MII_CLR(RL_MII_DIR); 491 492 /* Check for ack */ 493 MII_CLR(RL_MII_CLK); 494 DELAY(1); 495 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 496 MII_SET(RL_MII_CLK); 497 DELAY(1); 498 499 /* 500 * Now try reading data bits. If the ack failed, we still 501 * need to clock through 16 cycles to keep the PHY(s) in sync. 502 */ 503 if (ack) { 504 for(i = 0; i < 16; i++) { 505 MII_CLR(RL_MII_CLK); 506 DELAY(1); 507 MII_SET(RL_MII_CLK); 508 DELAY(1); 509 } 510 goto fail; 511 } 512 513 for (i = 0x8000; i; i >>= 1) { 514 MII_CLR(RL_MII_CLK); 515 DELAY(1); 516 if (!ack) { 517 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 518 frame->mii_data |= i; 519 DELAY(1); 520 } 521 MII_SET(RL_MII_CLK); 522 DELAY(1); 523 } 524 525fail: 526 527 MII_CLR(RL_MII_CLK); 528 DELAY(1); 529 MII_SET(RL_MII_CLK); 530 DELAY(1); 531 532 RL_UNLOCK(sc); 533 534 if (ack) 535 return(1); 536 return(0); 537} 538 539/* 540 * Write to a PHY register through the MII. 541 */ 542static int 543rl_mii_writereg(sc, frame) 544 struct rl_softc *sc; 545 struct rl_mii_frame *frame; 546 547{ 548 RL_LOCK(sc); 549 550 /* 551 * Set up frame for TX. 552 */ 553 554 frame->mii_stdelim = RL_MII_STARTDELIM; 555 frame->mii_opcode = RL_MII_WRITEOP; 556 frame->mii_turnaround = RL_MII_TURNAROUND; 557 558 /* 559 * Turn on data output. 560 */ 561 MII_SET(RL_MII_DIR); 562 563 rl_mii_sync(sc); 564 565 rl_mii_send(sc, frame->mii_stdelim, 2); 566 rl_mii_send(sc, frame->mii_opcode, 2); 567 rl_mii_send(sc, frame->mii_phyaddr, 5); 568 rl_mii_send(sc, frame->mii_regaddr, 5); 569 rl_mii_send(sc, frame->mii_turnaround, 2); 570 rl_mii_send(sc, frame->mii_data, 16); 571 572 /* Idle bit. */ 573 MII_SET(RL_MII_CLK); 574 DELAY(1); 575 MII_CLR(RL_MII_CLK); 576 DELAY(1); 577 578 /* 579 * Turn off xmit. 580 */ 581 MII_CLR(RL_MII_DIR); 582 583 RL_UNLOCK(sc); 584 585 return(0); 586} 587 588static int 589rl_miibus_readreg(dev, phy, reg) 590 device_t dev; 591 int phy, reg; 592{ 593 struct rl_softc *sc; 594 struct rl_mii_frame frame; 595 u_int16_t rval = 0; 596 u_int16_t rl8139_reg = 0; 597 598 sc = device_get_softc(dev); 599 RL_LOCK(sc); 600 601 if (sc->rl_type == RL_8139) { 602 /* Pretend the internal PHY is only at address 0 */ 603 if (phy) { 604 RL_UNLOCK(sc); 605 return(0); 606 } 607 switch(reg) { 608 case MII_BMCR: 609 rl8139_reg = RL_BMCR; 610 break; 611 case MII_BMSR: 612 rl8139_reg = RL_BMSR; 613 break; 614 case MII_ANAR: 615 rl8139_reg = RL_ANAR; 616 break; 617 case MII_ANER: 618 rl8139_reg = RL_ANER; 619 break; 620 case MII_ANLPAR: 621 rl8139_reg = RL_LPAR; 622 break; 623 case MII_PHYIDR1: 624 case MII_PHYIDR2: 625 RL_UNLOCK(sc); 626 return(0); 627 break; 628 /* 629 * Allow the rlphy driver to read the media status 630 * register. If we have a link partner which does not 631 * support NWAY, this is the register which will tell 632 * us the results of parallel detection. 633 */ 634 case RL_MEDIASTAT: 635 rval = CSR_READ_1(sc, RL_MEDIASTAT); 636 RL_UNLOCK(sc); 637 return(rval); 638 break; 639 default: 640 printf("rl%d: bad phy register\n", sc->rl_unit); 641 RL_UNLOCK(sc); 642 return(0); 643 } 644 rval = CSR_READ_2(sc, rl8139_reg); 645 RL_UNLOCK(sc); 646 return(rval); 647 } 648 649 bzero((char *)&frame, sizeof(frame)); 650 651 frame.mii_phyaddr = phy; 652 frame.mii_regaddr = reg; 653 rl_mii_readreg(sc, &frame); 654 RL_UNLOCK(sc); 655 656 return(frame.mii_data); 657} 658 659static int 660rl_miibus_writereg(dev, phy, reg, data) 661 device_t dev; 662 int phy, reg, data; 663{ 664 struct rl_softc *sc; 665 struct rl_mii_frame frame; 666 u_int16_t rl8139_reg = 0; 667 668 sc = device_get_softc(dev); 669 RL_LOCK(sc); 670 671 if (sc->rl_type == RL_8139) { 672 /* Pretend the internal PHY is only at address 0 */ 673 if (phy) { 674 RL_UNLOCK(sc); 675 return(0); 676 } 677 switch(reg) { 678 case MII_BMCR: 679 rl8139_reg = RL_BMCR; 680 break; 681 case MII_BMSR: 682 rl8139_reg = RL_BMSR; 683 break; 684 case MII_ANAR: 685 rl8139_reg = RL_ANAR; 686 break; 687 case MII_ANER: 688 rl8139_reg = RL_ANER; 689 break; 690 case MII_ANLPAR: 691 rl8139_reg = RL_LPAR; 692 break; 693 case MII_PHYIDR1: 694 case MII_PHYIDR2: 695 RL_UNLOCK(sc); 696 return(0); 697 break; 698 default: 699 printf("rl%d: bad phy register\n", sc->rl_unit); 700 RL_UNLOCK(sc); 701 return(0); 702 } 703 CSR_WRITE_2(sc, rl8139_reg, data); 704 RL_UNLOCK(sc); 705 return(0); 706 } 707 708 bzero((char *)&frame, sizeof(frame)); 709 710 frame.mii_phyaddr = phy; 711 frame.mii_regaddr = reg; 712 frame.mii_data = data; 713 714 rl_mii_writereg(sc, &frame); 715 716 RL_UNLOCK(sc); 717 return(0); 718} 719 720static void 721rl_miibus_statchg(dev) 722 device_t dev; 723{ 724 return; 725} 726 727/* 728 * Calculate CRC of a multicast group address, return the upper 6 bits. 729 */ 730static u_int8_t 731rl_calchash(addr) 732 caddr_t addr; 733{ 734 u_int32_t crc, carry; 735 int i, j; 736 u_int8_t c; 737 738 /* Compute CRC for the address value. */ 739 crc = 0xFFFFFFFF; /* initial value */ 740 741 for (i = 0; i < 6; i++) { 742 c = *(addr + i); 743 for (j = 0; j < 8; j++) { 744 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 745 crc <<= 1; 746 c >>= 1; 747 if (carry) 748 crc = (crc ^ 0x04c11db6) | carry; 749 } 750 } 751 752 /* return the filter bit position */ 753 return(crc >> 26); 754} 755 756/* 757 * Program the 64-bit multicast hash filter. 758 */ 759static void 760rl_setmulti(sc) 761 struct rl_softc *sc; 762{ 763 struct ifnet *ifp; 764 int h = 0; 765 u_int32_t hashes[2] = { 0, 0 }; 766 struct ifmultiaddr *ifma; 767 u_int32_t rxfilt; 768 int mcnt = 0; 769 770 ifp = &sc->arpcom.ac_if; 771 772 rxfilt = CSR_READ_4(sc, RL_RXCFG); 773 774 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 775 rxfilt |= RL_RXCFG_RX_MULTI; 776 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 777 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 778 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 779 return; 780 } 781 782 /* first, zot all the existing hash bits */ 783 CSR_WRITE_4(sc, RL_MAR0, 0); 784 CSR_WRITE_4(sc, RL_MAR4, 0); 785 786 /* now program new ones */ 787 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 788 if (ifma->ifma_addr->sa_family != AF_LINK) 789 continue; 790 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 791 if (h < 32) 792 hashes[0] |= (1 << h); 793 else 794 hashes[1] |= (1 << (h - 32)); 795 mcnt++; 796 } 797 798 if (mcnt) 799 rxfilt |= RL_RXCFG_RX_MULTI; 800 else 801 rxfilt &= ~RL_RXCFG_RX_MULTI; 802 803 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 804 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 805 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 806 807 return; 808} 809 810static void 811rl_reset(sc) 812 struct rl_softc *sc; 813{ 814 register int i; 815 816 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 817 818 for (i = 0; i < RL_TIMEOUT; i++) { 819 DELAY(10); 820 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 821 break; 822 } 823 if (i == RL_TIMEOUT) 824 printf("rl%d: reset never completed!\n", sc->rl_unit); 825 826 return; 827} 828 829/* 830 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 831 * IDs against our list and return a device name if we find a match. 832 */ 833static int 834rl_probe(dev) 835 device_t dev; 836{ 837 struct rl_type *t; 838 839 t = rl_devs; 840 841 while(t->rl_name != NULL) { 842 if ((pci_get_vendor(dev) == t->rl_vid) && 843 (pci_get_device(dev) == t->rl_did)) { 844 device_set_desc(dev, t->rl_name); 845 return(0); 846 } 847 t++; 848 } 849 850 return(ENXIO); 851} 852 853/* 854 * Attach the interface. Allocate softc structures, do ifmedia 855 * setup and ethernet/BPF attach. 856 */ 857static int 858rl_attach(dev) 859 device_t dev; 860{ 861 u_char eaddr[ETHER_ADDR_LEN]; 862 u_int32_t command; 863 u_int16_t as[3]; 864 struct rl_softc *sc; 865 struct ifnet *ifp; 866 u_int16_t rl_did = 0; 867 int unit, error = 0, rid, i; 868 869 sc = device_get_softc(dev); 870 unit = device_get_unit(dev); 871 bzero(sc, sizeof(struct rl_softc)); 872 873 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 874 MTX_DEF | MTX_RECURSE); 875 876 /* 877 * Handle power management nonsense. 878 */ 879 880 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 881 u_int32_t iobase, membase, irq; 882 883 /* Save important PCI config data. */ 884 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 885 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 886 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 887 888 /* Reset the power state. */ 889 printf("rl%d: chip is is in D%d power mode " 890 "-- setting to D0\n", unit, 891 pci_get_powerstate(dev)); 892 893 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 894 895 /* Restore PCI config data. */ 896 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 897 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 898 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 899 } 900 901 /* 902 * Map control/status registers. 903 */ 904 pci_enable_busmaster(dev); 905 pci_enable_io(dev, SYS_RES_IOPORT); 906 pci_enable_io(dev, SYS_RES_MEMORY); 907 command = pci_read_config(dev, PCIR_COMMAND, 4); 908 909#ifdef RL_USEIOSPACE 910 if (!(command & PCIM_CMD_PORTEN)) { 911 printf("rl%d: failed to enable I/O ports!\n", unit); 912 error = ENXIO; 913 goto fail; 914 } 915#else 916 if (!(command & PCIM_CMD_MEMEN)) { 917 printf("rl%d: failed to enable memory mapping!\n", unit); 918 error = ENXIO; 919 goto fail; 920 } 921#endif 922 923 rid = RL_RID; 924 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 925 0, ~0, 1, RF_ACTIVE); 926 927 if (sc->rl_res == NULL) { 928 printf ("rl%d: couldn't map ports/memory\n", unit); 929 error = ENXIO; 930 goto fail; 931 } 932 933 /* Detect the Realtek 8139B. For some reason, this chip is very 934 * unstable when left to autoselect the media 935 * The best workaround is to set the device to the required 936 * media type or to set it to the 10 Meg speed. 937 */ 938 939 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 940 printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit); 941 } 942 943 sc->rl_btag = rman_get_bustag(sc->rl_res); 944 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 945 946 rid = 0; 947 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 948 RF_SHAREABLE | RF_ACTIVE); 949 950 if (sc->rl_irq == NULL) { 951 printf("rl%d: couldn't map interrupt\n", unit); 952 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 953 error = ENXIO; 954 goto fail; 955 } 956 957 /* Reset the adapter. */ 958 rl_reset(sc); 959 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 960 rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 961 if (rl_did != 0x8129) 962 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 963 964 /* 965 * Get station address from the EEPROM. 966 */ 967 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 968 for (i = 0; i < 3; i++) { 969 eaddr[(i * 2) + 0] = as[i] & 0xff; 970 eaddr[(i * 2) + 1] = as[i] >> 8; 971 } 972 973 /* 974 * A RealTek chip was detected. Inform the world. 975 */ 976 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 977 978 sc->rl_unit = unit; 979 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 980 981 /* 982 * Now read the exact device type from the EEPROM to find 983 * out if it's an 8129 or 8139. 984 */ 985 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 986 987 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 988 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 989 rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS || 990 rl_did == DLINK_DEVICEID_690TXD || 991 rl_did == COREGA_DEVICEID_FETHERCBTXD || 992 rl_did == COREGA_DEVICEID_FETHERIICBTXD || 993 rl_did == PLANEX_DEVICEID_FNW3800TX) 994 sc->rl_type = RL_8139; 995 else if (rl_did == RT_DEVICEID_8129) 996 sc->rl_type = RL_8129; 997 else { 998 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 999 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1000 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1001 error = ENXIO; 1002 goto fail; 1003 } 1004 1005 /* 1006 * Allocate the parent bus DMA tag appropriate for PCI. 1007 */ 1008#define RL_NSEG_NEW 32 1009 error = bus_dma_tag_create(NULL, /* parent */ 1010 1, 0, /* alignment, boundary */ 1011 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1012 BUS_SPACE_MAXADDR, /* highaddr */ 1013 NULL, NULL, /* filter, filterarg */ 1014 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1015 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1016 BUS_DMA_ALLOCNOW, /* flags */ 1017 &sc->rl_parent_tag); 1018 1019 /* 1020 * Now allocate a tag for the DMA descriptor lists. 1021 * All of our lists are allocated as a contiguous block 1022 * of memory. 1023 */ 1024 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 1025 1, 0, /* alignment, boundary */ 1026 BUS_SPACE_MAXADDR, /* lowaddr */ 1027 BUS_SPACE_MAXADDR, /* highaddr */ 1028 NULL, NULL, /* filter, filterarg */ 1029 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 1030 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1031 0, /* flags */ 1032 &sc->rl_tag); 1033 1034 /* 1035 * Now allocate a chunk of DMA-able memory based on the 1036 * tag we just created. 1037 */ 1038 error = bus_dmamem_alloc(sc->rl_tag, 1039 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT, 1040 &sc->rl_cdata.rl_rx_dmamap); 1041 1042 if (sc->rl_cdata.rl_rx_buf == NULL) { 1043 printf("rl%d: no memory for list buffers!\n", unit); 1044 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1045 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1046 bus_dma_tag_destroy(sc->rl_tag); 1047 error = ENXIO; 1048 goto fail; 1049 } 1050 1051 /* Leave a few bytes before the start of the RX ring buffer. */ 1052 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1053 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1054 1055 /* Do MII setup */ 1056 if (mii_phy_probe(dev, &sc->rl_miibus, 1057 rl_ifmedia_upd, rl_ifmedia_sts)) { 1058 printf("rl%d: MII without any phy!\n", sc->rl_unit); 1059 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1060 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1061 bus_dmamem_free(sc->rl_tag, 1062 sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap); 1063 bus_dma_tag_destroy(sc->rl_tag); 1064 error = ENXIO; 1065 goto fail; 1066 } 1067 1068 ifp = &sc->arpcom.ac_if; 1069 ifp->if_softc = sc; 1070 ifp->if_unit = unit; 1071 ifp->if_name = "rl"; 1072 ifp->if_mtu = ETHERMTU; 1073 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1074 ifp->if_ioctl = rl_ioctl; 1075 ifp->if_output = ether_output; 1076 ifp->if_start = rl_start; 1077 ifp->if_watchdog = rl_watchdog; 1078 ifp->if_init = rl_init; 1079 ifp->if_baudrate = 10000000; 1080 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1081 1082 /* 1083 * Call MI attach routine. 1084 */ 1085 ether_ifattach(ifp, eaddr); 1086 1087 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1088 rl_intr, sc, &sc->rl_intrhand); 1089 1090 if (error) { 1091 printf("rl%d: couldn't set up irq\n", unit); 1092 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1093 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1094 bus_dmamem_free(sc->rl_tag, 1095 sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap); 1096 bus_dma_tag_destroy(sc->rl_tag); 1097 goto fail; 1098 } 1099 1100 callout_handle_init(&sc->rl_stat_ch); 1101fail: 1102 if (error != 0) 1103 mtx_destroy(&sc->rl_mtx); 1104 return (error); 1105} 1106 1107static int 1108rl_detach(dev) 1109 device_t dev; 1110{ 1111 struct rl_softc *sc; 1112 struct ifnet *ifp; 1113 1114 sc = device_get_softc(dev); 1115 RL_LOCK(sc); 1116 ifp = &sc->arpcom.ac_if; 1117 1118 ether_ifdetach(ifp); 1119 rl_stop(sc); 1120 1121 bus_generic_detach(dev); 1122 device_delete_child(dev, sc->rl_miibus); 1123 1124 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1125 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1126 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1127 1128 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1129 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1130 sc->rl_cdata.rl_rx_dmamap); 1131 bus_dma_tag_destroy(sc->rl_tag); 1132 bus_dma_tag_destroy(sc->rl_parent_tag); 1133 1134 RL_UNLOCK(sc); 1135 mtx_destroy(&sc->rl_mtx); 1136 1137 return(0); 1138} 1139 1140/* 1141 * Initialize the transmit descriptors. 1142 */ 1143static int 1144rl_list_tx_init(sc) 1145 struct rl_softc *sc; 1146{ 1147 struct rl_chain_data *cd; 1148 int i; 1149 1150 cd = &sc->rl_cdata; 1151 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1152 cd->rl_tx_chain[i] = NULL; 1153 CSR_WRITE_4(sc, 1154 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1155 } 1156 1157 sc->rl_cdata.cur_tx = 0; 1158 sc->rl_cdata.last_tx = 0; 1159 1160 return(0); 1161} 1162 1163/* 1164 * A frame has been uploaded: pass the resulting mbuf chain up to 1165 * the higher level protocols. 1166 * 1167 * You know there's something wrong with a PCI bus-master chip design 1168 * when you have to use m_devget(). 1169 * 1170 * The receive operation is badly documented in the datasheet, so I'll 1171 * attempt to document it here. The driver provides a buffer area and 1172 * places its base address in the RX buffer start address register. 1173 * The chip then begins copying frames into the RX buffer. Each frame 1174 * is preceded by a 32-bit RX status word which specifies the length 1175 * of the frame and certain other status bits. Each frame (starting with 1176 * the status word) is also 32-bit aligned. The frame length is in the 1177 * first 16 bits of the status word; the lower 15 bits correspond with 1178 * the 'rx status register' mentioned in the datasheet. 1179 * 1180 * Note: to make the Alpha happy, the frame payload needs to be aligned 1181 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1182 * as the offset argument to m_devget(). 1183 */ 1184static void 1185rl_rxeof(sc) 1186 struct rl_softc *sc; 1187{ 1188 struct mbuf *m; 1189 struct ifnet *ifp; 1190 int total_len = 0; 1191 u_int32_t rxstat; 1192 caddr_t rxbufpos; 1193 int wrap = 0; 1194 u_int16_t cur_rx; 1195 u_int16_t limit; 1196 u_int16_t rx_bytes = 0, max_bytes; 1197 1198 ifp = &sc->arpcom.ac_if; 1199 1200 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1201 BUS_DMASYNC_POSTREAD); 1202 1203 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1204 1205 /* Do not try to read past this point. */ 1206 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1207 1208 if (limit < cur_rx) 1209 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1210 else 1211 max_bytes = limit - cur_rx; 1212 1213 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1214#ifdef DEVICE_POLLING 1215 if (ifp->if_flags & IFF_POLLING) { 1216 if (sc->rxcycles <= 0) 1217 break; 1218 sc->rxcycles--; 1219 } 1220#endif /* DEVICE_POLLING */ 1221 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1222 rxstat = le32toh(*(u_int32_t *)rxbufpos); 1223 1224 /* 1225 * Here's a totally undocumented fact for you. When the 1226 * RealTek chip is in the process of copying a packet into 1227 * RAM for you, the length will be 0xfff0. If you spot a 1228 * packet header with this value, you need to stop. The 1229 * datasheet makes absolutely no mention of this and 1230 * RealTek should be shot for this. 1231 */ 1232 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1233 break; 1234 1235 if (!(rxstat & RL_RXSTAT_RXOK)) { 1236 ifp->if_ierrors++; 1237 rl_init(sc); 1238 return; 1239 } 1240 1241 /* No errors; receive the packet. */ 1242 total_len = rxstat >> 16; 1243 rx_bytes += total_len + 4; 1244 1245 /* 1246 * XXX The RealTek chip includes the CRC with every 1247 * received frame, and there's no way to turn this 1248 * behavior off (at least, I can't find anything in 1249 * the manual that explains how to do it) so we have 1250 * to trim off the CRC manually. 1251 */ 1252 total_len -= ETHER_CRC_LEN; 1253 1254 /* 1255 * Avoid trying to read more bytes than we know 1256 * the chip has prepared for us. 1257 */ 1258 if (rx_bytes > max_bytes) 1259 break; 1260 1261 rxbufpos = sc->rl_cdata.rl_rx_buf + 1262 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1263 1264 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1265 rxbufpos = sc->rl_cdata.rl_rx_buf; 1266 1267 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1268 1269 if (total_len > wrap) { 1270 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1271 NULL); 1272 if (m == NULL) { 1273 ifp->if_ierrors++; 1274 } else { 1275 m_copyback(m, wrap, total_len - wrap, 1276 sc->rl_cdata.rl_rx_buf); 1277 } 1278 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1279 } else { 1280 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1281 NULL); 1282 if (m == NULL) { 1283 ifp->if_ierrors++; 1284 } 1285 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1286 } 1287 1288 /* 1289 * Round up to 32-bit boundary. 1290 */ 1291 cur_rx = (cur_rx + 3) & ~3; 1292 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1293 1294 if (m == NULL) 1295 continue; 1296 1297 ifp->if_ipackets++; 1298 (*ifp->if_input)(ifp, m); 1299 } 1300 1301 return; 1302} 1303 1304/* 1305 * A frame was downloaded to the chip. It's safe for us to clean up 1306 * the list buffers. 1307 */ 1308static void 1309rl_txeof(sc) 1310 struct rl_softc *sc; 1311{ 1312 struct ifnet *ifp; 1313 u_int32_t txstat; 1314 1315 ifp = &sc->arpcom.ac_if; 1316 1317 /* 1318 * Go through our tx list and free mbufs for those 1319 * frames that have been uploaded. 1320 */ 1321 do { 1322 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1323 if (!(txstat & (RL_TXSTAT_TX_OK| 1324 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1325 break; 1326 1327 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1328 1329 if (RL_LAST_TXMBUF(sc) != NULL) { 1330 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1331 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1332 m_freem(RL_LAST_TXMBUF(sc)); 1333 RL_LAST_TXMBUF(sc) = NULL; 1334 } 1335 if (txstat & RL_TXSTAT_TX_OK) 1336 ifp->if_opackets++; 1337 else { 1338 int oldthresh; 1339 ifp->if_oerrors++; 1340 if ((txstat & RL_TXSTAT_TXABRT) || 1341 (txstat & RL_TXSTAT_OUTOFWIN)) 1342 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1343 oldthresh = sc->rl_txthresh; 1344 /* error recovery */ 1345 rl_reset(sc); 1346 rl_init(sc); 1347 /* 1348 * If there was a transmit underrun, 1349 * bump the TX threshold. 1350 */ 1351 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1352 sc->rl_txthresh = oldthresh + 32; 1353 return; 1354 } 1355 RL_INC(sc->rl_cdata.last_tx); 1356 ifp->if_flags &= ~IFF_OACTIVE; 1357 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1358 1359 ifp->if_timer = 1360 (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5; 1361 1362 return; 1363} 1364 1365static void 1366rl_tick(xsc) 1367 void *xsc; 1368{ 1369 struct rl_softc *sc; 1370 struct mii_data *mii; 1371 1372 sc = xsc; 1373 RL_LOCK(sc); 1374 mii = device_get_softc(sc->rl_miibus); 1375 1376 mii_tick(mii); 1377 1378 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1379 RL_UNLOCK(sc); 1380 1381 return; 1382} 1383 1384#ifdef DEVICE_POLLING 1385static void 1386rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1387{ 1388 struct rl_softc *sc = ifp->if_softc; 1389 1390 RL_LOCK(sc); 1391 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1392 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1393 goto done; 1394 } 1395 1396 sc->rxcycles = count; 1397 rl_rxeof(sc); 1398 rl_txeof(sc); 1399 if (ifp->if_snd.ifq_head != NULL) 1400 rl_start(ifp); 1401 1402 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1403 u_int16_t status; 1404 1405 status = CSR_READ_2(sc, RL_ISR); 1406 if (status == 0xffff) 1407 goto done; 1408 if (status) 1409 CSR_WRITE_2(sc, RL_ISR, status); 1410 1411 /* 1412 * XXX check behaviour on receiver stalls. 1413 */ 1414 1415 if (status & RL_ISR_SYSTEM_ERR) { 1416 rl_reset(sc); 1417 rl_init(sc); 1418 } 1419 } 1420done: 1421 RL_UNLOCK(sc); 1422} 1423#endif /* DEVICE_POLLING */ 1424 1425static void 1426rl_intr(arg) 1427 void *arg; 1428{ 1429 struct rl_softc *sc; 1430 struct ifnet *ifp; 1431 u_int16_t status; 1432 1433 sc = arg; 1434 1435 if (sc->suspended) { 1436 return; 1437 } 1438 1439 RL_LOCK(sc); 1440 ifp = &sc->arpcom.ac_if; 1441 1442#ifdef DEVICE_POLLING 1443 if (ifp->if_flags & IFF_POLLING) 1444 goto done; 1445 if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 1446 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1447 rl_poll(ifp, 0, 1); 1448 goto done; 1449 } 1450#endif /* DEVICE_POLLING */ 1451 1452 for (;;) { 1453 1454 status = CSR_READ_2(sc, RL_ISR); 1455 /* If the card has gone away the read returns 0xffff. */ 1456 if (status == 0xffff) 1457 break; 1458 if (status) 1459 CSR_WRITE_2(sc, RL_ISR, status); 1460 1461 if ((status & RL_INTRS) == 0) 1462 break; 1463 1464 if (status & RL_ISR_RX_OK) 1465 rl_rxeof(sc); 1466 1467 if (status & RL_ISR_RX_ERR) 1468 rl_rxeof(sc); 1469 1470 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1471 rl_txeof(sc); 1472 1473 if (status & RL_ISR_SYSTEM_ERR) { 1474 rl_reset(sc); 1475 rl_init(sc); 1476 } 1477 1478 } 1479 1480 if (ifp->if_snd.ifq_head != NULL) 1481 rl_start(ifp); 1482 1483#ifdef DEVICE_POLLING 1484done: 1485#endif 1486 RL_UNLOCK(sc); 1487 1488 return; 1489} 1490 1491/* 1492 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1493 * pointers to the fragment pointers. 1494 */ 1495static int 1496rl_encap(sc, m_head) 1497 struct rl_softc *sc; 1498 struct mbuf *m_head; 1499{ 1500 struct mbuf *m_new = NULL; 1501 1502 /* 1503 * The RealTek is brain damaged and wants longword-aligned 1504 * TX buffers, plus we can only have one fragment buffer 1505 * per packet. We have to copy pretty much all the time. 1506 */ 1507 1508 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1509 if (m_new == NULL) 1510 return(1); 1511 if (m_head->m_pkthdr.len > MHLEN) { 1512 MCLGET(m_new, M_DONTWAIT); 1513 if (!(m_new->m_flags & M_EXT)) { 1514 m_freem(m_new); 1515 return(1); 1516 } 1517 } 1518 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1519 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1520 m_freem(m_head); 1521 m_head = m_new; 1522 1523 /* Pad frames to at least 60 bytes. */ 1524 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1525 /* 1526 * Make security concious people happy: zero out the 1527 * bytes in the pad area, since we don't know what 1528 * this mbuf cluster buffer's previous user might 1529 * have left in it. 1530 */ 1531 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1532 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1533 m_head->m_pkthdr.len += 1534 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1535 m_head->m_len = m_head->m_pkthdr.len; 1536 } 1537 1538 RL_CUR_TXMBUF(sc) = m_head; 1539 1540 return(0); 1541} 1542 1543/* 1544 * Main transmit routine. 1545 */ 1546 1547static void 1548rl_start(ifp) 1549 struct ifnet *ifp; 1550{ 1551 struct rl_softc *sc; 1552 struct mbuf *m_head = NULL; 1553 1554 sc = ifp->if_softc; 1555 RL_LOCK(sc); 1556 1557 while(RL_CUR_TXMBUF(sc) == NULL) { 1558 IF_DEQUEUE(&ifp->if_snd, m_head); 1559 if (m_head == NULL) 1560 break; 1561 1562 if (rl_encap(sc, m_head)) { 1563 IF_PREPEND(&ifp->if_snd, m_head); 1564 ifp->if_flags |= IFF_OACTIVE; 1565 break; 1566 } 1567 1568 /* 1569 * If there's a BPF listener, bounce a copy of this frame 1570 * to him. 1571 */ 1572 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1573 1574 /* 1575 * Transmit the frame. 1576 */ 1577 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1578 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1579 mtod(RL_CUR_TXMBUF(sc), void *), 1580 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 1581 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1582 BUS_DMASYNC_PREREAD); 1583 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1584 RL_TXTHRESH(sc->rl_txthresh) | 1585 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1586 1587 RL_INC(sc->rl_cdata.cur_tx); 1588 } 1589 1590 /* 1591 * We broke out of the loop because all our TX slots are 1592 * full. Mark the NIC as busy until it drains some of the 1593 * packets from the queue. 1594 */ 1595 if (RL_CUR_TXMBUF(sc) != NULL) 1596 ifp->if_flags |= IFF_OACTIVE; 1597 1598 /* 1599 * Set a timeout in case the chip goes out to lunch. 1600 */ 1601 ifp->if_timer = 5; 1602 RL_UNLOCK(sc); 1603 1604 return; 1605} 1606 1607static void 1608rl_init(xsc) 1609 void *xsc; 1610{ 1611 struct rl_softc *sc = xsc; 1612 struct ifnet *ifp = &sc->arpcom.ac_if; 1613 struct mii_data *mii; 1614 int i; 1615 u_int32_t rxcfg = 0; 1616 1617 RL_LOCK(sc); 1618 mii = device_get_softc(sc->rl_miibus); 1619 1620 /* 1621 * Cancel pending I/O and free all RX/TX buffers. 1622 */ 1623 rl_stop(sc); 1624 1625 /* Init our MAC address */ 1626 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1627 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 1628 } 1629 1630 /* Init the RX buffer pointer register. */ 1631 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1632 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 1633 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1634 BUS_DMASYNC_PREWRITE); 1635 1636 /* Init TX descriptors. */ 1637 rl_list_tx_init(sc); 1638 1639 /* 1640 * Enable transmit and receive. 1641 */ 1642 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1643 1644 /* 1645 * Set the initial TX and RX configuration. 1646 */ 1647 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1648 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1649 1650 /* Set the individual bit to receive frames for this host only. */ 1651 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1652 rxcfg |= RL_RXCFG_RX_INDIV; 1653 1654 /* If we want promiscuous mode, set the allframes bit. */ 1655 if (ifp->if_flags & IFF_PROMISC) { 1656 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1657 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1658 } else { 1659 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1660 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1661 } 1662 1663 /* 1664 * Set capture broadcast bit to capture broadcast frames. 1665 */ 1666 if (ifp->if_flags & IFF_BROADCAST) { 1667 rxcfg |= RL_RXCFG_RX_BROAD; 1668 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1669 } else { 1670 rxcfg &= ~RL_RXCFG_RX_BROAD; 1671 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1672 } 1673 1674 /* 1675 * Program the multicast filter, if necessary. 1676 */ 1677 rl_setmulti(sc); 1678 1679#ifdef DEVICE_POLLING 1680 /* 1681 * Disable interrupts if we are polling. 1682 */ 1683 if (ifp->if_flags & IFF_POLLING) 1684 CSR_WRITE_2(sc, RL_IMR, 0); 1685 else /* otherwise ... */ 1686#endif /* DEVICE_POLLING */ 1687 /* 1688 * Enable interrupts. 1689 */ 1690 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1691 1692 /* Set initial TX threshold */ 1693 sc->rl_txthresh = RL_TX_THRESH_INIT; 1694 1695 /* Start RX/TX process. */ 1696 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1697 1698 /* Enable receiver and transmitter. */ 1699 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1700 1701 mii_mediachg(mii); 1702 1703 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1704 1705 ifp->if_flags |= IFF_RUNNING; 1706 ifp->if_flags &= ~IFF_OACTIVE; 1707 1708 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1709 RL_UNLOCK(sc); 1710 1711 return; 1712} 1713 1714/* 1715 * Set media options. 1716 */ 1717static int 1718rl_ifmedia_upd(ifp) 1719 struct ifnet *ifp; 1720{ 1721 struct rl_softc *sc; 1722 struct mii_data *mii; 1723 1724 sc = ifp->if_softc; 1725 mii = device_get_softc(sc->rl_miibus); 1726 mii_mediachg(mii); 1727 1728 return(0); 1729} 1730 1731/* 1732 * Report current media status. 1733 */ 1734static void 1735rl_ifmedia_sts(ifp, ifmr) 1736 struct ifnet *ifp; 1737 struct ifmediareq *ifmr; 1738{ 1739 struct rl_softc *sc; 1740 struct mii_data *mii; 1741 1742 sc = ifp->if_softc; 1743 mii = device_get_softc(sc->rl_miibus); 1744 1745 mii_pollstat(mii); 1746 ifmr->ifm_active = mii->mii_media_active; 1747 ifmr->ifm_status = mii->mii_media_status; 1748 1749 return; 1750} 1751 1752static int 1753rl_ioctl(ifp, command, data) 1754 struct ifnet *ifp; 1755 u_long command; 1756 caddr_t data; 1757{ 1758 struct rl_softc *sc = ifp->if_softc; 1759 struct ifreq *ifr = (struct ifreq *) data; 1760 struct mii_data *mii; 1761 int error = 0; 1762 1763 RL_LOCK(sc); 1764 1765 switch(command) { 1766 case SIOCSIFFLAGS: 1767 if (ifp->if_flags & IFF_UP) { 1768 rl_init(sc); 1769 } else { 1770 if (ifp->if_flags & IFF_RUNNING) 1771 rl_stop(sc); 1772 } 1773 error = 0; 1774 break; 1775 case SIOCADDMULTI: 1776 case SIOCDELMULTI: 1777 rl_setmulti(sc); 1778 error = 0; 1779 break; 1780 case SIOCGIFMEDIA: 1781 case SIOCSIFMEDIA: 1782 mii = device_get_softc(sc->rl_miibus); 1783 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1784 break; 1785 default: 1786 error = ether_ioctl(ifp, command, data); 1787 break; 1788 } 1789 1790 RL_UNLOCK(sc); 1791 1792 return(error); 1793} 1794 1795static void 1796rl_watchdog(ifp) 1797 struct ifnet *ifp; 1798{ 1799 struct rl_softc *sc; 1800 1801 sc = ifp->if_softc; 1802 RL_LOCK(sc); 1803 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1804 ifp->if_oerrors++; 1805 1806 rl_txeof(sc); 1807 rl_rxeof(sc); 1808 rl_init(sc); 1809 RL_UNLOCK(sc); 1810 1811 return; 1812} 1813 1814/* 1815 * Stop the adapter and free any mbufs allocated to the 1816 * RX and TX lists. 1817 */ 1818static void 1819rl_stop(sc) 1820 struct rl_softc *sc; 1821{ 1822 register int i; 1823 struct ifnet *ifp; 1824 1825 RL_LOCK(sc); 1826 ifp = &sc->arpcom.ac_if; 1827 ifp->if_timer = 0; 1828 1829 untimeout(rl_tick, sc, sc->rl_stat_ch); 1830 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1831#ifdef DEVICE_POLLING 1832 ether_poll_deregister(ifp); 1833#endif /* DEVICE_POLLING */ 1834 1835 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1836 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1837 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1838 1839 /* 1840 * Free the TX list buffers. 1841 */ 1842 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1843 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1844 bus_dmamap_unload(sc->rl_tag, 1845 sc->rl_cdata.rl_tx_dmamap[i]); 1846 bus_dmamap_destroy(sc->rl_tag, 1847 sc->rl_cdata.rl_tx_dmamap[i]); 1848 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1849 sc->rl_cdata.rl_tx_chain[i] = NULL; 1850 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1851 } 1852 } 1853 1854 RL_UNLOCK(sc); 1855 return; 1856} 1857 1858/* 1859 * Device suspend routine. Stop the interface and save some PCI 1860 * settings in case the BIOS doesn't restore them properly on 1861 * resume. 1862 */ 1863static int 1864rl_suspend(dev) 1865 device_t dev; 1866{ 1867 register int i; 1868 struct rl_softc *sc; 1869 1870 sc = device_get_softc(dev); 1871 1872 rl_stop(sc); 1873 1874 for (i = 0; i < 5; i++) 1875 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 1876 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1877 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1878 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1879 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1880 1881 sc->suspended = 1; 1882 1883 return (0); 1884} 1885 1886/* 1887 * Device resume routine. Restore some PCI settings in case the BIOS 1888 * doesn't, re-enable busmastering, and restart the interface if 1889 * appropriate. 1890 */ 1891static int 1892rl_resume(dev) 1893 device_t dev; 1894{ 1895 register int i; 1896 struct rl_softc *sc; 1897 struct ifnet *ifp; 1898 1899 sc = device_get_softc(dev); 1900 ifp = &sc->arpcom.ac_if; 1901 1902 /* better way to do this? */ 1903 for (i = 0; i < 5; i++) 1904 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 1905 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1906 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1907 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1908 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1909 1910 /* reenable busmastering */ 1911 pci_enable_busmaster(dev); 1912 pci_enable_io(dev, RL_RES); 1913 1914 /* reinitialize interface if necessary */ 1915 if (ifp->if_flags & IFF_UP) 1916 rl_init(sc); 1917 1918 sc->suspended = 0; 1919 1920 return (0); 1921} 1922 1923/* 1924 * Stop all chip I/O so that the kernel's probe routines don't 1925 * get confused by errant DMAs when rebooting. 1926 */ 1927static void 1928rl_shutdown(dev) 1929 device_t dev; 1930{ 1931 struct rl_softc *sc; 1932 1933 sc = device_get_softc(dev); 1934 1935 rl_stop(sc); 1936 1937 return; 1938} 1939