if_rl.c revision 109109
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * RealTek 8129/8139 PCI NIC driver 35 * 36 * Supports several extremely cheap PCI 10/100 adapters based on 37 * the RealTek chipset. Datasheets can be obtained from 38 * www.realtek.com.tw. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 47 * probably the worst PCI ethernet controller ever made, with the possible 48 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 49 * DMA, but it has a terrible interface that nullifies any performance 50 * gains that bus-master DMA usually offers. 51 * 52 * For transmission, the chip offers a series of four TX descriptor 53 * registers. Each transmit frame must be in a contiguous buffer, aligned 54 * on a longword (32-bit) boundary. This means we almost always have to 55 * do mbuf copies in order to transmit a frame, except in the unlikely 56 * case where a) the packet fits into a single mbuf, and b) the packet 57 * is 32-bit aligned within the mbuf's data area. The presence of only 58 * four descriptor registers means that we can never have more than four 59 * packets queued for transmission at any one time. 60 * 61 * Reception is not much better. The driver has to allocate a single large 62 * buffer area (up to 64K in size) into which the chip will DMA received 63 * frames. Because we don't know where within this region received packets 64 * will begin or end, we have no choice but to copy data from the buffer 65 * area into mbufs in order to pass the packets up to the higher protocol 66 * levels. 67 * 68 * It's impossible given this rotten design to really achieve decent 69 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 70 * some equally overmuscled CPU to drive it. 71 * 72 * On the bright side, the 8139 does have a built-in PHY, although 73 * rather than using an MDIO serial interface like most other NICs, the 74 * PHY registers are directly accessible through the 8139's register 75 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 76 * filter. 77 * 78 * The 8129 chip is an older version of the 8139 that uses an external PHY 79 * chip. The 8129 has a serial MDIO interface for accessing the MII where 80 * the 8139 lets you directly access the on-board PHY registers. We need 81 * to select which interface to use depending on the chip type. 82 */ 83 84#include <sys/param.h> 85#include <sys/endian.h> 86#include <sys/systm.h> 87#include <sys/sockio.h> 88#include <sys/mbuf.h> 89#include <sys/malloc.h> 90#include <sys/kernel.h> 91#include <sys/socket.h> 92 93#include <net/if.h> 94#include <net/if_arp.h> 95#include <net/ethernet.h> 96#include <net/if_dl.h> 97#include <net/if_media.h> 98 99#include <net/bpf.h> 100 101#include <machine/bus_pio.h> 102#include <machine/bus_memio.h> 103#include <machine/bus.h> 104#include <machine/resource.h> 105#include <sys/bus.h> 106#include <sys/rman.h> 107 108#include <dev/mii/mii.h> 109#include <dev/mii/miivar.h> 110 111#include <pci/pcireg.h> 112#include <pci/pcivar.h> 113 114MODULE_DEPEND(rl, miibus, 1, 1, 1); 115 116/* "controller miibus0" required. See GENERIC if you get errors here. */ 117#include "miibus_if.h" 118 119/* 120 * Default to using PIO access for this driver. On SMP systems, 121 * there appear to be problems with memory mapped mode: it looks like 122 * doing too many memory mapped access back to back in rapid succession 123 * can hang the bus. I'm inclined to blame this on crummy design/construction 124 * on the part of RealTek. Memory mapped mode does appear to work on 125 * uniprocessor systems though. 126 */ 127#define RL_USEIOSPACE 128 129#include <pci/if_rlreg.h> 130 131__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 109109 2003-01-11 16:11:21Z des $"); 132 133/* 134 * Various supported device vendors/types and their names. 135 */ 136static struct rl_type rl_devs[] = { 137 { RT_VENDORID, RT_DEVICEID_8129, 138 "RealTek 8129 10/100BaseTX" }, 139 { RT_VENDORID, RT_DEVICEID_8139, 140 "RealTek 8139 10/100BaseTX" }, 141 { RT_VENDORID, RT_DEVICEID_8138, 142 "RealTek 8139 10/100BaseTX CardBus" }, 143 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 144 "Accton MPX 5030/5038 10/100BaseTX" }, 145 { DELTA_VENDORID, DELTA_DEVICEID_8139, 146 "Delta Electronics 8139 10/100BaseTX" }, 147 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 148 "Addtron Technolgy 8139 10/100BaseTX" }, 149 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 150 "D-Link DFE-530TX+ 10/100BaseTX" }, 151 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, 152 "D-Link DFE-690TXD 10/100BaseTX" }, 153 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, 154 "Nortel Networks 10/100BaseTX" }, 155 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, 156 "Corega FEther CB-TXD" }, 157 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, 158 "Corega FEtherII CB-TXD" }, 159 { 0, 0, NULL } 160}; 161 162static int rl_probe (device_t); 163static int rl_attach (device_t); 164static int rl_detach (device_t); 165 166static int rl_encap (struct rl_softc *, struct mbuf * ); 167 168static void rl_rxeof (struct rl_softc *); 169static void rl_txeof (struct rl_softc *); 170static void rl_intr (void *); 171static void rl_tick (void *); 172static void rl_start (struct ifnet *); 173static int rl_ioctl (struct ifnet *, u_long, caddr_t); 174static void rl_init (void *); 175static void rl_stop (struct rl_softc *); 176static void rl_watchdog (struct ifnet *); 177static int rl_suspend (device_t); 178static int rl_resume (device_t); 179static void rl_shutdown (device_t); 180static int rl_ifmedia_upd (struct ifnet *); 181static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 182 183static void rl_eeprom_putbyte (struct rl_softc *, int); 184static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 185static void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 186static void rl_mii_sync (struct rl_softc *); 187static void rl_mii_send (struct rl_softc *, u_int32_t, int); 188static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 189static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 190 191static int rl_miibus_readreg (device_t, int, int); 192static int rl_miibus_writereg (device_t, int, int, int); 193static void rl_miibus_statchg (device_t); 194 195static u_int8_t rl_calchash (caddr_t); 196static void rl_setmulti (struct rl_softc *); 197static void rl_reset (struct rl_softc *); 198static int rl_list_tx_init (struct rl_softc *); 199 200static void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 201static void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 202 203#ifdef RL_USEIOSPACE 204#define RL_RES SYS_RES_IOPORT 205#define RL_RID RL_PCI_LOIO 206#else 207#define RL_RES SYS_RES_MEMORY 208#define RL_RID RL_PCI_LOMEM 209#endif 210 211static device_method_t rl_methods[] = { 212 /* Device interface */ 213 DEVMETHOD(device_probe, rl_probe), 214 DEVMETHOD(device_attach, rl_attach), 215 DEVMETHOD(device_detach, rl_detach), 216 DEVMETHOD(device_suspend, rl_suspend), 217 DEVMETHOD(device_resume, rl_resume), 218 DEVMETHOD(device_shutdown, rl_shutdown), 219 220 /* bus interface */ 221 DEVMETHOD(bus_print_child, bus_generic_print_child), 222 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 223 224 /* MII interface */ 225 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 226 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 227 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 228 229 { 0, 0 } 230}; 231 232static driver_t rl_driver = { 233 "rl", 234 rl_methods, 235 sizeof(struct rl_softc) 236}; 237 238static devclass_t rl_devclass; 239 240DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 241DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 242DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 243 244#define EE_SET(x) \ 245 CSR_WRITE_1(sc, RL_EECMD, \ 246 CSR_READ_1(sc, RL_EECMD) | x) 247 248#define EE_CLR(x) \ 249 CSR_WRITE_1(sc, RL_EECMD, \ 250 CSR_READ_1(sc, RL_EECMD) & ~x) 251 252static void 253rl_dma_map_rxbuf(arg, segs, nseg, error) 254 void *arg; 255 bus_dma_segment_t *segs; 256 int nseg, error; 257{ 258 struct rl_softc *sc; 259 260 sc = arg; 261 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 262 263 return; 264} 265 266static void 267rl_dma_map_txbuf(arg, segs, nseg, error) 268 void *arg; 269 bus_dma_segment_t *segs; 270 int nseg, error; 271{ 272 struct rl_softc *sc; 273 274 sc = arg; 275 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 276 277 return; 278} 279 280/* 281 * Send a read command and address to the EEPROM, check for ACK. 282 */ 283static void 284rl_eeprom_putbyte(sc, addr) 285 struct rl_softc *sc; 286 int addr; 287{ 288 register int d, i; 289 290 d = addr | sc->rl_eecmd_read; 291 292 /* 293 * Feed in each bit and strobe the clock. 294 */ 295 for (i = 0x400; i; i >>= 1) { 296 if (d & i) { 297 EE_SET(RL_EE_DATAIN); 298 } else { 299 EE_CLR(RL_EE_DATAIN); 300 } 301 DELAY(100); 302 EE_SET(RL_EE_CLK); 303 DELAY(150); 304 EE_CLR(RL_EE_CLK); 305 DELAY(100); 306 } 307 308 return; 309} 310 311/* 312 * Read a word of data stored in the EEPROM at address 'addr.' 313 */ 314static void 315rl_eeprom_getword(sc, addr, dest) 316 struct rl_softc *sc; 317 int addr; 318 u_int16_t *dest; 319{ 320 register int i; 321 u_int16_t word = 0; 322 323 /* Enter EEPROM access mode. */ 324 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 325 326 /* 327 * Send address of word we want to read. 328 */ 329 rl_eeprom_putbyte(sc, addr); 330 331 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 332 333 /* 334 * Start reading bits from EEPROM. 335 */ 336 for (i = 0x8000; i; i >>= 1) { 337 EE_SET(RL_EE_CLK); 338 DELAY(100); 339 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 340 word |= i; 341 EE_CLR(RL_EE_CLK); 342 DELAY(100); 343 } 344 345 /* Turn off EEPROM access mode. */ 346 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 347 348 *dest = word; 349 350 return; 351} 352 353/* 354 * Read a sequence of words from the EEPROM. 355 */ 356static void 357rl_read_eeprom(sc, dest, off, cnt, swap) 358 struct rl_softc *sc; 359 caddr_t dest; 360 int off; 361 int cnt; 362 int swap; 363{ 364 int i; 365 u_int16_t word = 0, *ptr; 366 367 for (i = 0; i < cnt; i++) { 368 rl_eeprom_getword(sc, off + i, &word); 369 ptr = (u_int16_t *)(dest + (i * 2)); 370 if (swap) 371 *ptr = ntohs(word); 372 else 373 *ptr = word; 374 } 375 376 return; 377} 378 379 380/* 381 * MII access routines are provided for the 8129, which 382 * doesn't have a built-in PHY. For the 8139, we fake things 383 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 384 * direct access PHY registers. 385 */ 386#define MII_SET(x) \ 387 CSR_WRITE_1(sc, RL_MII, \ 388 CSR_READ_1(sc, RL_MII) | (x)) 389 390#define MII_CLR(x) \ 391 CSR_WRITE_1(sc, RL_MII, \ 392 CSR_READ_1(sc, RL_MII) & ~(x)) 393 394/* 395 * Sync the PHYs by setting data bit and strobing the clock 32 times. 396 */ 397static void 398rl_mii_sync(sc) 399 struct rl_softc *sc; 400{ 401 register int i; 402 403 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 404 405 for (i = 0; i < 32; i++) { 406 MII_SET(RL_MII_CLK); 407 DELAY(1); 408 MII_CLR(RL_MII_CLK); 409 DELAY(1); 410 } 411 412 return; 413} 414 415/* 416 * Clock a series of bits through the MII. 417 */ 418static void 419rl_mii_send(sc, bits, cnt) 420 struct rl_softc *sc; 421 u_int32_t bits; 422 int cnt; 423{ 424 int i; 425 426 MII_CLR(RL_MII_CLK); 427 428 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 429 if (bits & i) { 430 MII_SET(RL_MII_DATAOUT); 431 } else { 432 MII_CLR(RL_MII_DATAOUT); 433 } 434 DELAY(1); 435 MII_CLR(RL_MII_CLK); 436 DELAY(1); 437 MII_SET(RL_MII_CLK); 438 } 439} 440 441/* 442 * Read an PHY register through the MII. 443 */ 444static int 445rl_mii_readreg(sc, frame) 446 struct rl_softc *sc; 447 struct rl_mii_frame *frame; 448 449{ 450 int i, ack; 451 452 RL_LOCK(sc); 453 454 /* 455 * Set up frame for RX. 456 */ 457 frame->mii_stdelim = RL_MII_STARTDELIM; 458 frame->mii_opcode = RL_MII_READOP; 459 frame->mii_turnaround = 0; 460 frame->mii_data = 0; 461 462 CSR_WRITE_2(sc, RL_MII, 0); 463 464 /* 465 * Turn on data xmit. 466 */ 467 MII_SET(RL_MII_DIR); 468 469 rl_mii_sync(sc); 470 471 /* 472 * Send command/address info. 473 */ 474 rl_mii_send(sc, frame->mii_stdelim, 2); 475 rl_mii_send(sc, frame->mii_opcode, 2); 476 rl_mii_send(sc, frame->mii_phyaddr, 5); 477 rl_mii_send(sc, frame->mii_regaddr, 5); 478 479 /* Idle bit */ 480 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 481 DELAY(1); 482 MII_SET(RL_MII_CLK); 483 DELAY(1); 484 485 /* Turn off xmit. */ 486 MII_CLR(RL_MII_DIR); 487 488 /* Check for ack */ 489 MII_CLR(RL_MII_CLK); 490 DELAY(1); 491 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 492 MII_SET(RL_MII_CLK); 493 DELAY(1); 494 495 /* 496 * Now try reading data bits. If the ack failed, we still 497 * need to clock through 16 cycles to keep the PHY(s) in sync. 498 */ 499 if (ack) { 500 for(i = 0; i < 16; i++) { 501 MII_CLR(RL_MII_CLK); 502 DELAY(1); 503 MII_SET(RL_MII_CLK); 504 DELAY(1); 505 } 506 goto fail; 507 } 508 509 for (i = 0x8000; i; i >>= 1) { 510 MII_CLR(RL_MII_CLK); 511 DELAY(1); 512 if (!ack) { 513 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 514 frame->mii_data |= i; 515 DELAY(1); 516 } 517 MII_SET(RL_MII_CLK); 518 DELAY(1); 519 } 520 521fail: 522 523 MII_CLR(RL_MII_CLK); 524 DELAY(1); 525 MII_SET(RL_MII_CLK); 526 DELAY(1); 527 528 RL_UNLOCK(sc); 529 530 if (ack) 531 return(1); 532 return(0); 533} 534 535/* 536 * Write to a PHY register through the MII. 537 */ 538static int 539rl_mii_writereg(sc, frame) 540 struct rl_softc *sc; 541 struct rl_mii_frame *frame; 542 543{ 544 RL_LOCK(sc); 545 546 /* 547 * Set up frame for TX. 548 */ 549 550 frame->mii_stdelim = RL_MII_STARTDELIM; 551 frame->mii_opcode = RL_MII_WRITEOP; 552 frame->mii_turnaround = RL_MII_TURNAROUND; 553 554 /* 555 * Turn on data output. 556 */ 557 MII_SET(RL_MII_DIR); 558 559 rl_mii_sync(sc); 560 561 rl_mii_send(sc, frame->mii_stdelim, 2); 562 rl_mii_send(sc, frame->mii_opcode, 2); 563 rl_mii_send(sc, frame->mii_phyaddr, 5); 564 rl_mii_send(sc, frame->mii_regaddr, 5); 565 rl_mii_send(sc, frame->mii_turnaround, 2); 566 rl_mii_send(sc, frame->mii_data, 16); 567 568 /* Idle bit. */ 569 MII_SET(RL_MII_CLK); 570 DELAY(1); 571 MII_CLR(RL_MII_CLK); 572 DELAY(1); 573 574 /* 575 * Turn off xmit. 576 */ 577 MII_CLR(RL_MII_DIR); 578 579 RL_UNLOCK(sc); 580 581 return(0); 582} 583 584static int 585rl_miibus_readreg(dev, phy, reg) 586 device_t dev; 587 int phy, reg; 588{ 589 struct rl_softc *sc; 590 struct rl_mii_frame frame; 591 u_int16_t rval = 0; 592 u_int16_t rl8139_reg = 0; 593 594 sc = device_get_softc(dev); 595 RL_LOCK(sc); 596 597 if (sc->rl_type == RL_8139) { 598 /* Pretend the internal PHY is only at address 0 */ 599 if (phy) { 600 RL_UNLOCK(sc); 601 return(0); 602 } 603 switch(reg) { 604 case MII_BMCR: 605 rl8139_reg = RL_BMCR; 606 break; 607 case MII_BMSR: 608 rl8139_reg = RL_BMSR; 609 break; 610 case MII_ANAR: 611 rl8139_reg = RL_ANAR; 612 break; 613 case MII_ANER: 614 rl8139_reg = RL_ANER; 615 break; 616 case MII_ANLPAR: 617 rl8139_reg = RL_LPAR; 618 break; 619 case MII_PHYIDR1: 620 case MII_PHYIDR2: 621 RL_UNLOCK(sc); 622 return(0); 623 break; 624 /* 625 * Allow the rlphy driver to read the media status 626 * register. If we have a link partner which does not 627 * support NWAY, this is the register which will tell 628 * us the results of parallel detection. 629 */ 630 case RL_MEDIASTAT: 631 rval = CSR_READ_1(sc, RL_MEDIASTAT); 632 RL_UNLOCK(sc); 633 return(rval); 634 break; 635 default: 636 printf("rl%d: bad phy register\n", sc->rl_unit); 637 RL_UNLOCK(sc); 638 return(0); 639 } 640 rval = CSR_READ_2(sc, rl8139_reg); 641 RL_UNLOCK(sc); 642 return(rval); 643 } 644 645 bzero((char *)&frame, sizeof(frame)); 646 647 frame.mii_phyaddr = phy; 648 frame.mii_regaddr = reg; 649 rl_mii_readreg(sc, &frame); 650 RL_UNLOCK(sc); 651 652 return(frame.mii_data); 653} 654 655static int 656rl_miibus_writereg(dev, phy, reg, data) 657 device_t dev; 658 int phy, reg, data; 659{ 660 struct rl_softc *sc; 661 struct rl_mii_frame frame; 662 u_int16_t rl8139_reg = 0; 663 664 sc = device_get_softc(dev); 665 RL_LOCK(sc); 666 667 if (sc->rl_type == RL_8139) { 668 /* Pretend the internal PHY is only at address 0 */ 669 if (phy) { 670 RL_UNLOCK(sc); 671 return(0); 672 } 673 switch(reg) { 674 case MII_BMCR: 675 rl8139_reg = RL_BMCR; 676 break; 677 case MII_BMSR: 678 rl8139_reg = RL_BMSR; 679 break; 680 case MII_ANAR: 681 rl8139_reg = RL_ANAR; 682 break; 683 case MII_ANER: 684 rl8139_reg = RL_ANER; 685 break; 686 case MII_ANLPAR: 687 rl8139_reg = RL_LPAR; 688 break; 689 case MII_PHYIDR1: 690 case MII_PHYIDR2: 691 RL_UNLOCK(sc); 692 return(0); 693 break; 694 default: 695 printf("rl%d: bad phy register\n", sc->rl_unit); 696 RL_UNLOCK(sc); 697 return(0); 698 } 699 CSR_WRITE_2(sc, rl8139_reg, data); 700 RL_UNLOCK(sc); 701 return(0); 702 } 703 704 bzero((char *)&frame, sizeof(frame)); 705 706 frame.mii_phyaddr = phy; 707 frame.mii_regaddr = reg; 708 frame.mii_data = data; 709 710 rl_mii_writereg(sc, &frame); 711 712 RL_UNLOCK(sc); 713 return(0); 714} 715 716static void 717rl_miibus_statchg(dev) 718 device_t dev; 719{ 720 return; 721} 722 723/* 724 * Calculate CRC of a multicast group address, return the upper 6 bits. 725 */ 726static u_int8_t 727rl_calchash(addr) 728 caddr_t addr; 729{ 730 u_int32_t crc, carry; 731 int i, j; 732 u_int8_t c; 733 734 /* Compute CRC for the address value. */ 735 crc = 0xFFFFFFFF; /* initial value */ 736 737 for (i = 0; i < 6; i++) { 738 c = *(addr + i); 739 for (j = 0; j < 8; j++) { 740 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 741 crc <<= 1; 742 c >>= 1; 743 if (carry) 744 crc = (crc ^ 0x04c11db6) | carry; 745 } 746 } 747 748 /* return the filter bit position */ 749 return(crc >> 26); 750} 751 752/* 753 * Program the 64-bit multicast hash filter. 754 */ 755static void 756rl_setmulti(sc) 757 struct rl_softc *sc; 758{ 759 struct ifnet *ifp; 760 int h = 0; 761 u_int32_t hashes[2] = { 0, 0 }; 762 struct ifmultiaddr *ifma; 763 u_int32_t rxfilt; 764 int mcnt = 0; 765 766 ifp = &sc->arpcom.ac_if; 767 768 rxfilt = CSR_READ_4(sc, RL_RXCFG); 769 770 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 771 rxfilt |= RL_RXCFG_RX_MULTI; 772 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 773 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 774 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 775 return; 776 } 777 778 /* first, zot all the existing hash bits */ 779 CSR_WRITE_4(sc, RL_MAR0, 0); 780 CSR_WRITE_4(sc, RL_MAR4, 0); 781 782 /* now program new ones */ 783 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 784 if (ifma->ifma_addr->sa_family != AF_LINK) 785 continue; 786 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 787 if (h < 32) 788 hashes[0] |= (1 << h); 789 else 790 hashes[1] |= (1 << (h - 32)); 791 mcnt++; 792 } 793 794 if (mcnt) 795 rxfilt |= RL_RXCFG_RX_MULTI; 796 else 797 rxfilt &= ~RL_RXCFG_RX_MULTI; 798 799 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 800 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 801 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 802 803 return; 804} 805 806static void 807rl_reset(sc) 808 struct rl_softc *sc; 809{ 810 register int i; 811 812 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 813 814 for (i = 0; i < RL_TIMEOUT; i++) { 815 DELAY(10); 816 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 817 break; 818 } 819 if (i == RL_TIMEOUT) 820 printf("rl%d: reset never completed!\n", sc->rl_unit); 821 822 return; 823} 824 825/* 826 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 827 * IDs against our list and return a device name if we find a match. 828 */ 829static int 830rl_probe(dev) 831 device_t dev; 832{ 833 struct rl_type *t; 834 835 t = rl_devs; 836 837 while(t->rl_name != NULL) { 838 if ((pci_get_vendor(dev) == t->rl_vid) && 839 (pci_get_device(dev) == t->rl_did)) { 840 device_set_desc(dev, t->rl_name); 841 return(0); 842 } 843 t++; 844 } 845 846 return(ENXIO); 847} 848 849/* 850 * Attach the interface. Allocate softc structures, do ifmedia 851 * setup and ethernet/BPF attach. 852 */ 853static int 854rl_attach(dev) 855 device_t dev; 856{ 857 u_char eaddr[ETHER_ADDR_LEN]; 858 u_int32_t command; 859 u_int16_t as[3]; 860 struct rl_softc *sc; 861 struct ifnet *ifp; 862 u_int16_t rl_did = 0; 863 int unit, error = 0, rid, i; 864 865 sc = device_get_softc(dev); 866 unit = device_get_unit(dev); 867 bzero(sc, sizeof(struct rl_softc)); 868 869 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 870 MTX_DEF | MTX_RECURSE); 871 872 /* 873 * Handle power management nonsense. 874 */ 875 876 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 877 u_int32_t iobase, membase, irq; 878 879 /* Save important PCI config data. */ 880 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 881 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 882 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 883 884 /* Reset the power state. */ 885 printf("rl%d: chip is is in D%d power mode " 886 "-- setting to D0\n", unit, 887 pci_get_powerstate(dev)); 888 889 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 890 891 /* Restore PCI config data. */ 892 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 893 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 894 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 895 } 896 897 /* 898 * Map control/status registers. 899 */ 900 pci_enable_busmaster(dev); 901 pci_enable_io(dev, SYS_RES_IOPORT); 902 pci_enable_io(dev, SYS_RES_MEMORY); 903 command = pci_read_config(dev, PCIR_COMMAND, 4); 904 905#ifdef RL_USEIOSPACE 906 if (!(command & PCIM_CMD_PORTEN)) { 907 printf("rl%d: failed to enable I/O ports!\n", unit); 908 error = ENXIO; 909 goto fail; 910 } 911#else 912 if (!(command & PCIM_CMD_MEMEN)) { 913 printf("rl%d: failed to enable memory mapping!\n", unit); 914 error = ENXIO; 915 goto fail; 916 } 917#endif 918 919 rid = RL_RID; 920 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 921 0, ~0, 1, RF_ACTIVE); 922 923 if (sc->rl_res == NULL) { 924 printf ("rl%d: couldn't map ports/memory\n", unit); 925 error = ENXIO; 926 goto fail; 927 } 928 929 /* Detect the Realtek 8139B. For some reason, this chip is very 930 * unstable when left to autoselect the media 931 * The best workaround is to set the device to the required 932 * media type or to set it to the 10 Meg speed. 933 */ 934 935 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 936 printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit); 937 } 938 939 sc->rl_btag = rman_get_bustag(sc->rl_res); 940 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 941 942 rid = 0; 943 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 944 RF_SHAREABLE | RF_ACTIVE); 945 946 if (sc->rl_irq == NULL) { 947 printf("rl%d: couldn't map interrupt\n", unit); 948 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 949 error = ENXIO; 950 goto fail; 951 } 952 953 /* Reset the adapter. */ 954 rl_reset(sc); 955 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 956 rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 957 if (rl_did != 0x8129) 958 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 959 960 /* 961 * Get station address from the EEPROM. 962 */ 963 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 964 for (i = 0; i < 3; i++) { 965 eaddr[(i * 2) + 0] = as[i] & 0xff; 966 eaddr[(i * 2) + 1] = as[i] >> 8; 967 } 968 969 /* 970 * A RealTek chip was detected. Inform the world. 971 */ 972 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 973 974 sc->rl_unit = unit; 975 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 976 977 /* 978 * Now read the exact device type from the EEPROM to find 979 * out if it's an 8129 or 8139. 980 */ 981 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 982 983 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 984 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 985 rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS || 986 rl_did == DLINK_DEVICEID_690TXD || 987 rl_did == COREGA_DEVICEID_FETHERCBTXD || 988 rl_did == COREGA_DEVICEID_FETHERIICBTXD) 989 sc->rl_type = RL_8139; 990 else if (rl_did == RT_DEVICEID_8129) 991 sc->rl_type = RL_8129; 992 else { 993 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 994 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 995 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 996 error = ENXIO; 997 goto fail; 998 } 999 1000 /* 1001 * Allocate the parent bus DMA tag appropriate for PCI. 1002 */ 1003#define RL_NSEG_NEW 32 1004 error = bus_dma_tag_create(NULL, /* parent */ 1005 1, 0, /* alignment, boundary */ 1006 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1007 BUS_SPACE_MAXADDR, /* highaddr */ 1008 NULL, NULL, /* filter, filterarg */ 1009 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1010 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1011 BUS_DMA_ALLOCNOW, /* flags */ 1012 &sc->rl_parent_tag); 1013 1014 /* 1015 * Now allocate a tag for the DMA descriptor lists. 1016 * All of our lists are allocated as a contiguous block 1017 * of memory. 1018 */ 1019 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 1020 1, 0, /* alignment, boundary */ 1021 BUS_SPACE_MAXADDR, /* lowaddr */ 1022 BUS_SPACE_MAXADDR, /* highaddr */ 1023 NULL, NULL, /* filter, filterarg */ 1024 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 1025 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1026 0, /* flags */ 1027 &sc->rl_tag); 1028 1029 /* 1030 * Now allocate a chunk of DMA-able memory based on the 1031 * tag we just created. 1032 */ 1033 error = bus_dmamem_alloc(sc->rl_tag, 1034 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT, 1035 &sc->rl_cdata.rl_rx_dmamap); 1036 1037 if (sc->rl_cdata.rl_rx_buf == NULL) { 1038 printf("rl%d: no memory for list buffers!\n", unit); 1039 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1040 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1041 bus_dma_tag_destroy(sc->rl_tag); 1042 error = ENXIO; 1043 goto fail; 1044 } 1045 1046 /* Leave a few bytes before the start of the RX ring buffer. */ 1047 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1048 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1049 1050 /* Do MII setup */ 1051 if (mii_phy_probe(dev, &sc->rl_miibus, 1052 rl_ifmedia_upd, rl_ifmedia_sts)) { 1053 printf("rl%d: MII without any phy!\n", sc->rl_unit); 1054 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1055 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1056 bus_dmamem_free(sc->rl_tag, 1057 sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap); 1058 bus_dma_tag_destroy(sc->rl_tag); 1059 error = ENXIO; 1060 goto fail; 1061 } 1062 1063 ifp = &sc->arpcom.ac_if; 1064 ifp->if_softc = sc; 1065 ifp->if_unit = unit; 1066 ifp->if_name = "rl"; 1067 ifp->if_mtu = ETHERMTU; 1068 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1069 ifp->if_ioctl = rl_ioctl; 1070 ifp->if_output = ether_output; 1071 ifp->if_start = rl_start; 1072 ifp->if_watchdog = rl_watchdog; 1073 ifp->if_init = rl_init; 1074 ifp->if_baudrate = 10000000; 1075 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1076 1077 /* 1078 * Call MI attach routine. 1079 */ 1080 ether_ifattach(ifp, eaddr); 1081 1082 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1083 rl_intr, sc, &sc->rl_intrhand); 1084 1085 if (error) { 1086 printf("rl%d: couldn't set up irq\n", unit); 1087 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1088 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1089 bus_dmamem_free(sc->rl_tag, 1090 sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap); 1091 bus_dma_tag_destroy(sc->rl_tag); 1092 goto fail; 1093 } 1094 1095 callout_handle_init(&sc->rl_stat_ch); 1096 return(0); 1097fail: 1098 mtx_destroy(&sc->rl_mtx); 1099 return(error); 1100} 1101 1102static int 1103rl_detach(dev) 1104 device_t dev; 1105{ 1106 struct rl_softc *sc; 1107 struct ifnet *ifp; 1108 1109 sc = device_get_softc(dev); 1110 RL_LOCK(sc); 1111 ifp = &sc->arpcom.ac_if; 1112 1113 ether_ifdetach(ifp); 1114 rl_stop(sc); 1115 1116 bus_generic_detach(dev); 1117 device_delete_child(dev, sc->rl_miibus); 1118 1119 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1120 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1121 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1122 1123 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1124 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1125 sc->rl_cdata.rl_rx_dmamap); 1126 bus_dma_tag_destroy(sc->rl_tag); 1127 bus_dma_tag_destroy(sc->rl_parent_tag); 1128 1129 RL_UNLOCK(sc); 1130 mtx_destroy(&sc->rl_mtx); 1131 1132 return(0); 1133} 1134 1135/* 1136 * Initialize the transmit descriptors. 1137 */ 1138static int 1139rl_list_tx_init(sc) 1140 struct rl_softc *sc; 1141{ 1142 struct rl_chain_data *cd; 1143 int i; 1144 1145 cd = &sc->rl_cdata; 1146 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1147 cd->rl_tx_chain[i] = NULL; 1148 CSR_WRITE_4(sc, 1149 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1150 } 1151 1152 sc->rl_cdata.cur_tx = 0; 1153 sc->rl_cdata.last_tx = 0; 1154 1155 return(0); 1156} 1157 1158/* 1159 * A frame has been uploaded: pass the resulting mbuf chain up to 1160 * the higher level protocols. 1161 * 1162 * You know there's something wrong with a PCI bus-master chip design 1163 * when you have to use m_devget(). 1164 * 1165 * The receive operation is badly documented in the datasheet, so I'll 1166 * attempt to document it here. The driver provides a buffer area and 1167 * places its base address in the RX buffer start address register. 1168 * The chip then begins copying frames into the RX buffer. Each frame 1169 * is preceded by a 32-bit RX status word which specifies the length 1170 * of the frame and certain other status bits. Each frame (starting with 1171 * the status word) is also 32-bit aligned. The frame length is in the 1172 * first 16 bits of the status word; the lower 15 bits correspond with 1173 * the 'rx status register' mentioned in the datasheet. 1174 * 1175 * Note: to make the Alpha happy, the frame payload needs to be aligned 1176 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1177 * as the offset argument to m_devget(). 1178 */ 1179static void 1180rl_rxeof(sc) 1181 struct rl_softc *sc; 1182{ 1183 struct mbuf *m; 1184 struct ifnet *ifp; 1185 int total_len = 0; 1186 u_int32_t rxstat; 1187 caddr_t rxbufpos; 1188 int wrap = 0; 1189 u_int16_t cur_rx; 1190 u_int16_t limit; 1191 u_int16_t rx_bytes = 0, max_bytes; 1192 1193 ifp = &sc->arpcom.ac_if; 1194 1195 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1196 BUS_DMASYNC_POSTREAD); 1197 1198 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1199 1200 /* Do not try to read past this point. */ 1201 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1202 1203 if (limit < cur_rx) 1204 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1205 else 1206 max_bytes = limit - cur_rx; 1207 1208 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1209#ifdef DEVICE_POLLING 1210 if (ifp->if_flags & IFF_POLLING) { 1211 if (sc->rxcycles <= 0) 1212 break; 1213 sc->rxcycles--; 1214 } 1215#endif /* DEVICE_POLLING */ 1216 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1217 rxstat = le32toh(*(u_int32_t *)rxbufpos); 1218 1219 /* 1220 * Here's a totally undocumented fact for you. When the 1221 * RealTek chip is in the process of copying a packet into 1222 * RAM for you, the length will be 0xfff0. If you spot a 1223 * packet header with this value, you need to stop. The 1224 * datasheet makes absolutely no mention of this and 1225 * RealTek should be shot for this. 1226 */ 1227 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1228 break; 1229 1230 if (!(rxstat & RL_RXSTAT_RXOK)) { 1231 ifp->if_ierrors++; 1232 rl_init(sc); 1233 return; 1234 } 1235 1236 /* No errors; receive the packet. */ 1237 total_len = rxstat >> 16; 1238 rx_bytes += total_len + 4; 1239 1240 /* 1241 * XXX The RealTek chip includes the CRC with every 1242 * received frame, and there's no way to turn this 1243 * behavior off (at least, I can't find anything in 1244 * the manual that explains how to do it) so we have 1245 * to trim off the CRC manually. 1246 */ 1247 total_len -= ETHER_CRC_LEN; 1248 1249 /* 1250 * Avoid trying to read more bytes than we know 1251 * the chip has prepared for us. 1252 */ 1253 if (rx_bytes > max_bytes) 1254 break; 1255 1256 rxbufpos = sc->rl_cdata.rl_rx_buf + 1257 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1258 1259 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1260 rxbufpos = sc->rl_cdata.rl_rx_buf; 1261 1262 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1263 1264 if (total_len > wrap) { 1265 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1266 NULL); 1267 if (m == NULL) { 1268 ifp->if_ierrors++; 1269 } else { 1270 m_copyback(m, wrap, total_len - wrap, 1271 sc->rl_cdata.rl_rx_buf); 1272 } 1273 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1274 } else { 1275 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1276 NULL); 1277 if (m == NULL) { 1278 ifp->if_ierrors++; 1279 } 1280 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1281 } 1282 1283 /* 1284 * Round up to 32-bit boundary. 1285 */ 1286 cur_rx = (cur_rx + 3) & ~3; 1287 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1288 1289 if (m == NULL) 1290 continue; 1291 1292 ifp->if_ipackets++; 1293 (*ifp->if_input)(ifp, m); 1294 } 1295 1296 return; 1297} 1298 1299/* 1300 * A frame was downloaded to the chip. It's safe for us to clean up 1301 * the list buffers. 1302 */ 1303static void 1304rl_txeof(sc) 1305 struct rl_softc *sc; 1306{ 1307 struct ifnet *ifp; 1308 u_int32_t txstat; 1309 1310 ifp = &sc->arpcom.ac_if; 1311 1312 /* 1313 * Go through our tx list and free mbufs for those 1314 * frames that have been uploaded. 1315 */ 1316 do { 1317 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1318 if (!(txstat & (RL_TXSTAT_TX_OK| 1319 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1320 break; 1321 1322 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1323 1324 if (RL_LAST_TXMBUF(sc) != NULL) { 1325 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1326 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1327 m_freem(RL_LAST_TXMBUF(sc)); 1328 RL_LAST_TXMBUF(sc) = NULL; 1329 } 1330 if (txstat & RL_TXSTAT_TX_OK) 1331 ifp->if_opackets++; 1332 else { 1333 int oldthresh; 1334 ifp->if_oerrors++; 1335 if ((txstat & RL_TXSTAT_TXABRT) || 1336 (txstat & RL_TXSTAT_OUTOFWIN)) 1337 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1338 oldthresh = sc->rl_txthresh; 1339 /* error recovery */ 1340 rl_reset(sc); 1341 rl_init(sc); 1342 /* 1343 * If there was a transmit underrun, 1344 * bump the TX threshold. 1345 */ 1346 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1347 sc->rl_txthresh = oldthresh + 32; 1348 return; 1349 } 1350 RL_INC(sc->rl_cdata.last_tx); 1351 ifp->if_flags &= ~IFF_OACTIVE; 1352 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1353 1354 ifp->if_timer = 1355 (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5; 1356 1357 return; 1358} 1359 1360static void 1361rl_tick(xsc) 1362 void *xsc; 1363{ 1364 struct rl_softc *sc; 1365 struct mii_data *mii; 1366 1367 sc = xsc; 1368 RL_LOCK(sc); 1369 mii = device_get_softc(sc->rl_miibus); 1370 1371 mii_tick(mii); 1372 1373 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1374 RL_UNLOCK(sc); 1375 1376 return; 1377} 1378 1379#ifdef DEVICE_POLLING 1380static void 1381rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1382{ 1383 struct rl_softc *sc = ifp->if_softc; 1384 1385 RL_LOCK(sc); 1386 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1387 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1388 goto done; 1389 } 1390 1391 sc->rxcycles = count; 1392 rl_rxeof(sc); 1393 rl_txeof(sc); 1394 if (ifp->if_snd.ifq_head != NULL) 1395 rl_start(ifp); 1396 1397 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1398 u_int16_t status; 1399 1400 status = CSR_READ_2(sc, RL_ISR); 1401 if (status == 0xffff) 1402 goto done; 1403 if (status) 1404 CSR_WRITE_2(sc, RL_ISR, status); 1405 1406 /* 1407 * XXX check behaviour on receiver stalls. 1408 */ 1409 1410 if (status & RL_ISR_SYSTEM_ERR) { 1411 rl_reset(sc); 1412 rl_init(sc); 1413 } 1414 } 1415done: 1416 RL_UNLOCK(sc); 1417} 1418#endif /* DEVICE_POLLING */ 1419 1420static void 1421rl_intr(arg) 1422 void *arg; 1423{ 1424 struct rl_softc *sc; 1425 struct ifnet *ifp; 1426 u_int16_t status; 1427 1428 sc = arg; 1429 1430 if (sc->suspended) { 1431 return; 1432 } 1433 1434 RL_LOCK(sc); 1435 ifp = &sc->arpcom.ac_if; 1436 1437#ifdef DEVICE_POLLING 1438 if (ifp->if_flags & IFF_POLLING) 1439 goto done; 1440 if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 1441 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1442 rl_poll(ifp, 0, 1); 1443 goto done; 1444 } 1445#endif /* DEVICE_POLLING */ 1446 1447 for (;;) { 1448 1449 status = CSR_READ_2(sc, RL_ISR); 1450 /* If the card has gone away the read returns 0xffff. */ 1451 if (status == 0xffff) 1452 break; 1453 if (status) 1454 CSR_WRITE_2(sc, RL_ISR, status); 1455 1456 if ((status & RL_INTRS) == 0) 1457 break; 1458 1459 if (status & RL_ISR_RX_OK) 1460 rl_rxeof(sc); 1461 1462 if (status & RL_ISR_RX_ERR) 1463 rl_rxeof(sc); 1464 1465 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1466 rl_txeof(sc); 1467 1468 if (status & RL_ISR_SYSTEM_ERR) { 1469 rl_reset(sc); 1470 rl_init(sc); 1471 } 1472 1473 } 1474 1475 if (ifp->if_snd.ifq_head != NULL) 1476 rl_start(ifp); 1477 1478#ifdef DEVICE_POLLING 1479done: 1480#endif 1481 RL_UNLOCK(sc); 1482 1483 return; 1484} 1485 1486/* 1487 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1488 * pointers to the fragment pointers. 1489 */ 1490static int 1491rl_encap(sc, m_head) 1492 struct rl_softc *sc; 1493 struct mbuf *m_head; 1494{ 1495 struct mbuf *m_new = NULL; 1496 1497 /* 1498 * The RealTek is brain damaged and wants longword-aligned 1499 * TX buffers, plus we can only have one fragment buffer 1500 * per packet. We have to copy pretty much all the time. 1501 */ 1502 1503 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1504 if (m_new == NULL) 1505 return(1); 1506 if (m_head->m_pkthdr.len > MHLEN) { 1507 MCLGET(m_new, M_DONTWAIT); 1508 if (!(m_new->m_flags & M_EXT)) { 1509 m_freem(m_new); 1510 return(1); 1511 } 1512 } 1513 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1514 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1515 m_freem(m_head); 1516 m_head = m_new; 1517 1518 /* Pad frames to at least 60 bytes. */ 1519 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1520 /* 1521 * Make security concious people happy: zero out the 1522 * bytes in the pad area, since we don't know what 1523 * this mbuf cluster buffer's previous user might 1524 * have left in it. 1525 */ 1526 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1527 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1528 m_head->m_pkthdr.len += 1529 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1530 m_head->m_len = m_head->m_pkthdr.len; 1531 } 1532 1533 RL_CUR_TXMBUF(sc) = m_head; 1534 1535 return(0); 1536} 1537 1538/* 1539 * Main transmit routine. 1540 */ 1541 1542static void 1543rl_start(ifp) 1544 struct ifnet *ifp; 1545{ 1546 struct rl_softc *sc; 1547 struct mbuf *m_head = NULL; 1548 1549 sc = ifp->if_softc; 1550 RL_LOCK(sc); 1551 1552 while(RL_CUR_TXMBUF(sc) == NULL) { 1553 IF_DEQUEUE(&ifp->if_snd, m_head); 1554 if (m_head == NULL) 1555 break; 1556 1557 if (rl_encap(sc, m_head)) { 1558 IF_PREPEND(&ifp->if_snd, m_head); 1559 ifp->if_flags |= IFF_OACTIVE; 1560 break; 1561 } 1562 1563 /* 1564 * If there's a BPF listener, bounce a copy of this frame 1565 * to him. 1566 */ 1567 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1568 1569 /* 1570 * Transmit the frame. 1571 */ 1572 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1573 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1574 mtod(RL_CUR_TXMBUF(sc), void *), 1575 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 1576 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1577 BUS_DMASYNC_PREREAD); 1578 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1579 RL_TXTHRESH(sc->rl_txthresh) | 1580 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1581 1582 RL_INC(sc->rl_cdata.cur_tx); 1583 } 1584 1585 /* 1586 * We broke out of the loop because all our TX slots are 1587 * full. Mark the NIC as busy until it drains some of the 1588 * packets from the queue. 1589 */ 1590 if (RL_CUR_TXMBUF(sc) != NULL) 1591 ifp->if_flags |= IFF_OACTIVE; 1592 1593 /* 1594 * Set a timeout in case the chip goes out to lunch. 1595 */ 1596 ifp->if_timer = 5; 1597 RL_UNLOCK(sc); 1598 1599 return; 1600} 1601 1602static void 1603rl_init(xsc) 1604 void *xsc; 1605{ 1606 struct rl_softc *sc = xsc; 1607 struct ifnet *ifp = &sc->arpcom.ac_if; 1608 struct mii_data *mii; 1609 int i; 1610 u_int32_t rxcfg = 0; 1611 1612 RL_LOCK(sc); 1613 mii = device_get_softc(sc->rl_miibus); 1614 1615 /* 1616 * Cancel pending I/O and free all RX/TX buffers. 1617 */ 1618 rl_stop(sc); 1619 1620 /* Init our MAC address */ 1621 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1622 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 1623 } 1624 1625 /* Init the RX buffer pointer register. */ 1626 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1627 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 1628 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1629 BUS_DMASYNC_PREWRITE); 1630 1631 /* Init TX descriptors. */ 1632 rl_list_tx_init(sc); 1633 1634 /* 1635 * Enable transmit and receive. 1636 */ 1637 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1638 1639 /* 1640 * Set the initial TX and RX configuration. 1641 */ 1642 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1643 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1644 1645 /* Set the individual bit to receive frames for this host only. */ 1646 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1647 rxcfg |= RL_RXCFG_RX_INDIV; 1648 1649 /* If we want promiscuous mode, set the allframes bit. */ 1650 if (ifp->if_flags & IFF_PROMISC) { 1651 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1652 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1653 } else { 1654 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1655 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1656 } 1657 1658 /* 1659 * Set capture broadcast bit to capture broadcast frames. 1660 */ 1661 if (ifp->if_flags & IFF_BROADCAST) { 1662 rxcfg |= RL_RXCFG_RX_BROAD; 1663 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1664 } else { 1665 rxcfg &= ~RL_RXCFG_RX_BROAD; 1666 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1667 } 1668 1669 /* 1670 * Program the multicast filter, if necessary. 1671 */ 1672 rl_setmulti(sc); 1673 1674#ifdef DEVICE_POLLING 1675 /* 1676 * Disable interrupts if we are polling. 1677 */ 1678 if (ifp->if_flags & IFF_POLLING) 1679 CSR_WRITE_2(sc, RL_IMR, 0); 1680 else /* otherwise ... */ 1681#endif /* DEVICE_POLLING */ 1682 /* 1683 * Enable interrupts. 1684 */ 1685 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1686 1687 /* Set initial TX threshold */ 1688 sc->rl_txthresh = RL_TX_THRESH_INIT; 1689 1690 /* Start RX/TX process. */ 1691 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1692 1693 /* Enable receiver and transmitter. */ 1694 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1695 1696 mii_mediachg(mii); 1697 1698 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1699 1700 ifp->if_flags |= IFF_RUNNING; 1701 ifp->if_flags &= ~IFF_OACTIVE; 1702 1703 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1704 RL_UNLOCK(sc); 1705 1706 return; 1707} 1708 1709/* 1710 * Set media options. 1711 */ 1712static int 1713rl_ifmedia_upd(ifp) 1714 struct ifnet *ifp; 1715{ 1716 struct rl_softc *sc; 1717 struct mii_data *mii; 1718 1719 sc = ifp->if_softc; 1720 mii = device_get_softc(sc->rl_miibus); 1721 mii_mediachg(mii); 1722 1723 return(0); 1724} 1725 1726/* 1727 * Report current media status. 1728 */ 1729static void 1730rl_ifmedia_sts(ifp, ifmr) 1731 struct ifnet *ifp; 1732 struct ifmediareq *ifmr; 1733{ 1734 struct rl_softc *sc; 1735 struct mii_data *mii; 1736 1737 sc = ifp->if_softc; 1738 mii = device_get_softc(sc->rl_miibus); 1739 1740 mii_pollstat(mii); 1741 ifmr->ifm_active = mii->mii_media_active; 1742 ifmr->ifm_status = mii->mii_media_status; 1743 1744 return; 1745} 1746 1747static int 1748rl_ioctl(ifp, command, data) 1749 struct ifnet *ifp; 1750 u_long command; 1751 caddr_t data; 1752{ 1753 struct rl_softc *sc = ifp->if_softc; 1754 struct ifreq *ifr = (struct ifreq *) data; 1755 struct mii_data *mii; 1756 int error = 0; 1757 1758 RL_LOCK(sc); 1759 1760 switch(command) { 1761 case SIOCSIFFLAGS: 1762 if (ifp->if_flags & IFF_UP) { 1763 rl_init(sc); 1764 } else { 1765 if (ifp->if_flags & IFF_RUNNING) 1766 rl_stop(sc); 1767 } 1768 error = 0; 1769 break; 1770 case SIOCADDMULTI: 1771 case SIOCDELMULTI: 1772 rl_setmulti(sc); 1773 error = 0; 1774 break; 1775 case SIOCGIFMEDIA: 1776 case SIOCSIFMEDIA: 1777 mii = device_get_softc(sc->rl_miibus); 1778 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1779 break; 1780 default: 1781 error = ether_ioctl(ifp, command, data); 1782 break; 1783 } 1784 1785 RL_UNLOCK(sc); 1786 1787 return(error); 1788} 1789 1790static void 1791rl_watchdog(ifp) 1792 struct ifnet *ifp; 1793{ 1794 struct rl_softc *sc; 1795 1796 sc = ifp->if_softc; 1797 RL_LOCK(sc); 1798 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1799 ifp->if_oerrors++; 1800 1801 rl_txeof(sc); 1802 rl_rxeof(sc); 1803 rl_init(sc); 1804 RL_UNLOCK(sc); 1805 1806 return; 1807} 1808 1809/* 1810 * Stop the adapter and free any mbufs allocated to the 1811 * RX and TX lists. 1812 */ 1813static void 1814rl_stop(sc) 1815 struct rl_softc *sc; 1816{ 1817 register int i; 1818 struct ifnet *ifp; 1819 1820 RL_LOCK(sc); 1821 ifp = &sc->arpcom.ac_if; 1822 ifp->if_timer = 0; 1823 1824 untimeout(rl_tick, sc, sc->rl_stat_ch); 1825 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1826#ifdef DEVICE_POLLING 1827 ether_poll_deregister(ifp); 1828#endif /* DEVICE_POLLING */ 1829 1830 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1831 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1832 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1833 1834 /* 1835 * Free the TX list buffers. 1836 */ 1837 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1838 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1839 bus_dmamap_unload(sc->rl_tag, 1840 sc->rl_cdata.rl_tx_dmamap[i]); 1841 bus_dmamap_destroy(sc->rl_tag, 1842 sc->rl_cdata.rl_tx_dmamap[i]); 1843 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1844 sc->rl_cdata.rl_tx_chain[i] = NULL; 1845 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1846 } 1847 } 1848 1849 RL_UNLOCK(sc); 1850 return; 1851} 1852 1853/* 1854 * Device suspend routine. Stop the interface and save some PCI 1855 * settings in case the BIOS doesn't restore them properly on 1856 * resume. 1857 */ 1858static int 1859rl_suspend(dev) 1860 device_t dev; 1861{ 1862 register int i; 1863 struct rl_softc *sc; 1864 1865 sc = device_get_softc(dev); 1866 1867 rl_stop(sc); 1868 1869 for (i = 0; i < 5; i++) 1870 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 1871 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1872 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1873 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1874 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1875 1876 sc->suspended = 1; 1877 1878 return (0); 1879} 1880 1881/* 1882 * Device resume routine. Restore some PCI settings in case the BIOS 1883 * doesn't, re-enable busmastering, and restart the interface if 1884 * appropriate. 1885 */ 1886static int 1887rl_resume(dev) 1888 device_t dev; 1889{ 1890 register int i; 1891 struct rl_softc *sc; 1892 struct ifnet *ifp; 1893 1894 sc = device_get_softc(dev); 1895 ifp = &sc->arpcom.ac_if; 1896 1897 /* better way to do this? */ 1898 for (i = 0; i < 5; i++) 1899 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 1900 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1901 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1902 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1903 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1904 1905 /* reenable busmastering */ 1906 pci_enable_busmaster(dev); 1907 pci_enable_io(dev, RL_RES); 1908 1909 /* reinitialize interface if necessary */ 1910 if (ifp->if_flags & IFF_UP) 1911 rl_init(sc); 1912 1913 sc->suspended = 0; 1914 1915 return (0); 1916} 1917 1918/* 1919 * Stop all chip I/O so that the kernel's probe routines don't 1920 * get confused by errant DMAs when rebooting. 1921 */ 1922static void 1923rl_shutdown(dev) 1924 device_t dev; 1925{ 1926 struct rl_softc *sc; 1927 1928 sc = device_get_softc(dev); 1929 1930 rl_stop(sc); 1931 1932 return; 1933} 1934