if_rl.c revision 102335
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_rl.c 102335 2002-08-23 23:49:02Z alfred $ 33 */ 34 35/* 36 * RealTek 8129/8139 PCI NIC driver 37 * 38 * Supports several extremely cheap PCI 10/100 adapters based on 39 * the RealTek chipset. Datasheets can be obtained from 40 * www.realtek.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86#include <sys/param.h> 87#include <sys/systm.h> 88#include <sys/sockio.h> 89#include <sys/mbuf.h> 90#include <sys/malloc.h> 91#include <sys/kernel.h> 92#include <sys/socket.h> 93 94#include <net/if.h> 95#include <net/if_arp.h> 96#include <net/ethernet.h> 97#include <net/if_dl.h> 98#include <net/if_media.h> 99 100#include <net/bpf.h> 101 102#include <machine/bus_pio.h> 103#include <machine/bus_memio.h> 104#include <machine/bus.h> 105#include <machine/resource.h> 106#include <sys/bus.h> 107#include <sys/rman.h> 108 109#include <dev/mii/mii.h> 110#include <dev/mii/miivar.h> 111 112#include <pci/pcireg.h> 113#include <pci/pcivar.h> 114 115MODULE_DEPEND(rl, miibus, 1, 1, 1); 116 117/* "controller miibus0" required. See GENERIC if you get errors here. */ 118#include "miibus_if.h" 119 120/* 121 * Default to using PIO access for this driver. On SMP systems, 122 * there appear to be problems with memory mapped mode: it looks like 123 * doing too many memory mapped access back to back in rapid succession 124 * can hang the bus. I'm inclined to blame this on crummy design/construction 125 * on the part of RealTek. Memory mapped mode does appear to work on 126 * uniprocessor systems though. 127 */ 128#define RL_USEIOSPACE 129 130#include <pci/if_rlreg.h> 131 132#ifndef lint 133static const char rcsid[] = 134 "$FreeBSD: head/sys/pci/if_rl.c 102335 2002-08-23 23:49:02Z alfred $"; 135#endif 136 137/* 138 * Various supported device vendors/types and their names. 139 */ 140static struct rl_type rl_devs[] = { 141 { RT_VENDORID, RT_DEVICEID_8129, 142 "RealTek 8129 10/100BaseTX" }, 143 { RT_VENDORID, RT_DEVICEID_8139, 144 "RealTek 8139 10/100BaseTX" }, 145 { RT_VENDORID, RT_DEVICEID_8138, 146 "RealTek 8139 10/100BaseTX CardBus" }, 147 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 148 "Accton MPX 5030/5038 10/100BaseTX" }, 149 { DELTA_VENDORID, DELTA_DEVICEID_8139, 150 "Delta Electronics 8139 10/100BaseTX" }, 151 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 152 "Addtron Technolgy 8139 10/100BaseTX" }, 153 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 154 "D-Link DFE-530TX+ 10/100BaseTX" }, 155 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, 156 "D-Link DFE-690TXD 10/100BaseTX" }, 157 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, 158 "Nortel Networks 10/100BaseTX" }, 159 { 0, 0, NULL } 160}; 161 162static int rl_probe (device_t); 163static int rl_attach (device_t); 164static int rl_detach (device_t); 165 166static int rl_encap (struct rl_softc *, struct mbuf * ); 167 168static void rl_rxeof (struct rl_softc *); 169static void rl_txeof (struct rl_softc *); 170static void rl_intr (void *); 171static void rl_tick (void *); 172static void rl_start (struct ifnet *); 173static int rl_ioctl (struct ifnet *, u_long, caddr_t); 174static void rl_init (void *); 175static void rl_stop (struct rl_softc *); 176static void rl_watchdog (struct ifnet *); 177static int rl_suspend (device_t); 178static int rl_resume (device_t); 179static void rl_shutdown (device_t); 180static int rl_ifmedia_upd (struct ifnet *); 181static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 182 183static void rl_eeprom_putbyte (struct rl_softc *, int); 184static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 185static void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 186static void rl_mii_sync (struct rl_softc *); 187static void rl_mii_send (struct rl_softc *, u_int32_t, int); 188static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 189static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 190 191static int rl_miibus_readreg (device_t, int, int); 192static int rl_miibus_writereg (device_t, int, int, int); 193static void rl_miibus_statchg (device_t); 194 195static u_int8_t rl_calchash (caddr_t); 196static void rl_setmulti (struct rl_softc *); 197static void rl_reset (struct rl_softc *); 198static int rl_list_tx_init (struct rl_softc *); 199 200static void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 201static void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 202 203#ifdef RL_USEIOSPACE 204#define RL_RES SYS_RES_IOPORT 205#define RL_RID RL_PCI_LOIO 206#else 207#define RL_RES SYS_RES_MEMORY 208#define RL_RID RL_PCI_LOMEM 209#endif 210 211static device_method_t rl_methods[] = { 212 /* Device interface */ 213 DEVMETHOD(device_probe, rl_probe), 214 DEVMETHOD(device_attach, rl_attach), 215 DEVMETHOD(device_detach, rl_detach), 216 DEVMETHOD(device_suspend, rl_suspend), 217 DEVMETHOD(device_resume, rl_resume), 218 DEVMETHOD(device_shutdown, rl_shutdown), 219 220 /* bus interface */ 221 DEVMETHOD(bus_print_child, bus_generic_print_child), 222 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 223 224 /* MII interface */ 225 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 226 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 227 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 228 229 { 0, 0 } 230}; 231 232static driver_t rl_driver = { 233 "rl", 234 rl_methods, 235 sizeof(struct rl_softc) 236}; 237 238static devclass_t rl_devclass; 239 240DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 241DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 242DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 243 244#define EE_SET(x) \ 245 CSR_WRITE_1(sc, RL_EECMD, \ 246 CSR_READ_1(sc, RL_EECMD) | x) 247 248#define EE_CLR(x) \ 249 CSR_WRITE_1(sc, RL_EECMD, \ 250 CSR_READ_1(sc, RL_EECMD) & ~x) 251 252static void 253rl_dma_map_rxbuf(arg, segs, nseg, error) 254 void *arg; 255 bus_dma_segment_t *segs; 256 int nseg, error; 257{ 258 struct rl_softc *sc; 259 260 sc = arg; 261 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 262 263 return; 264} 265 266static void 267rl_dma_map_txbuf(arg, segs, nseg, error) 268 void *arg; 269 bus_dma_segment_t *segs; 270 int nseg, error; 271{ 272 struct rl_softc *sc; 273 274 sc = arg; 275 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 276 277 return; 278} 279 280/* 281 * Send a read command and address to the EEPROM, check for ACK. 282 */ 283static void 284rl_eeprom_putbyte(sc, addr) 285 struct rl_softc *sc; 286 int addr; 287{ 288 register int d, i; 289 290 d = addr | sc->rl_eecmd_read; 291 292 /* 293 * Feed in each bit and strobe the clock. 294 */ 295 for (i = 0x400; i; i >>= 1) { 296 if (d & i) { 297 EE_SET(RL_EE_DATAIN); 298 } else { 299 EE_CLR(RL_EE_DATAIN); 300 } 301 DELAY(100); 302 EE_SET(RL_EE_CLK); 303 DELAY(150); 304 EE_CLR(RL_EE_CLK); 305 DELAY(100); 306 } 307 308 return; 309} 310 311/* 312 * Read a word of data stored in the EEPROM at address 'addr.' 313 */ 314static void 315rl_eeprom_getword(sc, addr, dest) 316 struct rl_softc *sc; 317 int addr; 318 u_int16_t *dest; 319{ 320 register int i; 321 u_int16_t word = 0; 322 323 /* Enter EEPROM access mode. */ 324 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 325 326 /* 327 * Send address of word we want to read. 328 */ 329 rl_eeprom_putbyte(sc, addr); 330 331 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 332 333 /* 334 * Start reading bits from EEPROM. 335 */ 336 for (i = 0x8000; i; i >>= 1) { 337 EE_SET(RL_EE_CLK); 338 DELAY(100); 339 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 340 word |= i; 341 EE_CLR(RL_EE_CLK); 342 DELAY(100); 343 } 344 345 /* Turn off EEPROM access mode. */ 346 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 347 348 *dest = word; 349 350 return; 351} 352 353/* 354 * Read a sequence of words from the EEPROM. 355 */ 356static void 357rl_read_eeprom(sc, dest, off, cnt, swap) 358 struct rl_softc *sc; 359 caddr_t dest; 360 int off; 361 int cnt; 362 int swap; 363{ 364 int i; 365 u_int16_t word = 0, *ptr; 366 367 for (i = 0; i < cnt; i++) { 368 rl_eeprom_getword(sc, off + i, &word); 369 ptr = (u_int16_t *)(dest + (i * 2)); 370 if (swap) 371 *ptr = ntohs(word); 372 else 373 *ptr = word; 374 } 375 376 return; 377} 378 379 380/* 381 * MII access routines are provided for the 8129, which 382 * doesn't have a built-in PHY. For the 8139, we fake things 383 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 384 * direct access PHY registers. 385 */ 386#define MII_SET(x) \ 387 CSR_WRITE_1(sc, RL_MII, \ 388 CSR_READ_1(sc, RL_MII) | x) 389 390#define MII_CLR(x) \ 391 CSR_WRITE_1(sc, RL_MII, \ 392 CSR_READ_1(sc, RL_MII) & ~x) 393 394/* 395 * Sync the PHYs by setting data bit and strobing the clock 32 times. 396 */ 397static void 398rl_mii_sync(sc) 399 struct rl_softc *sc; 400{ 401 register int i; 402 403 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 404 405 for (i = 0; i < 32; i++) { 406 MII_SET(RL_MII_CLK); 407 DELAY(1); 408 MII_CLR(RL_MII_CLK); 409 DELAY(1); 410 } 411 412 return; 413} 414 415/* 416 * Clock a series of bits through the MII. 417 */ 418static void 419rl_mii_send(sc, bits, cnt) 420 struct rl_softc *sc; 421 u_int32_t bits; 422 int cnt; 423{ 424 int i; 425 426 MII_CLR(RL_MII_CLK); 427 428 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 429 if (bits & i) { 430 MII_SET(RL_MII_DATAOUT); 431 } else { 432 MII_CLR(RL_MII_DATAOUT); 433 } 434 DELAY(1); 435 MII_CLR(RL_MII_CLK); 436 DELAY(1); 437 MII_SET(RL_MII_CLK); 438 } 439} 440 441/* 442 * Read an PHY register through the MII. 443 */ 444static int 445rl_mii_readreg(sc, frame) 446 struct rl_softc *sc; 447 struct rl_mii_frame *frame; 448 449{ 450 int i, ack; 451 452 RL_LOCK(sc); 453 454 /* 455 * Set up frame for RX. 456 */ 457 frame->mii_stdelim = RL_MII_STARTDELIM; 458 frame->mii_opcode = RL_MII_READOP; 459 frame->mii_turnaround = 0; 460 frame->mii_data = 0; 461 462 CSR_WRITE_2(sc, RL_MII, 0); 463 464 /* 465 * Turn on data xmit. 466 */ 467 MII_SET(RL_MII_DIR); 468 469 rl_mii_sync(sc); 470 471 /* 472 * Send command/address info. 473 */ 474 rl_mii_send(sc, frame->mii_stdelim, 2); 475 rl_mii_send(sc, frame->mii_opcode, 2); 476 rl_mii_send(sc, frame->mii_phyaddr, 5); 477 rl_mii_send(sc, frame->mii_regaddr, 5); 478 479 /* Idle bit */ 480 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 481 DELAY(1); 482 MII_SET(RL_MII_CLK); 483 DELAY(1); 484 485 /* Turn off xmit. */ 486 MII_CLR(RL_MII_DIR); 487 488 /* Check for ack */ 489 MII_CLR(RL_MII_CLK); 490 DELAY(1); 491 MII_SET(RL_MII_CLK); 492 DELAY(1); 493 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 494 495 /* 496 * Now try reading data bits. If the ack failed, we still 497 * need to clock through 16 cycles to keep the PHY(s) in sync. 498 */ 499 if (ack) { 500 for(i = 0; i < 16; i++) { 501 MII_CLR(RL_MII_CLK); 502 DELAY(1); 503 MII_SET(RL_MII_CLK); 504 DELAY(1); 505 } 506 goto fail; 507 } 508 509 for (i = 0x8000; i; i >>= 1) { 510 MII_CLR(RL_MII_CLK); 511 DELAY(1); 512 if (!ack) { 513 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 514 frame->mii_data |= i; 515 DELAY(1); 516 } 517 MII_SET(RL_MII_CLK); 518 DELAY(1); 519 } 520 521fail: 522 523 MII_CLR(RL_MII_CLK); 524 DELAY(1); 525 MII_SET(RL_MII_CLK); 526 DELAY(1); 527 528 RL_UNLOCK(sc); 529 530 if (ack) 531 return(1); 532 return(0); 533} 534 535/* 536 * Write to a PHY register through the MII. 537 */ 538static int 539rl_mii_writereg(sc, frame) 540 struct rl_softc *sc; 541 struct rl_mii_frame *frame; 542 543{ 544 RL_LOCK(sc); 545 546 /* 547 * Set up frame for TX. 548 */ 549 550 frame->mii_stdelim = RL_MII_STARTDELIM; 551 frame->mii_opcode = RL_MII_WRITEOP; 552 frame->mii_turnaround = RL_MII_TURNAROUND; 553 554 /* 555 * Turn on data output. 556 */ 557 MII_SET(RL_MII_DIR); 558 559 rl_mii_sync(sc); 560 561 rl_mii_send(sc, frame->mii_stdelim, 2); 562 rl_mii_send(sc, frame->mii_opcode, 2); 563 rl_mii_send(sc, frame->mii_phyaddr, 5); 564 rl_mii_send(sc, frame->mii_regaddr, 5); 565 rl_mii_send(sc, frame->mii_turnaround, 2); 566 rl_mii_send(sc, frame->mii_data, 16); 567 568 /* Idle bit. */ 569 MII_SET(RL_MII_CLK); 570 DELAY(1); 571 MII_CLR(RL_MII_CLK); 572 DELAY(1); 573 574 /* 575 * Turn off xmit. 576 */ 577 MII_CLR(RL_MII_DIR); 578 579 RL_UNLOCK(sc); 580 581 return(0); 582} 583 584static int 585rl_miibus_readreg(dev, phy, reg) 586 device_t dev; 587 int phy, reg; 588{ 589 struct rl_softc *sc; 590 struct rl_mii_frame frame; 591 u_int16_t rval = 0; 592 u_int16_t rl8139_reg = 0; 593 594 sc = device_get_softc(dev); 595 RL_LOCK(sc); 596 597 if (sc->rl_type == RL_8139) { 598 /* Pretend the internal PHY is only at address 0 */ 599 if (phy) { 600 RL_UNLOCK(sc); 601 return(0); 602 } 603 switch(reg) { 604 case MII_BMCR: 605 rl8139_reg = RL_BMCR; 606 break; 607 case MII_BMSR: 608 rl8139_reg = RL_BMSR; 609 break; 610 case MII_ANAR: 611 rl8139_reg = RL_ANAR; 612 break; 613 case MII_ANER: 614 rl8139_reg = RL_ANER; 615 break; 616 case MII_ANLPAR: 617 rl8139_reg = RL_LPAR; 618 break; 619 case MII_PHYIDR1: 620 case MII_PHYIDR2: 621 RL_UNLOCK(sc); 622 return(0); 623 break; 624 /* 625 * Allow the rlphy driver to read the media status 626 * register. If we have a link partner which does not 627 * support NWAY, this is the register which will tell 628 * us the results of parallel detection. 629 */ 630 case RL_MEDIASTAT: 631 rval = CSR_READ_1(sc, RL_MEDIASTAT); 632 RL_UNLOCK(sc); 633 return(rval); 634 break; 635 default: 636 printf("rl%d: bad phy register\n", sc->rl_unit); 637 RL_UNLOCK(sc); 638 return(0); 639 } 640 rval = CSR_READ_2(sc, rl8139_reg); 641 RL_UNLOCK(sc); 642 return(rval); 643 } 644 645 bzero((char *)&frame, sizeof(frame)); 646 647 frame.mii_phyaddr = phy; 648 frame.mii_regaddr = reg; 649 rl_mii_readreg(sc, &frame); 650 RL_UNLOCK(sc); 651 652 return(frame.mii_data); 653} 654 655static int 656rl_miibus_writereg(dev, phy, reg, data) 657 device_t dev; 658 int phy, reg, data; 659{ 660 struct rl_softc *sc; 661 struct rl_mii_frame frame; 662 u_int16_t rl8139_reg = 0; 663 664 sc = device_get_softc(dev); 665 RL_LOCK(sc); 666 667 if (sc->rl_type == RL_8139) { 668 /* Pretend the internal PHY is only at address 0 */ 669 if (phy) { 670 RL_UNLOCK(sc); 671 return(0); 672 } 673 switch(reg) { 674 case MII_BMCR: 675 rl8139_reg = RL_BMCR; 676 break; 677 case MII_BMSR: 678 rl8139_reg = RL_BMSR; 679 break; 680 case MII_ANAR: 681 rl8139_reg = RL_ANAR; 682 break; 683 case MII_ANER: 684 rl8139_reg = RL_ANER; 685 break; 686 case MII_ANLPAR: 687 rl8139_reg = RL_LPAR; 688 break; 689 case MII_PHYIDR1: 690 case MII_PHYIDR2: 691 RL_UNLOCK(sc); 692 return(0); 693 break; 694 default: 695 printf("rl%d: bad phy register\n", sc->rl_unit); 696 RL_UNLOCK(sc); 697 return(0); 698 } 699 CSR_WRITE_2(sc, rl8139_reg, data); 700 RL_UNLOCK(sc); 701 return(0); 702 } 703 704 bzero((char *)&frame, sizeof(frame)); 705 706 frame.mii_phyaddr = phy; 707 frame.mii_regaddr = reg; 708 frame.mii_data = data; 709 710 rl_mii_writereg(sc, &frame); 711 712 RL_UNLOCK(sc); 713 return(0); 714} 715 716static void 717rl_miibus_statchg(dev) 718 device_t dev; 719{ 720 return; 721} 722 723/* 724 * Calculate CRC of a multicast group address, return the upper 6 bits. 725 */ 726static u_int8_t 727rl_calchash(addr) 728 caddr_t addr; 729{ 730 u_int32_t crc, carry; 731 int i, j; 732 u_int8_t c; 733 734 /* Compute CRC for the address value. */ 735 crc = 0xFFFFFFFF; /* initial value */ 736 737 for (i = 0; i < 6; i++) { 738 c = *(addr + i); 739 for (j = 0; j < 8; j++) { 740 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 741 crc <<= 1; 742 c >>= 1; 743 if (carry) 744 crc = (crc ^ 0x04c11db6) | carry; 745 } 746 } 747 748 /* return the filter bit position */ 749 return(crc >> 26); 750} 751 752/* 753 * Program the 64-bit multicast hash filter. 754 */ 755static void 756rl_setmulti(sc) 757 struct rl_softc *sc; 758{ 759 struct ifnet *ifp; 760 int h = 0; 761 u_int32_t hashes[2] = { 0, 0 }; 762 struct ifmultiaddr *ifma; 763 u_int32_t rxfilt; 764 int mcnt = 0; 765 766 ifp = &sc->arpcom.ac_if; 767 768 rxfilt = CSR_READ_4(sc, RL_RXCFG); 769 770 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 771 rxfilt |= RL_RXCFG_RX_MULTI; 772 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 773 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 774 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 775 return; 776 } 777 778 /* first, zot all the existing hash bits */ 779 CSR_WRITE_4(sc, RL_MAR0, 0); 780 CSR_WRITE_4(sc, RL_MAR4, 0); 781 782 /* now program new ones */ 783 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 784 if (ifma->ifma_addr->sa_family != AF_LINK) 785 continue; 786 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 787 if (h < 32) 788 hashes[0] |= (1 << h); 789 else 790 hashes[1] |= (1 << (h - 32)); 791 mcnt++; 792 } 793 794 if (mcnt) 795 rxfilt |= RL_RXCFG_RX_MULTI; 796 else 797 rxfilt &= ~RL_RXCFG_RX_MULTI; 798 799 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 800 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 801 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 802 803 return; 804} 805 806static void 807rl_reset(sc) 808 struct rl_softc *sc; 809{ 810 register int i; 811 812 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 813 814 for (i = 0; i < RL_TIMEOUT; i++) { 815 DELAY(10); 816 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 817 break; 818 } 819 if (i == RL_TIMEOUT) 820 printf("rl%d: reset never completed!\n", sc->rl_unit); 821 822 return; 823} 824 825/* 826 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 827 * IDs against our list and return a device name if we find a match. 828 */ 829static int 830rl_probe(dev) 831 device_t dev; 832{ 833 struct rl_type *t; 834 835 t = rl_devs; 836 837 while(t->rl_name != NULL) { 838 if ((pci_get_vendor(dev) == t->rl_vid) && 839 (pci_get_device(dev) == t->rl_did)) { 840 device_set_desc(dev, t->rl_name); 841 return(0); 842 } 843 t++; 844 } 845 846 return(ENXIO); 847} 848 849/* 850 * Attach the interface. Allocate softc structures, do ifmedia 851 * setup and ethernet/BPF attach. 852 */ 853static int 854rl_attach(dev) 855 device_t dev; 856{ 857 u_char eaddr[ETHER_ADDR_LEN]; 858 u_int32_t command; 859 struct rl_softc *sc; 860 struct ifnet *ifp; 861 u_int16_t rl_did = 0; 862 int unit, error = 0, rid; 863 864 sc = device_get_softc(dev); 865 unit = device_get_unit(dev); 866 bzero(sc, sizeof(struct rl_softc)); 867 868 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 869 MTX_DEF | MTX_RECURSE); 870 RL_LOCK(sc); 871 872 /* 873 * Handle power management nonsense. 874 */ 875 876 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 877 u_int32_t iobase, membase, irq; 878 879 /* Save important PCI config data. */ 880 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 881 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 882 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 883 884 /* Reset the power state. */ 885 printf("rl%d: chip is is in D%d power mode " 886 "-- setting to D0\n", unit, 887 pci_get_powerstate(dev)); 888 889 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 890 891 /* Restore PCI config data. */ 892 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 893 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 894 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 895 } 896 897 /* 898 * Map control/status registers. 899 */ 900 pci_enable_busmaster(dev); 901 pci_enable_io(dev, SYS_RES_IOPORT); 902 pci_enable_io(dev, SYS_RES_MEMORY); 903 command = pci_read_config(dev, PCIR_COMMAND, 4); 904 905#ifdef RL_USEIOSPACE 906 if (!(command & PCIM_CMD_PORTEN)) { 907 printf("rl%d: failed to enable I/O ports!\n", unit); 908 error = ENXIO; 909 goto fail; 910 } 911#else 912 if (!(command & PCIM_CMD_MEMEN)) { 913 printf("rl%d: failed to enable memory mapping!\n", unit); 914 error = ENXIO; 915 goto fail; 916 } 917#endif 918 919 rid = RL_RID; 920 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 921 0, ~0, 1, RF_ACTIVE); 922 923 if (sc->rl_res == NULL) { 924 printf ("rl%d: couldn't map ports/memory\n", unit); 925 error = ENXIO; 926 goto fail; 927 } 928 929 /* Detect the Realtek 8139B. For some reason, this chip is very 930 * unstable when left to autoselect the media 931 * The best workaround is to set the device to the required 932 * media type or to set it to the 10 Meg speed. 933 */ 934 935 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 936 printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit); 937 } 938 939 sc->rl_btag = rman_get_bustag(sc->rl_res); 940 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 941 942 rid = 0; 943 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 944 RF_SHAREABLE | RF_ACTIVE); 945 946 if (sc->rl_irq == NULL) { 947 printf("rl%d: couldn't map interrupt\n", unit); 948 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 949 error = ENXIO; 950 goto fail; 951 } 952 953 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 954 rl_intr, sc, &sc->rl_intrhand); 955 956 if (error) { 957 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 958 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 959 printf("rl%d: couldn't set up irq\n", unit); 960 goto fail; 961 } 962 963 callout_handle_init(&sc->rl_stat_ch); 964 965 /* Reset the adapter. */ 966 rl_reset(sc); 967 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 968 rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 969 if (rl_did != 0x8129) 970 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 971 972 /* 973 * Get station address from the EEPROM. 974 */ 975 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 976 977 /* 978 * A RealTek chip was detected. Inform the world. 979 */ 980 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 981 982 sc->rl_unit = unit; 983 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 984 985 /* 986 * Now read the exact device type from the EEPROM to find 987 * out if it's an 8129 or 8139. 988 */ 989 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 990 991 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 992 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 993 rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS || 994 rl_did == DLINK_DEVICEID_690TXD) 995 sc->rl_type = RL_8139; 996 else if (rl_did == RT_DEVICEID_8129) 997 sc->rl_type = RL_8129; 998 else { 999 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 1000 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1001 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1002 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1003 error = ENXIO; 1004 goto fail; 1005 } 1006 1007 /* 1008 * Allocate the parent bus DMA tag appropriate for PCI. 1009 */ 1010#define RL_NSEG_NEW 32 1011 error = bus_dma_tag_create(NULL, /* parent */ 1012 1, 0, /* alignment, boundary */ 1013 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1014 BUS_SPACE_MAXADDR, /* highaddr */ 1015 NULL, NULL, /* filter, filterarg */ 1016 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1017 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1018 BUS_DMA_ALLOCNOW, /* flags */ 1019 &sc->rl_parent_tag); 1020 1021 /* 1022 * Now allocate a tag for the DMA descriptor lists. 1023 * All of our lists are allocated as a contiguous block 1024 * of memory. 1025 */ 1026 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 1027 1, 0, /* alignment, boundary */ 1028 BUS_SPACE_MAXADDR, /* lowaddr */ 1029 BUS_SPACE_MAXADDR, /* highaddr */ 1030 NULL, NULL, /* filter, filterarg */ 1031 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 1032 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1033 0, /* flags */ 1034 &sc->rl_tag); 1035 1036 /* 1037 * Now allocate a chunk of DMA-able memory based on the 1038 * tag we just created. 1039 */ 1040 error = bus_dmamem_alloc(sc->rl_tag, 1041 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT, 1042 &sc->rl_cdata.rl_rx_dmamap); 1043 1044 if (sc->rl_cdata.rl_rx_buf == NULL) { 1045 printf("rl%d: no memory for list buffers!\n", unit); 1046 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1047 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1048 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1049 bus_dma_tag_destroy(sc->rl_tag); 1050 error = ENXIO; 1051 goto fail; 1052 } 1053 1054 /* Leave a few bytes before the start of the RX ring buffer. */ 1055 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1056 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1057 1058 /* Do MII setup */ 1059 if (mii_phy_probe(dev, &sc->rl_miibus, 1060 rl_ifmedia_upd, rl_ifmedia_sts)) { 1061 printf("rl%d: MII without any phy!\n", sc->rl_unit); 1062 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1063 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1064 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1065 bus_dmamem_free(sc->rl_tag, 1066 sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap); 1067 bus_dma_tag_destroy(sc->rl_tag); 1068 error = ENXIO; 1069 goto fail; 1070 } 1071 1072 ifp = &sc->arpcom.ac_if; 1073 ifp->if_softc = sc; 1074 ifp->if_unit = unit; 1075 ifp->if_name = "rl"; 1076 ifp->if_mtu = ETHERMTU; 1077 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1078 ifp->if_ioctl = rl_ioctl; 1079 ifp->if_output = ether_output; 1080 ifp->if_start = rl_start; 1081 ifp->if_watchdog = rl_watchdog; 1082 ifp->if_init = rl_init; 1083 ifp->if_baudrate = 10000000; 1084 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1085 1086 /* 1087 * Call MI attach routine. 1088 */ 1089 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1090 RL_UNLOCK(sc); 1091 return(0); 1092 1093fail: 1094 RL_UNLOCK(sc); 1095 mtx_destroy(&sc->rl_mtx); 1096 return(error); 1097} 1098 1099static int 1100rl_detach(dev) 1101 device_t dev; 1102{ 1103 struct rl_softc *sc; 1104 struct ifnet *ifp; 1105 1106 sc = device_get_softc(dev); 1107 RL_LOCK(sc); 1108 ifp = &sc->arpcom.ac_if; 1109 1110 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1111 rl_stop(sc); 1112 1113 bus_generic_detach(dev); 1114 device_delete_child(dev, sc->rl_miibus); 1115 1116 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1117 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1118 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1119 1120 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1121 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1122 sc->rl_cdata.rl_rx_dmamap); 1123 bus_dma_tag_destroy(sc->rl_tag); 1124 bus_dma_tag_destroy(sc->rl_parent_tag); 1125 1126 RL_UNLOCK(sc); 1127 mtx_destroy(&sc->rl_mtx); 1128 1129 return(0); 1130} 1131 1132/* 1133 * Initialize the transmit descriptors. 1134 */ 1135static int 1136rl_list_tx_init(sc) 1137 struct rl_softc *sc; 1138{ 1139 struct rl_chain_data *cd; 1140 int i; 1141 1142 cd = &sc->rl_cdata; 1143 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1144 cd->rl_tx_chain[i] = NULL; 1145 CSR_WRITE_4(sc, 1146 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1147 } 1148 1149 sc->rl_cdata.cur_tx = 0; 1150 sc->rl_cdata.last_tx = 0; 1151 1152 return(0); 1153} 1154 1155/* 1156 * A frame has been uploaded: pass the resulting mbuf chain up to 1157 * the higher level protocols. 1158 * 1159 * You know there's something wrong with a PCI bus-master chip design 1160 * when you have to use m_devget(). 1161 * 1162 * The receive operation is badly documented in the datasheet, so I'll 1163 * attempt to document it here. The driver provides a buffer area and 1164 * places its base address in the RX buffer start address register. 1165 * The chip then begins copying frames into the RX buffer. Each frame 1166 * is preceded by a 32-bit RX status word which specifies the length 1167 * of the frame and certain other status bits. Each frame (starting with 1168 * the status word) is also 32-bit aligned. The frame length is in the 1169 * first 16 bits of the status word; the lower 15 bits correspond with 1170 * the 'rx status register' mentioned in the datasheet. 1171 * 1172 * Note: to make the Alpha happy, the frame payload needs to be aligned 1173 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1174 * as the offset argument to m_devget(). 1175 */ 1176static void 1177rl_rxeof(sc) 1178 struct rl_softc *sc; 1179{ 1180 struct ether_header *eh; 1181 struct mbuf *m; 1182 struct ifnet *ifp; 1183 int total_len = 0; 1184 u_int32_t rxstat; 1185 caddr_t rxbufpos; 1186 int wrap = 0; 1187 u_int16_t cur_rx; 1188 u_int16_t limit; 1189 u_int16_t rx_bytes = 0, max_bytes; 1190 1191 ifp = &sc->arpcom.ac_if; 1192 1193 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1194 BUS_DMASYNC_POSTWRITE); 1195 1196 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1197 1198 /* Do not try to read past this point. */ 1199 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1200 1201 if (limit < cur_rx) 1202 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1203 else 1204 max_bytes = limit - cur_rx; 1205 1206 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1207#ifdef DEVICE_POLLING 1208 if (ifp->if_flags & IFF_POLLING) { 1209 if (sc->rxcycles <= 0) 1210 break; 1211 sc->rxcycles--; 1212 } 1213#endif /* DEVICE_POLLING */ 1214 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1215 rxstat = *(u_int32_t *)rxbufpos; 1216 1217 /* 1218 * Here's a totally undocumented fact for you. When the 1219 * RealTek chip is in the process of copying a packet into 1220 * RAM for you, the length will be 0xfff0. If you spot a 1221 * packet header with this value, you need to stop. The 1222 * datasheet makes absolutely no mention of this and 1223 * RealTek should be shot for this. 1224 */ 1225 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1226 break; 1227 1228 if (!(rxstat & RL_RXSTAT_RXOK)) { 1229 ifp->if_ierrors++; 1230 rl_init(sc); 1231 return; 1232 } 1233 1234 /* No errors; receive the packet. */ 1235 total_len = rxstat >> 16; 1236 rx_bytes += total_len + 4; 1237 1238 /* 1239 * XXX The RealTek chip includes the CRC with every 1240 * received frame, and there's no way to turn this 1241 * behavior off (at least, I can't find anything in 1242 * the manual that explains how to do it) so we have 1243 * to trim off the CRC manually. 1244 */ 1245 total_len -= ETHER_CRC_LEN; 1246 1247 /* 1248 * Avoid trying to read more bytes than we know 1249 * the chip has prepared for us. 1250 */ 1251 if (rx_bytes > max_bytes) 1252 break; 1253 1254 rxbufpos = sc->rl_cdata.rl_rx_buf + 1255 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1256 1257 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1258 rxbufpos = sc->rl_cdata.rl_rx_buf; 1259 1260 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1261 1262 if (total_len > wrap) { 1263 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1264 NULL); 1265 if (m == NULL) { 1266 ifp->if_ierrors++; 1267 } else { 1268 m_copyback(m, wrap, total_len - wrap, 1269 sc->rl_cdata.rl_rx_buf); 1270 } 1271 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1272 } else { 1273 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1274 NULL); 1275 if (m == NULL) { 1276 ifp->if_ierrors++; 1277 } 1278 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1279 } 1280 1281 /* 1282 * Round up to 32-bit boundary. 1283 */ 1284 cur_rx = (cur_rx + 3) & ~3; 1285 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1286 1287 if (m == NULL) 1288 continue; 1289 1290 eh = mtod(m, struct ether_header *); 1291 ifp->if_ipackets++; 1292 1293 /* Remove header from mbuf and pass it on. */ 1294 m_adj(m, sizeof(struct ether_header)); 1295 ether_input(ifp, eh, m); 1296 } 1297 1298 return; 1299} 1300 1301/* 1302 * A frame was downloaded to the chip. It's safe for us to clean up 1303 * the list buffers. 1304 */ 1305static void 1306rl_txeof(sc) 1307 struct rl_softc *sc; 1308{ 1309 struct ifnet *ifp; 1310 u_int32_t txstat; 1311 1312 ifp = &sc->arpcom.ac_if; 1313 1314 /* 1315 * Go through our tx list and free mbufs for those 1316 * frames that have been uploaded. 1317 */ 1318 do { 1319 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1320 if (!(txstat & (RL_TXSTAT_TX_OK| 1321 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1322 break; 1323 1324 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1325 1326 if (RL_LAST_TXMBUF(sc) != NULL) { 1327 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1328 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1329 m_freem(RL_LAST_TXMBUF(sc)); 1330 RL_LAST_TXMBUF(sc) = NULL; 1331 } 1332 if (txstat & RL_TXSTAT_TX_OK) 1333 ifp->if_opackets++; 1334 else { 1335 int oldthresh; 1336 ifp->if_oerrors++; 1337 if ((txstat & RL_TXSTAT_TXABRT) || 1338 (txstat & RL_TXSTAT_OUTOFWIN)) 1339 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1340 oldthresh = sc->rl_txthresh; 1341 /* error recovery */ 1342 rl_reset(sc); 1343 rl_init(sc); 1344 /* 1345 * If there was a transmit underrun, 1346 * bump the TX threshold. 1347 */ 1348 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1349 sc->rl_txthresh = oldthresh + 32; 1350 return; 1351 } 1352 RL_INC(sc->rl_cdata.last_tx); 1353 ifp->if_flags &= ~IFF_OACTIVE; 1354 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1355 1356 ifp->if_timer = 1357 (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5; 1358 1359 return; 1360} 1361 1362static void 1363rl_tick(xsc) 1364 void *xsc; 1365{ 1366 struct rl_softc *sc; 1367 struct mii_data *mii; 1368 1369 sc = xsc; 1370 RL_LOCK(sc); 1371 mii = device_get_softc(sc->rl_miibus); 1372 1373 mii_tick(mii); 1374 1375 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1376 RL_UNLOCK(sc); 1377 1378 return; 1379} 1380 1381#ifdef DEVICE_POLLING 1382static void 1383rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1384{ 1385 struct rl_softc *sc = ifp->if_softc; 1386 1387 RL_LOCK(sc); 1388 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1389 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1390 goto done; 1391 } 1392 1393 sc->rxcycles = count; 1394 rl_rxeof(sc); 1395 rl_txeof(sc); 1396 if (ifp->if_snd.ifq_head != NULL) 1397 rl_start(ifp); 1398 1399 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1400 u_int16_t status; 1401 1402 status = CSR_READ_2(sc, RL_ISR); 1403 if (status == 0xffff) 1404 goto done; 1405 if (status) 1406 CSR_WRITE_2(sc, RL_ISR, status); 1407 1408 /* 1409 * XXX check behaviour on receiver stalls. 1410 */ 1411 1412 if (status & RL_ISR_SYSTEM_ERR) { 1413 rl_reset(sc); 1414 rl_init(sc); 1415 } 1416 } 1417done: 1418 RL_UNLOCK(sc); 1419} 1420#endif /* DEVICE_POLLING */ 1421 1422static void 1423rl_intr(arg) 1424 void *arg; 1425{ 1426 struct rl_softc *sc; 1427 struct ifnet *ifp; 1428 u_int16_t status; 1429 1430 sc = arg; 1431 1432 if (sc->suspended) { 1433 return; 1434 } 1435 1436 RL_LOCK(sc); 1437 ifp = &sc->arpcom.ac_if; 1438 1439#ifdef DEVICE_POLLING 1440 if (ifp->if_flags & IFF_POLLING) 1441 goto done; 1442 if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 1443 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1444 rl_poll(ifp, 0, 1); 1445 goto done; 1446 } 1447#endif /* DEVICE_POLLING */ 1448 1449 for (;;) { 1450 1451 status = CSR_READ_2(sc, RL_ISR); 1452 /* If the card has gone away the read returns 0xffff. */ 1453 if (status == 0xffff) 1454 break; 1455 if (status) 1456 CSR_WRITE_2(sc, RL_ISR, status); 1457 1458 if ((status & RL_INTRS) == 0) 1459 break; 1460 1461 if (status & RL_ISR_RX_OK) 1462 rl_rxeof(sc); 1463 1464 if (status & RL_ISR_RX_ERR) 1465 rl_rxeof(sc); 1466 1467 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1468 rl_txeof(sc); 1469 1470 if (status & RL_ISR_SYSTEM_ERR) { 1471 rl_reset(sc); 1472 rl_init(sc); 1473 } 1474 1475 } 1476 1477 if (ifp->if_snd.ifq_head != NULL) 1478 rl_start(ifp); 1479 1480#ifdef DEVICE_POLLING 1481done: 1482#endif 1483 RL_UNLOCK(sc); 1484 1485 return; 1486} 1487 1488/* 1489 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1490 * pointers to the fragment pointers. 1491 */ 1492static int 1493rl_encap(sc, m_head) 1494 struct rl_softc *sc; 1495 struct mbuf *m_head; 1496{ 1497 struct mbuf *m_new = NULL; 1498 1499 /* 1500 * The RealTek is brain damaged and wants longword-aligned 1501 * TX buffers, plus we can only have one fragment buffer 1502 * per packet. We have to copy pretty much all the time. 1503 */ 1504 1505 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1506 if (m_new == NULL) 1507 return(1); 1508 if (m_head->m_pkthdr.len > MHLEN) { 1509 MCLGET(m_new, M_DONTWAIT); 1510 if (!(m_new->m_flags & M_EXT)) { 1511 m_freem(m_new); 1512 return(1); 1513 } 1514 } 1515 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1516 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1517 m_freem(m_head); 1518 m_head = m_new; 1519 1520 /* Pad frames to at least 60 bytes. */ 1521 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1522 /* 1523 * Make security concious people happy: zero out the 1524 * bytes in the pad area, since we don't know what 1525 * this mbuf cluster buffer's previous user might 1526 * have left in it. 1527 */ 1528 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1529 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1530 m_head->m_pkthdr.len += 1531 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1532 m_head->m_len = m_head->m_pkthdr.len; 1533 } 1534 1535 RL_CUR_TXMBUF(sc) = m_head; 1536 1537 return(0); 1538} 1539 1540/* 1541 * Main transmit routine. 1542 */ 1543 1544static void 1545rl_start(ifp) 1546 struct ifnet *ifp; 1547{ 1548 struct rl_softc *sc; 1549 struct mbuf *m_head = NULL; 1550 1551 sc = ifp->if_softc; 1552 RL_LOCK(sc); 1553 1554 while(RL_CUR_TXMBUF(sc) == NULL) { 1555 IF_DEQUEUE(&ifp->if_snd, m_head); 1556 if (m_head == NULL) 1557 break; 1558 1559 if (rl_encap(sc, m_head)) { 1560 IF_PREPEND(&ifp->if_snd, m_head); 1561 ifp->if_flags |= IFF_OACTIVE; 1562 break; 1563 } 1564 1565 /* 1566 * If there's a BPF listener, bounce a copy of this frame 1567 * to him. 1568 */ 1569 if (ifp->if_bpf) 1570 bpf_mtap(ifp, RL_CUR_TXMBUF(sc)); 1571 1572 /* 1573 * Transmit the frame. 1574 */ 1575 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1576 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1577 mtod(RL_CUR_TXMBUF(sc), void *), 1578 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 1579 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1580 BUS_DMASYNC_PREREAD); 1581 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1582 RL_TXTHRESH(sc->rl_txthresh) | 1583 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1584 1585 RL_INC(sc->rl_cdata.cur_tx); 1586 } 1587 1588 /* 1589 * We broke out of the loop because all our TX slots are 1590 * full. Mark the NIC as busy until it drains some of the 1591 * packets from the queue. 1592 */ 1593 if (RL_CUR_TXMBUF(sc) != NULL) 1594 ifp->if_flags |= IFF_OACTIVE; 1595 1596 /* 1597 * Set a timeout in case the chip goes out to lunch. 1598 */ 1599 ifp->if_timer = 5; 1600 RL_UNLOCK(sc); 1601 1602 return; 1603} 1604 1605static void 1606rl_init(xsc) 1607 void *xsc; 1608{ 1609 struct rl_softc *sc = xsc; 1610 struct ifnet *ifp = &sc->arpcom.ac_if; 1611 struct mii_data *mii; 1612 int i; 1613 u_int32_t rxcfg = 0; 1614 1615 RL_LOCK(sc); 1616 mii = device_get_softc(sc->rl_miibus); 1617 1618 /* 1619 * Cancel pending I/O and free all RX/TX buffers. 1620 */ 1621 rl_stop(sc); 1622 1623 /* Init our MAC address */ 1624 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1625 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 1626 } 1627 1628 /* Init the RX buffer pointer register. */ 1629 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1630 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 1631 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1632 BUS_DMASYNC_PREWRITE); 1633 1634 /* Init TX descriptors. */ 1635 rl_list_tx_init(sc); 1636 1637 /* 1638 * Enable transmit and receive. 1639 */ 1640 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1641 1642 /* 1643 * Set the initial TX and RX configuration. 1644 */ 1645 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1646 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1647 1648 /* Set the individual bit to receive frames for this host only. */ 1649 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1650 rxcfg |= RL_RXCFG_RX_INDIV; 1651 1652 /* If we want promiscuous mode, set the allframes bit. */ 1653 if (ifp->if_flags & IFF_PROMISC) { 1654 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1655 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1656 } else { 1657 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1658 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1659 } 1660 1661 /* 1662 * Set capture broadcast bit to capture broadcast frames. 1663 */ 1664 if (ifp->if_flags & IFF_BROADCAST) { 1665 rxcfg |= RL_RXCFG_RX_BROAD; 1666 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1667 } else { 1668 rxcfg &= ~RL_RXCFG_RX_BROAD; 1669 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1670 } 1671 1672 /* 1673 * Program the multicast filter, if necessary. 1674 */ 1675 rl_setmulti(sc); 1676 1677#ifdef DEVICE_POLLING 1678 /* 1679 * Disable interrupts if we are polling. 1680 */ 1681 if (ifp->if_flags & IFF_POLLING) 1682 CSR_WRITE_2(sc, RL_IMR, 0); 1683 else /* otherwise ... */ 1684#endif /* DEVICE_POLLING */ 1685 /* 1686 * Enable interrupts. 1687 */ 1688 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1689 1690 /* Set initial TX threshold */ 1691 sc->rl_txthresh = RL_TX_THRESH_INIT; 1692 1693 /* Start RX/TX process. */ 1694 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1695 1696 /* Enable receiver and transmitter. */ 1697 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1698 1699 mii_mediachg(mii); 1700 1701 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1702 1703 ifp->if_flags |= IFF_RUNNING; 1704 ifp->if_flags &= ~IFF_OACTIVE; 1705 1706 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1707 RL_UNLOCK(sc); 1708 1709 return; 1710} 1711 1712/* 1713 * Set media options. 1714 */ 1715static int 1716rl_ifmedia_upd(ifp) 1717 struct ifnet *ifp; 1718{ 1719 struct rl_softc *sc; 1720 struct mii_data *mii; 1721 1722 sc = ifp->if_softc; 1723 mii = device_get_softc(sc->rl_miibus); 1724 mii_mediachg(mii); 1725 1726 return(0); 1727} 1728 1729/* 1730 * Report current media status. 1731 */ 1732static void 1733rl_ifmedia_sts(ifp, ifmr) 1734 struct ifnet *ifp; 1735 struct ifmediareq *ifmr; 1736{ 1737 struct rl_softc *sc; 1738 struct mii_data *mii; 1739 1740 sc = ifp->if_softc; 1741 mii = device_get_softc(sc->rl_miibus); 1742 1743 mii_pollstat(mii); 1744 ifmr->ifm_active = mii->mii_media_active; 1745 ifmr->ifm_status = mii->mii_media_status; 1746 1747 return; 1748} 1749 1750static int 1751rl_ioctl(ifp, command, data) 1752 struct ifnet *ifp; 1753 u_long command; 1754 caddr_t data; 1755{ 1756 struct rl_softc *sc = ifp->if_softc; 1757 struct ifreq *ifr = (struct ifreq *) data; 1758 struct mii_data *mii; 1759 int error = 0; 1760 1761 RL_LOCK(sc); 1762 1763 switch(command) { 1764 case SIOCSIFADDR: 1765 case SIOCGIFADDR: 1766 case SIOCSIFMTU: 1767 error = ether_ioctl(ifp, command, data); 1768 break; 1769 case SIOCSIFFLAGS: 1770 if (ifp->if_flags & IFF_UP) { 1771 rl_init(sc); 1772 } else { 1773 if (ifp->if_flags & IFF_RUNNING) 1774 rl_stop(sc); 1775 } 1776 error = 0; 1777 break; 1778 case SIOCADDMULTI: 1779 case SIOCDELMULTI: 1780 rl_setmulti(sc); 1781 error = 0; 1782 break; 1783 case SIOCGIFMEDIA: 1784 case SIOCSIFMEDIA: 1785 mii = device_get_softc(sc->rl_miibus); 1786 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1787 break; 1788 default: 1789 error = EINVAL; 1790 break; 1791 } 1792 1793 RL_UNLOCK(sc); 1794 1795 return(error); 1796} 1797 1798static void 1799rl_watchdog(ifp) 1800 struct ifnet *ifp; 1801{ 1802 struct rl_softc *sc; 1803 1804 sc = ifp->if_softc; 1805 RL_LOCK(sc); 1806 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1807 ifp->if_oerrors++; 1808 1809 rl_txeof(sc); 1810 rl_rxeof(sc); 1811 rl_init(sc); 1812 RL_UNLOCK(sc); 1813 1814 return; 1815} 1816 1817/* 1818 * Stop the adapter and free any mbufs allocated to the 1819 * RX and TX lists. 1820 */ 1821static void 1822rl_stop(sc) 1823 struct rl_softc *sc; 1824{ 1825 register int i; 1826 struct ifnet *ifp; 1827 1828 RL_LOCK(sc); 1829 ifp = &sc->arpcom.ac_if; 1830 ifp->if_timer = 0; 1831 1832 untimeout(rl_tick, sc, sc->rl_stat_ch); 1833 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1834#ifdef DEVICE_POLLING 1835 ether_poll_deregister(ifp); 1836#endif /* DEVICE_POLLING */ 1837 1838 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1839 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1840 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1841 1842 /* 1843 * Free the TX list buffers. 1844 */ 1845 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1846 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1847 bus_dmamap_unload(sc->rl_tag, 1848 sc->rl_cdata.rl_tx_dmamap[i]); 1849 bus_dmamap_destroy(sc->rl_tag, 1850 sc->rl_cdata.rl_tx_dmamap[i]); 1851 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1852 sc->rl_cdata.rl_tx_chain[i] = NULL; 1853 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1854 } 1855 } 1856 1857 RL_UNLOCK(sc); 1858 return; 1859} 1860 1861/* 1862 * Device suspend routine. Stop the interface and save some PCI 1863 * settings in case the BIOS doesn't restore them properly on 1864 * resume. 1865 */ 1866static int 1867rl_suspend(dev) 1868 device_t dev; 1869{ 1870 register int i; 1871 struct rl_softc *sc; 1872 1873 sc = device_get_softc(dev); 1874 1875 rl_stop(sc); 1876 1877 for (i = 0; i < 5; i++) 1878 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 1879 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1880 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1881 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1882 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1883 1884 sc->suspended = 1; 1885 1886 return (0); 1887} 1888 1889/* 1890 * Device resume routine. Restore some PCI settings in case the BIOS 1891 * doesn't, re-enable busmastering, and restart the interface if 1892 * appropriate. 1893 */ 1894static int 1895rl_resume(dev) 1896 device_t dev; 1897{ 1898 register int i; 1899 struct rl_softc *sc; 1900 struct ifnet *ifp; 1901 1902 sc = device_get_softc(dev); 1903 ifp = &sc->arpcom.ac_if; 1904 1905 /* better way to do this? */ 1906 for (i = 0; i < 5; i++) 1907 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 1908 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1909 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1910 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1911 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1912 1913 /* reenable busmastering */ 1914 pci_enable_busmaster(dev); 1915 pci_enable_io(dev, RL_RES); 1916 1917 /* reinitialize interface if necessary */ 1918 if (ifp->if_flags & IFF_UP) 1919 rl_init(sc); 1920 1921 sc->suspended = 0; 1922 1923 return (0); 1924} 1925 1926/* 1927 * Stop all chip I/O so that the kernel's probe routines don't 1928 * get confused by errant DMAs when rebooting. 1929 */ 1930static void 1931rl_shutdown(dev) 1932 device_t dev; 1933{ 1934 struct rl_softc *sc; 1935 1936 sc = device_get_softc(dev); 1937 1938 rl_stop(sc); 1939 1940 return; 1941} 1942