rt2860.c revision 288087
1/*- 2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $OpenBSD: rt2860.c,v 1.65 2010/10/23 14:24:54 damien Exp $ 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/ral/rt2860.c 288087 2015-09-22 02:44:59Z adrian $"); 22 23/*- 24 * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28#include <sys/param.h> 29#include <sys/sysctl.h> 30#include <sys/sockio.h> 31#include <sys/mbuf.h> 32#include <sys/kernel.h> 33#include <sys/socket.h> 34#include <sys/systm.h> 35#include <sys/malloc.h> 36#include <sys/lock.h> 37#include <sys/mutex.h> 38#include <sys/module.h> 39#include <sys/bus.h> 40#include <sys/endian.h> 41#include <sys/firmware.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <sys/rman.h> 46 47#include <net/bpf.h> 48#include <net/if.h> 49#include <net/if_var.h> 50#include <net/if_arp.h> 51#include <net/ethernet.h> 52#include <net/if_dl.h> 53#include <net/if_media.h> 54#include <net/if_types.h> 55 56#include <net80211/ieee80211_var.h> 57#include <net80211/ieee80211_radiotap.h> 58#include <net80211/ieee80211_regdomain.h> 59#include <net80211/ieee80211_ratectl.h> 60 61#include <netinet/in.h> 62#include <netinet/in_systm.h> 63#include <netinet/in_var.h> 64#include <netinet/ip.h> 65#include <netinet/if_ether.h> 66 67#include <dev/ral/rt2860reg.h> 68#include <dev/ral/rt2860var.h> 69 70#define RAL_DEBUG 71#ifdef RAL_DEBUG 72#define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0) 73#define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0) 74#else 75#define DPRINTF(x) 76#define DPRINTFN(n, x) 77#endif 78 79static struct ieee80211vap *rt2860_vap_create(struct ieee80211com *, 80 const char [IFNAMSIZ], int, enum ieee80211_opmode, 81 int, const uint8_t [IEEE80211_ADDR_LEN], 82 const uint8_t [IEEE80211_ADDR_LEN]); 83static void rt2860_vap_delete(struct ieee80211vap *); 84static void rt2860_dma_map_addr(void *, bus_dma_segment_t *, int, int); 85static int rt2860_alloc_tx_ring(struct rt2860_softc *, 86 struct rt2860_tx_ring *); 87static void rt2860_reset_tx_ring(struct rt2860_softc *, 88 struct rt2860_tx_ring *); 89static void rt2860_free_tx_ring(struct rt2860_softc *, 90 struct rt2860_tx_ring *); 91static int rt2860_alloc_tx_pool(struct rt2860_softc *); 92static void rt2860_free_tx_pool(struct rt2860_softc *); 93static int rt2860_alloc_rx_ring(struct rt2860_softc *, 94 struct rt2860_rx_ring *); 95static void rt2860_reset_rx_ring(struct rt2860_softc *, 96 struct rt2860_rx_ring *); 97static void rt2860_free_rx_ring(struct rt2860_softc *, 98 struct rt2860_rx_ring *); 99static void rt2860_updatestats(struct rt2860_softc *); 100static void rt2860_newassoc(struct ieee80211_node *, int); 101static void rt2860_node_free(struct ieee80211_node *); 102#ifdef IEEE80211_HT 103static int rt2860_ampdu_rx_start(struct ieee80211com *, 104 struct ieee80211_node *, uint8_t); 105static void rt2860_ampdu_rx_stop(struct ieee80211com *, 106 struct ieee80211_node *, uint8_t); 107#endif 108static int rt2860_newstate(struct ieee80211vap *, enum ieee80211_state, 109 int); 110static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 111static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 112static void rt2860_intr_coherent(struct rt2860_softc *); 113static void rt2860_drain_stats_fifo(struct rt2860_softc *); 114static void rt2860_tx_intr(struct rt2860_softc *, int); 115static void rt2860_rx_intr(struct rt2860_softc *); 116static void rt2860_tbtt_intr(struct rt2860_softc *); 117static void rt2860_gp_intr(struct rt2860_softc *); 118static int rt2860_tx(struct rt2860_softc *, struct mbuf *, 119 struct ieee80211_node *); 120static int rt2860_raw_xmit(struct ieee80211_node *, struct mbuf *, 121 const struct ieee80211_bpf_params *); 122static int rt2860_tx_raw(struct rt2860_softc *, struct mbuf *, 123 struct ieee80211_node *, 124 const struct ieee80211_bpf_params *params); 125static int rt2860_transmit(struct ieee80211com *, struct mbuf *); 126static void rt2860_start(struct rt2860_softc *); 127static void rt2860_watchdog(void *); 128static void rt2860_parent(struct ieee80211com *); 129static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 130static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 131static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 132static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 133static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 134static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 135static void rt2860_enable_mrr(struct rt2860_softc *); 136static void rt2860_set_txpreamble(struct rt2860_softc *); 137static void rt2860_set_basicrates(struct rt2860_softc *, 138 const struct ieee80211_rateset *); 139static void rt2860_scan_start(struct ieee80211com *); 140static void rt2860_scan_end(struct ieee80211com *); 141static void rt2860_set_channel(struct ieee80211com *); 142static void rt2860_select_chan_group(struct rt2860_softc *, int); 143static void rt2860_set_chan(struct rt2860_softc *, u_int); 144static void rt3090_set_chan(struct rt2860_softc *, u_int); 145static void rt5390_set_chan(struct rt2860_softc *, u_int); 146static int rt3090_rf_init(struct rt2860_softc *); 147static void rt5390_rf_init(struct rt2860_softc *); 148static void rt3090_rf_wakeup(struct rt2860_softc *); 149static void rt5390_rf_wakeup(struct rt2860_softc *); 150static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 151 uint8_t *); 152static void rt3090_rf_setup(struct rt2860_softc *); 153static void rt2860_set_leds(struct rt2860_softc *, uint16_t); 154static void rt2860_set_gp_timer(struct rt2860_softc *, int); 155static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 156static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 157static void rt2860_update_promisc(struct ieee80211com *); 158static void rt2860_updateslot(struct ieee80211com *); 159static void rt2860_updateprot(struct rt2860_softc *); 160static int rt2860_updateedca(struct ieee80211com *); 161#ifdef HW_CRYPTO 162static int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *, 163 struct ieee80211_key *); 164static void rt2860_delete_key(struct ieee80211com *, 165 struct ieee80211_node *, struct ieee80211_key *); 166#endif 167static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 168static const char *rt2860_get_rf(uint8_t); 169static int rt2860_read_eeprom(struct rt2860_softc *, 170 uint8_t macaddr[IEEE80211_ADDR_LEN]); 171static int rt2860_bbp_init(struct rt2860_softc *); 172static void rt5390_bbp_init(struct rt2860_softc *); 173static int rt2860_txrx_enable(struct rt2860_softc *); 174static void rt2860_init(void *); 175static void rt2860_init_locked(struct rt2860_softc *); 176static void rt2860_stop(void *); 177static void rt2860_stop_locked(struct rt2860_softc *); 178static int rt2860_load_microcode(struct rt2860_softc *); 179#ifdef NOT_YET 180static void rt2860_calib(struct rt2860_softc *); 181#endif 182static void rt3090_set_rx_antenna(struct rt2860_softc *, int); 183static void rt2860_switch_chan(struct rt2860_softc *, 184 struct ieee80211_channel *); 185static int rt2860_setup_beacon(struct rt2860_softc *, 186 struct ieee80211vap *); 187static void rt2860_enable_tsf_sync(struct rt2860_softc *); 188 189static const struct { 190 uint32_t reg; 191 uint32_t val; 192} rt2860_def_mac[] = { 193 RT2860_DEF_MAC 194}; 195 196static const struct { 197 uint8_t reg; 198 uint8_t val; 199} rt2860_def_bbp[] = { 200 RT2860_DEF_BBP 201}, rt5390_def_bbp[] = { 202 RT5390_DEF_BBP 203}; 204 205static const struct rfprog { 206 uint8_t chan; 207 uint32_t r1, r2, r3, r4; 208} rt2860_rf2850[] = { 209 RT2860_RF2850 210}; 211 212struct { 213 uint8_t n, r, k; 214} rt3090_freqs[] = { 215 RT3070_RF3052 216}; 217 218static const struct { 219 uint8_t reg; 220 uint8_t val; 221} rt3090_def_rf[] = { 222 RT3070_DEF_RF 223}, rt5390_def_rf[] = { 224 RT5390_DEF_RF 225}, rt5392_def_rf[] = { 226 RT5392_DEF_RF 227}; 228 229int 230rt2860_attach(device_t dev, int id) 231{ 232 struct rt2860_softc *sc = device_get_softc(dev); 233 struct ieee80211com *ic = &sc->sc_ic; 234 uint32_t tmp; 235 int error, ntries, qid; 236 uint8_t bands; 237 238 sc->sc_dev = dev; 239 sc->sc_debug = 0; 240 241 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 242 MTX_DEF | MTX_RECURSE); 243 244 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 245 mbufq_init(&sc->sc_snd, ifqmaxlen); 246 247 /* wait for NIC to initialize */ 248 for (ntries = 0; ntries < 100; ntries++) { 249 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID); 250 if (tmp != 0 && tmp != 0xffffffff) 251 break; 252 DELAY(10); 253 } 254 if (ntries == 100) { 255 device_printf(sc->sc_dev, 256 "timeout waiting for NIC to initialize\n"); 257 error = EIO; 258 goto fail1; 259 } 260 sc->mac_ver = tmp >> 16; 261 sc->mac_rev = tmp & 0xffff; 262 263 if (sc->mac_ver != 0x2860 && 264 (id == 0x0681 || id == 0x0781 || id == 0x1059)) 265 sc->sc_flags |= RT2860_ADVANCED_PS; 266 267 /* retrieve RF rev. no and various other things from EEPROM */ 268 rt2860_read_eeprom(sc, ic->ic_macaddr); 269 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), " 270 "RF %s (MIMO %dT%dR), address %6D\n", 271 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev), 272 sc->ntxchains, sc->nrxchains, ic->ic_macaddr, ":"); 273 274 /* 275 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 276 */ 277 for (qid = 0; qid < 6; qid++) { 278 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 279 device_printf(sc->sc_dev, 280 "could not allocate Tx ring %d\n", qid); 281 goto fail2; 282 } 283 } 284 285 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 286 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 287 goto fail2; 288 } 289 290 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 291 device_printf(sc->sc_dev, "could not allocate Tx pool\n"); 292 goto fail3; 293 } 294 295 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 296 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 297 WME_AC_VO : 5; 298 299 ic->ic_softc = sc; 300 ic->ic_name = device_get_nameunit(dev); 301 ic->ic_opmode = IEEE80211_M_STA; 302 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 303 304 /* set device capabilities */ 305 ic->ic_caps = 306 IEEE80211_C_STA /* station mode */ 307 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 308 | IEEE80211_C_HOSTAP /* hostap mode */ 309 | IEEE80211_C_MONITOR /* monitor mode */ 310 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 311 | IEEE80211_C_WDS /* 4-address traffic works */ 312 | IEEE80211_C_MBSS /* mesh point link mode */ 313 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 314 | IEEE80211_C_SHSLOT /* short slot time supported */ 315 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 316#if 0 317 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 318#endif 319 | IEEE80211_C_WME /* 802.11e */ 320 ; 321 322 bands = 0; 323 setbit(&bands, IEEE80211_MODE_11B); 324 setbit(&bands, IEEE80211_MODE_11G); 325 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) 326 setbit(&bands, IEEE80211_MODE_11A); 327 ieee80211_init_channels(ic, NULL, &bands); 328 329 ieee80211_ifattach(ic); 330 331 ic->ic_wme.wme_update = rt2860_updateedca; 332 ic->ic_scan_start = rt2860_scan_start; 333 ic->ic_scan_end = rt2860_scan_end; 334 ic->ic_set_channel = rt2860_set_channel; 335 ic->ic_updateslot = rt2860_updateslot; 336 ic->ic_update_promisc = rt2860_update_promisc; 337 ic->ic_raw_xmit = rt2860_raw_xmit; 338 sc->sc_node_free = ic->ic_node_free; 339 ic->ic_node_free = rt2860_node_free; 340 ic->ic_newassoc = rt2860_newassoc; 341 ic->ic_transmit = rt2860_transmit; 342 ic->ic_parent = rt2860_parent; 343 ic->ic_vap_create = rt2860_vap_create; 344 ic->ic_vap_delete = rt2860_vap_delete; 345 346 ieee80211_radiotap_attach(ic, 347 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 348 RT2860_TX_RADIOTAP_PRESENT, 349 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 350 RT2860_RX_RADIOTAP_PRESENT); 351 352#ifdef RAL_DEBUG 353 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 354 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 355 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 356#endif 357 if (bootverbose) 358 ieee80211_announce(ic); 359 360 return 0; 361 362fail3: rt2860_free_rx_ring(sc, &sc->rxq); 363fail2: while (--qid >= 0) 364 rt2860_free_tx_ring(sc, &sc->txq[qid]); 365fail1: mtx_destroy(&sc->sc_mtx); 366 return error; 367} 368 369int 370rt2860_detach(void *xsc) 371{ 372 struct rt2860_softc *sc = xsc; 373 struct ieee80211com *ic = &sc->sc_ic; 374 int qid; 375 376 RAL_LOCK(sc); 377 rt2860_stop_locked(sc); 378 RAL_UNLOCK(sc); 379 380 ieee80211_ifdetach(ic); 381 mbufq_drain(&sc->sc_snd); 382 for (qid = 0; qid < 6; qid++) 383 rt2860_free_tx_ring(sc, &sc->txq[qid]); 384 rt2860_free_rx_ring(sc, &sc->rxq); 385 rt2860_free_tx_pool(sc); 386 387 mtx_destroy(&sc->sc_mtx); 388 389 return 0; 390} 391 392void 393rt2860_shutdown(void *xsc) 394{ 395 struct rt2860_softc *sc = xsc; 396 397 rt2860_stop(sc); 398} 399 400void 401rt2860_suspend(void *xsc) 402{ 403 struct rt2860_softc *sc = xsc; 404 405 rt2860_stop(sc); 406} 407 408void 409rt2860_resume(void *xsc) 410{ 411 struct rt2860_softc *sc = xsc; 412 413 if (sc->sc_ic.ic_nrunning > 0) 414 rt2860_init(sc); 415} 416 417static struct ieee80211vap * 418rt2860_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 419 enum ieee80211_opmode opmode, int flags, 420 const uint8_t bssid[IEEE80211_ADDR_LEN], 421 const uint8_t mac[IEEE80211_ADDR_LEN]) 422{ 423 struct rt2860_softc *sc = ic->ic_softc; 424 struct rt2860_vap *rvp; 425 struct ieee80211vap *vap; 426 427 switch (opmode) { 428 case IEEE80211_M_STA: 429 case IEEE80211_M_IBSS: 430 case IEEE80211_M_AHDEMO: 431 case IEEE80211_M_MONITOR: 432 case IEEE80211_M_HOSTAP: 433 case IEEE80211_M_MBSS: 434 /* XXXRP: TBD */ 435 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 436 device_printf(sc->sc_dev, "only 1 vap supported\n"); 437 return NULL; 438 } 439 if (opmode == IEEE80211_M_STA) 440 flags |= IEEE80211_CLONE_NOBEACONS; 441 break; 442 case IEEE80211_M_WDS: 443 if (TAILQ_EMPTY(&ic->ic_vaps) || 444 ic->ic_opmode != IEEE80211_M_HOSTAP) { 445 device_printf(sc->sc_dev, 446 "wds only supported in ap mode\n"); 447 return NULL; 448 } 449 /* 450 * Silently remove any request for a unique 451 * bssid; WDS vap's always share the local 452 * mac address. 453 */ 454 flags &= ~IEEE80211_CLONE_BSSID; 455 break; 456 default: 457 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 458 return NULL; 459 } 460 rvp = malloc(sizeof(struct rt2860_vap), M_80211_VAP, M_WAITOK | M_ZERO); 461 vap = &rvp->ral_vap; 462 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 463 464 /* override state transition machine */ 465 rvp->ral_newstate = vap->iv_newstate; 466 vap->iv_newstate = rt2860_newstate; 467#if 0 468 vap->iv_update_beacon = rt2860_beacon_update; 469#endif 470 471 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 472 vap->iv_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 473 474 ieee80211_ratectl_init(vap); 475 /* complete setup */ 476 ieee80211_vap_attach(vap, ieee80211_media_change, 477 ieee80211_media_status, mac); 478 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 479 ic->ic_opmode = opmode; 480 return vap; 481} 482 483static void 484rt2860_vap_delete(struct ieee80211vap *vap) 485{ 486 struct rt2860_vap *rvp = RT2860_VAP(vap); 487 488 ieee80211_ratectl_deinit(vap); 489 ieee80211_vap_detach(vap); 490 free(rvp, M_80211_VAP); 491} 492 493static void 494rt2860_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 495{ 496 if (error != 0) 497 return; 498 499 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 500 501 *(bus_addr_t *)arg = segs[0].ds_addr; 502} 503 504 505static int 506rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 507{ 508 int size, error; 509 510 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 511 512 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 513 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 514 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 515 if (error != 0) { 516 device_printf(sc->sc_dev, "could not create desc DMA map\n"); 517 goto fail; 518 } 519 520 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->txd, 521 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 522 if (error != 0) { 523 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 524 goto fail; 525 } 526 527 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->txd, 528 size, rt2860_dma_map_addr, &ring->paddr, 0); 529 if (error != 0) { 530 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 531 goto fail; 532 } 533 534 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 535 536 return 0; 537 538fail: rt2860_free_tx_ring(sc, ring); 539 return error; 540} 541 542void 543rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 544{ 545 struct rt2860_tx_data *data; 546 int i; 547 548 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 549 if ((data = ring->data[i]) == NULL) 550 continue; /* nothing mapped in this slot */ 551 552 if (data->m != NULL) { 553 bus_dmamap_sync(sc->txwi_dmat, data->map, 554 BUS_DMASYNC_POSTWRITE); 555 bus_dmamap_unload(sc->txwi_dmat, data->map); 556 m_freem(data->m); 557 data->m = NULL; 558 } 559 if (data->ni != NULL) { 560 ieee80211_free_node(data->ni); 561 data->ni = NULL; 562 } 563 564 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 565 ring->data[i] = NULL; 566 } 567 568 ring->queued = 0; 569 ring->cur = ring->next = 0; 570} 571 572void 573rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 574{ 575 struct rt2860_tx_data *data; 576 int i; 577 578 if (ring->txd != NULL) { 579 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 580 BUS_DMASYNC_POSTWRITE); 581 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 582 bus_dmamem_free(ring->desc_dmat, ring->txd, ring->desc_map); 583 } 584 if (ring->desc_dmat != NULL) 585 bus_dma_tag_destroy(ring->desc_dmat); 586 587 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 588 if ((data = ring->data[i]) == NULL) 589 continue; /* nothing mapped in this slot */ 590 591 if (data->m != NULL) { 592 bus_dmamap_sync(sc->txwi_dmat, data->map, 593 BUS_DMASYNC_POSTWRITE); 594 bus_dmamap_unload(sc->txwi_dmat, data->map); 595 m_freem(data->m); 596 } 597 if (data->ni != NULL) 598 ieee80211_free_node(data->ni); 599 600 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 601 } 602} 603 604/* 605 * Allocate a pool of TX Wireless Information blocks. 606 */ 607int 608rt2860_alloc_tx_pool(struct rt2860_softc *sc) 609{ 610 caddr_t vaddr; 611 bus_addr_t paddr; 612 int i, size, error; 613 614 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 615 616 /* init data_pool early in case of failure.. */ 617 SLIST_INIT(&sc->data_pool); 618 619 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 620 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 621 size, 1, size, 0, NULL, NULL, &sc->txwi_dmat); 622 if (error != 0) { 623 device_printf(sc->sc_dev, "could not create txwi DMA tag\n"); 624 goto fail; 625 } 626 627 error = bus_dmamem_alloc(sc->txwi_dmat, (void **)&sc->txwi_vaddr, 628 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->txwi_map); 629 if (error != 0) { 630 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 631 goto fail; 632 } 633 634 error = bus_dmamap_load(sc->txwi_dmat, sc->txwi_map, 635 sc->txwi_vaddr, size, rt2860_dma_map_addr, &paddr, 0); 636 if (error != 0) { 637 device_printf(sc->sc_dev, "could not load txwi DMA map\n"); 638 goto fail; 639 } 640 641 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 642 643 vaddr = sc->txwi_vaddr; 644 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 645 struct rt2860_tx_data *data = &sc->data[i]; 646 647 error = bus_dmamap_create(sc->txwi_dmat, 0, &data->map); 648 if (error != 0) { 649 device_printf(sc->sc_dev, "could not create DMA map\n"); 650 goto fail; 651 } 652 data->txwi = (struct rt2860_txwi *)vaddr; 653 data->paddr = paddr; 654 vaddr += RT2860_TXWI_DMASZ; 655 paddr += RT2860_TXWI_DMASZ; 656 657 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 658 } 659 660 return 0; 661 662fail: rt2860_free_tx_pool(sc); 663 return error; 664} 665 666void 667rt2860_free_tx_pool(struct rt2860_softc *sc) 668{ 669 if (sc->txwi_vaddr != NULL) { 670 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, 671 BUS_DMASYNC_POSTWRITE); 672 bus_dmamap_unload(sc->txwi_dmat, sc->txwi_map); 673 bus_dmamem_free(sc->txwi_dmat, sc->txwi_vaddr, sc->txwi_map); 674 } 675 if (sc->txwi_dmat != NULL) 676 bus_dma_tag_destroy(sc->txwi_dmat); 677 678 while (!SLIST_EMPTY(&sc->data_pool)) { 679 struct rt2860_tx_data *data; 680 data = SLIST_FIRST(&sc->data_pool); 681 bus_dmamap_destroy(sc->txwi_dmat, data->map); 682 SLIST_REMOVE_HEAD(&sc->data_pool, next); 683 } 684} 685 686int 687rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 688{ 689 bus_addr_t physaddr; 690 int i, size, error; 691 692 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 693 694 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 695 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 696 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 697 if (error != 0) { 698 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 699 goto fail; 700 } 701 702 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->rxd, 703 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 704 if (error != 0) { 705 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 706 goto fail; 707 } 708 709 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->rxd, 710 size, rt2860_dma_map_addr, &ring->paddr, 0); 711 if (error != 0) { 712 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 713 goto fail; 714 } 715 716 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 717 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 718 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 719 if (error != 0) { 720 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 721 goto fail; 722 } 723 724 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 725 struct rt2860_rx_data *data = &ring->data[i]; 726 struct rt2860_rxd *rxd = &ring->rxd[i]; 727 728 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 729 if (error != 0) { 730 device_printf(sc->sc_dev, "could not create DMA map\n"); 731 goto fail; 732 } 733 734 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 735 if (data->m == NULL) { 736 device_printf(sc->sc_dev, 737 "could not allocate rx mbuf\n"); 738 error = ENOMEM; 739 goto fail; 740 } 741 742 error = bus_dmamap_load(ring->data_dmat, data->map, 743 mtod(data->m, void *), MCLBYTES, rt2860_dma_map_addr, 744 &physaddr, 0); 745 if (error != 0) { 746 device_printf(sc->sc_dev, 747 "could not load rx buf DMA map"); 748 goto fail; 749 } 750 751 rxd->sdp0 = htole32(physaddr); 752 rxd->sdl0 = htole16(MCLBYTES); 753 } 754 755 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 756 757 return 0; 758 759fail: rt2860_free_rx_ring(sc, ring); 760 return error; 761} 762 763void 764rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 765{ 766 int i; 767 768 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 769 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 770 771 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 772 773 ring->cur = 0; 774} 775 776void 777rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 778{ 779 int i; 780 781 if (ring->rxd != NULL) { 782 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 783 BUS_DMASYNC_POSTWRITE); 784 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 785 bus_dmamem_free(ring->desc_dmat, ring->rxd, ring->desc_map); 786 } 787 if (ring->desc_dmat != NULL) 788 bus_dma_tag_destroy(ring->desc_dmat); 789 790 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 791 struct rt2860_rx_data *data = &ring->data[i]; 792 793 if (data->m != NULL) { 794 bus_dmamap_sync(ring->data_dmat, data->map, 795 BUS_DMASYNC_POSTREAD); 796 bus_dmamap_unload(ring->data_dmat, data->map); 797 m_freem(data->m); 798 } 799 if (data->map != NULL) 800 bus_dmamap_destroy(ring->data_dmat, data->map); 801 } 802 if (ring->data_dmat != NULL) 803 bus_dma_tag_destroy(ring->data_dmat); 804} 805 806static void 807rt2860_updatestats(struct rt2860_softc *sc) 808{ 809 struct ieee80211com *ic = &sc->sc_ic; 810 811 /* 812 * In IBSS or HostAP modes (when the hardware sends beacons), the 813 * MAC can run into a livelock and start sending CTS-to-self frames 814 * like crazy if protection is enabled. Fortunately, we can detect 815 * when such a situation occurs and reset the MAC. 816 */ 817 if (ic->ic_curmode != IEEE80211_M_STA) { 818 /* check if we're in a livelock situation.. */ 819 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 820 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 821 /* ..and reset MAC/BBP for a while.. */ 822 DPRINTF(("CTS-to-self livelock detected\n")); 823 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 824 RAL_BARRIER_WRITE(sc); 825 DELAY(1); 826 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 827 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 828 } 829 } 830} 831 832static void 833rt2860_newassoc(struct ieee80211_node *ni, int isnew) 834{ 835 struct ieee80211com *ic = ni->ni_ic; 836 struct rt2860_softc *sc = ic->ic_softc; 837 uint8_t wcid; 838 839 wcid = IEEE80211_AID(ni->ni_associd); 840 if (isnew && ni->ni_associd != 0) { 841 sc->wcid2ni[wcid] = ni; 842 843 /* init WCID table entry */ 844 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 845 ni->ni_macaddr, IEEE80211_ADDR_LEN); 846 } 847 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 848 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 849} 850 851static void 852rt2860_node_free(struct ieee80211_node *ni) 853{ 854 struct ieee80211com *ic = ni->ni_ic; 855 struct rt2860_softc *sc = ic->ic_softc; 856 uint8_t wcid; 857 858 if (ni->ni_associd != 0) { 859 wcid = IEEE80211_AID(ni->ni_associd); 860 861 /* clear Rx WCID search table entry */ 862 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2); 863 } 864 sc->sc_node_free(ni); 865} 866 867#ifdef IEEE80211_HT 868static int 869rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 870 uint8_t tid) 871{ 872 struct rt2860_softc *sc = ic->ic_softc; 873 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 874 uint32_t tmp; 875 876 /* update BA session mask */ 877 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 878 tmp |= (1 << tid) << 16; 879 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 880 return 0; 881} 882 883static void 884rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 885 uint8_t tid) 886{ 887 struct rt2860_softc *sc = ic->ic_softc; 888 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 889 uint32_t tmp; 890 891 /* update BA session mask */ 892 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 893 tmp &= ~((1 << tid) << 16); 894 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 895} 896#endif 897 898int 899rt2860_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 900{ 901 struct rt2860_vap *rvp = RT2860_VAP(vap); 902 struct ieee80211com *ic = vap->iv_ic; 903 struct rt2860_softc *sc = ic->ic_softc; 904 uint32_t tmp; 905 int error; 906 907 if (vap->iv_state == IEEE80211_S_RUN) { 908 /* turn link LED off */ 909 rt2860_set_leds(sc, RT2860_LED_RADIO); 910 } 911 912 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 913 /* abort TSF synchronization */ 914 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 915 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 916 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 917 RT2860_TBTT_TIMER_EN)); 918 } 919 920 rt2860_set_gp_timer(sc, 0); 921 922 error = rvp->ral_newstate(vap, nstate, arg); 923 if (error != 0) 924 return (error); 925 926 if (nstate == IEEE80211_S_RUN) { 927 struct ieee80211_node *ni = vap->iv_bss; 928 929 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 930 rt2860_enable_mrr(sc); 931 rt2860_set_txpreamble(sc); 932 rt2860_set_basicrates(sc, &ni->ni_rates); 933 rt2860_set_bssid(sc, ni->ni_bssid); 934 } 935 936 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 937 vap->iv_opmode == IEEE80211_M_IBSS || 938 vap->iv_opmode == IEEE80211_M_MBSS) { 939 error = rt2860_setup_beacon(sc, vap); 940 if (error != 0) 941 return error; 942 } 943 944 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 945 rt2860_enable_tsf_sync(sc); 946 rt2860_set_gp_timer(sc, 500); 947 } 948 949 /* turn link LED on */ 950 rt2860_set_leds(sc, RT2860_LED_RADIO | 951 (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan) ? 952 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 953 } 954 return error; 955} 956 957/* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 958static uint16_t 959rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 960{ 961 uint32_t tmp; 962 uint16_t reg; 963 int ntries; 964 965 addr *= 2; 966 /*- 967 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 968 * DATA0: F E D C 969 * DATA1: B A 9 8 970 * DATA2: 7 6 5 4 971 * DATA3: 3 2 1 0 972 */ 973 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 974 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 975 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 976 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 977 for (ntries = 0; ntries < 500; ntries++) { 978 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 979 if (!(tmp & RT3070_EFSROM_KICK)) 980 break; 981 DELAY(2); 982 } 983 if (ntries == 500) 984 return 0xffff; 985 986 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 987 return 0xffff; /* address not found */ 988 989 /* determine to which 32-bit register our 16-bit word belongs */ 990 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 991 tmp = RAL_READ(sc, reg); 992 993 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 994} 995 996/* 997 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 998 * 93C66 or 93C86). 999 */ 1000static uint16_t 1001rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1002{ 1003 uint32_t tmp; 1004 uint16_t val; 1005 int n; 1006 1007 /* clock C once before the first command */ 1008 RT2860_EEPROM_CTL(sc, 0); 1009 1010 RT2860_EEPROM_CTL(sc, RT2860_S); 1011 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1012 RT2860_EEPROM_CTL(sc, RT2860_S); 1013 1014 /* write start bit (1) */ 1015 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1016 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1017 1018 /* write READ opcode (10) */ 1019 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1020 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1021 RT2860_EEPROM_CTL(sc, RT2860_S); 1022 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1023 1024 /* write address (A5-A0 or A7-A0) */ 1025 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1026 for (; n >= 0; n--) { 1027 RT2860_EEPROM_CTL(sc, RT2860_S | 1028 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1029 RT2860_EEPROM_CTL(sc, RT2860_S | 1030 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1031 } 1032 1033 RT2860_EEPROM_CTL(sc, RT2860_S); 1034 1035 /* read data Q15-Q0 */ 1036 val = 0; 1037 for (n = 15; n >= 0; n--) { 1038 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1039 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1040 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1041 RT2860_EEPROM_CTL(sc, RT2860_S); 1042 } 1043 1044 RT2860_EEPROM_CTL(sc, 0); 1045 1046 /* clear Chip Select and clock C */ 1047 RT2860_EEPROM_CTL(sc, RT2860_S); 1048 RT2860_EEPROM_CTL(sc, 0); 1049 RT2860_EEPROM_CTL(sc, RT2860_C); 1050 1051 return val; 1052} 1053 1054static __inline uint16_t 1055rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1056{ 1057 /* either eFUSE ROM or EEPROM */ 1058 return sc->sc_srom_read(sc, addr); 1059} 1060 1061static void 1062rt2860_intr_coherent(struct rt2860_softc *sc) 1063{ 1064 uint32_t tmp; 1065 1066 /* DMA finds data coherent event when checking the DDONE bit */ 1067 1068 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1069 1070 /* restart DMA engine */ 1071 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1072 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1073 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1074 1075 (void)rt2860_txrx_enable(sc); 1076} 1077 1078static void 1079rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1080{ 1081 struct ieee80211_node *ni; 1082 uint32_t stat; 1083 int retrycnt; 1084 uint8_t wcid, mcs, pid; 1085 1086 /* drain Tx status FIFO (maxsize = 16) */ 1087 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1088 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1089 1090 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1091 ni = sc->wcid2ni[wcid]; 1092 1093 /* if no ACK was requested, no feedback is available */ 1094 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff || ni == NULL) 1095 continue; 1096 1097 /* update per-STA AMRR stats */ 1098 if (stat & RT2860_TXQ_OK) { 1099 /* 1100 * Check if there were retries, ie if the Tx success 1101 * rate is different from the requested rate. Note 1102 * that it works only because we do not allow rate 1103 * fallback from OFDM to CCK. 1104 */ 1105 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1106 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1107 if (mcs + 1 != pid) 1108 retrycnt = 1; 1109 else 1110 retrycnt = 0; 1111 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 1112 IEEE80211_RATECTL_TX_SUCCESS, &retrycnt, NULL); 1113 } else { 1114 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 1115 IEEE80211_RATECTL_TX_FAILURE, &retrycnt, NULL); 1116 if_inc_counter(ni->ni_vap->iv_ifp, 1117 IFCOUNTER_OERRORS, 1); 1118 } 1119 } 1120} 1121 1122static void 1123rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1124{ 1125 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1126 uint32_t hw; 1127 1128 rt2860_drain_stats_fifo(sc); 1129 1130 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1131 while (ring->next != hw) { 1132 struct rt2860_tx_data *data = ring->data[ring->next]; 1133 1134 if (data != NULL) { 1135 bus_dmamap_sync(sc->txwi_dmat, data->map, 1136 BUS_DMASYNC_POSTWRITE); 1137 bus_dmamap_unload(sc->txwi_dmat, data->map); 1138 if (data->m->m_flags & M_TXCB) { 1139 ieee80211_process_callback(data->ni, data->m, 1140 0); 1141 } 1142 ieee80211_tx_complete(data->ni, data->m, 0); 1143 data->ni = NULL; 1144 data->m = NULL; 1145 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1146 ring->data[ring->next] = NULL; 1147 } 1148 ring->queued--; 1149 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1150 } 1151 1152 sc->sc_tx_timer = 0; 1153 if (ring->queued < RT2860_TX_RING_COUNT) 1154 sc->qfullmsk &= ~(1 << qid); 1155 rt2860_start(sc); 1156} 1157 1158/* 1159 * Return the Rx chain with the highest RSSI for a given frame. 1160 */ 1161static __inline uint8_t 1162rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1163{ 1164 uint8_t rxchain = 0; 1165 1166 if (sc->nrxchains > 1) { 1167 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1168 rxchain = 1; 1169 if (sc->nrxchains > 2) 1170 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1171 rxchain = 2; 1172 } 1173 return rxchain; 1174} 1175 1176static void 1177rt2860_rx_intr(struct rt2860_softc *sc) 1178{ 1179 struct rt2860_rx_radiotap_header *tap; 1180 struct ieee80211com *ic = &sc->sc_ic; 1181 struct ieee80211_frame *wh; 1182 struct ieee80211_node *ni; 1183 struct mbuf *m, *m1; 1184 bus_addr_t physaddr; 1185 uint32_t hw; 1186 uint16_t phy; 1187 uint8_t ant; 1188 int8_t rssi, nf; 1189 int error; 1190 1191 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1192 while (sc->rxq.cur != hw) { 1193 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1194 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1195 struct rt2860_rxwi *rxwi; 1196 1197 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1198 BUS_DMASYNC_POSTREAD); 1199 1200 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1201 DPRINTF(("RXD DDONE bit not set!\n")); 1202 break; /* should not happen */ 1203 } 1204 1205 if (__predict_false(rxd->flags & 1206 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1207 counter_u64_add(ic->ic_ierrors, 1); 1208 goto skip; 1209 } 1210 1211#ifdef HW_CRYPTO 1212 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1213 /* report MIC failures to net80211 for TKIP */ 1214 ic->ic_stats.is_rx_locmicfail++; 1215 ieee80211_michael_mic_failure(ic, 0/* XXX */); 1216 counter_u64_add(ic->ic_ierrors, 1); 1217 goto skip; 1218 } 1219#endif 1220 1221 m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1222 if (__predict_false(m1 == NULL)) { 1223 counter_u64_add(ic->ic_ierrors, 1); 1224 goto skip; 1225 } 1226 1227 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1228 BUS_DMASYNC_POSTREAD); 1229 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1230 1231 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1232 mtod(m1, void *), MCLBYTES, rt2860_dma_map_addr, 1233 &physaddr, 0); 1234 if (__predict_false(error != 0)) { 1235 m_freem(m1); 1236 1237 /* try to reload the old mbuf */ 1238 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1239 mtod(data->m, void *), MCLBYTES, 1240 rt2860_dma_map_addr, &physaddr, 0); 1241 if (__predict_false(error != 0)) { 1242 panic("%s: could not load old rx mbuf", 1243 device_get_name(sc->sc_dev)); 1244 } 1245 /* physical address may have changed */ 1246 rxd->sdp0 = htole32(physaddr); 1247 counter_u64_add(ic->ic_ierrors, 1); 1248 goto skip; 1249 } 1250 1251 /* 1252 * New mbuf successfully loaded, update Rx ring and continue 1253 * processing. 1254 */ 1255 m = data->m; 1256 data->m = m1; 1257 rxd->sdp0 = htole32(physaddr); 1258 1259 rxwi = mtod(m, struct rt2860_rxwi *); 1260 1261 /* finalize mbuf */ 1262 m->m_data = (caddr_t)(rxwi + 1); 1263 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff; 1264 1265 wh = mtod(m, struct ieee80211_frame *); 1266#ifdef HW_CRYPTO 1267 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1268 /* frame is decrypted by hardware */ 1269 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1270 } 1271#endif 1272 1273 /* HW may insert 2 padding bytes after 802.11 header */ 1274 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1275 u_int hdrlen = ieee80211_hdrsize(wh); 1276 ovbcopy(wh, (caddr_t)wh + 2, hdrlen); 1277 m->m_data += 2; 1278 wh = mtod(m, struct ieee80211_frame *); 1279 } 1280 1281 ant = rt2860_maxrssi_chain(sc, rxwi); 1282 rssi = rt2860_rssi2dbm(sc, rxwi->rssi[ant], ant); 1283 nf = RT2860_NOISE_FLOOR; 1284 1285 if (ieee80211_radiotap_active(ic)) { 1286 tap = &sc->sc_rxtap; 1287 tap->wr_flags = 0; 1288 tap->wr_antenna = ant; 1289 tap->wr_antsignal = nf + rssi; 1290 tap->wr_antnoise = nf; 1291 /* in case it can't be found below */ 1292 tap->wr_rate = 2; 1293 phy = le16toh(rxwi->phy); 1294 switch (phy & RT2860_PHY_MODE) { 1295 case RT2860_PHY_CCK: 1296 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1297 case 0: tap->wr_rate = 2; break; 1298 case 1: tap->wr_rate = 4; break; 1299 case 2: tap->wr_rate = 11; break; 1300 case 3: tap->wr_rate = 22; break; 1301 } 1302 if (phy & RT2860_PHY_SHPRE) 1303 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1304 break; 1305 case RT2860_PHY_OFDM: 1306 switch (phy & RT2860_PHY_MCS) { 1307 case 0: tap->wr_rate = 12; break; 1308 case 1: tap->wr_rate = 18; break; 1309 case 2: tap->wr_rate = 24; break; 1310 case 3: tap->wr_rate = 36; break; 1311 case 4: tap->wr_rate = 48; break; 1312 case 5: tap->wr_rate = 72; break; 1313 case 6: tap->wr_rate = 96; break; 1314 case 7: tap->wr_rate = 108; break; 1315 } 1316 break; 1317 } 1318 } 1319 1320 RAL_UNLOCK(sc); 1321 wh = mtod(m, struct ieee80211_frame *); 1322 1323 /* send the frame to the 802.11 layer */ 1324 ni = ieee80211_find_rxnode(ic, 1325 (struct ieee80211_frame_min *)wh); 1326 if (ni != NULL) { 1327 (void)ieee80211_input(ni, m, rssi - nf, nf); 1328 ieee80211_free_node(ni); 1329 } else 1330 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 1331 1332 RAL_LOCK(sc); 1333 1334skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1335 1336 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1337 BUS_DMASYNC_PREWRITE); 1338 1339 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1340 } 1341 1342 /* tell HW what we have processed */ 1343 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1344 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1345} 1346 1347static void 1348rt2860_tbtt_intr(struct rt2860_softc *sc) 1349{ 1350#if 0 1351 struct ieee80211com *ic = &sc->sc_ic; 1352 1353#ifndef IEEE80211_STA_ONLY 1354 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1355 /* one less beacon until next DTIM */ 1356 if (ic->ic_dtim_count == 0) 1357 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1358 else 1359 ic->ic_dtim_count--; 1360 1361 /* update dynamic parts of beacon */ 1362 rt2860_setup_beacon(sc); 1363 1364 /* flush buffered multicast frames */ 1365 if (ic->ic_dtim_count == 0) 1366 ieee80211_notify_dtim(ic); 1367 } 1368#endif 1369 /* check if protection mode has changed */ 1370 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1371 rt2860_updateprot(sc); 1372 sc->sc_ic_flags = ic->ic_flags; 1373 } 1374#endif 1375} 1376 1377static void 1378rt2860_gp_intr(struct rt2860_softc *sc) 1379{ 1380 struct ieee80211com *ic = &sc->sc_ic; 1381 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1382 1383 DPRINTFN(2, ("GP timeout state=%d\n", vap->iv_state)); 1384 1385 if (vap->iv_state == IEEE80211_S_RUN) 1386 rt2860_updatestats(sc); 1387} 1388 1389void 1390rt2860_intr(void *arg) 1391{ 1392 struct rt2860_softc *sc = arg; 1393 uint32_t r; 1394 1395 RAL_LOCK(sc); 1396 1397 r = RAL_READ(sc, RT2860_INT_STATUS); 1398 if (__predict_false(r == 0xffffffff)) { 1399 RAL_UNLOCK(sc); 1400 return; /* device likely went away */ 1401 } 1402 if (r == 0) { 1403 RAL_UNLOCK(sc); 1404 return; /* not for us */ 1405 } 1406 1407 /* acknowledge interrupts */ 1408 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1409 1410 if (r & RT2860_TX_RX_COHERENT) 1411 rt2860_intr_coherent(sc); 1412 1413 if (r & RT2860_MAC_INT_2) /* TX status */ 1414 rt2860_drain_stats_fifo(sc); 1415 1416 if (r & RT2860_TX_DONE_INT5) 1417 rt2860_tx_intr(sc, 5); 1418 1419 if (r & RT2860_RX_DONE_INT) 1420 rt2860_rx_intr(sc); 1421 1422 if (r & RT2860_TX_DONE_INT4) 1423 rt2860_tx_intr(sc, 4); 1424 1425 if (r & RT2860_TX_DONE_INT3) 1426 rt2860_tx_intr(sc, 3); 1427 1428 if (r & RT2860_TX_DONE_INT2) 1429 rt2860_tx_intr(sc, 2); 1430 1431 if (r & RT2860_TX_DONE_INT1) 1432 rt2860_tx_intr(sc, 1); 1433 1434 if (r & RT2860_TX_DONE_INT0) 1435 rt2860_tx_intr(sc, 0); 1436 1437 if (r & RT2860_MAC_INT_0) /* TBTT */ 1438 rt2860_tbtt_intr(sc); 1439 1440 if (r & RT2860_MAC_INT_3) /* Auto wakeup */ 1441 /* TBD wakeup */; 1442 1443 if (r & RT2860_MAC_INT_4) /* GP timer */ 1444 rt2860_gp_intr(sc); 1445 1446 RAL_UNLOCK(sc); 1447} 1448 1449static int 1450rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1451{ 1452 struct ieee80211com *ic = &sc->sc_ic; 1453 struct ieee80211vap *vap = ni->ni_vap; 1454 struct rt2860_tx_ring *ring; 1455 struct rt2860_tx_data *data; 1456 struct rt2860_txd *txd; 1457 struct rt2860_txwi *txwi; 1458 struct ieee80211_frame *wh; 1459 const struct ieee80211_txparam *tp; 1460 struct ieee80211_key *k; 1461 struct mbuf *m1; 1462 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1463 bus_dma_segment_t *seg; 1464 u_int hdrlen; 1465 uint16_t qos, dur; 1466 uint8_t type, qsel, mcs, pid, tid, qid; 1467 int i, nsegs, ntxds, pad, rate, ridx, error; 1468 1469 /* the data pool contains at least one element, pick the first */ 1470 data = SLIST_FIRST(&sc->data_pool); 1471 1472 wh = mtod(m, struct ieee80211_frame *); 1473 1474 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1475 k = ieee80211_crypto_encap(ni, m); 1476 if (k == NULL) { 1477 m_freem(m); 1478 return ENOBUFS; 1479 } 1480 1481 /* packet header may have moved, reset our local pointer */ 1482 wh = mtod(m, struct ieee80211_frame *); 1483 } 1484 1485 hdrlen = ieee80211_anyhdrsize(wh); 1486 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1487 1488 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1489 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1490 rate = tp->mcastrate; 1491 } else if (m->m_flags & M_EAPOL) { 1492 rate = tp->mgmtrate; 1493 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1494 rate = tp->ucastrate; 1495 } else { 1496 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1497 rate = ni->ni_txrate; 1498 } 1499 rate &= IEEE80211_RATE_VAL; 1500 1501 qid = M_WME_GETAC(m); 1502 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1503 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 1504 tid = qos & IEEE80211_QOS_TID; 1505 } else { 1506 qos = 0; 1507 tid = 0; 1508 } 1509 ring = &sc->txq[qid]; 1510 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, rate); 1511 1512 /* get MCS code from rate index */ 1513 mcs = rt2860_rates[ridx].mcs; 1514 1515 /* setup TX Wireless Information */ 1516 txwi = data->txwi; 1517 txwi->flags = 0; 1518 /* let HW generate seq numbers for non-QoS frames */ 1519 txwi->xflags = qos ? 0 : RT2860_TX_NSEQ; 1520 if (type == IEEE80211_FC0_TYPE_DATA) 1521 txwi->wcid = IEEE80211_AID(ni->ni_associd); 1522 else 1523 txwi->wcid = 0xff; 1524 txwi->len = htole16(m->m_pkthdr.len); 1525 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1526 txwi->phy = htole16(RT2860_PHY_CCK); 1527 if (ridx != RT2860_RIDX_CCK1 && 1528 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1529 mcs |= RT2860_PHY_SHPRE; 1530 } else 1531 txwi->phy = htole16(RT2860_PHY_OFDM); 1532 txwi->phy |= htole16(mcs); 1533 1534 /* 1535 * We store the MCS code into the driver-private PacketID field. 1536 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1537 * that we know at which initial rate the frame was transmitted. 1538 * We add 1 to the MCS code because setting the PacketID field to 1539 * 0 means that we don't want feedback in TX_STAT_FIFO. 1540 */ 1541 pid = (mcs + 1) & 0xf; 1542 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1543 1544 /* check if RTS/CTS or CTS-to-self protection is required */ 1545 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1546 (m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold || 1547 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1548 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1549 txwi->txop = RT2860_TX_TXOP_HT; 1550 else 1551 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1552 1553 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1554 (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 1555 IEEE80211_QOS_ACKPOLICY_NOACK)) { 1556 txwi->xflags |= RT2860_TX_ACK; 1557 1558 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1559 dur = rt2860_rates[ridx].sp_ack_dur; 1560 else 1561 dur = rt2860_rates[ridx].lp_ack_dur; 1562 *(uint16_t *)wh->i_dur = htole16(dur); 1563 } 1564 /* ask MAC to insert timestamp into probe responses */ 1565 if ((wh->i_fc[0] & 1566 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1567 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1568 /* NOTE: beacons do not pass through tx_data() */ 1569 txwi->flags |= RT2860_TX_TS; 1570 1571 if (ieee80211_radiotap_active_vap(vap)) { 1572 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1573 1574 tap->wt_flags = 0; 1575 tap->wt_rate = rate; 1576 if (mcs & RT2860_PHY_SHPRE) 1577 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1578 1579 ieee80211_radiotap_tx(vap, m); 1580 } 1581 1582 pad = (hdrlen + 3) & ~3; 1583 1584 /* copy and trim 802.11 header */ 1585 memcpy(txwi + 1, wh, hdrlen); 1586 m_adj(m, hdrlen); 1587 1588 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1589 &nsegs, 0); 1590 if (__predict_false(error != 0 && error != EFBIG)) { 1591 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1592 error); 1593 m_freem(m); 1594 return error; 1595 } 1596 if (__predict_true(error == 0)) { 1597 /* determine how many TXDs are required */ 1598 ntxds = 1 + (nsegs / 2); 1599 1600 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1601 /* not enough free TXDs, force mbuf defrag */ 1602 bus_dmamap_unload(sc->txwi_dmat, data->map); 1603 error = EFBIG; 1604 } 1605 } 1606 if (__predict_false(error != 0)) { 1607 m1 = m_defrag(m, M_NOWAIT); 1608 if (m1 == NULL) { 1609 device_printf(sc->sc_dev, 1610 "could not defragment mbuf\n"); 1611 m_freem(m); 1612 return ENOBUFS; 1613 } 1614 m = m1; 1615 1616 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1617 segs, &nsegs, 0); 1618 if (__predict_false(error != 0)) { 1619 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1620 error); 1621 m_freem(m); 1622 return error; 1623 } 1624 1625 /* determine how many TXDs are now required */ 1626 ntxds = 1 + (nsegs / 2); 1627 1628 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1629 /* this is a hopeless case, drop the mbuf! */ 1630 bus_dmamap_unload(sc->txwi_dmat, data->map); 1631 m_freem(m); 1632 return ENOBUFS; 1633 } 1634 } 1635 1636 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1637 1638 /* first segment is TXWI + 802.11 header */ 1639 txd = &ring->txd[ring->cur]; 1640 txd->sdp0 = htole32(data->paddr); 1641 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1642 txd->flags = qsel; 1643 1644 /* setup payload segments */ 1645 seg = &segs[0]; 1646 for (i = nsegs; i >= 2; i -= 2) { 1647 txd->sdp1 = htole32(seg->ds_addr); 1648 txd->sdl1 = htole16(seg->ds_len); 1649 seg++; 1650 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1651 /* grab a new Tx descriptor */ 1652 txd = &ring->txd[ring->cur]; 1653 txd->sdp0 = htole32(seg->ds_addr); 1654 txd->sdl0 = htole16(seg->ds_len); 1655 txd->flags = qsel; 1656 seg++; 1657 } 1658 /* finalize last segment */ 1659 if (i > 0) { 1660 txd->sdp1 = htole32(seg->ds_addr); 1661 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1662 } else { 1663 txd->sdl0 |= htole16(RT2860_TX_LS0); 1664 txd->sdl1 = 0; 1665 } 1666 1667 /* remove from the free pool and link it into the SW Tx slot */ 1668 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1669 data->m = m; 1670 data->ni = ni; 1671 ring->data[ring->cur] = data; 1672 1673 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1674 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1675 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1676 1677 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1678 qid, txwi->wcid, nsegs, ridx)); 1679 1680 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1681 ring->queued += ntxds; 1682 if (ring->queued >= RT2860_TX_RING_COUNT) 1683 sc->qfullmsk |= 1 << qid; 1684 1685 /* kick Tx */ 1686 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1687 1688 return 0; 1689} 1690 1691static int 1692rt2860_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1693 const struct ieee80211_bpf_params *params) 1694{ 1695 struct ieee80211com *ic = ni->ni_ic; 1696 struct rt2860_softc *sc = ic->ic_softc; 1697 int error; 1698 1699 RAL_LOCK(sc); 1700 1701 /* prevent management frames from being sent if we're not ready */ 1702 if (!(sc->sc_flags & RT2860_RUNNNING)) { 1703 RAL_UNLOCK(sc); 1704 m_freem(m); 1705 ieee80211_free_node(ni); 1706 return ENETDOWN; 1707 } 1708 if (params == NULL) { 1709 /* 1710 * Legacy path; interpret frame contents to decide 1711 * precisely how to send the frame. 1712 */ 1713 error = rt2860_tx(sc, m, ni); 1714 } else { 1715 /* 1716 * Caller supplied explicit parameters to use in 1717 * sending the frame. 1718 */ 1719 error = rt2860_tx_raw(sc, m, ni, params); 1720 } 1721 if (error != 0) { 1722 /* NB: m is reclaimed on tx failure */ 1723 ieee80211_free_node(ni); 1724 } 1725 sc->sc_tx_timer = 5; 1726 RAL_UNLOCK(sc); 1727 return error; 1728} 1729 1730static int 1731rt2860_tx_raw(struct rt2860_softc *sc, struct mbuf *m, 1732 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 1733{ 1734 struct ieee80211com *ic = &sc->sc_ic; 1735 struct ieee80211vap *vap = ni->ni_vap; 1736 struct rt2860_tx_ring *ring; 1737 struct rt2860_tx_data *data; 1738 struct rt2860_txd *txd; 1739 struct rt2860_txwi *txwi; 1740 struct ieee80211_frame *wh; 1741 struct mbuf *m1; 1742 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1743 bus_dma_segment_t *seg; 1744 u_int hdrlen; 1745 uint16_t dur; 1746 uint8_t type, qsel, mcs, pid, tid, qid; 1747 int i, nsegs, ntxds, pad, rate, ridx, error; 1748 1749 /* the data pool contains at least one element, pick the first */ 1750 data = SLIST_FIRST(&sc->data_pool); 1751 1752 wh = mtod(m, struct ieee80211_frame *); 1753 hdrlen = ieee80211_hdrsize(wh); 1754 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1755 1756 /* Choose a TX rate index. */ 1757 rate = params->ibp_rate0; 1758 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 1759 rate & IEEE80211_RATE_VAL); 1760 if (ridx == (uint8_t)-1) { 1761 /* XXX fall back to mcast/mgmt rate? */ 1762 m_freem(m); 1763 return EINVAL; 1764 } 1765 1766 qid = params->ibp_pri & 3; 1767 tid = 0; 1768 ring = &sc->txq[qid]; 1769 1770 /* get MCS code from rate index */ 1771 mcs = rt2860_rates[ridx].mcs; 1772 1773 /* setup TX Wireless Information */ 1774 txwi = data->txwi; 1775 txwi->flags = 0; 1776 /* let HW generate seq numbers for non-QoS frames */ 1777 txwi->xflags = params->ibp_pri & 3 ? 0 : RT2860_TX_NSEQ; 1778 txwi->wcid = 0xff; 1779 txwi->len = htole16(m->m_pkthdr.len); 1780 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1781 txwi->phy = htole16(RT2860_PHY_CCK); 1782 if (ridx != RT2860_RIDX_CCK1 && 1783 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1784 mcs |= RT2860_PHY_SHPRE; 1785 } else 1786 txwi->phy = htole16(RT2860_PHY_OFDM); 1787 txwi->phy |= htole16(mcs); 1788 1789 /* 1790 * We store the MCS code into the driver-private PacketID field. 1791 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1792 * that we know at which initial rate the frame was transmitted. 1793 * We add 1 to the MCS code because setting the PacketID field to 1794 * 0 means that we don't want feedback in TX_STAT_FIFO. 1795 */ 1796 pid = (mcs + 1) & 0xf; 1797 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1798 1799 /* check if RTS/CTS or CTS-to-self protection is required */ 1800 if (params->ibp_flags & IEEE80211_BPF_RTS || 1801 params->ibp_flags & IEEE80211_BPF_CTS) 1802 txwi->txop = RT2860_TX_TXOP_HT; 1803 else 1804 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1805 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 1806 txwi->xflags |= RT2860_TX_ACK; 1807 1808 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1809 dur = rt2860_rates[ridx].sp_ack_dur; 1810 else 1811 dur = rt2860_rates[ridx].lp_ack_dur; 1812 *(uint16_t *)wh->i_dur = htole16(dur); 1813 } 1814 /* ask MAC to insert timestamp into probe responses */ 1815 if ((wh->i_fc[0] & 1816 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1817 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1818 /* NOTE: beacons do not pass through tx_data() */ 1819 txwi->flags |= RT2860_TX_TS; 1820 1821 if (ieee80211_radiotap_active_vap(vap)) { 1822 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1823 1824 tap->wt_flags = 0; 1825 tap->wt_rate = rate; 1826 if (mcs & RT2860_PHY_SHPRE) 1827 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1828 1829 ieee80211_radiotap_tx(vap, m); 1830 } 1831 1832 pad = (hdrlen + 3) & ~3; 1833 1834 /* copy and trim 802.11 header */ 1835 memcpy(txwi + 1, wh, hdrlen); 1836 m_adj(m, hdrlen); 1837 1838 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1839 &nsegs, 0); 1840 if (__predict_false(error != 0 && error != EFBIG)) { 1841 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1842 error); 1843 m_freem(m); 1844 return error; 1845 } 1846 if (__predict_true(error == 0)) { 1847 /* determine how many TXDs are required */ 1848 ntxds = 1 + (nsegs / 2); 1849 1850 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1851 /* not enough free TXDs, force mbuf defrag */ 1852 bus_dmamap_unload(sc->txwi_dmat, data->map); 1853 error = EFBIG; 1854 } 1855 } 1856 if (__predict_false(error != 0)) { 1857 m1 = m_defrag(m, M_NOWAIT); 1858 if (m1 == NULL) { 1859 device_printf(sc->sc_dev, 1860 "could not defragment mbuf\n"); 1861 m_freem(m); 1862 return ENOBUFS; 1863 } 1864 m = m1; 1865 1866 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1867 segs, &nsegs, 0); 1868 if (__predict_false(error != 0)) { 1869 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1870 error); 1871 m_freem(m); 1872 return error; 1873 } 1874 1875 /* determine how many TXDs are now required */ 1876 ntxds = 1 + (nsegs / 2); 1877 1878 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1879 /* this is a hopeless case, drop the mbuf! */ 1880 bus_dmamap_unload(sc->txwi_dmat, data->map); 1881 m_freem(m); 1882 return ENOBUFS; 1883 } 1884 } 1885 1886 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1887 1888 /* first segment is TXWI + 802.11 header */ 1889 txd = &ring->txd[ring->cur]; 1890 txd->sdp0 = htole32(data->paddr); 1891 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1892 txd->flags = qsel; 1893 1894 /* setup payload segments */ 1895 seg = &segs[0]; 1896 for (i = nsegs; i >= 2; i -= 2) { 1897 txd->sdp1 = htole32(seg->ds_addr); 1898 txd->sdl1 = htole16(seg->ds_len); 1899 seg++; 1900 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1901 /* grab a new Tx descriptor */ 1902 txd = &ring->txd[ring->cur]; 1903 txd->sdp0 = htole32(seg->ds_addr); 1904 txd->sdl0 = htole16(seg->ds_len); 1905 txd->flags = qsel; 1906 seg++; 1907 } 1908 /* finalize last segment */ 1909 if (i > 0) { 1910 txd->sdp1 = htole32(seg->ds_addr); 1911 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1912 } else { 1913 txd->sdl0 |= htole16(RT2860_TX_LS0); 1914 txd->sdl1 = 0; 1915 } 1916 1917 /* remove from the free pool and link it into the SW Tx slot */ 1918 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1919 data->m = m; 1920 data->ni = ni; 1921 ring->data[ring->cur] = data; 1922 1923 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1924 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1925 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1926 1927 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1928 qid, txwi->wcid, nsegs, ridx)); 1929 1930 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1931 ring->queued += ntxds; 1932 if (ring->queued >= RT2860_TX_RING_COUNT) 1933 sc->qfullmsk |= 1 << qid; 1934 1935 /* kick Tx */ 1936 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1937 1938 return 0; 1939} 1940 1941static int 1942rt2860_transmit(struct ieee80211com *ic, struct mbuf *m) 1943{ 1944 struct rt2860_softc *sc = ic->ic_softc; 1945 int error; 1946 1947 RAL_LOCK(sc); 1948 if ((sc->sc_flags & RT2860_RUNNNING) == 0) { 1949 RAL_UNLOCK(sc); 1950 return (ENXIO); 1951 } 1952 error = mbufq_enqueue(&sc->sc_snd, m); 1953 if (error) { 1954 RAL_UNLOCK(sc); 1955 return (error); 1956 } 1957 rt2860_start(sc); 1958 RAL_UNLOCK(sc); 1959 1960 return (0); 1961} 1962 1963static void 1964rt2860_start(struct rt2860_softc *sc) 1965{ 1966 struct ieee80211_node *ni; 1967 struct mbuf *m; 1968 1969 RAL_LOCK_ASSERT(sc); 1970 1971 if ((sc->sc_flags & RT2860_RUNNNING) == 0) 1972 return; 1973 1974 while (!SLIST_EMPTY(&sc->data_pool) && sc->qfullmsk == 0 && 1975 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1976 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1977 if (rt2860_tx(sc, m, ni) != 0) { 1978 if_inc_counter(ni->ni_vap->iv_ifp, 1979 IFCOUNTER_OERRORS, 1); 1980 ieee80211_free_node(ni); 1981 continue; 1982 } 1983 sc->sc_tx_timer = 5; 1984 } 1985} 1986 1987static void 1988rt2860_watchdog(void *arg) 1989{ 1990 struct rt2860_softc *sc = arg; 1991 1992 RAL_LOCK_ASSERT(sc); 1993 1994 KASSERT(sc->sc_flags & RT2860_RUNNNING, ("not running")); 1995 1996 if (sc->sc_invalid) /* card ejected */ 1997 return; 1998 1999 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 2000 device_printf(sc->sc_dev, "device timeout\n"); 2001 rt2860_stop_locked(sc); 2002 rt2860_init_locked(sc); 2003 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2004 return; 2005 } 2006 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 2007} 2008 2009static void 2010rt2860_parent(struct ieee80211com *ic) 2011{ 2012 struct rt2860_softc *sc = ic->ic_softc; 2013 int startall = 0; 2014 2015 RAL_LOCK(sc); 2016 if (ic->ic_nrunning> 0) { 2017 if (!(sc->sc_flags & RT2860_RUNNNING)) { 2018 rt2860_init_locked(sc); 2019 startall = 1; 2020 } else 2021 rt2860_update_promisc(ic); 2022 } else if (sc->sc_flags & RT2860_RUNNNING) 2023 rt2860_stop_locked(sc); 2024 RAL_UNLOCK(sc); 2025 if (startall) 2026 ieee80211_start_all(ic); 2027} 2028 2029/* 2030 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 2031 * We access the BBP through the 8051 microcontroller unit which means that 2032 * the microcode must be loaded first. 2033 */ 2034void 2035rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2036{ 2037 int ntries; 2038 2039 for (ntries = 0; ntries < 100; ntries++) { 2040 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2041 break; 2042 DELAY(1); 2043 } 2044 if (ntries == 100) { 2045 device_printf(sc->sc_dev, 2046 "could not write to BBP through MCU\n"); 2047 return; 2048 } 2049 2050 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2051 RT2860_BBP_CSR_KICK | reg << 8 | val); 2052 RAL_BARRIER_WRITE(sc); 2053 2054 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2055 DELAY(1000); 2056} 2057 2058uint8_t 2059rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 2060{ 2061 uint32_t val; 2062 int ntries; 2063 2064 for (ntries = 0; ntries < 100; ntries++) { 2065 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2066 break; 2067 DELAY(1); 2068 } 2069 if (ntries == 100) { 2070 device_printf(sc->sc_dev, 2071 "could not read from BBP through MCU\n"); 2072 return 0; 2073 } 2074 2075 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2076 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 2077 RAL_BARRIER_WRITE(sc); 2078 2079 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2080 DELAY(1000); 2081 2082 for (ntries = 0; ntries < 100; ntries++) { 2083 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 2084 if (!(val & RT2860_BBP_CSR_KICK)) 2085 return val & 0xff; 2086 DELAY(1); 2087 } 2088 device_printf(sc->sc_dev, "could not read from BBP through MCU\n"); 2089 2090 return 0; 2091} 2092 2093/* 2094 * Write to one of the 4 programmable 24-bit RF registers. 2095 */ 2096static void 2097rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 2098{ 2099 uint32_t tmp; 2100 int ntries; 2101 2102 for (ntries = 0; ntries < 100; ntries++) { 2103 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 2104 break; 2105 DELAY(1); 2106 } 2107 if (ntries == 100) { 2108 device_printf(sc->sc_dev, "could not write to RF\n"); 2109 return; 2110 } 2111 2112 /* RF registers are 24-bit on the RT2860 */ 2113 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 2114 (val & 0x3fffff) << 2 | (reg & 3); 2115 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 2116} 2117 2118static uint8_t 2119rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 2120{ 2121 uint32_t tmp; 2122 int ntries; 2123 2124 for (ntries = 0; ntries < 100; ntries++) { 2125 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2126 break; 2127 DELAY(1); 2128 } 2129 if (ntries == 100) { 2130 device_printf(sc->sc_dev, "could not read RF register\n"); 2131 return 0xff; 2132 } 2133 tmp = RT3070_RF_KICK | reg << 8; 2134 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2135 2136 for (ntries = 0; ntries < 100; ntries++) { 2137 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 2138 if (!(tmp & RT3070_RF_KICK)) 2139 break; 2140 DELAY(1); 2141 } 2142 if (ntries == 100) { 2143 device_printf(sc->sc_dev, "could not read RF register\n"); 2144 return 0xff; 2145 } 2146 return tmp & 0xff; 2147} 2148 2149void 2150rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2151{ 2152 uint32_t tmp; 2153 int ntries; 2154 2155 for (ntries = 0; ntries < 10; ntries++) { 2156 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2157 break; 2158 DELAY(10); 2159 } 2160 if (ntries == 10) { 2161 device_printf(sc->sc_dev, "could not write to RF\n"); 2162 return; 2163 } 2164 2165 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2166 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2167} 2168 2169/* 2170 * Send a command to the 8051 microcontroller unit. 2171 */ 2172int 2173rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2174{ 2175 int slot, ntries; 2176 uint32_t tmp; 2177 uint8_t cid; 2178 2179 for (ntries = 0; ntries < 100; ntries++) { 2180 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2181 break; 2182 DELAY(2); 2183 } 2184 if (ntries == 100) 2185 return EIO; 2186 2187 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2188 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2189 RAL_BARRIER_WRITE(sc); 2190 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2191 2192 if (!wait) 2193 return 0; 2194 /* wait for the command to complete */ 2195 for (ntries = 0; ntries < 200; ntries++) { 2196 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2197 /* find the command slot */ 2198 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2199 if ((tmp & 0xff) == cid) 2200 break; 2201 if (slot < 4) 2202 break; 2203 DELAY(100); 2204 } 2205 if (ntries == 200) { 2206 /* clear command and status */ 2207 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2208 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2209 return ETIMEDOUT; 2210 } 2211 /* get command status (1 means success) */ 2212 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2213 tmp = (tmp >> (slot * 8)) & 0xff; 2214 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2215 cmd, slot, tmp)); 2216 /* clear command and status */ 2217 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2218 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2219 return (tmp == 1) ? 0 : EIO; 2220} 2221 2222static void 2223rt2860_enable_mrr(struct rt2860_softc *sc) 2224{ 2225#define CCK(mcs) (mcs) 2226#define OFDM(mcs) (1 << 3 | (mcs)) 2227 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2228 OFDM(6) << 28 | /* 54->48 */ 2229 OFDM(5) << 24 | /* 48->36 */ 2230 OFDM(4) << 20 | /* 36->24 */ 2231 OFDM(3) << 16 | /* 24->18 */ 2232 OFDM(2) << 12 | /* 18->12 */ 2233 OFDM(1) << 8 | /* 12-> 9 */ 2234 OFDM(0) << 4 | /* 9-> 6 */ 2235 OFDM(0)); /* 6-> 6 */ 2236 2237 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2238 CCK(2) << 12 | /* 11->5.5 */ 2239 CCK(1) << 8 | /* 5.5-> 2 */ 2240 CCK(0) << 4 | /* 2-> 1 */ 2241 CCK(0)); /* 1-> 1 */ 2242#undef OFDM 2243#undef CCK 2244} 2245 2246static void 2247rt2860_set_txpreamble(struct rt2860_softc *sc) 2248{ 2249 struct ieee80211com *ic = &sc->sc_ic; 2250 uint32_t tmp; 2251 2252 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2253 tmp &= ~RT2860_CCK_SHORT_EN; 2254 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2255 tmp |= RT2860_CCK_SHORT_EN; 2256 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2257} 2258 2259void 2260rt2860_set_basicrates(struct rt2860_softc *sc, 2261 const struct ieee80211_rateset *rs) 2262{ 2263 struct ieee80211com *ic = &sc->sc_ic; 2264 uint32_t mask = 0; 2265 uint8_t rate; 2266 int i; 2267 2268 for (i = 0; i < rs->rs_nrates; i++) { 2269 rate = rs->rs_rates[i]; 2270 2271 if (!(rate & IEEE80211_RATE_BASIC)) 2272 continue; 2273 2274 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt, 2275 IEEE80211_RV(rate)); 2276 } 2277 2278 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, mask); 2279} 2280 2281static void 2282rt2860_scan_start(struct ieee80211com *ic) 2283{ 2284 struct rt2860_softc *sc = ic->ic_softc; 2285 uint32_t tmp; 2286 2287 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 2288 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 2289 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 2290 RT2860_TBTT_TIMER_EN)); 2291 rt2860_set_gp_timer(sc, 0); 2292} 2293 2294static void 2295rt2860_scan_end(struct ieee80211com *ic) 2296{ 2297 struct rt2860_softc *sc = ic->ic_softc; 2298 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2299 2300 if (vap->iv_state == IEEE80211_S_RUN) { 2301 rt2860_enable_tsf_sync(sc); 2302 rt2860_set_gp_timer(sc, 500); 2303 } 2304} 2305 2306static void 2307rt2860_set_channel(struct ieee80211com *ic) 2308{ 2309 struct rt2860_softc *sc = ic->ic_softc; 2310 2311 RAL_LOCK(sc); 2312 rt2860_switch_chan(sc, ic->ic_curchan); 2313 RAL_UNLOCK(sc); 2314} 2315 2316static void 2317rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2318{ 2319 uint32_t tmp; 2320 uint8_t agc; 2321 2322 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2323 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2324 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2325 rt2860_mcu_bbp_write(sc, 86, 0x00); 2326 2327 if (group == 0) { 2328 if (sc->ext_2ghz_lna) { 2329 rt2860_mcu_bbp_write(sc, 82, 0x62); 2330 rt2860_mcu_bbp_write(sc, 75, 0x46); 2331 } else { 2332 rt2860_mcu_bbp_write(sc, 82, 0x84); 2333 rt2860_mcu_bbp_write(sc, 75, 0x50); 2334 } 2335 } else { 2336 if (sc->ext_5ghz_lna) { 2337 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2338 rt2860_mcu_bbp_write(sc, 75, 0x46); 2339 } else { 2340 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2341 rt2860_mcu_bbp_write(sc, 75, 0x50); 2342 } 2343 } 2344 2345 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2346 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2347 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2348 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2349 2350 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2351 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2352 if (sc->nrxchains > 1) 2353 tmp |= RT2860_LNA_PE1_EN; 2354 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2355 tmp |= RT3593_LNA_PE2_EN; 2356 if (group == 0) { /* 2GHz */ 2357 tmp |= RT2860_PA_PE_G0_EN; 2358 if (sc->ntxchains > 1) 2359 tmp |= RT2860_PA_PE_G1_EN; 2360 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2361 tmp |= RT3593_PA_PE_G2_EN; 2362 } else { /* 5GHz */ 2363 tmp |= RT2860_PA_PE_A0_EN; 2364 if (sc->ntxchains > 1) 2365 tmp |= RT2860_PA_PE_A1_EN; 2366 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2367 tmp |= RT3593_PA_PE_A2_EN; 2368 } 2369 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2370 2371 if (sc->mac_ver == 0x3593) { 2372 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2373 if (sc->sc_flags & RT2860_PCIE) { 2374 tmp &= ~0x01010000; 2375 if (group == 0) 2376 tmp |= 0x00010000; 2377 } else { 2378 tmp &= ~0x00008080; 2379 if (group == 0) 2380 tmp |= 0x00000080; 2381 } 2382 tmp = (tmp & ~0x00001000) | 0x00000010; 2383 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2384 } 2385 2386 /* set initial AGC value */ 2387 if (group == 0) { /* 2GHz band */ 2388 if (sc->mac_ver >= 0x3071) 2389 agc = 0x1c + sc->lna[0] * 2; 2390 else 2391 agc = 0x2e + sc->lna[0]; 2392 } else { /* 5GHz band */ 2393 agc = 0x32 + (sc->lna[group] * 5) / 3; 2394 } 2395 rt2860_mcu_bbp_write(sc, 66, agc); 2396 2397 DELAY(1000); 2398} 2399 2400static void 2401rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2402{ 2403 const struct rfprog *rfprog = rt2860_rf2850; 2404 uint32_t r2, r3, r4; 2405 int8_t txpow1, txpow2; 2406 u_int i; 2407 2408 /* find the settings for this channel (we know it exists) */ 2409 for (i = 0; rfprog[i].chan != chan; i++); 2410 2411 r2 = rfprog[i].r2; 2412 if (sc->ntxchains == 1) 2413 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2414 if (sc->nrxchains == 1) 2415 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2416 else if (sc->nrxchains == 2) 2417 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2418 2419 /* use Tx power values from EEPROM */ 2420 txpow1 = sc->txpow1[i]; 2421 txpow2 = sc->txpow2[i]; 2422 if (chan > 14) { 2423 if (txpow1 >= 0) 2424 txpow1 = txpow1 << 1 | 1; 2425 else 2426 txpow1 = (7 + txpow1) << 1; 2427 if (txpow2 >= 0) 2428 txpow2 = txpow2 << 1 | 1; 2429 else 2430 txpow2 = (7 + txpow2) << 1; 2431 } 2432 r3 = rfprog[i].r3 | txpow1 << 7; 2433 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2434 2435 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2436 rt2860_rf_write(sc, RT2860_RF2, r2); 2437 rt2860_rf_write(sc, RT2860_RF3, r3); 2438 rt2860_rf_write(sc, RT2860_RF4, r4); 2439 2440 DELAY(200); 2441 2442 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2443 rt2860_rf_write(sc, RT2860_RF2, r2); 2444 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2445 rt2860_rf_write(sc, RT2860_RF4, r4); 2446 2447 DELAY(200); 2448 2449 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2450 rt2860_rf_write(sc, RT2860_RF2, r2); 2451 rt2860_rf_write(sc, RT2860_RF3, r3); 2452 rt2860_rf_write(sc, RT2860_RF4, r4); 2453} 2454 2455static void 2456rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2457{ 2458 int8_t txpow1, txpow2; 2459 uint8_t rf; 2460 int i; 2461 2462 /* RT3090 is 2GHz only */ 2463 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2464 2465 /* find the settings for this channel (we know it exists) */ 2466 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2467 2468 /* use Tx power values from EEPROM */ 2469 txpow1 = sc->txpow1[i]; 2470 txpow2 = sc->txpow2[i]; 2471 2472 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2473 rf = rt3090_rf_read(sc, 3); 2474 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2475 rt3090_rf_write(sc, 3, rf); 2476 rf = rt3090_rf_read(sc, 6); 2477 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2478 rt3090_rf_write(sc, 6, rf); 2479 2480 /* set Tx0 power */ 2481 rf = rt3090_rf_read(sc, 12); 2482 rf = (rf & ~0x1f) | txpow1; 2483 rt3090_rf_write(sc, 12, rf); 2484 2485 /* set Tx1 power */ 2486 rf = rt3090_rf_read(sc, 13); 2487 rf = (rf & ~0x1f) | txpow2; 2488 rt3090_rf_write(sc, 13, rf); 2489 2490 rf = rt3090_rf_read(sc, 1); 2491 rf &= ~0xfc; 2492 if (sc->ntxchains == 1) 2493 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2494 else if (sc->ntxchains == 2) 2495 rf |= RT3070_TX2_PD; 2496 if (sc->nrxchains == 1) 2497 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2498 else if (sc->nrxchains == 2) 2499 rf |= RT3070_RX2_PD; 2500 rt3090_rf_write(sc, 1, rf); 2501 2502 /* set RF offset */ 2503 rf = rt3090_rf_read(sc, 23); 2504 rf = (rf & ~0x7f) | sc->freq; 2505 rt3090_rf_write(sc, 23, rf); 2506 2507 /* program RF filter */ 2508 rf = rt3090_rf_read(sc, 24); /* Tx */ 2509 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2510 rt3090_rf_write(sc, 24, rf); 2511 rf = rt3090_rf_read(sc, 31); /* Rx */ 2512 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2513 rt3090_rf_write(sc, 31, rf); 2514 2515 /* enable RF tuning */ 2516 rf = rt3090_rf_read(sc, 7); 2517 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2518} 2519 2520static void 2521rt5390_set_chan(struct rt2860_softc *sc, u_int chan) 2522{ 2523 uint8_t h20mhz, rf, tmp; 2524 int8_t txpow1, txpow2; 2525 int i; 2526 2527 /* RT5390 is 2GHz only */ 2528 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2529 2530 /* find the settings for this channel (we know it exists) */ 2531 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2532 2533 /* use Tx power values from EEPROM */ 2534 txpow1 = sc->txpow1[i]; 2535 txpow2 = sc->txpow2[i]; 2536 2537 rt3090_rf_write(sc, 8, rt3090_freqs[i].n); 2538 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f); 2539 rf = rt3090_rf_read(sc, 11); 2540 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03); 2541 rt3090_rf_write(sc, 11, rf); 2542 2543 rf = rt3090_rf_read(sc, 49); 2544 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 2545 /* the valid range of the RF R49 is 0x00~0x27 */ 2546 if ((rf & 0x3f) > 0x27) 2547 rf = (rf & ~0x3f) | 0x27; 2548 rt3090_rf_write(sc, 49, rf); 2549 if (sc->mac_ver == 0x5392) { 2550 rf = rt3090_rf_read(sc, 50); 2551 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 2552 /* the valid range of the RF R50 is 0x00~0x27 */ 2553 if ((rf & 0x3f) > 0x27) 2554 rf = (rf & ~0x3f) | 0x27; 2555 rt3090_rf_write(sc, 50, rf); 2556 } 2557 2558 rf = rt3090_rf_read(sc, 1); 2559 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 2560 if (sc->mac_ver == 0x5392) 2561 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2562 rt3090_rf_write(sc, 1, rf); 2563 2564 rf = rt3090_rf_read(sc, 2); 2565 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2566 DELAY(1000); 2567 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2568 2569 rf = rt3090_rf_read(sc, 17); 2570 tmp = rf; 2571 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 2572 rf = MIN(rf, 0x5f); 2573 if (tmp != rf) 2574 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0); 2575 2576 if (sc->mac_ver == 0x5390) { 2577 if (chan <= 4) 2578 rf = 0x73; 2579 else if (chan >= 5 && chan <= 6) 2580 rf = 0x63; 2581 else if (chan >= 7 && chan <= 10) 2582 rf = 0x53; 2583 else 2584 rf = 43; 2585 rt3090_rf_write(sc, 55, rf); 2586 2587 if (chan == 1) 2588 rf = 0x0c; 2589 else if (chan == 2) 2590 rf = 0x0b; 2591 else if (chan == 3) 2592 rf = 0x0a; 2593 else if (chan >= 4 && chan <= 6) 2594 rf = 0x09; 2595 else if (chan >= 7 && chan <= 12) 2596 rf = 0x08; 2597 else if (chan == 13) 2598 rf = 0x07; 2599 else 2600 rf = 0x06; 2601 rt3090_rf_write(sc, 59, rf); 2602 } 2603 2604 /* Tx/Rx h20M */ 2605 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 2606 rf = rt3090_rf_read(sc, 30); 2607 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 2608 rt3090_rf_write(sc, 30, rf); 2609 2610 /* Rx BB filter VCM */ 2611 rf = rt3090_rf_read(sc, 30); 2612 rf = (rf & ~0x18) | 0x10; 2613 rt3090_rf_write(sc, 30, rf); 2614 2615 /* Initiate VCO calibration. */ 2616 rf = rt3090_rf_read(sc, 3); 2617 rf |= RT3593_VCOCAL; 2618 rt3090_rf_write(sc, 3, rf); 2619} 2620 2621static int 2622rt3090_rf_init(struct rt2860_softc *sc) 2623{ 2624 uint32_t tmp; 2625 uint8_t rf, bbp; 2626 int i; 2627 2628 rf = rt3090_rf_read(sc, 30); 2629 /* toggle RF R30 bit 7 */ 2630 rt3090_rf_write(sc, 30, rf | 0x80); 2631 DELAY(1000); 2632 rt3090_rf_write(sc, 30, rf & ~0x80); 2633 2634 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2635 tmp &= ~0x1f000000; 2636 if (sc->patch_dac && sc->mac_rev < 0x0211) 2637 tmp |= 0x0d000000; /* 1.35V */ 2638 else 2639 tmp |= 0x01000000; /* 1.2V */ 2640 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2641 2642 /* patch LNA_PE_G1 */ 2643 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2644 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2645 2646 /* initialize RF registers to default value */ 2647 for (i = 0; i < nitems(rt3090_def_rf); i++) { 2648 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2649 rt3090_def_rf[i].val); 2650 } 2651 2652 /* select 20MHz bandwidth */ 2653 rt3090_rf_write(sc, 31, 0x14); 2654 2655 rf = rt3090_rf_read(sc, 6); 2656 rt3090_rf_write(sc, 6, rf | 0x40); 2657 2658 if (sc->mac_ver != 0x3593) { 2659 /* calibrate filter for 20MHz bandwidth */ 2660 sc->rf24_20mhz = 0x1f; /* default value */ 2661 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2662 2663 /* select 40MHz bandwidth */ 2664 bbp = rt2860_mcu_bbp_read(sc, 4); 2665 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2666 rf = rt3090_rf_read(sc, 31); 2667 rt3090_rf_write(sc, 31, rf | 0x20); 2668 2669 /* calibrate filter for 40MHz bandwidth */ 2670 sc->rf24_40mhz = 0x2f; /* default value */ 2671 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2672 2673 /* go back to 20MHz bandwidth */ 2674 bbp = rt2860_mcu_bbp_read(sc, 4); 2675 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2676 } 2677 if (sc->mac_rev < 0x0211) 2678 rt3090_rf_write(sc, 27, 0x03); 2679 2680 tmp = RAL_READ(sc, RT3070_OPT_14); 2681 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2682 2683 if (sc->rf_rev == RT3070_RF_3020) 2684 rt3090_set_rx_antenna(sc, 0); 2685 2686 bbp = rt2860_mcu_bbp_read(sc, 138); 2687 if (sc->mac_ver == 0x3593) { 2688 if (sc->ntxchains == 1) 2689 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2690 else if (sc->ntxchains == 2) 2691 bbp |= 0x40; /* turn off DAC2 */ 2692 if (sc->nrxchains == 1) 2693 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2694 else if (sc->nrxchains == 2) 2695 bbp &= ~0x04; /* turn off ADC2 */ 2696 } else { 2697 if (sc->ntxchains == 1) 2698 bbp |= 0x20; /* turn off DAC1 */ 2699 if (sc->nrxchains == 1) 2700 bbp &= ~0x02; /* turn off ADC1 */ 2701 } 2702 rt2860_mcu_bbp_write(sc, 138, bbp); 2703 2704 rf = rt3090_rf_read(sc, 1); 2705 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2706 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2707 rt3090_rf_write(sc, 1, rf); 2708 2709 rf = rt3090_rf_read(sc, 15); 2710 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2711 2712 rf = rt3090_rf_read(sc, 17); 2713 rf &= ~RT3070_TX_LO1; 2714 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2715 rf |= 0x20; /* fix for long range Rx issue */ 2716 if (sc->txmixgain_2ghz >= 2) 2717 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2718 rt3090_rf_write(sc, 17, rf); 2719 2720 rf = rt3090_rf_read(sc, 20); 2721 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2722 2723 rf = rt3090_rf_read(sc, 21); 2724 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2725 2726 return (0); 2727} 2728 2729static void 2730rt5390_rf_init(struct rt2860_softc *sc) 2731{ 2732 uint8_t rf, bbp; 2733 int i; 2734 2735 rf = rt3090_rf_read(sc, 2); 2736 /* Toggle RF R2 bit 7. */ 2737 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2738 DELAY(1000); 2739 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2740 2741 /* Initialize RF registers to default value. */ 2742 if (sc->mac_ver == 0x5392) { 2743 for (i = 0; i < nitems(rt5392_def_rf); i++) { 2744 rt3090_rf_write(sc, rt5392_def_rf[i].reg, 2745 rt5392_def_rf[i].val); 2746 } 2747 } else { 2748 for (i = 0; i < nitems(rt5390_def_rf); i++) { 2749 rt3090_rf_write(sc, rt5390_def_rf[i].reg, 2750 rt5390_def_rf[i].val); 2751 } 2752 } 2753 2754 sc->rf24_20mhz = 0x1f; 2755 sc->rf24_40mhz = 0x2f; 2756 2757 if (sc->mac_rev < 0x0211) 2758 rt3090_rf_write(sc, 27, 0x03); 2759 2760 /* Set led open drain enable. */ 2761 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1); 2762 2763 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2764 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2765 2766 if (sc->mac_ver == 0x5390) 2767 rt3090_set_rx_antenna(sc, 0); 2768 2769 /* Patch RSSI inaccurate issue. */ 2770 rt2860_mcu_bbp_write(sc, 79, 0x13); 2771 rt2860_mcu_bbp_write(sc, 80, 0x05); 2772 rt2860_mcu_bbp_write(sc, 81, 0x33); 2773 2774 /* Enable DC filter. */ 2775 if (sc->mac_rev >= 0x0211) 2776 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2777 2778 bbp = rt2860_mcu_bbp_read(sc, 138); 2779 if (sc->ntxchains == 1) 2780 bbp |= 0x20; /* Turn off DAC1. */ 2781 if (sc->nrxchains == 1) 2782 bbp &= ~0x02; /* Turn off ADC1. */ 2783 rt2860_mcu_bbp_write(sc, 138, bbp); 2784 2785 /* Enable RX LO1 and LO2. */ 2786 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1); 2787 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2); 2788 2789 /* Avoid data lost and CRC error. */ 2790 rt2860_mcu_bbp_write(sc, 4, 2791 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL); 2792 2793 rf = rt3090_rf_read(sc, 30); 2794 rf = (rf & ~0x18) | 0x10; 2795 rt3090_rf_write(sc, 30, rf); 2796} 2797 2798static void 2799rt3090_rf_wakeup(struct rt2860_softc *sc) 2800{ 2801 uint32_t tmp; 2802 uint8_t rf; 2803 2804 if (sc->mac_ver == 0x3593) { 2805 /* enable VCO */ 2806 rf = rt3090_rf_read(sc, 1); 2807 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2808 2809 /* initiate VCO calibration */ 2810 rf = rt3090_rf_read(sc, 3); 2811 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2812 2813 /* enable VCO bias current control */ 2814 rf = rt3090_rf_read(sc, 6); 2815 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2816 2817 /* initiate res calibration */ 2818 rf = rt3090_rf_read(sc, 2); 2819 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2820 2821 /* set reference current control to 0.33 mA */ 2822 rf = rt3090_rf_read(sc, 22); 2823 rf &= ~RT3593_CP_IC_MASK; 2824 rf |= 1 << RT3593_CP_IC_SHIFT; 2825 rt3090_rf_write(sc, 22, rf); 2826 2827 /* enable RX CTB */ 2828 rf = rt3090_rf_read(sc, 46); 2829 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2830 2831 rf = rt3090_rf_read(sc, 20); 2832 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2833 rt3090_rf_write(sc, 20, rf); 2834 } else { 2835 /* enable RF block */ 2836 rf = rt3090_rf_read(sc, 1); 2837 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2838 2839 /* enable VCO bias current control */ 2840 rf = rt3090_rf_read(sc, 7); 2841 rt3090_rf_write(sc, 7, rf | 0x30); 2842 2843 rf = rt3090_rf_read(sc, 9); 2844 rt3090_rf_write(sc, 9, rf | 0x0e); 2845 2846 /* enable RX CTB */ 2847 rf = rt3090_rf_read(sc, 21); 2848 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2849 2850 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2851 rf = rt3090_rf_read(sc, 27); 2852 rf &= ~0x77; 2853 if (sc->mac_rev < 0x0211) 2854 rf |= 0x03; 2855 rt3090_rf_write(sc, 27, rf); 2856 } 2857 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2858 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2859 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2860 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2861 } 2862} 2863 2864static void 2865rt5390_rf_wakeup(struct rt2860_softc *sc) 2866{ 2867 uint32_t tmp; 2868 uint8_t rf; 2869 2870 rf = rt3090_rf_read(sc, 1); 2871 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | 2872 RT3070_TX0_PD; 2873 if (sc->mac_ver == 0x5392) 2874 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2875 rt3090_rf_write(sc, 1, rf); 2876 2877 rf = rt3090_rf_read(sc, 6); 2878 rf |= RT3593_VCO_IC | RT3593_VCOCAL; 2879 if (sc->mac_ver == 0x5390) 2880 rf &= ~RT3593_VCO_IC; 2881 rt3090_rf_write(sc, 6, rf); 2882 2883 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL); 2884 2885 rf = rt3090_rf_read(sc, 22); 2886 rf = (rf & ~0xe0) | 0x20; 2887 rt3090_rf_write(sc, 22, rf); 2888 2889 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB); 2890 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77); 2891 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL); 2892 2893 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2894 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2895 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2896 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2897 } 2898} 2899 2900static int 2901rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2902 uint8_t *val) 2903{ 2904 uint8_t rf22, rf24; 2905 uint8_t bbp55_pb, bbp55_sb, delta; 2906 int ntries; 2907 2908 /* program filter */ 2909 rf24 = rt3090_rf_read(sc, 24); 2910 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2911 rt3090_rf_write(sc, 24, rf24); 2912 2913 /* enable baseband loopback mode */ 2914 rf22 = rt3090_rf_read(sc, 22); 2915 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2916 2917 /* set power and frequency of passband test tone */ 2918 rt2860_mcu_bbp_write(sc, 24, 0x00); 2919 for (ntries = 0; ntries < 100; ntries++) { 2920 /* transmit test tone */ 2921 rt2860_mcu_bbp_write(sc, 25, 0x90); 2922 DELAY(1000); 2923 /* read received power */ 2924 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2925 if (bbp55_pb != 0) 2926 break; 2927 } 2928 if (ntries == 100) 2929 return (ETIMEDOUT); 2930 2931 /* set power and frequency of stopband test tone */ 2932 rt2860_mcu_bbp_write(sc, 24, 0x06); 2933 for (ntries = 0; ntries < 100; ntries++) { 2934 /* transmit test tone */ 2935 rt2860_mcu_bbp_write(sc, 25, 0x90); 2936 DELAY(1000); 2937 /* read received power */ 2938 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2939 2940 delta = bbp55_pb - bbp55_sb; 2941 if (delta > target) 2942 break; 2943 2944 /* reprogram filter */ 2945 rf24++; 2946 rt3090_rf_write(sc, 24, rf24); 2947 } 2948 if (ntries < 100) { 2949 if (rf24 != init) 2950 rf24--; /* backtrack */ 2951 *val = rf24; 2952 rt3090_rf_write(sc, 24, rf24); 2953 } 2954 2955 /* restore initial state */ 2956 rt2860_mcu_bbp_write(sc, 24, 0x00); 2957 2958 /* disable baseband loopback mode */ 2959 rf22 = rt3090_rf_read(sc, 22); 2960 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 2961 2962 return (0); 2963} 2964 2965static void 2966rt3090_rf_setup(struct rt2860_softc *sc) 2967{ 2968 uint8_t bbp; 2969 int i; 2970 2971 if (sc->mac_rev >= 0x0211) { 2972 /* enable DC filter */ 2973 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2974 2975 /* improve power consumption */ 2976 bbp = rt2860_mcu_bbp_read(sc, 31); 2977 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 2978 } 2979 2980 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2981 if (sc->mac_rev < 0x0211) { 2982 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 2983 sc->patch_dac ? 0x2c : 0x0f); 2984 } else 2985 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2986 2987 /* initialize RF registers from ROM */ 2988 if (sc->mac_ver < 0x5390) { 2989 for (i = 0; i < 10; i++) { 2990 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 2991 continue; 2992 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 2993 } 2994 } 2995} 2996 2997static void 2998rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 2999{ 3000 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3001 which | (sc->leds & 0x7f), 0); 3002} 3003 3004/* 3005 * Hardware has a general-purpose programmable timer interrupt that can 3006 * periodically raise MAC_INT_4. 3007 */ 3008static void 3009rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 3010{ 3011 uint32_t tmp; 3012 3013 /* disable GP timer before reprogramming it */ 3014 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3015 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 3016 3017 if (ms == 0) 3018 return; 3019 3020 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 3021 ms *= 16; /* Unit: 64us */ 3022 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 3023 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 3024 3025 /* enable GP timer */ 3026 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3027 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 3028} 3029 3030static void 3031rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 3032{ 3033 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 3034 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3035 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 3036 bssid[4] | bssid[5] << 8); 3037} 3038 3039static void 3040rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 3041{ 3042 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 3043 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3044 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 3045 addr[4] | addr[5] << 8 | 0xff << 16); 3046} 3047 3048static void 3049rt2860_updateslot(struct ieee80211com *ic) 3050{ 3051 struct rt2860_softc *sc = ic->ic_softc; 3052 uint32_t tmp; 3053 3054 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 3055 tmp &= ~0xff; 3056 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 3057 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3058} 3059 3060static void 3061rt2860_updateprot(struct rt2860_softc *sc) 3062{ 3063 struct ieee80211com *ic = &sc->sc_ic; 3064 uint32_t tmp; 3065 3066 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3067 /* setup protection frame rate (MCS code) */ 3068 tmp |= IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 3069 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 3070 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3071 3072 /* CCK frames don't require protection */ 3073 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 3074 3075 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3076 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3077 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3078 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3079 tmp |= RT2860_PROT_CTRL_CTS; 3080 } 3081 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 3082} 3083 3084static void 3085rt2860_update_promisc(struct ieee80211com *ic) 3086{ 3087 struct rt2860_softc *sc = ic->ic_softc; 3088 uint32_t tmp; 3089 3090 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG); 3091 tmp &= ~RT2860_DROP_NOT_MYBSS; 3092 if (ic->ic_promisc == 0) 3093 tmp |= RT2860_DROP_NOT_MYBSS; 3094 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3095} 3096 3097static int 3098rt2860_updateedca(struct ieee80211com *ic) 3099{ 3100 struct rt2860_softc *sc = ic->ic_softc; 3101 const struct wmeParams *wmep; 3102 int aci; 3103 3104 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 3105 3106 /* update MAC TX configuration registers */ 3107 for (aci = 0; aci < WME_NUM_AC; aci++) { 3108 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 3109 wmep[aci].wmep_logcwmax << 16 | 3110 wmep[aci].wmep_logcwmin << 12 | 3111 wmep[aci].wmep_aifsn << 8 | 3112 wmep[aci].wmep_txopLimit); 3113 } 3114 3115 /* update SCH/DMA registers too */ 3116 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 3117 wmep[WME_AC_VO].wmep_aifsn << 12 | 3118 wmep[WME_AC_VI].wmep_aifsn << 8 | 3119 wmep[WME_AC_BK].wmep_aifsn << 4 | 3120 wmep[WME_AC_BE].wmep_aifsn); 3121 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 3122 wmep[WME_AC_VO].wmep_logcwmin << 12 | 3123 wmep[WME_AC_VI].wmep_logcwmin << 8 | 3124 wmep[WME_AC_BK].wmep_logcwmin << 4 | 3125 wmep[WME_AC_BE].wmep_logcwmin); 3126 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 3127 wmep[WME_AC_VO].wmep_logcwmax << 12 | 3128 wmep[WME_AC_VI].wmep_logcwmax << 8 | 3129 wmep[WME_AC_BK].wmep_logcwmax << 4 | 3130 wmep[WME_AC_BE].wmep_logcwmax); 3131 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 3132 wmep[WME_AC_BK].wmep_txopLimit << 16 | 3133 wmep[WME_AC_BE].wmep_txopLimit); 3134 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 3135 wmep[WME_AC_VO].wmep_txopLimit << 16 | 3136 wmep[WME_AC_VI].wmep_txopLimit); 3137 3138 return 0; 3139} 3140 3141#ifdef HW_CRYPTO 3142static int 3143rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3144 struct ieee80211_key *k) 3145{ 3146 struct rt2860_softc *sc = ic->ic_softc; 3147 bus_size_t base; 3148 uint32_t attr; 3149 uint8_t mode, wcid, iv[8]; 3150 3151 /* defer setting of WEP keys until interface is brought up */ 3152 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 3153 (IFF_UP | IFF_RUNNING)) 3154 return 0; 3155 3156 /* map net80211 cipher to RT2860 security mode */ 3157 switch (k->k_cipher) { 3158 case IEEE80211_CIPHER_WEP40: 3159 mode = RT2860_MODE_WEP40; 3160 break; 3161 case IEEE80211_CIPHER_WEP104: 3162 mode = RT2860_MODE_WEP104; 3163 break; 3164 case IEEE80211_CIPHER_TKIP: 3165 mode = RT2860_MODE_TKIP; 3166 break; 3167 case IEEE80211_CIPHER_CCMP: 3168 mode = RT2860_MODE_AES_CCMP; 3169 break; 3170 default: 3171 return EINVAL; 3172 } 3173 3174 if (k->k_flags & IEEE80211_KEY_GROUP) { 3175 wcid = 0; /* NB: update WCID0 for group keys */ 3176 base = RT2860_SKEY(0, k->k_id); 3177 } else { 3178 wcid = ((struct rt2860_node *)ni)->wcid; 3179 base = RT2860_PKEY(wcid); 3180 } 3181 3182 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3183 RAL_WRITE_REGION_1(sc, base, k->k_key, 16); 3184#ifndef IEEE80211_STA_ONLY 3185 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3186 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8); 3187 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8); 3188 } else 3189#endif 3190 { 3191 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8); 3192 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8); 3193 } 3194 } else 3195 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len); 3196 3197 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 3198 (k->k_flags & IEEE80211_KEY_TX)) { 3199 /* set initial packet number in IV+EIV */ 3200 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 3201 k->k_cipher == IEEE80211_CIPHER_WEP104) { 3202 uint32_t val = arc4random(); 3203 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 3204 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 3205 val += 0x000100; 3206 iv[0] = val; 3207 iv[1] = val >> 8; 3208 iv[2] = val >> 16; 3209 iv[3] = k->k_id << 6; 3210 iv[4] = iv[5] = iv[6] = iv[7] = 0; 3211 } else { 3212 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3213 iv[0] = k->k_tsc >> 8; 3214 iv[1] = (iv[0] | 0x20) & 0x7f; 3215 iv[2] = k->k_tsc; 3216 } else /* CCMP */ { 3217 iv[0] = k->k_tsc; 3218 iv[1] = k->k_tsc >> 8; 3219 iv[2] = 0; 3220 } 3221 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3222 iv[4] = k->k_tsc >> 16; 3223 iv[5] = k->k_tsc >> 24; 3224 iv[6] = k->k_tsc >> 32; 3225 iv[7] = k->k_tsc >> 40; 3226 } 3227 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 3228 } 3229 3230 if (k->k_flags & IEEE80211_KEY_GROUP) { 3231 /* install group key */ 3232 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3233 attr &= ~(0xf << (k->k_id * 4)); 3234 attr |= mode << (k->k_id * 4); 3235 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3236 } else { 3237 /* install pairwise key */ 3238 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3239 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 3240 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3241 } 3242 return 0; 3243} 3244 3245static void 3246rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3247 struct ieee80211_key *k) 3248{ 3249 struct rt2860_softc *sc = ic->ic_softc; 3250 uint32_t attr; 3251 uint8_t wcid; 3252 3253 if (k->k_flags & IEEE80211_KEY_GROUP) { 3254 /* remove group key */ 3255 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3256 attr &= ~(0xf << (k->k_id * 4)); 3257 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3258 3259 } else { 3260 /* remove pairwise key */ 3261 wcid = ((struct rt2860_node *)ni)->wcid; 3262 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3263 attr &= ~0xf; 3264 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3265 } 3266} 3267#endif 3268 3269static int8_t 3270rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 3271{ 3272 struct ieee80211com *ic = &sc->sc_ic; 3273 struct ieee80211_channel *c = ic->ic_curchan; 3274 int delta; 3275 3276 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3277 u_int chan = ieee80211_chan2ieee(ic, c); 3278 delta = sc->rssi_5ghz[rxchain]; 3279 3280 /* determine channel group */ 3281 if (chan <= 64) 3282 delta -= sc->lna[1]; 3283 else if (chan <= 128) 3284 delta -= sc->lna[2]; 3285 else 3286 delta -= sc->lna[3]; 3287 } else 3288 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3289 3290 return -12 - delta - rssi; 3291} 3292 3293/* 3294 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 3295 * Used to adjust per-rate Tx power registers. 3296 */ 3297static __inline uint32_t 3298b4inc(uint32_t b32, int8_t delta) 3299{ 3300 int8_t i, b4; 3301 3302 for (i = 0; i < 8; i++) { 3303 b4 = b32 & 0xf; 3304 b4 += delta; 3305 if (b4 < 0) 3306 b4 = 0; 3307 else if (b4 > 0xf) 3308 b4 = 0xf; 3309 b32 = b32 >> 4 | b4 << 28; 3310 } 3311 return b32; 3312} 3313 3314static const char * 3315rt2860_get_rf(uint8_t rev) 3316{ 3317 switch (rev) { 3318 case RT2860_RF_2820: return "RT2820"; 3319 case RT2860_RF_2850: return "RT2850"; 3320 case RT2860_RF_2720: return "RT2720"; 3321 case RT2860_RF_2750: return "RT2750"; 3322 case RT3070_RF_3020: return "RT3020"; 3323 case RT3070_RF_2020: return "RT2020"; 3324 case RT3070_RF_3021: return "RT3021"; 3325 case RT3070_RF_3022: return "RT3022"; 3326 case RT3070_RF_3052: return "RT3052"; 3327 case RT3070_RF_3320: return "RT3320"; 3328 case RT3070_RF_3053: return "RT3053"; 3329 case RT5390_RF_5390: return "RT5390"; 3330 default: return "unknown"; 3331 } 3332} 3333 3334static int 3335rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 3336{ 3337 int8_t delta_2ghz, delta_5ghz; 3338 uint32_t tmp; 3339 uint16_t val; 3340 int ridx, ant, i; 3341 3342 /* check whether the ROM is eFUSE ROM or EEPROM */ 3343 sc->sc_srom_read = rt2860_eeprom_read_2; 3344 if (sc->mac_ver >= 0x3071) { 3345 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 3346 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3347 if (tmp & RT3070_SEL_EFUSE) 3348 sc->sc_srom_read = rt3090_efuse_read_2; 3349 } 3350 3351 /* read EEPROM version */ 3352 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 3353 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val >> 8, val & 0xff)); 3354 3355 /* read MAC address */ 3356 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 3357 macaddr[0] = val & 0xff; 3358 macaddr[1] = val >> 8; 3359 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 3360 macaddr[2] = val & 0xff; 3361 macaddr[3] = val >> 8; 3362 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 3363 macaddr[4] = val & 0xff; 3364 macaddr[5] = val >> 8; 3365 3366 /* read country code */ 3367 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 3368 DPRINTF(("EEPROM region code=0x%04x\n", val)); 3369 3370 /* read vendor BBP settings */ 3371 for (i = 0; i < 8; i++) { 3372 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 3373 sc->bbp[i].val = val & 0xff; 3374 sc->bbp[i].reg = val >> 8; 3375 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 3376 } 3377 if (sc->mac_ver >= 0x3071) { 3378 /* read vendor RF settings */ 3379 for (i = 0; i < 10; i++) { 3380 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 3381 sc->rf[i].val = val & 0xff; 3382 sc->rf[i].reg = val >> 8; 3383 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3384 sc->rf[i].val)); 3385 } 3386 } 3387 3388 /* read RF frequency offset from EEPROM */ 3389 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3390 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3391 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3392 if ((val >> 8) != 0xff) { 3393 /* read LEDs operating mode */ 3394 sc->leds = val >> 8; 3395 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3396 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3397 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3398 } else { 3399 /* broken EEPROM, use default settings */ 3400 sc->leds = 0x01; 3401 sc->led[0] = 0x5555; 3402 sc->led[1] = 0x2221; 3403 sc->led[2] = 0xa9f8; 3404 } 3405 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3406 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3407 3408 /* read RF information */ 3409 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3410 if (val == 0xffff) { 3411 DPRINTF(("invalid EEPROM antenna info, using default\n")); 3412 if (sc->mac_ver >= 0x5390) { 3413 /* default to RF5390 */ 3414 sc->rf_rev = RT5390_RF_5390; 3415 sc->ntxchains = (sc->mac_ver == 0x5392) ? 2 : 1; 3416 sc->nrxchains = (sc->mac_ver == 0x5392) ? 2 : 1; 3417 } else if (sc->mac_ver == 0x3593) { 3418 /* default to RF3053 3T3R */ 3419 sc->rf_rev = RT3070_RF_3053; 3420 sc->ntxchains = 3; 3421 sc->nrxchains = 3; 3422 } else if (sc->mac_ver >= 0x3071) { 3423 /* default to RF3020 1T1R */ 3424 sc->rf_rev = RT3070_RF_3020; 3425 sc->ntxchains = 1; 3426 sc->nrxchains = 1; 3427 } else { 3428 /* default to RF2820 1T2R */ 3429 sc->rf_rev = RT2860_RF_2820; 3430 sc->ntxchains = 1; 3431 sc->nrxchains = 2; 3432 } 3433 } else { 3434 sc->rf_rev = (val >> 8) & 0xf; 3435 if (sc->mac_ver >= 0x5390) { 3436 sc->ntxchains = (sc->mac_ver == 0x5392) ? 2 : 1; 3437 sc->nrxchains = (sc->mac_ver == 0x5392) ? 2 : 1; 3438 } else { 3439 sc->ntxchains = (val >> 4) & 0xf; 3440 sc->nrxchains = val & 0xf; 3441 } 3442 } 3443 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3444 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3445 3446 /* check if RF supports automatic Tx access gain control */ 3447 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3448 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3449 /* check if driver should patch the DAC issue */ 3450 if ((val >> 8) != 0xff) 3451 sc->patch_dac = (val >> 15) & 1; 3452 if ((val & 0xff) != 0xff) { 3453 sc->ext_5ghz_lna = (val >> 3) & 1; 3454 sc->ext_2ghz_lna = (val >> 2) & 1; 3455 /* check if RF supports automatic Tx access gain control */ 3456 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */; 3457 /* check if we have a hardware radio switch */ 3458 sc->rfswitch = val & 1; 3459 } 3460 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3461 /* read PCIe power save level */ 3462 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3463 if ((val & 0xff) != 0xff) { 3464 sc->pslevel = val & 0x3; 3465 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3466 if ((val & 0xff80) != 0x9280) 3467 sc->pslevel = MIN(sc->pslevel, 1); 3468 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3469 } 3470 } 3471 3472 /* read power settings for 2GHz channels */ 3473 for (i = 0; i < 14; i += 2) { 3474 val = rt2860_srom_read(sc, 3475 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3476 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3477 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3478 3479 if (sc->mac_ver != 0x5390) { 3480 val = rt2860_srom_read(sc, 3481 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3482 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3483 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3484 } 3485 } 3486 /* fix broken Tx power entries */ 3487 for (i = 0; i < 14; i++) { 3488 if (sc->txpow1[i] < 0 || 3489 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31)) 3490 sc->txpow1[i] = 5; 3491 if (sc->mac_ver != 0x5390) { 3492 if (sc->txpow2[i] < 0 || 3493 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31)) 3494 sc->txpow2[i] = 5; 3495 } 3496 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3497 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3498 } 3499 /* read power settings for 5GHz channels */ 3500 for (i = 0; i < 40; i += 2) { 3501 val = rt2860_srom_read(sc, 3502 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3503 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3504 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3505 3506 val = rt2860_srom_read(sc, 3507 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3508 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3509 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3510 } 3511 /* fix broken Tx power entries */ 3512 for (i = 0; i < 40; i++) { 3513 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3514 sc->txpow1[14 + i] = 5; 3515 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3516 sc->txpow2[14 + i] = 5; 3517 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3518 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3519 sc->txpow2[14 + i])); 3520 } 3521 3522 /* read Tx power compensation for each Tx rate */ 3523 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3524 delta_2ghz = delta_5ghz = 0; 3525 if ((val & 0xff) != 0xff && (val & 0x80)) { 3526 delta_2ghz = val & 0xf; 3527 if (!(val & 0x40)) /* negative number */ 3528 delta_2ghz = -delta_2ghz; 3529 } 3530 val >>= 8; 3531 if ((val & 0xff) != 0xff && (val & 0x80)) { 3532 delta_5ghz = val & 0xf; 3533 if (!(val & 0x40)) /* negative number */ 3534 delta_5ghz = -delta_5ghz; 3535 } 3536 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3537 delta_2ghz, delta_5ghz)); 3538 3539 for (ridx = 0; ridx < 5; ridx++) { 3540 uint32_t reg; 3541 3542 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3543 reg = val; 3544 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3545 reg |= (uint32_t)val << 16; 3546 3547 sc->txpow20mhz[ridx] = reg; 3548 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3549 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3550 3551 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3552 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3553 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3554 } 3555 3556 /* read factory-calibrated samples for temperature compensation */ 3557 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3558 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3559 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3560 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3561 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3562 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3563 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3564 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3565 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3566 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3567 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3568 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3569 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3570 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3571 sc->step_2ghz = val >> 8; 3572 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3573 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3574 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3575 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3576 sc->tssi_2ghz[8], sc->step_2ghz)); 3577 /* check that ref value is correct, otherwise disable calibration */ 3578 if (sc->tssi_2ghz[4] == 0xff) 3579 sc->calib_2ghz = 0; 3580 3581 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3582 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3583 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3584 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3585 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3586 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3587 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3588 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3589 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3590 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3591 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3592 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3593 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3594 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3595 sc->step_5ghz = val >> 8; 3596 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3597 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3598 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3599 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3600 sc->tssi_5ghz[8], sc->step_5ghz)); 3601 /* check that ref value is correct, otherwise disable calibration */ 3602 if (sc->tssi_5ghz[4] == 0xff) 3603 sc->calib_5ghz = 0; 3604 3605 /* read RSSI offsets and LNA gains from EEPROM */ 3606 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3607 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3608 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3609 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3610 if (sc->mac_ver >= 0x3071) { 3611 /* 3612 * On RT3090 chips (limited to 2 Rx chains), this ROM 3613 * field contains the Tx mixer gain for the 2GHz band. 3614 */ 3615 if ((val & 0xff) != 0xff) 3616 sc->txmixgain_2ghz = val & 0x7; 3617 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3618 } else 3619 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3620 sc->lna[2] = val >> 8; /* channel group 2 */ 3621 3622 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3623 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3624 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3625 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3626 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3627 sc->lna[3] = val >> 8; /* channel group 3 */ 3628 3629 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3630 if (sc->mac_ver >= 0x3071) 3631 sc->lna[0] = RT3090_DEF_LNA; 3632 else /* channel group 0 */ 3633 sc->lna[0] = val & 0xff; 3634 sc->lna[1] = val >> 8; /* channel group 1 */ 3635 3636 /* fix broken 5GHz LNA entries */ 3637 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3638 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3639 sc->lna[2] = sc->lna[1]; 3640 } 3641 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3642 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3643 sc->lna[3] = sc->lna[1]; 3644 } 3645 3646 /* fix broken RSSI offset entries */ 3647 for (ant = 0; ant < 3; ant++) { 3648 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3649 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3650 ant + 1, sc->rssi_2ghz[ant])); 3651 sc->rssi_2ghz[ant] = 0; 3652 } 3653 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3654 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3655 ant + 1, sc->rssi_5ghz[ant])); 3656 sc->rssi_5ghz[ant] = 0; 3657 } 3658 } 3659 3660 return 0; 3661} 3662 3663static int 3664rt2860_bbp_init(struct rt2860_softc *sc) 3665{ 3666 int i, ntries; 3667 3668 /* wait for BBP to wake up */ 3669 for (ntries = 0; ntries < 20; ntries++) { 3670 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3671 if (bbp0 != 0 && bbp0 != 0xff) 3672 break; 3673 } 3674 if (ntries == 20) { 3675 device_printf(sc->sc_dev, 3676 "timeout waiting for BBP to wake up\n"); 3677 return (ETIMEDOUT); 3678 } 3679 3680 /* initialize BBP registers to default values */ 3681 if (sc->mac_ver >= 0x5390) 3682 rt5390_bbp_init(sc); 3683 else { 3684 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3685 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3686 rt2860_def_bbp[i].val); 3687 } 3688 } 3689 3690 /* fix BBP84 for RT2860E */ 3691 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3692 rt2860_mcu_bbp_write(sc, 84, 0x19); 3693 3694 if (sc->mac_ver >= 0x3071) { 3695 rt2860_mcu_bbp_write(sc, 79, 0x13); 3696 rt2860_mcu_bbp_write(sc, 80, 0x05); 3697 rt2860_mcu_bbp_write(sc, 81, 0x33); 3698 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3699 rt2860_mcu_bbp_write(sc, 69, 0x16); 3700 rt2860_mcu_bbp_write(sc, 73, 0x12); 3701 } 3702 3703 return 0; 3704} 3705 3706static void 3707rt5390_bbp_init(struct rt2860_softc *sc) 3708{ 3709 uint8_t bbp; 3710 int i; 3711 3712 /* Apply maximum likelihood detection for 2 stream case. */ 3713 if (sc->nrxchains > 1) { 3714 bbp = rt2860_mcu_bbp_read(sc, 105); 3715 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD); 3716 } 3717 3718 /* Avoid data lost and CRC error. */ 3719 bbp = rt2860_mcu_bbp_read(sc, 4); 3720 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3721 3722 for (i = 0; i < nitems(rt5390_def_bbp); i++) { 3723 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg, 3724 rt5390_def_bbp[i].val); 3725 } 3726 3727 if (sc->mac_ver == 0x5392) { 3728 rt2860_mcu_bbp_write(sc, 84, 0x9a); 3729 rt2860_mcu_bbp_write(sc, 95, 0x9a); 3730 rt2860_mcu_bbp_write(sc, 98, 0x12); 3731 rt2860_mcu_bbp_write(sc, 106, 0x05); 3732 rt2860_mcu_bbp_write(sc, 134, 0xd0); 3733 rt2860_mcu_bbp_write(sc, 135, 0xf6); 3734 } 3735 3736 bbp = rt2860_mcu_bbp_read(sc, 152); 3737 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80); 3738 3739 /* Disable hardware antenna diversity. */ 3740 if (sc->mac_ver == 0x5390) 3741 rt2860_mcu_bbp_write(sc, 154, 0); 3742} 3743 3744static int 3745rt2860_txrx_enable(struct rt2860_softc *sc) 3746{ 3747 struct ieee80211com *ic = &sc->sc_ic; 3748 uint32_t tmp; 3749 int ntries; 3750 3751 /* enable Tx/Rx DMA engine */ 3752 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3753 RAL_BARRIER_READ_WRITE(sc); 3754 for (ntries = 0; ntries < 200; ntries++) { 3755 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3756 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3757 break; 3758 DELAY(1000); 3759 } 3760 if (ntries == 200) { 3761 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3762 return ETIMEDOUT; 3763 } 3764 3765 DELAY(50); 3766 3767 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3768 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3769 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3770 3771 /* set Rx filter */ 3772 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3773 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3774 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3775 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3776 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3777 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3778 if (ic->ic_opmode == IEEE80211_M_STA) 3779 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3780 } 3781 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3782 3783 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3784 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3785 3786 return 0; 3787} 3788 3789static void 3790rt2860_init(void *arg) 3791{ 3792 struct rt2860_softc *sc = arg; 3793 struct ieee80211com *ic = &sc->sc_ic; 3794 3795 RAL_LOCK(sc); 3796 rt2860_init_locked(sc); 3797 RAL_UNLOCK(sc); 3798 3799 if (sc->sc_flags & RT2860_RUNNNING) 3800 ieee80211_start_all(ic); 3801} 3802 3803static void 3804rt2860_init_locked(struct rt2860_softc *sc) 3805{ 3806 struct ieee80211com *ic = &sc->sc_ic; 3807 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3808 uint32_t tmp; 3809 uint8_t bbp1, bbp3; 3810 int i, qid, ridx, ntries, error; 3811 3812 RAL_LOCK_ASSERT(sc); 3813 3814 if (sc->rfswitch) { 3815 /* hardware has a radio switch on GPIO pin 2 */ 3816 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3817 device_printf(sc->sc_dev, 3818 "radio is disabled by hardware switch\n"); 3819#ifdef notyet 3820 rt2860_stop_locked(sc); 3821 return; 3822#endif 3823 } 3824 } 3825 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3826 3827 /* disable DMA */ 3828 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3829 tmp &= 0xff0; 3830 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3831 3832 /* PBF hardware reset */ 3833 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3834 RAL_BARRIER_WRITE(sc); 3835 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3836 3837 if ((error = rt2860_load_microcode(sc)) != 0) { 3838 device_printf(sc->sc_dev, "could not load 8051 microcode\n"); 3839 rt2860_stop_locked(sc); 3840 return; 3841 } 3842 3843 rt2860_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 3844 3845 /* init Tx power for all Tx rates (from EEPROM) */ 3846 for (ridx = 0; ridx < 5; ridx++) { 3847 if (sc->txpow20mhz[ridx] == 0xffffffff) 3848 continue; 3849 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3850 } 3851 3852 for (ntries = 0; ntries < 100; ntries++) { 3853 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3854 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3855 break; 3856 DELAY(1000); 3857 } 3858 if (ntries == 100) { 3859 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3860 rt2860_stop_locked(sc); 3861 return; 3862 } 3863 tmp &= 0xff0; 3864 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3865 3866 /* reset Rx ring and all 6 Tx rings */ 3867 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3868 3869 /* PBF hardware reset */ 3870 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3871 RAL_BARRIER_WRITE(sc); 3872 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3873 3874 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3875 3876 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3877 RAL_BARRIER_WRITE(sc); 3878 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3879 3880 for (i = 0; i < nitems(rt2860_def_mac); i++) 3881 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3882 if (sc->mac_ver >= 0x5390) 3883 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404); 3884 else if (sc->mac_ver >= 0x3071) { 3885 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3886 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3887 4 << RT2860_DLY_PAPE_EN_SHIFT); 3888 } 3889 3890 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3891 sc->sc_flags |= RT2860_PCIE; 3892 /* PCIe has different clock cycle count than PCI */ 3893 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3894 tmp = (tmp & ~0xff) | 0x7d; 3895 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3896 } 3897 3898 /* wait while MAC is busy */ 3899 for (ntries = 0; ntries < 100; ntries++) { 3900 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3901 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3902 break; 3903 DELAY(1000); 3904 } 3905 if (ntries == 100) { 3906 device_printf(sc->sc_dev, "timeout waiting for MAC\n"); 3907 rt2860_stop_locked(sc); 3908 return; 3909 } 3910 3911 /* clear Host to MCU mailbox */ 3912 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3913 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3914 3915 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3916 DELAY(1000); 3917 3918 if ((error = rt2860_bbp_init(sc)) != 0) { 3919 rt2860_stop_locked(sc); 3920 return; 3921 } 3922 3923 /* clear RX WCID search table */ 3924 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3925 /* clear pairwise key table */ 3926 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3927 /* clear IV/EIV table */ 3928 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3929 /* clear WCID attribute table */ 3930 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3931 /* clear shared key table */ 3932 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3933 /* clear shared key mode */ 3934 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3935 3936 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3937 for (qid = 0; qid < 6; qid++) { 3938 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3939 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3940 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 3941 } 3942 3943 /* init Rx ring */ 3944 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 3945 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 3946 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 3947 3948 /* setup maximum buffer sizes */ 3949 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 3950 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 3951 3952 for (ntries = 0; ntries < 100; ntries++) { 3953 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3954 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3955 break; 3956 DELAY(1000); 3957 } 3958 if (ntries == 100) { 3959 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3960 rt2860_stop_locked(sc); 3961 return; 3962 } 3963 tmp &= 0xff0; 3964 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3965 3966 /* disable interrupts mitigation */ 3967 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 3968 3969 /* write vendor-specific BBP values (from EEPROM) */ 3970 for (i = 0; i < 8; i++) { 3971 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 3972 continue; 3973 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 3974 } 3975 3976 /* select Main antenna for 1T1R devices */ 3977 if (sc->rf_rev == RT3070_RF_2020 || 3978 sc->rf_rev == RT3070_RF_3020 || 3979 sc->rf_rev == RT3070_RF_3320 || 3980 sc->mac_ver == 0x5390) 3981 rt3090_set_rx_antenna(sc, 0); 3982 3983 /* send LEDs operating mode to microcontroller */ 3984 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 3985 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 3986 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 3987 3988 if (sc->mac_ver >= 0x5390) 3989 rt5390_rf_init(sc); 3990 else if (sc->mac_ver >= 0x3071) { 3991 if ((error = rt3090_rf_init(sc)) != 0) { 3992 rt2860_stop_locked(sc); 3993 return; 3994 } 3995 } 3996 3997 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 3998 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 3999 4000 if (sc->mac_ver >= 0x5390) 4001 rt5390_rf_wakeup(sc); 4002 else if (sc->mac_ver >= 0x3071) 4003 rt3090_rf_wakeup(sc); 4004 4005 /* disable non-existing Rx chains */ 4006 bbp3 = rt2860_mcu_bbp_read(sc, 3); 4007 bbp3 &= ~(1 << 3 | 1 << 4); 4008 if (sc->nrxchains == 2) 4009 bbp3 |= 1 << 3; 4010 else if (sc->nrxchains == 3) 4011 bbp3 |= 1 << 4; 4012 rt2860_mcu_bbp_write(sc, 3, bbp3); 4013 4014 /* disable non-existing Tx chains */ 4015 bbp1 = rt2860_mcu_bbp_read(sc, 1); 4016 if (sc->ntxchains == 1) 4017 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 4018 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 4019 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 4020 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 4021 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 4022 rt2860_mcu_bbp_write(sc, 1, bbp1); 4023 4024 if (sc->mac_ver >= 0x3071) 4025 rt3090_rf_setup(sc); 4026 4027 /* select default channel */ 4028 rt2860_switch_chan(sc, ic->ic_curchan); 4029 4030 /* reset RF from MCU */ 4031 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 4032 4033 /* set RTS threshold */ 4034 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 4035 tmp &= ~0xffff00; 4036 tmp |= IEEE80211_RTS_DEFAULT << 8; 4037 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 4038 4039 /* setup initial protection mode */ 4040 rt2860_updateprot(sc); 4041 4042 /* turn radio LED on */ 4043 rt2860_set_leds(sc, RT2860_LED_RADIO); 4044 4045 /* enable Tx/Rx DMA engine */ 4046 if ((error = rt2860_txrx_enable(sc)) != 0) { 4047 rt2860_stop_locked(sc); 4048 return; 4049 } 4050 4051 /* clear pending interrupts */ 4052 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 4053 /* enable interrupts */ 4054 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 4055 4056 if (sc->sc_flags & RT2860_ADVANCED_PS) 4057 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 4058 4059 sc->sc_flags |= RT2860_RUNNNING; 4060 4061 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 4062} 4063 4064static void 4065rt2860_stop(void *arg) 4066{ 4067 struct rt2860_softc *sc = arg; 4068 4069 RAL_LOCK(sc); 4070 rt2860_stop_locked(sc); 4071 RAL_UNLOCK(sc); 4072} 4073 4074static void 4075rt2860_stop_locked(struct rt2860_softc *sc) 4076{ 4077 uint32_t tmp; 4078 int qid; 4079 4080 if (sc->sc_flags & RT2860_RUNNNING) 4081 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 4082 4083 callout_stop(&sc->watchdog_ch); 4084 sc->sc_tx_timer = 0; 4085 sc->sc_flags &= ~RT2860_RUNNNING; 4086 4087 /* disable interrupts */ 4088 RAL_WRITE(sc, RT2860_INT_MASK, 0); 4089 4090 /* disable GP timer */ 4091 rt2860_set_gp_timer(sc, 0); 4092 4093 /* disable Rx */ 4094 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 4095 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4096 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 4097 4098 /* reset adapter */ 4099 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4100 RAL_BARRIER_WRITE(sc); 4101 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 4102 4103 /* reset Tx and Rx rings (and reclaim TXWIs) */ 4104 sc->qfullmsk = 0; 4105 for (qid = 0; qid < 6; qid++) 4106 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 4107 rt2860_reset_rx_ring(sc, &sc->rxq); 4108} 4109 4110int 4111rt2860_load_microcode(struct rt2860_softc *sc) 4112{ 4113 const struct firmware *fp; 4114 int ntries, error; 4115 4116 RAL_LOCK_ASSERT(sc); 4117 4118 RAL_UNLOCK(sc); 4119 fp = firmware_get("rt2860fw"); 4120 RAL_LOCK(sc); 4121 if (fp == NULL) { 4122 device_printf(sc->sc_dev, 4123 "unable to receive rt2860fw firmware image\n"); 4124 return EINVAL; 4125 } 4126 4127 /* set "host program ram write selection" bit */ 4128 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 4129 /* write microcode image */ 4130 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, fp->data, fp->datasize); 4131 /* kick microcontroller unit */ 4132 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 4133 RAL_BARRIER_WRITE(sc); 4134 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 4135 4136 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 4137 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 4138 4139 /* wait until microcontroller is ready */ 4140 RAL_BARRIER_READ_WRITE(sc); 4141 for (ntries = 0; ntries < 1000; ntries++) { 4142 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 4143 break; 4144 DELAY(1000); 4145 } 4146 if (ntries == 1000) { 4147 device_printf(sc->sc_dev, 4148 "timeout waiting for MCU to initialize\n"); 4149 error = ETIMEDOUT; 4150 } else 4151 error = 0; 4152 4153 firmware_put(fp, FIRMWARE_UNLOAD); 4154 return error; 4155} 4156 4157/* 4158 * This function is called periodically to adjust Tx power based on 4159 * temperature variation. 4160 */ 4161#ifdef NOT_YET 4162static void 4163rt2860_calib(struct rt2860_softc *sc) 4164{ 4165 struct ieee80211com *ic = &sc->sc_ic; 4166 const uint8_t *tssi; 4167 uint8_t step, bbp49; 4168 int8_t ridx, d; 4169 4170 /* read current temperature */ 4171 bbp49 = rt2860_mcu_bbp_read(sc, 49); 4172 4173 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 4174 tssi = &sc->tssi_2ghz[4]; 4175 step = sc->step_2ghz; 4176 } else { 4177 tssi = &sc->tssi_5ghz[4]; 4178 step = sc->step_5ghz; 4179 } 4180 4181 if (bbp49 < tssi[0]) { /* lower than reference */ 4182 /* use higher Tx power than default */ 4183 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 4184 } else if (bbp49 > tssi[0]) { /* greater than reference */ 4185 /* use lower Tx power than default */ 4186 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 4187 } else { 4188 /* use default Tx power */ 4189 d = 0; 4190 } 4191 d *= step; 4192 4193 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 4194 4195 /* write adjusted Tx power values for each Tx rate */ 4196 for (ridx = 0; ridx < 5; ridx++) { 4197 if (sc->txpow20mhz[ridx] == 0xffffffff) 4198 continue; 4199 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 4200 b4inc(sc->txpow20mhz[ridx], d)); 4201 } 4202} 4203#endif 4204 4205static void 4206rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 4207{ 4208 uint32_t tmp; 4209 4210 if (aux) { 4211 if (sc->mac_ver == 0x5390) { 4212 rt2860_mcu_bbp_write(sc, 152, 4213 rt2860_mcu_bbp_read(sc, 152) & ~0x80); 4214 } else { 4215 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4216 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C); 4217 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4218 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 4219 } 4220 } else { 4221 if (sc->mac_ver == 0x5390) { 4222 rt2860_mcu_bbp_write(sc, 152, 4223 rt2860_mcu_bbp_read(sc, 152) | 0x80); 4224 } else { 4225 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4226 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C); 4227 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4228 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 4229 } 4230 } 4231} 4232 4233static void 4234rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 4235{ 4236 struct ieee80211com *ic = &sc->sc_ic; 4237 u_int chan, group; 4238 4239 chan = ieee80211_chan2ieee(ic, c); 4240 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 4241 return; 4242 4243 if (sc->mac_ver >= 0x5390) 4244 rt5390_set_chan(sc, chan); 4245 else if (sc->mac_ver >= 0x3071) 4246 rt3090_set_chan(sc, chan); 4247 else 4248 rt2860_set_chan(sc, chan); 4249 4250 /* determine channel group */ 4251 if (chan <= 14) 4252 group = 0; 4253 else if (chan <= 64) 4254 group = 1; 4255 else if (chan <= 128) 4256 group = 2; 4257 else 4258 group = 3; 4259 4260 /* XXX necessary only when group has changed! */ 4261 if (sc->mac_ver < 0x5390) 4262 rt2860_select_chan_group(sc, group); 4263 4264 DELAY(1000); 4265} 4266 4267static int 4268rt2860_setup_beacon(struct rt2860_softc *sc, struct ieee80211vap *vap) 4269{ 4270 struct ieee80211com *ic = vap->iv_ic; 4271 struct ieee80211_beacon_offsets bo; 4272 struct rt2860_txwi txwi; 4273 struct mbuf *m; 4274 int ridx; 4275 4276 if ((m = ieee80211_beacon_alloc(vap->iv_bss, &bo)) == NULL) 4277 return ENOBUFS; 4278 4279 memset(&txwi, 0, sizeof txwi); 4280 txwi.wcid = 0xff; 4281 txwi.len = htole16(m->m_pkthdr.len); 4282 /* send beacons at the lowest available rate */ 4283 ridx = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 4284 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4285 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4286 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4287 txwi.phy |= htole16(RT2860_PHY_OFDM); 4288 txwi.txop = RT2860_TX_TXOP_HT; 4289 txwi.flags = RT2860_TX_TS; 4290 txwi.xflags = RT2860_TX_NSEQ; 4291 4292 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 4293 (uint8_t *)&txwi, sizeof txwi); 4294 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 4295 mtod(m, uint8_t *), m->m_pkthdr.len); 4296 4297 m_freem(m); 4298 4299 return 0; 4300} 4301 4302static void 4303rt2860_enable_tsf_sync(struct rt2860_softc *sc) 4304{ 4305 struct ieee80211com *ic = &sc->sc_ic; 4306 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4307 uint32_t tmp; 4308 4309 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 4310 4311 tmp &= ~0x1fffff; 4312 tmp |= vap->iv_bss->ni_intval * 16; 4313 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 4314 if (vap->iv_opmode == IEEE80211_M_STA) { 4315 /* 4316 * Local TSF is always updated with remote TSF on beacon 4317 * reception. 4318 */ 4319 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 4320 } 4321 else if (vap->iv_opmode == IEEE80211_M_IBSS || 4322 vap->iv_opmode == IEEE80211_M_MBSS) { 4323 tmp |= RT2860_BCN_TX_EN; 4324 /* 4325 * Local TSF is updated with remote TSF on beacon reception 4326 * only if the remote TSF is greater than local TSF. 4327 */ 4328 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 4329 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) { 4330 tmp |= RT2860_BCN_TX_EN; 4331 /* SYNC with nobody */ 4332 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 4333 } 4334 4335 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 4336} 4337