rt2860.c revision 260444
1/*- 2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $OpenBSD: rt2860.c,v 1.65 2010/10/23 14:24:54 damien Exp $ 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/ral/rt2860.c 260444 2014-01-08 08:06:56Z kevlo $"); 22 23/*- 24 * Ralink Technology RT2860/RT3090/RT3390/RT3562 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28#include <sys/param.h> 29#include <sys/sysctl.h> 30#include <sys/sockio.h> 31#include <sys/mbuf.h> 32#include <sys/kernel.h> 33#include <sys/socket.h> 34#include <sys/systm.h> 35#include <sys/malloc.h> 36#include <sys/lock.h> 37#include <sys/mutex.h> 38#include <sys/module.h> 39#include <sys/bus.h> 40#include <sys/endian.h> 41#include <sys/firmware.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <sys/rman.h> 46 47#include <net/bpf.h> 48#include <net/if.h> 49#include <net/if_var.h> 50#include <net/if_arp.h> 51#include <net/ethernet.h> 52#include <net/if_dl.h> 53#include <net/if_media.h> 54#include <net/if_types.h> 55 56#include <net80211/ieee80211_var.h> 57#include <net80211/ieee80211_radiotap.h> 58#include <net80211/ieee80211_regdomain.h> 59#include <net80211/ieee80211_ratectl.h> 60 61#include <netinet/in.h> 62#include <netinet/in_systm.h> 63#include <netinet/in_var.h> 64#include <netinet/ip.h> 65#include <netinet/if_ether.h> 66 67#include <dev/ral/rt2860reg.h> 68#include <dev/ral/rt2860var.h> 69 70#define RAL_DEBUG 71#ifdef RAL_DEBUG 72#define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0) 73#define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0) 74#else 75#define DPRINTF(x) 76#define DPRINTFN(n, x) 77#endif 78 79static struct ieee80211vap *rt2860_vap_create(struct ieee80211com *, 80 const char [IFNAMSIZ], int, enum ieee80211_opmode, 81 int, const uint8_t [IEEE80211_ADDR_LEN], 82 const uint8_t [IEEE80211_ADDR_LEN]); 83static void rt2860_vap_delete(struct ieee80211vap *); 84static void rt2860_dma_map_addr(void *, bus_dma_segment_t *, int, int); 85static int rt2860_alloc_tx_ring(struct rt2860_softc *, 86 struct rt2860_tx_ring *); 87static void rt2860_reset_tx_ring(struct rt2860_softc *, 88 struct rt2860_tx_ring *); 89static void rt2860_free_tx_ring(struct rt2860_softc *, 90 struct rt2860_tx_ring *); 91static int rt2860_alloc_tx_pool(struct rt2860_softc *); 92static void rt2860_free_tx_pool(struct rt2860_softc *); 93static int rt2860_alloc_rx_ring(struct rt2860_softc *, 94 struct rt2860_rx_ring *); 95static void rt2860_reset_rx_ring(struct rt2860_softc *, 96 struct rt2860_rx_ring *); 97static void rt2860_free_rx_ring(struct rt2860_softc *, 98 struct rt2860_rx_ring *); 99static void rt2860_updatestats(struct rt2860_softc *); 100static void rt2860_newassoc(struct ieee80211_node *, int); 101static void rt2860_node_free(struct ieee80211_node *); 102#ifdef IEEE80211_HT 103static int rt2860_ampdu_rx_start(struct ieee80211com *, 104 struct ieee80211_node *, uint8_t); 105static void rt2860_ampdu_rx_stop(struct ieee80211com *, 106 struct ieee80211_node *, uint8_t); 107#endif 108static int rt2860_newstate(struct ieee80211vap *, enum ieee80211_state, 109 int); 110static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 111static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 112static void rt2860_intr_coherent(struct rt2860_softc *); 113static void rt2860_drain_stats_fifo(struct rt2860_softc *); 114static void rt2860_tx_intr(struct rt2860_softc *, int); 115static void rt2860_rx_intr(struct rt2860_softc *); 116static void rt2860_tbtt_intr(struct rt2860_softc *); 117static void rt2860_gp_intr(struct rt2860_softc *); 118static int rt2860_tx(struct rt2860_softc *, struct mbuf *, 119 struct ieee80211_node *); 120static int rt2860_raw_xmit(struct ieee80211_node *, struct mbuf *, 121 const struct ieee80211_bpf_params *); 122static int rt2860_tx_raw(struct rt2860_softc *, struct mbuf *, 123 struct ieee80211_node *, 124 const struct ieee80211_bpf_params *params); 125static void rt2860_start(struct ifnet *); 126static void rt2860_start_locked(struct ifnet *); 127static void rt2860_watchdog(void *); 128static int rt2860_ioctl(struct ifnet *, u_long, caddr_t); 129static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 130static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 131static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 132static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 133static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 134static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 135static void rt2860_enable_mrr(struct rt2860_softc *); 136static void rt2860_set_txpreamble(struct rt2860_softc *); 137static void rt2860_set_basicrates(struct rt2860_softc *, 138 const struct ieee80211_rateset *); 139static void rt2860_scan_start(struct ieee80211com *); 140static void rt2860_scan_end(struct ieee80211com *); 141static void rt2860_set_channel(struct ieee80211com *); 142static void rt2860_select_chan_group(struct rt2860_softc *, int); 143static void rt2860_set_chan(struct rt2860_softc *, u_int); 144static void rt3090_set_chan(struct rt2860_softc *, u_int); 145static int rt3090_rf_init(struct rt2860_softc *); 146static void rt3090_rf_wakeup(struct rt2860_softc *); 147static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 148 uint8_t *); 149static void rt3090_rf_setup(struct rt2860_softc *); 150static void rt2860_set_leds(struct rt2860_softc *, uint16_t); 151static void rt2860_set_gp_timer(struct rt2860_softc *, int); 152static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 153static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 154static void rt2860_update_promisc(struct ifnet *); 155static void rt2860_updateslot(struct ifnet *); 156static void rt2860_updateprot(struct ifnet *); 157static int rt2860_updateedca(struct ieee80211com *); 158#ifdef HW_CRYPTO 159static int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *, 160 struct ieee80211_key *); 161static void rt2860_delete_key(struct ieee80211com *, 162 struct ieee80211_node *, struct ieee80211_key *); 163#endif 164static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 165static const char *rt2860_get_rf(uint8_t); 166static int rt2860_read_eeprom(struct rt2860_softc *, 167 uint8_t macaddr[IEEE80211_ADDR_LEN]); 168static int rt2860_bbp_init(struct rt2860_softc *); 169static int rt2860_txrx_enable(struct rt2860_softc *); 170static void rt2860_init(void *); 171static void rt2860_init_locked(struct rt2860_softc *); 172static void rt2860_stop(void *); 173static void rt2860_stop_locked(struct rt2860_softc *); 174static int rt2860_load_microcode(struct rt2860_softc *); 175#ifdef NOT_YET 176static void rt2860_calib(struct rt2860_softc *); 177#endif 178static void rt3090_set_rx_antenna(struct rt2860_softc *, int); 179static void rt2860_switch_chan(struct rt2860_softc *, 180 struct ieee80211_channel *); 181static int rt2860_setup_beacon(struct rt2860_softc *, 182 struct ieee80211vap *); 183static void rt2860_enable_tsf_sync(struct rt2860_softc *); 184 185static const struct { 186 uint32_t reg; 187 uint32_t val; 188} rt2860_def_mac[] = { 189 RT2860_DEF_MAC 190}; 191 192static const struct { 193 uint8_t reg; 194 uint8_t val; 195} rt2860_def_bbp[] = { 196 RT2860_DEF_BBP 197}; 198 199static const struct rfprog { 200 uint8_t chan; 201 uint32_t r1, r2, r3, r4; 202} rt2860_rf2850[] = { 203 RT2860_RF2850 204}; 205 206struct { 207 uint8_t n, r, k; 208} rt3090_freqs[] = { 209 RT3070_RF3052 210}; 211 212static const struct { 213 uint8_t reg; 214 uint8_t val; 215} rt3090_def_rf[] = { 216 RT3070_DEF_RF 217}; 218 219int 220rt2860_attach(device_t dev, int id) 221{ 222 struct rt2860_softc *sc = device_get_softc(dev); 223 struct ieee80211com *ic; 224 struct ifnet *ifp; 225 uint32_t tmp; 226 int error, ntries, qid; 227 uint8_t bands; 228 uint8_t macaddr[IEEE80211_ADDR_LEN]; 229 230 sc->sc_dev = dev; 231 sc->sc_debug = 0; 232 233 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 234 if (ifp == NULL) { 235 device_printf(sc->sc_dev, "can not if_alloc()\n"); 236 return ENOMEM; 237 } 238 ic = ifp->if_l2com; 239 240 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 241 MTX_DEF | MTX_RECURSE); 242 243 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 244 245 /* wait for NIC to initialize */ 246 for (ntries = 0; ntries < 100; ntries++) { 247 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID); 248 if (tmp != 0 && tmp != 0xffffffff) 249 break; 250 DELAY(10); 251 } 252 if (ntries == 100) { 253 device_printf(sc->sc_dev, 254 "timeout waiting for NIC to initialize\n"); 255 error = EIO; 256 goto fail1; 257 } 258 sc->mac_ver = tmp >> 16; 259 sc->mac_rev = tmp & 0xffff; 260 261 if (sc->mac_ver != 0x2860 && 262 (id == 0x0681 || id == 0x0781 || id == 0x1059)) 263 sc->sc_flags |= RT2860_ADVANCED_PS; 264 265 /* retrieve RF rev. no and various other things from EEPROM */ 266 rt2860_read_eeprom(sc, macaddr); 267 if (bootverbose) { 268 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), " 269 "RF %s (MIMO %dT%dR), address %6D\n", 270 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev), 271 sc->ntxchains, sc->nrxchains, macaddr, ":"); 272 } 273 274 /* 275 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 276 */ 277 for (qid = 0; qid < 6; qid++) { 278 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 279 device_printf(sc->sc_dev, 280 "could not allocate Tx ring %d\n", qid); 281 goto fail2; 282 } 283 } 284 285 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 286 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 287 goto fail2; 288 } 289 290 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 291 device_printf(sc->sc_dev, "could not allocate Tx pool\n"); 292 goto fail3; 293 } 294 295 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 296 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 297 WME_AC_VO : 5; 298 299 ifp->if_softc = sc; 300 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 301 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 302 ifp->if_init = rt2860_init; 303 ifp->if_ioctl = rt2860_ioctl; 304 ifp->if_start = rt2860_start; 305 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 306 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 307 IFQ_SET_READY(&ifp->if_snd); 308 309 ic->ic_ifp = ifp; 310 ic->ic_opmode = IEEE80211_M_STA; 311 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 312 313 /* set device capabilities */ 314 ic->ic_caps = 315 IEEE80211_C_STA /* station mode */ 316 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 317 | IEEE80211_C_HOSTAP /* hostap mode */ 318 | IEEE80211_C_MONITOR /* monitor mode */ 319 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 320 | IEEE80211_C_WDS /* 4-address traffic works */ 321 | IEEE80211_C_MBSS /* mesh point link mode */ 322 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 323 | IEEE80211_C_SHSLOT /* short slot time supported */ 324 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 325#if 0 326 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 327#endif 328 | IEEE80211_C_WME /* 802.11e */ 329 ; 330 331 bands = 0; 332 setbit(&bands, IEEE80211_MODE_11B); 333 setbit(&bands, IEEE80211_MODE_11G); 334 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) 335 setbit(&bands, IEEE80211_MODE_11A); 336 ieee80211_init_channels(ic, NULL, &bands); 337 338 ieee80211_ifattach(ic, macaddr); 339 340 ic->ic_wme.wme_update = rt2860_updateedca; 341 ic->ic_scan_start = rt2860_scan_start; 342 ic->ic_scan_end = rt2860_scan_end; 343 ic->ic_set_channel = rt2860_set_channel; 344 ic->ic_updateslot = rt2860_updateslot; 345 ic->ic_update_promisc = rt2860_update_promisc; 346 ic->ic_raw_xmit = rt2860_raw_xmit; 347 sc->sc_node_free = ic->ic_node_free; 348 ic->ic_node_free = rt2860_node_free; 349 ic->ic_newassoc = rt2860_newassoc; 350 351 ic->ic_vap_create = rt2860_vap_create; 352 ic->ic_vap_delete = rt2860_vap_delete; 353 354 ieee80211_radiotap_attach(ic, 355 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 356 RT2860_TX_RADIOTAP_PRESENT, 357 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 358 RT2860_RX_RADIOTAP_PRESENT); 359 360#ifdef RAL_DEBUG 361 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 362 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 363 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 364#endif 365 if (bootverbose) 366 ieee80211_announce(ic); 367 368 return 0; 369 370fail3: rt2860_free_rx_ring(sc, &sc->rxq); 371fail2: while (--qid >= 0) 372 rt2860_free_tx_ring(sc, &sc->txq[qid]); 373fail1: mtx_destroy(&sc->sc_mtx); 374 if_free(ifp); 375 return error; 376} 377 378int 379rt2860_detach(void *xsc) 380{ 381 struct rt2860_softc *sc = xsc; 382 struct ifnet *ifp = sc->sc_ifp; 383 struct ieee80211com *ic = ifp->if_l2com; 384 int qid; 385 386 RAL_LOCK(sc); 387 rt2860_stop_locked(sc); 388 RAL_UNLOCK(sc); 389 390 ieee80211_ifdetach(ic); 391 392 for (qid = 0; qid < 6; qid++) 393 rt2860_free_tx_ring(sc, &sc->txq[qid]); 394 rt2860_free_rx_ring(sc, &sc->rxq); 395 rt2860_free_tx_pool(sc); 396 397 if_free(ifp); 398 399 mtx_destroy(&sc->sc_mtx); 400 401 return 0; 402} 403 404void 405rt2860_shutdown(void *xsc) 406{ 407 struct rt2860_softc *sc = xsc; 408 409 rt2860_stop(sc); 410} 411 412void 413rt2860_suspend(void *xsc) 414{ 415 struct rt2860_softc *sc = xsc; 416 417 rt2860_stop(sc); 418} 419 420void 421rt2860_resume(void *xsc) 422{ 423 struct rt2860_softc *sc = xsc; 424 struct ifnet *ifp = sc->sc_ifp; 425 426 if (ifp->if_flags & IFF_UP) 427 rt2860_init(sc); 428} 429 430static struct ieee80211vap * 431rt2860_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 432 enum ieee80211_opmode opmode, int flags, 433 const uint8_t bssid[IEEE80211_ADDR_LEN], 434 const uint8_t mac[IEEE80211_ADDR_LEN]) 435{ 436 struct ifnet *ifp = ic->ic_ifp; 437 struct rt2860_vap *rvp; 438 struct ieee80211vap *vap; 439 440 switch (opmode) { 441 case IEEE80211_M_STA: 442 case IEEE80211_M_IBSS: 443 case IEEE80211_M_AHDEMO: 444 case IEEE80211_M_MONITOR: 445 case IEEE80211_M_HOSTAP: 446 case IEEE80211_M_MBSS: 447 /* XXXRP: TBD */ 448 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 449 if_printf(ifp, "only 1 vap supported\n"); 450 return NULL; 451 } 452 if (opmode == IEEE80211_M_STA) 453 flags |= IEEE80211_CLONE_NOBEACONS; 454 break; 455 case IEEE80211_M_WDS: 456 if (TAILQ_EMPTY(&ic->ic_vaps) || 457 ic->ic_opmode != IEEE80211_M_HOSTAP) { 458 if_printf(ifp, "wds only supported in ap mode\n"); 459 return NULL; 460 } 461 /* 462 * Silently remove any request for a unique 463 * bssid; WDS vap's always share the local 464 * mac address. 465 */ 466 flags &= ~IEEE80211_CLONE_BSSID; 467 break; 468 default: 469 if_printf(ifp, "unknown opmode %d\n", opmode); 470 return NULL; 471 } 472 rvp = malloc(sizeof(struct rt2860_vap), M_80211_VAP, M_NOWAIT | M_ZERO); 473 if (rvp == NULL) 474 return NULL; 475 vap = &rvp->ral_vap; 476 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 477 478 /* override state transition machine */ 479 rvp->ral_newstate = vap->iv_newstate; 480 vap->iv_newstate = rt2860_newstate; 481#if 0 482 vap->iv_update_beacon = rt2860_beacon_update; 483#endif 484 485 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 486 vap->iv_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 487 488 ieee80211_ratectl_init(vap); 489 /* complete setup */ 490 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); 491 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 492 ic->ic_opmode = opmode; 493 return vap; 494} 495 496static void 497rt2860_vap_delete(struct ieee80211vap *vap) 498{ 499 struct rt2860_vap *rvp = RT2860_VAP(vap); 500 501 ieee80211_ratectl_deinit(vap); 502 ieee80211_vap_detach(vap); 503 free(rvp, M_80211_VAP); 504} 505 506static void 507rt2860_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 508{ 509 if (error != 0) 510 return; 511 512 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 513 514 *(bus_addr_t *)arg = segs[0].ds_addr; 515} 516 517 518static int 519rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 520{ 521 int size, error; 522 523 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 524 525 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 526 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 527 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 528 if (error != 0) { 529 device_printf(sc->sc_dev, "could not create desc DMA map\n"); 530 goto fail; 531 } 532 533 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->txd, 534 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 535 if (error != 0) { 536 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 537 goto fail; 538 } 539 540 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->txd, 541 size, rt2860_dma_map_addr, &ring->paddr, 0); 542 if (error != 0) { 543 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 544 goto fail; 545 } 546 547 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 548 549 return 0; 550 551fail: rt2860_free_tx_ring(sc, ring); 552 return error; 553} 554 555void 556rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 557{ 558 struct rt2860_tx_data *data; 559 int i; 560 561 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 562 if ((data = ring->data[i]) == NULL) 563 continue; /* nothing mapped in this slot */ 564 565 if (data->m != NULL) { 566 bus_dmamap_sync(sc->txwi_dmat, data->map, 567 BUS_DMASYNC_POSTWRITE); 568 bus_dmamap_unload(sc->txwi_dmat, data->map); 569 m_freem(data->m); 570 data->m = NULL; 571 } 572 if (data->ni != NULL) { 573 ieee80211_free_node(data->ni); 574 data->ni = NULL; 575 } 576 577 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 578 ring->data[i] = NULL; 579 } 580 581 ring->queued = 0; 582 ring->cur = ring->next = 0; 583} 584 585void 586rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 587{ 588 struct rt2860_tx_data *data; 589 int i; 590 591 if (ring->txd != NULL) { 592 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 593 BUS_DMASYNC_POSTWRITE); 594 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 595 bus_dmamem_free(ring->desc_dmat, ring->txd, ring->desc_map); 596 } 597 if (ring->desc_dmat != NULL) 598 bus_dma_tag_destroy(ring->desc_dmat); 599 600 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 601 if ((data = ring->data[i]) == NULL) 602 continue; /* nothing mapped in this slot */ 603 604 if (data->m != NULL) { 605 bus_dmamap_sync(sc->txwi_dmat, data->map, 606 BUS_DMASYNC_POSTWRITE); 607 bus_dmamap_unload(sc->txwi_dmat, data->map); 608 m_freem(data->m); 609 } 610 if (data->ni != NULL) 611 ieee80211_free_node(data->ni); 612 613 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 614 } 615} 616 617/* 618 * Allocate a pool of TX Wireless Information blocks. 619 */ 620int 621rt2860_alloc_tx_pool(struct rt2860_softc *sc) 622{ 623 caddr_t vaddr; 624 bus_addr_t paddr; 625 int i, size, error; 626 627 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 628 629 /* init data_pool early in case of failure.. */ 630 SLIST_INIT(&sc->data_pool); 631 632 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 633 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 634 size, 1, size, 0, NULL, NULL, &sc->txwi_dmat); 635 if (error != 0) { 636 device_printf(sc->sc_dev, "could not create txwi DMA tag\n"); 637 goto fail; 638 } 639 640 error = bus_dmamem_alloc(sc->txwi_dmat, (void **)&sc->txwi_vaddr, 641 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->txwi_map); 642 if (error != 0) { 643 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 644 goto fail; 645 } 646 647 error = bus_dmamap_load(sc->txwi_dmat, sc->txwi_map, 648 sc->txwi_vaddr, size, rt2860_dma_map_addr, &paddr, 0); 649 if (error != 0) { 650 device_printf(sc->sc_dev, "could not load txwi DMA map\n"); 651 goto fail; 652 } 653 654 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 655 656 vaddr = sc->txwi_vaddr; 657 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 658 struct rt2860_tx_data *data = &sc->data[i]; 659 660 error = bus_dmamap_create(sc->txwi_dmat, 0, &data->map); 661 if (error != 0) { 662 device_printf(sc->sc_dev, "could not create DMA map\n"); 663 goto fail; 664 } 665 data->txwi = (struct rt2860_txwi *)vaddr; 666 data->paddr = paddr; 667 vaddr += RT2860_TXWI_DMASZ; 668 paddr += RT2860_TXWI_DMASZ; 669 670 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 671 } 672 673 return 0; 674 675fail: rt2860_free_tx_pool(sc); 676 return error; 677} 678 679void 680rt2860_free_tx_pool(struct rt2860_softc *sc) 681{ 682 if (sc->txwi_vaddr != NULL) { 683 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, 684 BUS_DMASYNC_POSTWRITE); 685 bus_dmamap_unload(sc->txwi_dmat, sc->txwi_map); 686 bus_dmamem_free(sc->txwi_dmat, sc->txwi_vaddr, sc->txwi_map); 687 } 688 if (sc->txwi_dmat != NULL) 689 bus_dma_tag_destroy(sc->txwi_dmat); 690 691 while (!SLIST_EMPTY(&sc->data_pool)) { 692 struct rt2860_tx_data *data; 693 data = SLIST_FIRST(&sc->data_pool); 694 bus_dmamap_destroy(sc->txwi_dmat, data->map); 695 SLIST_REMOVE_HEAD(&sc->data_pool, next); 696 } 697} 698 699int 700rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 701{ 702 bus_addr_t physaddr; 703 int i, size, error; 704 705 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 706 707 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 708 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 709 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 710 if (error != 0) { 711 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 712 goto fail; 713 } 714 715 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->rxd, 716 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 717 if (error != 0) { 718 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 719 goto fail; 720 } 721 722 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->rxd, 723 size, rt2860_dma_map_addr, &ring->paddr, 0); 724 if (error != 0) { 725 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 726 goto fail; 727 } 728 729 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 730 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 731 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 732 if (error != 0) { 733 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 734 goto fail; 735 } 736 737 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 738 struct rt2860_rx_data *data = &ring->data[i]; 739 struct rt2860_rxd *rxd = &ring->rxd[i]; 740 741 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 742 if (error != 0) { 743 device_printf(sc->sc_dev, "could not create DMA map\n"); 744 goto fail; 745 } 746 747 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 748 if (data->m == NULL) { 749 device_printf(sc->sc_dev, 750 "could not allocate rx mbuf\n"); 751 error = ENOMEM; 752 goto fail; 753 } 754 755 error = bus_dmamap_load(ring->data_dmat, data->map, 756 mtod(data->m, void *), MCLBYTES, rt2860_dma_map_addr, 757 &physaddr, 0); 758 if (error != 0) { 759 device_printf(sc->sc_dev, 760 "could not load rx buf DMA map"); 761 goto fail; 762 } 763 764 rxd->sdp0 = htole32(physaddr); 765 rxd->sdl0 = htole16(MCLBYTES); 766 } 767 768 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 769 770 return 0; 771 772fail: rt2860_free_rx_ring(sc, ring); 773 return error; 774} 775 776void 777rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 778{ 779 int i; 780 781 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 782 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 783 784 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 785 786 ring->cur = 0; 787} 788 789void 790rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 791{ 792 int i; 793 794 if (ring->rxd != NULL) { 795 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 796 BUS_DMASYNC_POSTWRITE); 797 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 798 bus_dmamem_free(ring->desc_dmat, ring->rxd, ring->desc_map); 799 } 800 if (ring->desc_dmat != NULL) 801 bus_dma_tag_destroy(ring->desc_dmat); 802 803 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 804 struct rt2860_rx_data *data = &ring->data[i]; 805 806 if (data->m != NULL) { 807 bus_dmamap_sync(ring->data_dmat, data->map, 808 BUS_DMASYNC_POSTREAD); 809 bus_dmamap_unload(ring->data_dmat, data->map); 810 m_freem(data->m); 811 } 812 if (data->map != NULL) 813 bus_dmamap_destroy(ring->data_dmat, data->map); 814 } 815 if (ring->data_dmat != NULL) 816 bus_dma_tag_destroy(ring->data_dmat); 817} 818 819static void 820rt2860_updatestats(struct rt2860_softc *sc) 821{ 822 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 823 824 /* 825 * In IBSS or HostAP modes (when the hardware sends beacons), the 826 * MAC can run into a livelock and start sending CTS-to-self frames 827 * like crazy if protection is enabled. Fortunately, we can detect 828 * when such a situation occurs and reset the MAC. 829 */ 830 if (ic->ic_curmode != IEEE80211_M_STA) { 831 /* check if we're in a livelock situation.. */ 832 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 833 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 834 /* ..and reset MAC/BBP for a while.. */ 835 DPRINTF(("CTS-to-self livelock detected\n")); 836 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 837 RAL_BARRIER_WRITE(sc); 838 DELAY(1); 839 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 840 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 841 } 842 } 843} 844 845static void 846rt2860_newassoc(struct ieee80211_node *ni, int isnew) 847{ 848 struct ieee80211com *ic = ni->ni_ic; 849 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 850 uint8_t wcid; 851 852 wcid = IEEE80211_AID(ni->ni_associd); 853 if (isnew && ni->ni_associd != 0) { 854 sc->wcid2ni[wcid] = ni; 855 856 /* init WCID table entry */ 857 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 858 ni->ni_macaddr, IEEE80211_ADDR_LEN); 859 } 860 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 861 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 862} 863 864static void 865rt2860_node_free(struct ieee80211_node *ni) 866{ 867 struct ieee80211com *ic = ni->ni_ic; 868 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 869 uint8_t wcid; 870 871 if (ni->ni_associd != 0) { 872 wcid = IEEE80211_AID(ni->ni_associd); 873 874 /* clear Rx WCID search table entry */ 875 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2); 876 } 877 sc->sc_node_free(ni); 878} 879 880#ifdef IEEE80211_HT 881static int 882rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 883 uint8_t tid) 884{ 885 struct rt2860_softc *sc = ic->ic_softc; 886 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 887 uint32_t tmp; 888 889 /* update BA session mask */ 890 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 891 tmp |= (1 << tid) << 16; 892 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 893 return 0; 894} 895 896static void 897rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 898 uint8_t tid) 899{ 900 struct rt2860_softc *sc = ic->ic_softc; 901 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 902 uint32_t tmp; 903 904 /* update BA session mask */ 905 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 906 tmp &= ~((1 << tid) << 16); 907 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 908} 909#endif 910 911int 912rt2860_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 913{ 914 struct rt2860_vap *rvp = RT2860_VAP(vap); 915 struct ieee80211com *ic = vap->iv_ic; 916 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 917 uint32_t tmp; 918 int error; 919 920 if (vap->iv_state == IEEE80211_S_RUN) { 921 /* turn link LED off */ 922 rt2860_set_leds(sc, RT2860_LED_RADIO); 923 } 924 925 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 926 /* abort TSF synchronization */ 927 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 928 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 929 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 930 RT2860_TBTT_TIMER_EN)); 931 } 932 933 rt2860_set_gp_timer(sc, 0); 934 935 error = rvp->ral_newstate(vap, nstate, arg); 936 if (error != 0) 937 return (error); 938 939 if (nstate == IEEE80211_S_RUN) { 940 struct ieee80211_node *ni = vap->iv_bss; 941 942 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 943 rt2860_enable_mrr(sc); 944 rt2860_set_txpreamble(sc); 945 rt2860_set_basicrates(sc, &ni->ni_rates); 946 rt2860_set_bssid(sc, ni->ni_bssid); 947 } 948 949 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 950 vap->iv_opmode == IEEE80211_M_IBSS || 951 vap->iv_opmode == IEEE80211_M_MBSS) { 952 error = rt2860_setup_beacon(sc, vap); 953 if (error != 0) 954 return error; 955 } 956 957 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 958 rt2860_enable_tsf_sync(sc); 959 rt2860_set_gp_timer(sc, 500); 960 } 961 962 /* turn link LED on */ 963 rt2860_set_leds(sc, RT2860_LED_RADIO | 964 (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan) ? 965 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 966 } 967 return error; 968} 969 970/* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 971static uint16_t 972rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 973{ 974 uint32_t tmp; 975 uint16_t reg; 976 int ntries; 977 978 addr *= 2; 979 /*- 980 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 981 * DATA0: F E D C 982 * DATA1: B A 9 8 983 * DATA2: 7 6 5 4 984 * DATA3: 3 2 1 0 985 */ 986 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 987 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 988 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 989 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 990 for (ntries = 0; ntries < 500; ntries++) { 991 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 992 if (!(tmp & RT3070_EFSROM_KICK)) 993 break; 994 DELAY(2); 995 } 996 if (ntries == 500) 997 return 0xffff; 998 999 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 1000 return 0xffff; /* address not found */ 1001 1002 /* determine to which 32-bit register our 16-bit word belongs */ 1003 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1004 tmp = RAL_READ(sc, reg); 1005 1006 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 1007} 1008 1009/* 1010 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 1011 * 93C66 or 93C86). 1012 */ 1013static uint16_t 1014rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1015{ 1016 uint32_t tmp; 1017 uint16_t val; 1018 int n; 1019 1020 /* clock C once before the first command */ 1021 RT2860_EEPROM_CTL(sc, 0); 1022 1023 RT2860_EEPROM_CTL(sc, RT2860_S); 1024 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1025 RT2860_EEPROM_CTL(sc, RT2860_S); 1026 1027 /* write start bit (1) */ 1028 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1029 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1030 1031 /* write READ opcode (10) */ 1032 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1033 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1034 RT2860_EEPROM_CTL(sc, RT2860_S); 1035 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1036 1037 /* write address (A5-A0 or A7-A0) */ 1038 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1039 for (; n >= 0; n--) { 1040 RT2860_EEPROM_CTL(sc, RT2860_S | 1041 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1042 RT2860_EEPROM_CTL(sc, RT2860_S | 1043 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1044 } 1045 1046 RT2860_EEPROM_CTL(sc, RT2860_S); 1047 1048 /* read data Q15-Q0 */ 1049 val = 0; 1050 for (n = 15; n >= 0; n--) { 1051 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1052 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1053 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1054 RT2860_EEPROM_CTL(sc, RT2860_S); 1055 } 1056 1057 RT2860_EEPROM_CTL(sc, 0); 1058 1059 /* clear Chip Select and clock C */ 1060 RT2860_EEPROM_CTL(sc, RT2860_S); 1061 RT2860_EEPROM_CTL(sc, 0); 1062 RT2860_EEPROM_CTL(sc, RT2860_C); 1063 1064 return val; 1065} 1066 1067static __inline uint16_t 1068rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1069{ 1070 /* either eFUSE ROM or EEPROM */ 1071 return sc->sc_srom_read(sc, addr); 1072} 1073 1074static void 1075rt2860_intr_coherent(struct rt2860_softc *sc) 1076{ 1077 uint32_t tmp; 1078 1079 /* DMA finds data coherent event when checking the DDONE bit */ 1080 1081 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1082 1083 /* restart DMA engine */ 1084 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1085 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1086 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1087 1088 (void)rt2860_txrx_enable(sc); 1089} 1090 1091static void 1092rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1093{ 1094 struct ifnet *ifp = sc->sc_ifp; 1095 struct ieee80211_node *ni; 1096 uint32_t stat; 1097 int retrycnt; 1098 uint8_t wcid, mcs, pid; 1099 1100 /* drain Tx status FIFO (maxsize = 16) */ 1101 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1102 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1103 1104 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1105 ni = sc->wcid2ni[wcid]; 1106 1107 /* if no ACK was requested, no feedback is available */ 1108 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff || ni == NULL) 1109 continue; 1110 1111 /* update per-STA AMRR stats */ 1112 if (stat & RT2860_TXQ_OK) { 1113 /* 1114 * Check if there were retries, ie if the Tx success 1115 * rate is different from the requested rate. Note 1116 * that it works only because we do not allow rate 1117 * fallback from OFDM to CCK. 1118 */ 1119 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1120 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1121 if (mcs + 1 != pid) 1122 retrycnt = 1; 1123 else 1124 retrycnt = 0; 1125 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 1126 IEEE80211_RATECTL_TX_SUCCESS, &retrycnt, NULL); 1127 } else { 1128 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 1129 IEEE80211_RATECTL_TX_FAILURE, &retrycnt, NULL); 1130 ifp->if_oerrors++; 1131 } 1132 } 1133} 1134 1135static void 1136rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1137{ 1138 struct ifnet *ifp = sc->sc_ifp; 1139 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1140 uint32_t hw; 1141 1142 rt2860_drain_stats_fifo(sc); 1143 1144 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1145 while (ring->next != hw) { 1146 struct rt2860_tx_data *data = ring->data[ring->next]; 1147 1148 if (data != NULL) { 1149 bus_dmamap_sync(sc->txwi_dmat, data->map, 1150 BUS_DMASYNC_POSTWRITE); 1151 bus_dmamap_unload(sc->txwi_dmat, data->map); 1152 if (data->m->m_flags & M_TXCB) { 1153 ieee80211_process_callback(data->ni, data->m, 1154 0); 1155 } 1156 m_freem(data->m); 1157 ieee80211_free_node(data->ni); 1158 data->m = NULL; 1159 data->ni = NULL; 1160 1161 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1162 ring->data[ring->next] = NULL; 1163 1164 ifp->if_opackets++; 1165 } 1166 ring->queued--; 1167 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1168 } 1169 1170 sc->sc_tx_timer = 0; 1171 if (ring->queued < RT2860_TX_RING_COUNT) 1172 sc->qfullmsk &= ~(1 << qid); 1173 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1174 rt2860_start_locked(ifp); 1175} 1176 1177/* 1178 * Return the Rx chain with the highest RSSI for a given frame. 1179 */ 1180static __inline uint8_t 1181rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1182{ 1183 uint8_t rxchain = 0; 1184 1185 if (sc->nrxchains > 1) { 1186 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1187 rxchain = 1; 1188 if (sc->nrxchains > 2) 1189 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1190 rxchain = 2; 1191 } 1192 return rxchain; 1193} 1194 1195static void 1196rt2860_rx_intr(struct rt2860_softc *sc) 1197{ 1198 struct rt2860_rx_radiotap_header *tap; 1199 struct ifnet *ifp = sc->sc_ifp; 1200 struct ieee80211com *ic = ifp->if_l2com; 1201 struct ieee80211_frame *wh; 1202 struct ieee80211_node *ni; 1203 struct mbuf *m, *m1; 1204 bus_addr_t physaddr; 1205 uint32_t hw; 1206 uint16_t phy; 1207 uint8_t ant; 1208 int8_t rssi, nf; 1209 int error; 1210 1211 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1212 while (sc->rxq.cur != hw) { 1213 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1214 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1215 struct rt2860_rxwi *rxwi; 1216 1217 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1218 BUS_DMASYNC_POSTREAD); 1219 1220 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1221 DPRINTF(("RXD DDONE bit not set!\n")); 1222 break; /* should not happen */ 1223 } 1224 1225 if (__predict_false(rxd->flags & 1226 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1227 ifp->if_ierrors++; 1228 goto skip; 1229 } 1230 1231#ifdef HW_CRYPTO 1232 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1233 /* report MIC failures to net80211 for TKIP */ 1234 ic->ic_stats.is_rx_locmicfail++; 1235 ieee80211_michael_mic_failure(ic, 0/* XXX */); 1236 ifp->if_ierrors++; 1237 goto skip; 1238 } 1239#endif 1240 1241 m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1242 if (__predict_false(m1 == NULL)) { 1243 ifp->if_ierrors++; 1244 goto skip; 1245 } 1246 1247 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1248 BUS_DMASYNC_POSTREAD); 1249 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1250 1251 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1252 mtod(m1, void *), MCLBYTES, rt2860_dma_map_addr, 1253 &physaddr, 0); 1254 if (__predict_false(error != 0)) { 1255 m_freem(m1); 1256 1257 /* try to reload the old mbuf */ 1258 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1259 mtod(data->m, void *), MCLBYTES, 1260 rt2860_dma_map_addr, &physaddr, 0); 1261 if (__predict_false(error != 0)) { 1262 panic("%s: could not load old rx mbuf", 1263 device_get_name(sc->sc_dev)); 1264 } 1265 /* physical address may have changed */ 1266 rxd->sdp0 = htole32(physaddr); 1267 ifp->if_ierrors++; 1268 goto skip; 1269 } 1270 1271 /* 1272 * New mbuf successfully loaded, update Rx ring and continue 1273 * processing. 1274 */ 1275 m = data->m; 1276 data->m = m1; 1277 rxd->sdp0 = htole32(physaddr); 1278 1279 rxwi = mtod(m, struct rt2860_rxwi *); 1280 1281 /* finalize mbuf */ 1282 m->m_pkthdr.rcvif = ifp; 1283 m->m_data = (caddr_t)(rxwi + 1); 1284 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff; 1285 1286 wh = mtod(m, struct ieee80211_frame *); 1287#ifdef HW_CRYPTO 1288 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1289 /* frame is decrypted by hardware */ 1290 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1291 } 1292#endif 1293 1294 /* HW may insert 2 padding bytes after 802.11 header */ 1295 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1296 u_int hdrlen = ieee80211_hdrsize(wh); 1297 ovbcopy(wh, (caddr_t)wh + 2, hdrlen); 1298 m->m_data += 2; 1299 wh = mtod(m, struct ieee80211_frame *); 1300 } 1301 1302 ant = rt2860_maxrssi_chain(sc, rxwi); 1303 rssi = rt2860_rssi2dbm(sc, rxwi->rssi[ant], ant); 1304 nf = RT2860_NOISE_FLOOR; 1305 1306 if (ieee80211_radiotap_active(ic)) { 1307 tap = &sc->sc_rxtap; 1308 tap->wr_flags = 0; 1309 tap->wr_antenna = ant; 1310 tap->wr_antsignal = nf + rssi; 1311 tap->wr_antnoise = nf; 1312 /* in case it can't be found below */ 1313 tap->wr_rate = 2; 1314 phy = le16toh(rxwi->phy); 1315 switch (phy & RT2860_PHY_MODE) { 1316 case RT2860_PHY_CCK: 1317 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1318 case 0: tap->wr_rate = 2; break; 1319 case 1: tap->wr_rate = 4; break; 1320 case 2: tap->wr_rate = 11; break; 1321 case 3: tap->wr_rate = 22; break; 1322 } 1323 if (phy & RT2860_PHY_SHPRE) 1324 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1325 break; 1326 case RT2860_PHY_OFDM: 1327 switch (phy & RT2860_PHY_MCS) { 1328 case 0: tap->wr_rate = 12; break; 1329 case 1: tap->wr_rate = 18; break; 1330 case 2: tap->wr_rate = 24; break; 1331 case 3: tap->wr_rate = 36; break; 1332 case 4: tap->wr_rate = 48; break; 1333 case 5: tap->wr_rate = 72; break; 1334 case 6: tap->wr_rate = 96; break; 1335 case 7: tap->wr_rate = 108; break; 1336 } 1337 break; 1338 } 1339 } 1340 1341 RAL_UNLOCK(sc); 1342 wh = mtod(m, struct ieee80211_frame *); 1343 1344 /* send the frame to the 802.11 layer */ 1345 ni = ieee80211_find_rxnode(ic, 1346 (struct ieee80211_frame_min *)wh); 1347 if (ni != NULL) { 1348 (void)ieee80211_input(ni, m, rssi - nf, nf); 1349 ieee80211_free_node(ni); 1350 } else 1351 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 1352 1353 RAL_LOCK(sc); 1354 1355skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1356 1357 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1358 BUS_DMASYNC_PREWRITE); 1359 1360 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1361 } 1362 1363 /* tell HW what we have processed */ 1364 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1365 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1366} 1367 1368static void 1369rt2860_tbtt_intr(struct rt2860_softc *sc) 1370{ 1371#if 0 1372 struct ieee80211com *ic = &sc->sc_ic; 1373 1374#ifndef IEEE80211_STA_ONLY 1375 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1376 /* one less beacon until next DTIM */ 1377 if (ic->ic_dtim_count == 0) 1378 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1379 else 1380 ic->ic_dtim_count--; 1381 1382 /* update dynamic parts of beacon */ 1383 rt2860_setup_beacon(sc); 1384 1385 /* flush buffered multicast frames */ 1386 if (ic->ic_dtim_count == 0) 1387 ieee80211_notify_dtim(ic); 1388 } 1389#endif 1390 /* check if protection mode has changed */ 1391 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1392 rt2860_updateprot(ic); 1393 sc->sc_ic_flags = ic->ic_flags; 1394 } 1395#endif 1396} 1397 1398static void 1399rt2860_gp_intr(struct rt2860_softc *sc) 1400{ 1401 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1402 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1403 1404 DPRINTFN(2, ("GP timeout state=%d\n", vap->iv_state)); 1405 1406 if (vap->iv_state == IEEE80211_S_RUN) 1407 rt2860_updatestats(sc); 1408} 1409 1410void 1411rt2860_intr(void *arg) 1412{ 1413 struct rt2860_softc *sc = arg; 1414 uint32_t r; 1415 1416 RAL_LOCK(sc); 1417 1418 r = RAL_READ(sc, RT2860_INT_STATUS); 1419 if (__predict_false(r == 0xffffffff)) { 1420 RAL_UNLOCK(sc); 1421 return; /* device likely went away */ 1422 } 1423 if (r == 0) { 1424 RAL_UNLOCK(sc); 1425 return; /* not for us */ 1426 } 1427 1428 /* acknowledge interrupts */ 1429 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1430 1431 if (r & RT2860_TX_RX_COHERENT) 1432 rt2860_intr_coherent(sc); 1433 1434 if (r & RT2860_MAC_INT_2) /* TX status */ 1435 rt2860_drain_stats_fifo(sc); 1436 1437 if (r & RT2860_TX_DONE_INT5) 1438 rt2860_tx_intr(sc, 5); 1439 1440 if (r & RT2860_RX_DONE_INT) 1441 rt2860_rx_intr(sc); 1442 1443 if (r & RT2860_TX_DONE_INT4) 1444 rt2860_tx_intr(sc, 4); 1445 1446 if (r & RT2860_TX_DONE_INT3) 1447 rt2860_tx_intr(sc, 3); 1448 1449 if (r & RT2860_TX_DONE_INT2) 1450 rt2860_tx_intr(sc, 2); 1451 1452 if (r & RT2860_TX_DONE_INT1) 1453 rt2860_tx_intr(sc, 1); 1454 1455 if (r & RT2860_TX_DONE_INT0) 1456 rt2860_tx_intr(sc, 0); 1457 1458 if (r & RT2860_MAC_INT_0) /* TBTT */ 1459 rt2860_tbtt_intr(sc); 1460 1461 if (r & RT2860_MAC_INT_3) /* Auto wakeup */ 1462 /* TBD wakeup */; 1463 1464 if (r & RT2860_MAC_INT_4) /* GP timer */ 1465 rt2860_gp_intr(sc); 1466 1467 RAL_UNLOCK(sc); 1468} 1469 1470static int 1471rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1472{ 1473 struct ifnet *ifp = sc->sc_ifp; 1474 struct ieee80211com *ic = ifp->if_l2com; 1475 struct ieee80211vap *vap = ni->ni_vap; 1476 struct rt2860_tx_ring *ring; 1477 struct rt2860_tx_data *data; 1478 struct rt2860_txd *txd; 1479 struct rt2860_txwi *txwi; 1480 struct ieee80211_frame *wh; 1481 const struct ieee80211_txparam *tp; 1482 struct ieee80211_key *k; 1483 struct mbuf *m1; 1484 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1485 bus_dma_segment_t *seg; 1486 u_int hdrlen; 1487 uint16_t qos, dur; 1488 uint8_t type, qsel, mcs, pid, tid, qid; 1489 int i, nsegs, ntxds, pad, rate, ridx, error; 1490 1491 /* the data pool contains at least one element, pick the first */ 1492 data = SLIST_FIRST(&sc->data_pool); 1493 1494 wh = mtod(m, struct ieee80211_frame *); 1495 1496 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1497 k = ieee80211_crypto_encap(ni, m); 1498 if (k == NULL) { 1499 m_freem(m); 1500 return ENOBUFS; 1501 } 1502 1503 /* packet header may have moved, reset our local pointer */ 1504 wh = mtod(m, struct ieee80211_frame *); 1505 } 1506 1507 hdrlen = ieee80211_anyhdrsize(wh); 1508 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1509 1510 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1511 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1512 rate = tp->mcastrate; 1513 } else if (m->m_flags & M_EAPOL) { 1514 rate = tp->mgmtrate; 1515 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1516 rate = tp->ucastrate; 1517 } else { 1518 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1519 rate = ni->ni_txrate; 1520 } 1521 rate &= IEEE80211_RATE_VAL; 1522 1523 qid = M_WME_GETAC(m); 1524 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1525 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 1526 tid = qos & IEEE80211_QOS_TID; 1527 } else { 1528 qos = 0; 1529 tid = 0; 1530 } 1531 ring = &sc->txq[qid]; 1532 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, rate); 1533 1534 /* get MCS code from rate index */ 1535 mcs = rt2860_rates[ridx].mcs; 1536 1537 /* setup TX Wireless Information */ 1538 txwi = data->txwi; 1539 txwi->flags = 0; 1540 /* let HW generate seq numbers for non-QoS frames */ 1541 txwi->xflags = qos ? 0 : RT2860_TX_NSEQ; 1542 if (type == IEEE80211_FC0_TYPE_DATA) 1543 txwi->wcid = IEEE80211_AID(ni->ni_associd); 1544 else 1545 txwi->wcid = 0xff; 1546 txwi->len = htole16(m->m_pkthdr.len); 1547 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1548 txwi->phy = htole16(RT2860_PHY_CCK); 1549 if (ridx != RT2860_RIDX_CCK1 && 1550 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1551 mcs |= RT2860_PHY_SHPRE; 1552 } else 1553 txwi->phy = htole16(RT2860_PHY_OFDM); 1554 txwi->phy |= htole16(mcs); 1555 1556 /* 1557 * We store the MCS code into the driver-private PacketID field. 1558 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1559 * that we know at which initial rate the frame was transmitted. 1560 * We add 1 to the MCS code because setting the PacketID field to 1561 * 0 means that we don't want feedback in TX_STAT_FIFO. 1562 */ 1563 pid = (mcs + 1) & 0xf; 1564 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1565 1566 /* check if RTS/CTS or CTS-to-self protection is required */ 1567 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1568 (m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold || 1569 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1570 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1571 txwi->txop = RT2860_TX_TXOP_HT; 1572 else 1573 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1574 1575 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1576 (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 1577 IEEE80211_QOS_ACKPOLICY_NOACK)) { 1578 txwi->xflags |= RT2860_TX_ACK; 1579 1580 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1581 dur = rt2860_rates[ridx].sp_ack_dur; 1582 else 1583 dur = rt2860_rates[ridx].lp_ack_dur; 1584 *(uint16_t *)wh->i_dur = htole16(dur); 1585 } 1586 /* ask MAC to insert timestamp into probe responses */ 1587 if ((wh->i_fc[0] & 1588 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1589 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1590 /* NOTE: beacons do not pass through tx_data() */ 1591 txwi->flags |= RT2860_TX_TS; 1592 1593 if (ieee80211_radiotap_active_vap(vap)) { 1594 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1595 1596 tap->wt_flags = 0; 1597 tap->wt_rate = rate; 1598 if (mcs & RT2860_PHY_SHPRE) 1599 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1600 1601 ieee80211_radiotap_tx(vap, m); 1602 } 1603 1604 pad = (hdrlen + 3) & ~3; 1605 1606 /* copy and trim 802.11 header */ 1607 memcpy(txwi + 1, wh, hdrlen); 1608 m_adj(m, hdrlen); 1609 1610 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1611 &nsegs, 0); 1612 if (__predict_false(error != 0 && error != EFBIG)) { 1613 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1614 error); 1615 m_freem(m); 1616 return error; 1617 } 1618 if (__predict_true(error == 0)) { 1619 /* determine how many TXDs are required */ 1620 ntxds = 1 + (nsegs / 2); 1621 1622 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1623 /* not enough free TXDs, force mbuf defrag */ 1624 bus_dmamap_unload(sc->txwi_dmat, data->map); 1625 error = EFBIG; 1626 } 1627 } 1628 if (__predict_false(error != 0)) { 1629 m1 = m_defrag(m, M_NOWAIT); 1630 if (m1 == NULL) { 1631 device_printf(sc->sc_dev, 1632 "could not defragment mbuf\n"); 1633 m_freem(m); 1634 return ENOBUFS; 1635 } 1636 m = m1; 1637 1638 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1639 segs, &nsegs, 0); 1640 if (__predict_false(error != 0)) { 1641 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1642 error); 1643 m_freem(m); 1644 return error; 1645 } 1646 1647 /* determine how many TXDs are now required */ 1648 ntxds = 1 + (nsegs / 2); 1649 1650 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1651 /* this is a hopeless case, drop the mbuf! */ 1652 bus_dmamap_unload(sc->txwi_dmat, data->map); 1653 m_freem(m); 1654 return ENOBUFS; 1655 } 1656 } 1657 1658 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1659 1660 /* first segment is TXWI + 802.11 header */ 1661 txd = &ring->txd[ring->cur]; 1662 txd->sdp0 = htole32(data->paddr); 1663 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1664 txd->flags = qsel; 1665 1666 /* setup payload segments */ 1667 seg = &segs[0]; 1668 for (i = nsegs; i >= 2; i -= 2) { 1669 txd->sdp1 = htole32(seg->ds_addr); 1670 txd->sdl1 = htole16(seg->ds_len); 1671 seg++; 1672 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1673 /* grab a new Tx descriptor */ 1674 txd = &ring->txd[ring->cur]; 1675 txd->sdp0 = htole32(seg->ds_addr); 1676 txd->sdl0 = htole16(seg->ds_len); 1677 txd->flags = qsel; 1678 seg++; 1679 } 1680 /* finalize last segment */ 1681 if (i > 0) { 1682 txd->sdp1 = htole32(seg->ds_addr); 1683 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1684 } else { 1685 txd->sdl0 |= htole16(RT2860_TX_LS0); 1686 txd->sdl1 = 0; 1687 } 1688 1689 /* remove from the free pool and link it into the SW Tx slot */ 1690 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1691 data->m = m; 1692 data->ni = ni; 1693 ring->data[ring->cur] = data; 1694 1695 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1696 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1697 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1698 1699 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1700 qid, txwi->wcid, nsegs, ridx)); 1701 1702 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1703 ring->queued += ntxds; 1704 if (ring->queued >= RT2860_TX_RING_COUNT) 1705 sc->qfullmsk |= 1 << qid; 1706 1707 /* kick Tx */ 1708 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1709 1710 return 0; 1711} 1712 1713static int 1714rt2860_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1715 const struct ieee80211_bpf_params *params) 1716{ 1717 struct ieee80211com *ic = ni->ni_ic; 1718 struct ifnet *ifp = ic->ic_ifp; 1719 struct rt2860_softc *sc = ifp->if_softc; 1720 int error; 1721 1722 RAL_LOCK(sc); 1723 1724 /* prevent management frames from being sent if we're not ready */ 1725 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1726 RAL_UNLOCK(sc); 1727 m_freem(m); 1728 ieee80211_free_node(ni); 1729 return ENETDOWN; 1730 } 1731 if (params == NULL) { 1732 /* 1733 * Legacy path; interpret frame contents to decide 1734 * precisely how to send the frame. 1735 */ 1736 error = rt2860_tx(sc, m, ni); 1737 } else { 1738 /* 1739 * Caller supplied explicit parameters to use in 1740 * sending the frame. 1741 */ 1742 error = rt2860_tx_raw(sc, m, ni, params); 1743 } 1744 if (error != 0) { 1745 /* NB: m is reclaimed on tx failure */ 1746 ieee80211_free_node(ni); 1747 ifp->if_oerrors++; 1748 } 1749 sc->sc_tx_timer = 5; 1750 RAL_UNLOCK(sc); 1751 return error; 1752} 1753 1754static int 1755rt2860_tx_raw(struct rt2860_softc *sc, struct mbuf *m, 1756 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 1757{ 1758 struct ifnet *ifp = sc->sc_ifp; 1759 struct ieee80211com *ic = ifp->if_l2com; 1760 struct ieee80211vap *vap = ni->ni_vap; 1761 struct rt2860_tx_ring *ring; 1762 struct rt2860_tx_data *data; 1763 struct rt2860_txd *txd; 1764 struct rt2860_txwi *txwi; 1765 struct ieee80211_frame *wh; 1766 struct mbuf *m1; 1767 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1768 bus_dma_segment_t *seg; 1769 u_int hdrlen; 1770 uint16_t dur; 1771 uint8_t type, qsel, mcs, pid, tid, qid; 1772 int i, nsegs, ntxds, pad, rate, ridx, error; 1773 1774 /* the data pool contains at least one element, pick the first */ 1775 data = SLIST_FIRST(&sc->data_pool); 1776 1777 wh = mtod(m, struct ieee80211_frame *); 1778 hdrlen = ieee80211_hdrsize(wh); 1779 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1780 1781 /* Choose a TX rate index. */ 1782 rate = params->ibp_rate0; 1783 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 1784 rate & IEEE80211_RATE_VAL); 1785 if (ridx == (uint8_t)-1) { 1786 /* XXX fall back to mcast/mgmt rate? */ 1787 m_freem(m); 1788 return EINVAL; 1789 } 1790 1791 qid = params->ibp_pri & 3; 1792 tid = 0; 1793 ring = &sc->txq[qid]; 1794 1795 /* get MCS code from rate index */ 1796 mcs = rt2860_rates[ridx].mcs; 1797 1798 /* setup TX Wireless Information */ 1799 txwi = data->txwi; 1800 txwi->flags = 0; 1801 /* let HW generate seq numbers for non-QoS frames */ 1802 txwi->xflags = params->ibp_pri & 3 ? 0 : RT2860_TX_NSEQ; 1803 txwi->wcid = 0xff; 1804 txwi->len = htole16(m->m_pkthdr.len); 1805 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1806 txwi->phy = htole16(RT2860_PHY_CCK); 1807 if (ridx != RT2860_RIDX_CCK1 && 1808 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1809 mcs |= RT2860_PHY_SHPRE; 1810 } else 1811 txwi->phy = htole16(RT2860_PHY_OFDM); 1812 txwi->phy |= htole16(mcs); 1813 1814 /* 1815 * We store the MCS code into the driver-private PacketID field. 1816 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1817 * that we know at which initial rate the frame was transmitted. 1818 * We add 1 to the MCS code because setting the PacketID field to 1819 * 0 means that we don't want feedback in TX_STAT_FIFO. 1820 */ 1821 pid = (mcs + 1) & 0xf; 1822 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1823 1824 /* check if RTS/CTS or CTS-to-self protection is required */ 1825 if (params->ibp_flags & IEEE80211_BPF_RTS || 1826 params->ibp_flags & IEEE80211_BPF_CTS) 1827 txwi->txop = RT2860_TX_TXOP_HT; 1828 else 1829 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1830 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 1831 txwi->xflags |= RT2860_TX_ACK; 1832 1833 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1834 dur = rt2860_rates[ridx].sp_ack_dur; 1835 else 1836 dur = rt2860_rates[ridx].lp_ack_dur; 1837 *(uint16_t *)wh->i_dur = htole16(dur); 1838 } 1839 /* ask MAC to insert timestamp into probe responses */ 1840 if ((wh->i_fc[0] & 1841 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1842 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1843 /* NOTE: beacons do not pass through tx_data() */ 1844 txwi->flags |= RT2860_TX_TS; 1845 1846 if (ieee80211_radiotap_active_vap(vap)) { 1847 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1848 1849 tap->wt_flags = 0; 1850 tap->wt_rate = rate; 1851 if (mcs & RT2860_PHY_SHPRE) 1852 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1853 1854 ieee80211_radiotap_tx(vap, m); 1855 } 1856 1857 pad = (hdrlen + 3) & ~3; 1858 1859 /* copy and trim 802.11 header */ 1860 memcpy(txwi + 1, wh, hdrlen); 1861 m_adj(m, hdrlen); 1862 1863 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1864 &nsegs, 0); 1865 if (__predict_false(error != 0 && error != EFBIG)) { 1866 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1867 error); 1868 m_freem(m); 1869 return error; 1870 } 1871 if (__predict_true(error == 0)) { 1872 /* determine how many TXDs are required */ 1873 ntxds = 1 + (nsegs / 2); 1874 1875 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1876 /* not enough free TXDs, force mbuf defrag */ 1877 bus_dmamap_unload(sc->txwi_dmat, data->map); 1878 error = EFBIG; 1879 } 1880 } 1881 if (__predict_false(error != 0)) { 1882 m1 = m_defrag(m, M_NOWAIT); 1883 if (m1 == NULL) { 1884 device_printf(sc->sc_dev, 1885 "could not defragment mbuf\n"); 1886 m_freem(m); 1887 return ENOBUFS; 1888 } 1889 m = m1; 1890 1891 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1892 segs, &nsegs, 0); 1893 if (__predict_false(error != 0)) { 1894 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1895 error); 1896 m_freem(m); 1897 return error; 1898 } 1899 1900 /* determine how many TXDs are now required */ 1901 ntxds = 1 + (nsegs / 2); 1902 1903 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1904 /* this is a hopeless case, drop the mbuf! */ 1905 bus_dmamap_unload(sc->txwi_dmat, data->map); 1906 m_freem(m); 1907 return ENOBUFS; 1908 } 1909 } 1910 1911 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1912 1913 /* first segment is TXWI + 802.11 header */ 1914 txd = &ring->txd[ring->cur]; 1915 txd->sdp0 = htole32(data->paddr); 1916 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1917 txd->flags = qsel; 1918 1919 /* setup payload segments */ 1920 seg = &segs[0]; 1921 for (i = nsegs; i >= 2; i -= 2) { 1922 txd->sdp1 = htole32(seg->ds_addr); 1923 txd->sdl1 = htole16(seg->ds_len); 1924 seg++; 1925 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1926 /* grab a new Tx descriptor */ 1927 txd = &ring->txd[ring->cur]; 1928 txd->sdp0 = htole32(seg->ds_addr); 1929 txd->sdl0 = htole16(seg->ds_len); 1930 txd->flags = qsel; 1931 seg++; 1932 } 1933 /* finalize last segment */ 1934 if (i > 0) { 1935 txd->sdp1 = htole32(seg->ds_addr); 1936 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1937 } else { 1938 txd->sdl0 |= htole16(RT2860_TX_LS0); 1939 txd->sdl1 = 0; 1940 } 1941 1942 /* remove from the free pool and link it into the SW Tx slot */ 1943 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1944 data->m = m; 1945 data->ni = ni; 1946 ring->data[ring->cur] = data; 1947 1948 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1949 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1950 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1951 1952 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1953 qid, txwi->wcid, nsegs, ridx)); 1954 1955 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1956 ring->queued += ntxds; 1957 if (ring->queued >= RT2860_TX_RING_COUNT) 1958 sc->qfullmsk |= 1 << qid; 1959 1960 /* kick Tx */ 1961 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1962 1963 return 0; 1964} 1965 1966static void 1967rt2860_start(struct ifnet *ifp) 1968{ 1969 struct rt2860_softc *sc = ifp->if_softc; 1970 1971 RAL_LOCK(sc); 1972 rt2860_start_locked(ifp); 1973 RAL_UNLOCK(sc); 1974} 1975 1976static void 1977rt2860_start_locked(struct ifnet *ifp) 1978{ 1979 struct rt2860_softc *sc = ifp->if_softc; 1980 struct ieee80211_node *ni; 1981 struct mbuf *m; 1982 1983 RAL_LOCK_ASSERT(sc); 1984 1985 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1986 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) 1987 return; 1988 1989 for (;;) { 1990 if (SLIST_EMPTY(&sc->data_pool) || sc->qfullmsk != 0) { 1991 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1992 break; 1993 } 1994 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1995 if (m == NULL) 1996 break; 1997 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1998 if (rt2860_tx(sc, m, ni) != 0) { 1999 ieee80211_free_node(ni); 2000 ifp->if_oerrors++; 2001 continue; 2002 } 2003 sc->sc_tx_timer = 5; 2004 } 2005} 2006 2007static void 2008rt2860_watchdog(void *arg) 2009{ 2010 struct rt2860_softc *sc = arg; 2011 struct ifnet *ifp = sc->sc_ifp; 2012 2013 RAL_LOCK_ASSERT(sc); 2014 2015 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running")); 2016 2017 if (sc->sc_invalid) /* card ejected */ 2018 return; 2019 2020 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 2021 if_printf(ifp, "device timeout\n"); 2022 rt2860_stop_locked(sc); 2023 rt2860_init_locked(sc); 2024 ifp->if_oerrors++; 2025 return; 2026 } 2027 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 2028} 2029 2030static int 2031rt2860_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2032{ 2033 struct rt2860_softc *sc = ifp->if_softc; 2034 struct ieee80211com *ic = ifp->if_l2com; 2035 struct ifreq *ifr = (struct ifreq *)data; 2036 int error = 0, startall = 0; 2037 2038 switch (cmd) { 2039 case SIOCSIFFLAGS: 2040 RAL_LOCK(sc); 2041 if (ifp->if_flags & IFF_UP) { 2042 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2043 rt2860_init_locked(sc); 2044 startall = 1; 2045 } else 2046 rt2860_update_promisc(ifp); 2047 } else { 2048 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2049 rt2860_stop_locked(sc); 2050 } 2051 RAL_UNLOCK(sc); 2052 if (startall) 2053 ieee80211_start_all(ic); 2054 break; 2055 case SIOCGIFMEDIA: 2056 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 2057 break; 2058 case SIOCSIFADDR: 2059 error = ether_ioctl(ifp, cmd, data); 2060 break; 2061 default: 2062 error = EINVAL; 2063 break; 2064 } 2065 return error; 2066} 2067 2068/* 2069 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 2070 * We access the BBP through the 8051 microcontroller unit which means that 2071 * the microcode must be loaded first. 2072 */ 2073void 2074rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2075{ 2076 int ntries; 2077 2078 for (ntries = 0; ntries < 100; ntries++) { 2079 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2080 break; 2081 DELAY(1); 2082 } 2083 if (ntries == 100) { 2084 device_printf(sc->sc_dev, 2085 "could not write to BBP through MCU\n"); 2086 return; 2087 } 2088 2089 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2090 RT2860_BBP_CSR_KICK | reg << 8 | val); 2091 RAL_BARRIER_WRITE(sc); 2092 2093 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2094 DELAY(1000); 2095} 2096 2097uint8_t 2098rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 2099{ 2100 uint32_t val; 2101 int ntries; 2102 2103 for (ntries = 0; ntries < 100; ntries++) { 2104 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2105 break; 2106 DELAY(1); 2107 } 2108 if (ntries == 100) { 2109 device_printf(sc->sc_dev, 2110 "could not read from BBP through MCU\n"); 2111 return 0; 2112 } 2113 2114 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2115 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 2116 RAL_BARRIER_WRITE(sc); 2117 2118 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2119 DELAY(1000); 2120 2121 for (ntries = 0; ntries < 100; ntries++) { 2122 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 2123 if (!(val & RT2860_BBP_CSR_KICK)) 2124 return val & 0xff; 2125 DELAY(1); 2126 } 2127 device_printf(sc->sc_dev, "could not read from BBP through MCU\n"); 2128 2129 return 0; 2130} 2131 2132/* 2133 * Write to one of the 4 programmable 24-bit RF registers. 2134 */ 2135static void 2136rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 2137{ 2138 uint32_t tmp; 2139 int ntries; 2140 2141 for (ntries = 0; ntries < 100; ntries++) { 2142 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 2143 break; 2144 DELAY(1); 2145 } 2146 if (ntries == 100) { 2147 device_printf(sc->sc_dev, "could not write to RF\n"); 2148 return; 2149 } 2150 2151 /* RF registers are 24-bit on the RT2860 */ 2152 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 2153 (val & 0x3fffff) << 2 | (reg & 3); 2154 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 2155} 2156 2157static uint8_t 2158rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 2159{ 2160 uint32_t tmp; 2161 int ntries; 2162 2163 for (ntries = 0; ntries < 100; ntries++) { 2164 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2165 break; 2166 DELAY(1); 2167 } 2168 if (ntries == 100) { 2169 device_printf(sc->sc_dev, "could not read RF register\n"); 2170 return 0xff; 2171 } 2172 tmp = RT3070_RF_KICK | reg << 8; 2173 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2174 2175 for (ntries = 0; ntries < 100; ntries++) { 2176 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 2177 if (!(tmp & RT3070_RF_KICK)) 2178 break; 2179 DELAY(1); 2180 } 2181 if (ntries == 100) { 2182 device_printf(sc->sc_dev, "could not read RF register\n"); 2183 return 0xff; 2184 } 2185 return tmp & 0xff; 2186} 2187 2188void 2189rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2190{ 2191 uint32_t tmp; 2192 int ntries; 2193 2194 for (ntries = 0; ntries < 10; ntries++) { 2195 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2196 break; 2197 DELAY(10); 2198 } 2199 if (ntries == 10) { 2200 device_printf(sc->sc_dev, "could not write to RF\n"); 2201 return; 2202 } 2203 2204 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2205 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2206} 2207 2208/* 2209 * Send a command to the 8051 microcontroller unit. 2210 */ 2211int 2212rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2213{ 2214 int slot, ntries; 2215 uint32_t tmp; 2216 uint8_t cid; 2217 2218 for (ntries = 0; ntries < 100; ntries++) { 2219 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2220 break; 2221 DELAY(2); 2222 } 2223 if (ntries == 100) 2224 return EIO; 2225 2226 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2227 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2228 RAL_BARRIER_WRITE(sc); 2229 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2230 2231 if (!wait) 2232 return 0; 2233 /* wait for the command to complete */ 2234 for (ntries = 0; ntries < 200; ntries++) { 2235 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2236 /* find the command slot */ 2237 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2238 if ((tmp & 0xff) == cid) 2239 break; 2240 if (slot < 4) 2241 break; 2242 DELAY(100); 2243 } 2244 if (ntries == 200) { 2245 /* clear command and status */ 2246 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2247 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2248 return ETIMEDOUT; 2249 } 2250 /* get command status (1 means success) */ 2251 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2252 tmp = (tmp >> (slot * 8)) & 0xff; 2253 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2254 cmd, slot, tmp)); 2255 /* clear command and status */ 2256 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2257 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2258 return (tmp == 1) ? 0 : EIO; 2259} 2260 2261static void 2262rt2860_enable_mrr(struct rt2860_softc *sc) 2263{ 2264#define CCK(mcs) (mcs) 2265#define OFDM(mcs) (1 << 3 | (mcs)) 2266 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2267 OFDM(6) << 28 | /* 54->48 */ 2268 OFDM(5) << 24 | /* 48->36 */ 2269 OFDM(4) << 20 | /* 36->24 */ 2270 OFDM(3) << 16 | /* 24->18 */ 2271 OFDM(2) << 12 | /* 18->12 */ 2272 OFDM(1) << 8 | /* 12-> 9 */ 2273 OFDM(0) << 4 | /* 9-> 6 */ 2274 OFDM(0)); /* 6-> 6 */ 2275 2276 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2277 CCK(2) << 12 | /* 11->5.5 */ 2278 CCK(1) << 8 | /* 5.5-> 2 */ 2279 CCK(0) << 4 | /* 2-> 1 */ 2280 CCK(0)); /* 1-> 1 */ 2281#undef OFDM 2282#undef CCK 2283} 2284 2285static void 2286rt2860_set_txpreamble(struct rt2860_softc *sc) 2287{ 2288 struct ifnet *ifp = sc->sc_ifp; 2289 struct ieee80211com *ic = ifp->if_l2com; 2290 uint32_t tmp; 2291 2292 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2293 tmp &= ~RT2860_CCK_SHORT_EN; 2294 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2295 tmp |= RT2860_CCK_SHORT_EN; 2296 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2297} 2298 2299void 2300rt2860_set_basicrates(struct rt2860_softc *sc, 2301 const struct ieee80211_rateset *rs) 2302{ 2303#define RV(r) ((r) & IEEE80211_RATE_VAL) 2304 struct ifnet *ifp = sc->sc_ifp; 2305 struct ieee80211com *ic = ifp->if_l2com; 2306 uint32_t mask = 0; 2307 uint8_t rate; 2308 int i; 2309 2310 for (i = 0; i < rs->rs_nrates; i++) { 2311 rate = rs->rs_rates[i]; 2312 2313 if (!(rate & IEEE80211_RATE_BASIC)) 2314 continue; 2315 2316 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt, RV(rate)); 2317 } 2318 2319 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, mask); 2320#undef RV 2321} 2322 2323static void 2324rt2860_scan_start(struct ieee80211com *ic) 2325{ 2326 struct ifnet *ifp = ic->ic_ifp; 2327 struct rt2860_softc *sc = ifp->if_softc; 2328 uint32_t tmp; 2329 2330 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 2331 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 2332 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 2333 RT2860_TBTT_TIMER_EN)); 2334 rt2860_set_gp_timer(sc, 0); 2335} 2336 2337static void 2338rt2860_scan_end(struct ieee80211com *ic) 2339{ 2340 struct ifnet *ifp = ic->ic_ifp; 2341 struct rt2860_softc *sc = ifp->if_softc; 2342 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2343 2344 if (vap->iv_state == IEEE80211_S_RUN) { 2345 rt2860_enable_tsf_sync(sc); 2346 rt2860_set_gp_timer(sc, 500); 2347 } 2348} 2349 2350static void 2351rt2860_set_channel(struct ieee80211com *ic) 2352{ 2353 struct ifnet *ifp = ic->ic_ifp; 2354 struct rt2860_softc *sc = ifp->if_softc; 2355 2356 RAL_LOCK(sc); 2357 rt2860_switch_chan(sc, ic->ic_curchan); 2358 RAL_UNLOCK(sc); 2359} 2360 2361static void 2362rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2363{ 2364 uint32_t tmp; 2365 uint8_t agc; 2366 2367 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2368 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2369 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2370 rt2860_mcu_bbp_write(sc, 86, 0x00); 2371 2372 if (group == 0) { 2373 if (sc->ext_2ghz_lna) { 2374 rt2860_mcu_bbp_write(sc, 82, 0x62); 2375 rt2860_mcu_bbp_write(sc, 75, 0x46); 2376 } else { 2377 rt2860_mcu_bbp_write(sc, 82, 0x84); 2378 rt2860_mcu_bbp_write(sc, 75, 0x50); 2379 } 2380 } else { 2381 if (sc->ext_5ghz_lna) { 2382 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2383 rt2860_mcu_bbp_write(sc, 75, 0x46); 2384 } else { 2385 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2386 rt2860_mcu_bbp_write(sc, 75, 0x50); 2387 } 2388 } 2389 2390 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2391 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2392 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2393 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2394 2395 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2396 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2397 if (sc->nrxchains > 1) 2398 tmp |= RT2860_LNA_PE1_EN; 2399 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2400 tmp |= RT3593_LNA_PE2_EN; 2401 if (group == 0) { /* 2GHz */ 2402 tmp |= RT2860_PA_PE_G0_EN; 2403 if (sc->ntxchains > 1) 2404 tmp |= RT2860_PA_PE_G1_EN; 2405 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2406 tmp |= RT3593_PA_PE_G2_EN; 2407 } else { /* 5GHz */ 2408 tmp |= RT2860_PA_PE_A0_EN; 2409 if (sc->ntxchains > 1) 2410 tmp |= RT2860_PA_PE_A1_EN; 2411 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2412 tmp |= RT3593_PA_PE_A2_EN; 2413 } 2414 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2415 2416 if (sc->mac_ver == 0x3593) { 2417 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2418 if (sc->sc_flags & RT2860_PCIE) { 2419 tmp &= ~0x01010000; 2420 if (group == 0) 2421 tmp |= 0x00010000; 2422 } else { 2423 tmp &= ~0x00008080; 2424 if (group == 0) 2425 tmp |= 0x00000080; 2426 } 2427 tmp = (tmp & ~0x00001000) | 0x00000010; 2428 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2429 } 2430 2431 /* set initial AGC value */ 2432 if (group == 0) { /* 2GHz band */ 2433 if (sc->mac_ver >= 0x3071) 2434 agc = 0x1c + sc->lna[0] * 2; 2435 else 2436 agc = 0x2e + sc->lna[0]; 2437 } else { /* 5GHz band */ 2438 agc = 0x32 + (sc->lna[group] * 5) / 3; 2439 } 2440 rt2860_mcu_bbp_write(sc, 66, agc); 2441 2442 DELAY(1000); 2443} 2444 2445static void 2446rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2447{ 2448 const struct rfprog *rfprog = rt2860_rf2850; 2449 uint32_t r2, r3, r4; 2450 int8_t txpow1, txpow2; 2451 u_int i; 2452 2453 /* find the settings for this channel (we know it exists) */ 2454 for (i = 0; rfprog[i].chan != chan; i++); 2455 2456 r2 = rfprog[i].r2; 2457 if (sc->ntxchains == 1) 2458 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2459 if (sc->nrxchains == 1) 2460 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2461 else if (sc->nrxchains == 2) 2462 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2463 2464 /* use Tx power values from EEPROM */ 2465 txpow1 = sc->txpow1[i]; 2466 txpow2 = sc->txpow2[i]; 2467 if (chan > 14) { 2468 if (txpow1 >= 0) 2469 txpow1 = txpow1 << 1 | 1; 2470 else 2471 txpow1 = (7 + txpow1) << 1; 2472 if (txpow2 >= 0) 2473 txpow2 = txpow2 << 1 | 1; 2474 else 2475 txpow2 = (7 + txpow2) << 1; 2476 } 2477 r3 = rfprog[i].r3 | txpow1 << 7; 2478 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2479 2480 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2481 rt2860_rf_write(sc, RT2860_RF2, r2); 2482 rt2860_rf_write(sc, RT2860_RF3, r3); 2483 rt2860_rf_write(sc, RT2860_RF4, r4); 2484 2485 DELAY(200); 2486 2487 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2488 rt2860_rf_write(sc, RT2860_RF2, r2); 2489 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2490 rt2860_rf_write(sc, RT2860_RF4, r4); 2491 2492 DELAY(200); 2493 2494 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2495 rt2860_rf_write(sc, RT2860_RF2, r2); 2496 rt2860_rf_write(sc, RT2860_RF3, r3); 2497 rt2860_rf_write(sc, RT2860_RF4, r4); 2498} 2499 2500static void 2501rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2502{ 2503 int8_t txpow1, txpow2; 2504 uint8_t rf; 2505 int i; 2506 2507 /* RT3090 is 2GHz only */ 2508 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2509 2510 /* find the settings for this channel (we know it exists) */ 2511 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2512 2513 /* use Tx power values from EEPROM */ 2514 txpow1 = sc->txpow1[i]; 2515 txpow2 = sc->txpow2[i]; 2516 2517 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2518 rf = rt3090_rf_read(sc, 3); 2519 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2520 rt3090_rf_write(sc, 3, rf); 2521 rf = rt3090_rf_read(sc, 6); 2522 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2523 rt3090_rf_write(sc, 6, rf); 2524 2525 /* set Tx0 power */ 2526 rf = rt3090_rf_read(sc, 12); 2527 rf = (rf & ~0x1f) | txpow1; 2528 rt3090_rf_write(sc, 12, rf); 2529 2530 /* set Tx1 power */ 2531 rf = rt3090_rf_read(sc, 13); 2532 rf = (rf & ~0x1f) | txpow2; 2533 rt3090_rf_write(sc, 13, rf); 2534 2535 rf = rt3090_rf_read(sc, 1); 2536 rf &= ~0xfc; 2537 if (sc->ntxchains == 1) 2538 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2539 else if (sc->ntxchains == 2) 2540 rf |= RT3070_TX2_PD; 2541 if (sc->nrxchains == 1) 2542 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2543 else if (sc->nrxchains == 2) 2544 rf |= RT3070_RX2_PD; 2545 rt3090_rf_write(sc, 1, rf); 2546 2547 /* set RF offset */ 2548 rf = rt3090_rf_read(sc, 23); 2549 rf = (rf & ~0x7f) | sc->freq; 2550 rt3090_rf_write(sc, 23, rf); 2551 2552 /* program RF filter */ 2553 rf = rt3090_rf_read(sc, 24); /* Tx */ 2554 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2555 rt3090_rf_write(sc, 24, rf); 2556 rf = rt3090_rf_read(sc, 31); /* Rx */ 2557 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2558 rt3090_rf_write(sc, 31, rf); 2559 2560 /* enable RF tuning */ 2561 rf = rt3090_rf_read(sc, 7); 2562 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2563} 2564 2565static int 2566rt3090_rf_init(struct rt2860_softc *sc) 2567{ 2568#define N(a) (sizeof (a) / sizeof ((a)[0])) 2569 uint32_t tmp; 2570 uint8_t rf, bbp; 2571 int i; 2572 2573 rf = rt3090_rf_read(sc, 30); 2574 /* toggle RF R30 bit 7 */ 2575 rt3090_rf_write(sc, 30, rf | 0x80); 2576 DELAY(1000); 2577 rt3090_rf_write(sc, 30, rf & ~0x80); 2578 2579 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2580 tmp &= ~0x1f000000; 2581 if (sc->patch_dac && sc->mac_rev < 0x0211) 2582 tmp |= 0x0d000000; /* 1.35V */ 2583 else 2584 tmp |= 0x01000000; /* 1.2V */ 2585 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2586 2587 /* patch LNA_PE_G1 */ 2588 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2589 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2590 2591 /* initialize RF registers to default value */ 2592 for (i = 0; i < N(rt3090_def_rf); i++) { 2593 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2594 rt3090_def_rf[i].val); 2595 } 2596 2597 /* select 20MHz bandwidth */ 2598 rt3090_rf_write(sc, 31, 0x14); 2599 2600 rf = rt3090_rf_read(sc, 6); 2601 rt3090_rf_write(sc, 6, rf | 0x40); 2602 2603 if (sc->mac_ver != 0x3593) { 2604 /* calibrate filter for 20MHz bandwidth */ 2605 sc->rf24_20mhz = 0x1f; /* default value */ 2606 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2607 2608 /* select 40MHz bandwidth */ 2609 bbp = rt2860_mcu_bbp_read(sc, 4); 2610 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2611 rf = rt3090_rf_read(sc, 31); 2612 rt3090_rf_write(sc, 31, rf | 0x20); 2613 2614 /* calibrate filter for 40MHz bandwidth */ 2615 sc->rf24_40mhz = 0x2f; /* default value */ 2616 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2617 2618 /* go back to 20MHz bandwidth */ 2619 bbp = rt2860_mcu_bbp_read(sc, 4); 2620 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2621 } 2622 if (sc->mac_rev < 0x0211) 2623 rt3090_rf_write(sc, 27, 0x03); 2624 2625 tmp = RAL_READ(sc, RT3070_OPT_14); 2626 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2627 2628 if (sc->rf_rev == RT3070_RF_3020) 2629 rt3090_set_rx_antenna(sc, 0); 2630 2631 bbp = rt2860_mcu_bbp_read(sc, 138); 2632 if (sc->mac_ver == 0x3593) { 2633 if (sc->ntxchains == 1) 2634 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2635 else if (sc->ntxchains == 2) 2636 bbp |= 0x40; /* turn off DAC2 */ 2637 if (sc->nrxchains == 1) 2638 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2639 else if (sc->nrxchains == 2) 2640 bbp &= ~0x04; /* turn off ADC2 */ 2641 } else { 2642 if (sc->ntxchains == 1) 2643 bbp |= 0x20; /* turn off DAC1 */ 2644 if (sc->nrxchains == 1) 2645 bbp &= ~0x02; /* turn off ADC1 */ 2646 } 2647 rt2860_mcu_bbp_write(sc, 138, bbp); 2648 2649 rf = rt3090_rf_read(sc, 1); 2650 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2651 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2652 rt3090_rf_write(sc, 1, rf); 2653 2654 rf = rt3090_rf_read(sc, 15); 2655 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2656 2657 rf = rt3090_rf_read(sc, 17); 2658 rf &= ~RT3070_TX_LO1; 2659 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2660 rf |= 0x20; /* fix for long range Rx issue */ 2661 if (sc->txmixgain_2ghz >= 2) 2662 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2663 rt3090_rf_write(sc, 17, rf); 2664 2665 rf = rt3090_rf_read(sc, 20); 2666 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2667 2668 rf = rt3090_rf_read(sc, 21); 2669 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2670 2671 return 0; 2672#undef N 2673} 2674 2675void 2676rt3090_rf_wakeup(struct rt2860_softc *sc) 2677{ 2678 uint32_t tmp; 2679 uint8_t rf; 2680 2681 if (sc->mac_ver == 0x3593) { 2682 /* enable VCO */ 2683 rf = rt3090_rf_read(sc, 1); 2684 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2685 2686 /* initiate VCO calibration */ 2687 rf = rt3090_rf_read(sc, 3); 2688 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2689 2690 /* enable VCO bias current control */ 2691 rf = rt3090_rf_read(sc, 6); 2692 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2693 2694 /* initiate res calibration */ 2695 rf = rt3090_rf_read(sc, 2); 2696 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2697 2698 /* set reference current control to 0.33 mA */ 2699 rf = rt3090_rf_read(sc, 22); 2700 rf &= ~RT3593_CP_IC_MASK; 2701 rf |= 1 << RT3593_CP_IC_SHIFT; 2702 rt3090_rf_write(sc, 22, rf); 2703 2704 /* enable RX CTB */ 2705 rf = rt3090_rf_read(sc, 46); 2706 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2707 2708 rf = rt3090_rf_read(sc, 20); 2709 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2710 rt3090_rf_write(sc, 20, rf); 2711 } else { 2712 /* enable RF block */ 2713 rf = rt3090_rf_read(sc, 1); 2714 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2715 2716 /* enable VCO bias current control */ 2717 rf = rt3090_rf_read(sc, 7); 2718 rt3090_rf_write(sc, 7, rf | 0x30); 2719 2720 rf = rt3090_rf_read(sc, 9); 2721 rt3090_rf_write(sc, 9, rf | 0x0e); 2722 2723 /* enable RX CTB */ 2724 rf = rt3090_rf_read(sc, 21); 2725 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2726 2727 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2728 rf = rt3090_rf_read(sc, 27); 2729 rf &= ~0x77; 2730 if (sc->mac_rev < 0x0211) 2731 rf |= 0x03; 2732 rt3090_rf_write(sc, 27, rf); 2733 } 2734 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2735 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2736 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2737 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2738 } 2739} 2740 2741int 2742rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2743 uint8_t *val) 2744{ 2745 uint8_t rf22, rf24; 2746 uint8_t bbp55_pb, bbp55_sb, delta; 2747 int ntries; 2748 2749 /* program filter */ 2750 rf24 = rt3090_rf_read(sc, 24); 2751 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2752 rt3090_rf_write(sc, 24, rf24); 2753 2754 /* enable baseband loopback mode */ 2755 rf22 = rt3090_rf_read(sc, 22); 2756 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2757 2758 /* set power and frequency of passband test tone */ 2759 rt2860_mcu_bbp_write(sc, 24, 0x00); 2760 for (ntries = 0; ntries < 100; ntries++) { 2761 /* transmit test tone */ 2762 rt2860_mcu_bbp_write(sc, 25, 0x90); 2763 DELAY(1000); 2764 /* read received power */ 2765 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2766 if (bbp55_pb != 0) 2767 break; 2768 } 2769 if (ntries == 100) 2770 return ETIMEDOUT; 2771 2772 /* set power and frequency of stopband test tone */ 2773 rt2860_mcu_bbp_write(sc, 24, 0x06); 2774 for (ntries = 0; ntries < 100; ntries++) { 2775 /* transmit test tone */ 2776 rt2860_mcu_bbp_write(sc, 25, 0x90); 2777 DELAY(1000); 2778 /* read received power */ 2779 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2780 2781 delta = bbp55_pb - bbp55_sb; 2782 if (delta > target) 2783 break; 2784 2785 /* reprogram filter */ 2786 rf24++; 2787 rt3090_rf_write(sc, 24, rf24); 2788 } 2789 if (ntries < 100) { 2790 if (rf24 != init) 2791 rf24--; /* backtrack */ 2792 *val = rf24; 2793 rt3090_rf_write(sc, 24, rf24); 2794 } 2795 2796 /* restore initial state */ 2797 rt2860_mcu_bbp_write(sc, 24, 0x00); 2798 2799 /* disable baseband loopback mode */ 2800 rf22 = rt3090_rf_read(sc, 22); 2801 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 2802 2803 return 0; 2804} 2805 2806static void 2807rt3090_rf_setup(struct rt2860_softc *sc) 2808{ 2809 uint8_t bbp; 2810 int i; 2811 2812 if (sc->mac_rev >= 0x0211) { 2813 /* enable DC filter */ 2814 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2815 2816 /* improve power consumption */ 2817 bbp = rt2860_mcu_bbp_read(sc, 31); 2818 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 2819 } 2820 2821 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2822 if (sc->mac_rev < 0x0211) { 2823 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 2824 sc->patch_dac ? 0x2c : 0x0f); 2825 } else 2826 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2827 2828 /* initialize RF registers from ROM */ 2829 for (i = 0; i < 10; i++) { 2830 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 2831 continue; 2832 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 2833 } 2834} 2835 2836static void 2837rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 2838{ 2839 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 2840 which | (sc->leds & 0x7f), 0); 2841} 2842 2843/* 2844 * Hardware has a general-purpose programmable timer interrupt that can 2845 * periodically raise MAC_INT_4. 2846 */ 2847static void 2848rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 2849{ 2850 uint32_t tmp; 2851 2852 /* disable GP timer before reprogramming it */ 2853 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 2854 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 2855 2856 if (ms == 0) 2857 return; 2858 2859 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 2860 ms *= 16; /* Unit: 64us */ 2861 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 2862 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 2863 2864 /* enable GP timer */ 2865 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 2866 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 2867} 2868 2869static void 2870rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 2871{ 2872 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 2873 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 2874 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 2875 bssid[4] | bssid[5] << 8); 2876} 2877 2878static void 2879rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 2880{ 2881 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 2882 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2883 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 2884 addr[4] | addr[5] << 8 | 0xff << 16); 2885} 2886 2887static void 2888rt2860_updateslot(struct ifnet *ifp) 2889{ 2890 struct rt2860_softc *sc = ifp->if_softc; 2891 struct ieee80211com *ic = ifp->if_l2com; 2892 uint32_t tmp; 2893 2894 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 2895 tmp &= ~0xff; 2896 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2897 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 2898} 2899 2900static void 2901rt2860_updateprot(struct ifnet *ifp) 2902{ 2903 struct rt2860_softc *sc = ifp->if_softc; 2904 struct ieee80211com *ic = ifp->if_l2com; 2905 uint32_t tmp; 2906 2907 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 2908 /* setup protection frame rate (MCS code) */ 2909 tmp |= IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 2910 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 2911 rt2860_rates[RT2860_RIDX_CCK11].mcs; 2912 2913 /* CCK frames don't require protection */ 2914 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 2915 2916 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2917 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 2918 tmp |= RT2860_PROT_CTRL_RTS_CTS; 2919 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 2920 tmp |= RT2860_PROT_CTRL_CTS; 2921 } 2922 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 2923} 2924 2925static void 2926rt2860_update_promisc(struct ifnet *ifp) 2927{ 2928 struct rt2860_softc *sc = ifp->if_softc; 2929 uint32_t tmp; 2930 2931 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG); 2932 tmp &= ~RT2860_DROP_NOT_MYBSS; 2933 if (!(ifp->if_flags & IFF_PROMISC)) 2934 tmp |= RT2860_DROP_NOT_MYBSS; 2935 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 2936} 2937 2938static int 2939rt2860_updateedca(struct ieee80211com *ic) 2940{ 2941 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 2942 const struct wmeParams *wmep; 2943 int aci; 2944 2945 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2946 2947 /* update MAC TX configuration registers */ 2948 for (aci = 0; aci < WME_NUM_AC; aci++) { 2949 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 2950 wmep[aci].wmep_logcwmax << 16 | 2951 wmep[aci].wmep_logcwmin << 12 | 2952 wmep[aci].wmep_aifsn << 8 | 2953 wmep[aci].wmep_txopLimit); 2954 } 2955 2956 /* update SCH/DMA registers too */ 2957 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 2958 wmep[WME_AC_VO].wmep_aifsn << 12 | 2959 wmep[WME_AC_VI].wmep_aifsn << 8 | 2960 wmep[WME_AC_BK].wmep_aifsn << 4 | 2961 wmep[WME_AC_BE].wmep_aifsn); 2962 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 2963 wmep[WME_AC_VO].wmep_logcwmin << 12 | 2964 wmep[WME_AC_VI].wmep_logcwmin << 8 | 2965 wmep[WME_AC_BK].wmep_logcwmin << 4 | 2966 wmep[WME_AC_BE].wmep_logcwmin); 2967 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 2968 wmep[WME_AC_VO].wmep_logcwmax << 12 | 2969 wmep[WME_AC_VI].wmep_logcwmax << 8 | 2970 wmep[WME_AC_BK].wmep_logcwmax << 4 | 2971 wmep[WME_AC_BE].wmep_logcwmax); 2972 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 2973 wmep[WME_AC_BK].wmep_txopLimit << 16 | 2974 wmep[WME_AC_BE].wmep_txopLimit); 2975 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 2976 wmep[WME_AC_VO].wmep_txopLimit << 16 | 2977 wmep[WME_AC_VI].wmep_txopLimit); 2978 2979 return 0; 2980} 2981 2982#ifdef HW_CRYPTO 2983static int 2984rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2985 struct ieee80211_key *k) 2986{ 2987 struct rt2860_softc *sc = ic->ic_softc; 2988 bus_size_t base; 2989 uint32_t attr; 2990 uint8_t mode, wcid, iv[8]; 2991 2992 /* defer setting of WEP keys until interface is brought up */ 2993 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 2994 (IFF_UP | IFF_RUNNING)) 2995 return 0; 2996 2997 /* map net80211 cipher to RT2860 security mode */ 2998 switch (k->k_cipher) { 2999 case IEEE80211_CIPHER_WEP40: 3000 mode = RT2860_MODE_WEP40; 3001 break; 3002 case IEEE80211_CIPHER_WEP104: 3003 mode = RT2860_MODE_WEP104; 3004 break; 3005 case IEEE80211_CIPHER_TKIP: 3006 mode = RT2860_MODE_TKIP; 3007 break; 3008 case IEEE80211_CIPHER_CCMP: 3009 mode = RT2860_MODE_AES_CCMP; 3010 break; 3011 default: 3012 return EINVAL; 3013 } 3014 3015 if (k->k_flags & IEEE80211_KEY_GROUP) { 3016 wcid = 0; /* NB: update WCID0 for group keys */ 3017 base = RT2860_SKEY(0, k->k_id); 3018 } else { 3019 wcid = ((struct rt2860_node *)ni)->wcid; 3020 base = RT2860_PKEY(wcid); 3021 } 3022 3023 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3024 RAL_WRITE_REGION_1(sc, base, k->k_key, 16); 3025#ifndef IEEE80211_STA_ONLY 3026 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3027 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8); 3028 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8); 3029 } else 3030#endif 3031 { 3032 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8); 3033 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8); 3034 } 3035 } else 3036 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len); 3037 3038 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 3039 (k->k_flags & IEEE80211_KEY_TX)) { 3040 /* set initial packet number in IV+EIV */ 3041 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 3042 k->k_cipher == IEEE80211_CIPHER_WEP104) { 3043 uint32_t val = arc4random(); 3044 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 3045 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 3046 val += 0x000100; 3047 iv[0] = val; 3048 iv[1] = val >> 8; 3049 iv[2] = val >> 16; 3050 iv[3] = k->k_id << 6; 3051 iv[4] = iv[5] = iv[6] = iv[7] = 0; 3052 } else { 3053 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3054 iv[0] = k->k_tsc >> 8; 3055 iv[1] = (iv[0] | 0x20) & 0x7f; 3056 iv[2] = k->k_tsc; 3057 } else /* CCMP */ { 3058 iv[0] = k->k_tsc; 3059 iv[1] = k->k_tsc >> 8; 3060 iv[2] = 0; 3061 } 3062 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3063 iv[4] = k->k_tsc >> 16; 3064 iv[5] = k->k_tsc >> 24; 3065 iv[6] = k->k_tsc >> 32; 3066 iv[7] = k->k_tsc >> 40; 3067 } 3068 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 3069 } 3070 3071 if (k->k_flags & IEEE80211_KEY_GROUP) { 3072 /* install group key */ 3073 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3074 attr &= ~(0xf << (k->k_id * 4)); 3075 attr |= mode << (k->k_id * 4); 3076 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3077 } else { 3078 /* install pairwise key */ 3079 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3080 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 3081 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3082 } 3083 return 0; 3084} 3085 3086static void 3087rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3088 struct ieee80211_key *k) 3089{ 3090 struct rt2860_softc *sc = ic->ic_softc; 3091 uint32_t attr; 3092 uint8_t wcid; 3093 3094 if (k->k_flags & IEEE80211_KEY_GROUP) { 3095 /* remove group key */ 3096 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3097 attr &= ~(0xf << (k->k_id * 4)); 3098 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3099 3100 } else { 3101 /* remove pairwise key */ 3102 wcid = ((struct rt2860_node *)ni)->wcid; 3103 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3104 attr &= ~0xf; 3105 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3106 } 3107} 3108#endif 3109 3110static int8_t 3111rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 3112{ 3113 struct ifnet *ifp = sc->sc_ifp; 3114 struct ieee80211com *ic = ifp->if_l2com; 3115 struct ieee80211_channel *c = ic->ic_curchan; 3116 int delta; 3117 3118 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3119 u_int chan = ieee80211_chan2ieee(ic, c); 3120 delta = sc->rssi_5ghz[rxchain]; 3121 3122 /* determine channel group */ 3123 if (chan <= 64) 3124 delta -= sc->lna[1]; 3125 else if (chan <= 128) 3126 delta -= sc->lna[2]; 3127 else 3128 delta -= sc->lna[3]; 3129 } else 3130 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3131 3132 return -12 - delta - rssi; 3133} 3134 3135/* 3136 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 3137 * Used to adjust per-rate Tx power registers. 3138 */ 3139static __inline uint32_t 3140b4inc(uint32_t b32, int8_t delta) 3141{ 3142 int8_t i, b4; 3143 3144 for (i = 0; i < 8; i++) { 3145 b4 = b32 & 0xf; 3146 b4 += delta; 3147 if (b4 < 0) 3148 b4 = 0; 3149 else if (b4 > 0xf) 3150 b4 = 0xf; 3151 b32 = b32 >> 4 | b4 << 28; 3152 } 3153 return b32; 3154} 3155 3156static const char * 3157rt2860_get_rf(uint8_t rev) 3158{ 3159 switch (rev) { 3160 case RT2860_RF_2820: return "RT2820"; 3161 case RT2860_RF_2850: return "RT2850"; 3162 case RT2860_RF_2720: return "RT2720"; 3163 case RT2860_RF_2750: return "RT2750"; 3164 case RT3070_RF_3020: return "RT3020"; 3165 case RT3070_RF_2020: return "RT2020"; 3166 case RT3070_RF_3021: return "RT3021"; 3167 case RT3070_RF_3022: return "RT3022"; 3168 case RT3070_RF_3052: return "RT3052"; 3169 case RT3070_RF_3320: return "RT3320"; 3170 case RT3070_RF_3053: return "RT3053"; 3171 default: return "unknown"; 3172 } 3173} 3174 3175static int 3176rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 3177{ 3178 int8_t delta_2ghz, delta_5ghz; 3179 uint32_t tmp; 3180 uint16_t val; 3181 int ridx, ant, i; 3182 3183 /* check whether the ROM is eFUSE ROM or EEPROM */ 3184 sc->sc_srom_read = rt2860_eeprom_read_2; 3185 if (sc->mac_ver >= 0x3071) { 3186 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 3187 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3188 if (tmp & RT3070_SEL_EFUSE) 3189 sc->sc_srom_read = rt3090_efuse_read_2; 3190 } 3191 3192 /* read EEPROM version */ 3193 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 3194 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 3195 3196 /* read MAC address */ 3197 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 3198 macaddr[0] = val & 0xff; 3199 macaddr[1] = val >> 8; 3200 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 3201 macaddr[2] = val & 0xff; 3202 macaddr[3] = val >> 8; 3203 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 3204 macaddr[4] = val & 0xff; 3205 macaddr[5] = val >> 8; 3206 3207 /* read country code */ 3208 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 3209 DPRINTF(("EEPROM region code=0x%04x\n", val)); 3210 3211 /* read vendor BBP settings */ 3212 for (i = 0; i < 8; i++) { 3213 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 3214 sc->bbp[i].val = val & 0xff; 3215 sc->bbp[i].reg = val >> 8; 3216 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 3217 } 3218 if (sc->mac_ver >= 0x3071) { 3219 /* read vendor RF settings */ 3220 for (i = 0; i < 10; i++) { 3221 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 3222 sc->rf[i].val = val & 0xff; 3223 sc->rf[i].reg = val >> 8; 3224 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3225 sc->rf[i].val)); 3226 } 3227 } 3228 3229 /* read RF frequency offset from EEPROM */ 3230 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3231 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3232 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3233 if ((val >> 8) != 0xff) { 3234 /* read LEDs operating mode */ 3235 sc->leds = val >> 8; 3236 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3237 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3238 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3239 } else { 3240 /* broken EEPROM, use default settings */ 3241 sc->leds = 0x01; 3242 sc->led[0] = 0x5555; 3243 sc->led[1] = 0x2221; 3244 sc->led[2] = 0xa9f8; 3245 } 3246 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3247 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3248 3249 /* read RF information */ 3250 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3251 if (val == 0xffff) { 3252 DPRINTF(("invalid EEPROM antenna info, using default\n")); 3253 if (sc->mac_ver == 0x3593) { 3254 /* default to RF3053 3T3R */ 3255 sc->rf_rev = RT3070_RF_3053; 3256 sc->ntxchains = 3; 3257 sc->nrxchains = 3; 3258 } else if (sc->mac_ver >= 0x3071) { 3259 /* default to RF3020 1T1R */ 3260 sc->rf_rev = RT3070_RF_3020; 3261 sc->ntxchains = 1; 3262 sc->nrxchains = 1; 3263 } else { 3264 /* default to RF2820 1T2R */ 3265 sc->rf_rev = RT2860_RF_2820; 3266 sc->ntxchains = 1; 3267 sc->nrxchains = 2; 3268 } 3269 } else { 3270 sc->rf_rev = (val >> 8) & 0xf; 3271 sc->ntxchains = (val >> 4) & 0xf; 3272 sc->nrxchains = val & 0xf; 3273 } 3274 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3275 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3276 3277 /* check if RF supports automatic Tx access gain control */ 3278 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3279 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3280 /* check if driver should patch the DAC issue */ 3281 if ((val >> 8) != 0xff) 3282 sc->patch_dac = (val >> 15) & 1; 3283 if ((val & 0xff) != 0xff) { 3284 sc->ext_5ghz_lna = (val >> 3) & 1; 3285 sc->ext_2ghz_lna = (val >> 2) & 1; 3286 /* check if RF supports automatic Tx access gain control */ 3287 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */; 3288 /* check if we have a hardware radio switch */ 3289 sc->rfswitch = val & 1; 3290 } 3291 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3292 /* read PCIe power save level */ 3293 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3294 if ((val & 0xff) != 0xff) { 3295 sc->pslevel = val & 0x3; 3296 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3297 if ((val & 0xff80) != 0x9280) 3298 sc->pslevel = MIN(sc->pslevel, 1); 3299 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3300 } 3301 } 3302 3303 /* read power settings for 2GHz channels */ 3304 for (i = 0; i < 14; i += 2) { 3305 val = rt2860_srom_read(sc, 3306 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3307 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3308 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3309 3310 val = rt2860_srom_read(sc, 3311 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3312 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3313 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3314 } 3315 /* fix broken Tx power entries */ 3316 for (i = 0; i < 14; i++) { 3317 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) 3318 sc->txpow1[i] = 5; 3319 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) 3320 sc->txpow2[i] = 5; 3321 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3322 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3323 } 3324 /* read power settings for 5GHz channels */ 3325 for (i = 0; i < 40; i += 2) { 3326 val = rt2860_srom_read(sc, 3327 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3328 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3329 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3330 3331 val = rt2860_srom_read(sc, 3332 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3333 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3334 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3335 } 3336 /* fix broken Tx power entries */ 3337 for (i = 0; i < 40; i++) { 3338 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3339 sc->txpow1[14 + i] = 5; 3340 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3341 sc->txpow2[14 + i] = 5; 3342 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3343 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3344 sc->txpow2[14 + i])); 3345 } 3346 3347 /* read Tx power compensation for each Tx rate */ 3348 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3349 delta_2ghz = delta_5ghz = 0; 3350 if ((val & 0xff) != 0xff && (val & 0x80)) { 3351 delta_2ghz = val & 0xf; 3352 if (!(val & 0x40)) /* negative number */ 3353 delta_2ghz = -delta_2ghz; 3354 } 3355 val >>= 8; 3356 if ((val & 0xff) != 0xff && (val & 0x80)) { 3357 delta_5ghz = val & 0xf; 3358 if (!(val & 0x40)) /* negative number */ 3359 delta_5ghz = -delta_5ghz; 3360 } 3361 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3362 delta_2ghz, delta_5ghz)); 3363 3364 for (ridx = 0; ridx < 5; ridx++) { 3365 uint32_t reg; 3366 3367 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3368 reg = val; 3369 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3370 reg |= (uint32_t)val << 16; 3371 3372 sc->txpow20mhz[ridx] = reg; 3373 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3374 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3375 3376 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3377 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3378 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3379 } 3380 3381 /* read factory-calibrated samples for temperature compensation */ 3382 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3383 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3384 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3385 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3386 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3387 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3388 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3389 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3390 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3391 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3392 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3393 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3394 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3395 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3396 sc->step_2ghz = val >> 8; 3397 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3398 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3399 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3400 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3401 sc->tssi_2ghz[8], sc->step_2ghz)); 3402 /* check that ref value is correct, otherwise disable calibration */ 3403 if (sc->tssi_2ghz[4] == 0xff) 3404 sc->calib_2ghz = 0; 3405 3406 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3407 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3408 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3409 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3410 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3411 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3412 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3413 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3414 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3415 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3416 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3417 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3418 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3419 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3420 sc->step_5ghz = val >> 8; 3421 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3422 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3423 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3424 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3425 sc->tssi_5ghz[8], sc->step_5ghz)); 3426 /* check that ref value is correct, otherwise disable calibration */ 3427 if (sc->tssi_5ghz[4] == 0xff) 3428 sc->calib_5ghz = 0; 3429 3430 /* read RSSI offsets and LNA gains from EEPROM */ 3431 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3432 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3433 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3434 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3435 if (sc->mac_ver >= 0x3071) { 3436 /* 3437 * On RT3090 chips (limited to 2 Rx chains), this ROM 3438 * field contains the Tx mixer gain for the 2GHz band. 3439 */ 3440 if ((val & 0xff) != 0xff) 3441 sc->txmixgain_2ghz = val & 0x7; 3442 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3443 } else 3444 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3445 sc->lna[2] = val >> 8; /* channel group 2 */ 3446 3447 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3448 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3449 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3450 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3451 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3452 sc->lna[3] = val >> 8; /* channel group 3 */ 3453 3454 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3455 if (sc->mac_ver >= 0x3071) 3456 sc->lna[0] = RT3090_DEF_LNA; 3457 else /* channel group 0 */ 3458 sc->lna[0] = val & 0xff; 3459 sc->lna[1] = val >> 8; /* channel group 1 */ 3460 3461 /* fix broken 5GHz LNA entries */ 3462 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3463 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3464 sc->lna[2] = sc->lna[1]; 3465 } 3466 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3467 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3468 sc->lna[3] = sc->lna[1]; 3469 } 3470 3471 /* fix broken RSSI offset entries */ 3472 for (ant = 0; ant < 3; ant++) { 3473 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3474 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3475 ant + 1, sc->rssi_2ghz[ant])); 3476 sc->rssi_2ghz[ant] = 0; 3477 } 3478 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3479 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3480 ant + 1, sc->rssi_5ghz[ant])); 3481 sc->rssi_5ghz[ant] = 0; 3482 } 3483 } 3484 3485 return 0; 3486} 3487 3488int 3489rt2860_bbp_init(struct rt2860_softc *sc) 3490{ 3491#define N(a) (sizeof (a) / sizeof ((a)[0])) 3492 int i, ntries; 3493 3494 /* wait for BBP to wake up */ 3495 for (ntries = 0; ntries < 20; ntries++) { 3496 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3497 if (bbp0 != 0 && bbp0 != 0xff) 3498 break; 3499 } 3500 if (ntries == 20) { 3501 device_printf(sc->sc_dev, 3502 "timeout waiting for BBP to wake up\n"); 3503 return ETIMEDOUT; 3504 } 3505 3506 /* initialize BBP registers to default values */ 3507 for (i = 0; i < N(rt2860_def_bbp); i++) { 3508 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3509 rt2860_def_bbp[i].val); 3510 } 3511 3512 /* fix BBP84 for RT2860E */ 3513 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3514 rt2860_mcu_bbp_write(sc, 84, 0x19); 3515 3516 if (sc->mac_ver >= 0x3071) { 3517 rt2860_mcu_bbp_write(sc, 79, 0x13); 3518 rt2860_mcu_bbp_write(sc, 80, 0x05); 3519 rt2860_mcu_bbp_write(sc, 81, 0x33); 3520 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3521 rt2860_mcu_bbp_write(sc, 69, 0x16); 3522 rt2860_mcu_bbp_write(sc, 73, 0x12); 3523 } 3524 3525 return 0; 3526#undef N 3527} 3528 3529static int 3530rt2860_txrx_enable(struct rt2860_softc *sc) 3531{ 3532 struct ifnet *ifp = sc->sc_ifp; 3533 struct ieee80211com *ic = ifp->if_l2com; 3534 uint32_t tmp; 3535 int ntries; 3536 3537 /* enable Tx/Rx DMA engine */ 3538 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3539 RAL_BARRIER_READ_WRITE(sc); 3540 for (ntries = 0; ntries < 200; ntries++) { 3541 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3542 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3543 break; 3544 DELAY(1000); 3545 } 3546 if (ntries == 200) { 3547 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3548 return ETIMEDOUT; 3549 } 3550 3551 DELAY(50); 3552 3553 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3554 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3555 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3556 3557 /* set Rx filter */ 3558 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3559 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3560 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3561 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3562 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3563 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3564 if (ic->ic_opmode == IEEE80211_M_STA) 3565 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3566 } 3567 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3568 3569 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3570 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3571 3572 return 0; 3573} 3574 3575static void 3576rt2860_init(void *arg) 3577{ 3578 struct rt2860_softc *sc = arg; 3579 struct ifnet *ifp = sc->sc_ifp; 3580 struct ieee80211com *ic = ifp->if_l2com; 3581 3582 RAL_LOCK(sc); 3583 rt2860_init_locked(sc); 3584 RAL_UNLOCK(sc); 3585 3586 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3587 ieee80211_start_all(ic); 3588} 3589 3590static void 3591rt2860_init_locked(struct rt2860_softc *sc) 3592{ 3593#define N(a) (sizeof (a) / sizeof ((a)[0])) 3594 struct ifnet *ifp = sc->sc_ifp; 3595 struct ieee80211com *ic = ifp->if_l2com; 3596 uint32_t tmp; 3597 uint8_t bbp1, bbp3; 3598 int i, qid, ridx, ntries, error; 3599 3600 RAL_LOCK_ASSERT(sc); 3601 3602 if (sc->rfswitch) { 3603 /* hardware has a radio switch on GPIO pin 2 */ 3604 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3605 device_printf(sc->sc_dev, 3606 "radio is disabled by hardware switch\n"); 3607#ifdef notyet 3608 rt2860_stop_locked(sc); 3609 return; 3610#endif 3611 } 3612 } 3613 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3614 3615 /* disable DMA */ 3616 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3617 tmp &= 0xff0; 3618 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3619 3620 /* PBF hardware reset */ 3621 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3622 RAL_BARRIER_WRITE(sc); 3623 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3624 3625 if ((error = rt2860_load_microcode(sc)) != 0) { 3626 device_printf(sc->sc_dev, "could not load 8051 microcode\n"); 3627 rt2860_stop_locked(sc); 3628 return; 3629 } 3630 3631 rt2860_set_macaddr(sc, IF_LLADDR(ifp)); 3632 3633 /* init Tx power for all Tx rates (from EEPROM) */ 3634 for (ridx = 0; ridx < 5; ridx++) { 3635 if (sc->txpow20mhz[ridx] == 0xffffffff) 3636 continue; 3637 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3638 } 3639 3640 for (ntries = 0; ntries < 100; ntries++) { 3641 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3642 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3643 break; 3644 DELAY(1000); 3645 } 3646 if (ntries == 100) { 3647 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3648 rt2860_stop_locked(sc); 3649 return; 3650 } 3651 tmp &= 0xff0; 3652 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3653 3654 /* reset Rx ring and all 6 Tx rings */ 3655 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3656 3657 /* PBF hardware reset */ 3658 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3659 RAL_BARRIER_WRITE(sc); 3660 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3661 3662 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3663 3664 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3665 RAL_BARRIER_WRITE(sc); 3666 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3667 3668 for (i = 0; i < N(rt2860_def_mac); i++) 3669 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3670 if (sc->mac_ver >= 0x3071) { 3671 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3672 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3673 4 << RT2860_DLY_PAPE_EN_SHIFT); 3674 } 3675 3676 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3677 sc->sc_flags |= RT2860_PCIE; 3678 /* PCIe has different clock cycle count than PCI */ 3679 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3680 tmp = (tmp & ~0xff) | 0x7d; 3681 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3682 } 3683 3684 /* wait while MAC is busy */ 3685 for (ntries = 0; ntries < 100; ntries++) { 3686 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3687 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3688 break; 3689 DELAY(1000); 3690 } 3691 if (ntries == 100) { 3692 device_printf(sc->sc_dev, "timeout waiting for MAC\n"); 3693 rt2860_stop_locked(sc); 3694 return; 3695 } 3696 3697 /* clear Host to MCU mailbox */ 3698 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3699 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3700 3701 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3702 DELAY(1000); 3703 3704 if ((error = rt2860_bbp_init(sc)) != 0) { 3705 rt2860_stop_locked(sc); 3706 return; 3707 } 3708 3709 /* clear RX WCID search table */ 3710 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3711 /* clear pairwise key table */ 3712 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3713 /* clear IV/EIV table */ 3714 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3715 /* clear WCID attribute table */ 3716 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3717 /* clear shared key table */ 3718 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3719 /* clear shared key mode */ 3720 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3721 3722 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3723 for (qid = 0; qid < 6; qid++) { 3724 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3725 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3726 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 3727 } 3728 3729 /* init Rx ring */ 3730 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 3731 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 3732 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 3733 3734 /* setup maximum buffer sizes */ 3735 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 3736 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 3737 3738 for (ntries = 0; ntries < 100; ntries++) { 3739 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3740 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3741 break; 3742 DELAY(1000); 3743 } 3744 if (ntries == 100) { 3745 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3746 rt2860_stop_locked(sc); 3747 return; 3748 } 3749 tmp &= 0xff0; 3750 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3751 3752 /* disable interrupts mitigation */ 3753 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 3754 3755 /* write vendor-specific BBP values (from EEPROM) */ 3756 for (i = 0; i < 8; i++) { 3757 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 3758 continue; 3759 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 3760 } 3761 3762 /* select Main antenna for 1T1R devices */ 3763 if (sc->rf_rev == RT3070_RF_2020 || 3764 sc->rf_rev == RT3070_RF_3020 || 3765 sc->rf_rev == RT3070_RF_3320) 3766 rt3090_set_rx_antenna(sc, 0); 3767 3768 /* send LEDs operating mode to microcontroller */ 3769 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 3770 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 3771 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 3772 3773 if (sc->mac_ver >= 0x3071) 3774 rt3090_rf_init(sc); 3775 3776 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 3777 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 3778 3779 if (sc->mac_ver >= 0x3071) 3780 rt3090_rf_wakeup(sc); 3781 3782 /* disable non-existing Rx chains */ 3783 bbp3 = rt2860_mcu_bbp_read(sc, 3); 3784 bbp3 &= ~(1 << 3 | 1 << 4); 3785 if (sc->nrxchains == 2) 3786 bbp3 |= 1 << 3; 3787 else if (sc->nrxchains == 3) 3788 bbp3 |= 1 << 4; 3789 rt2860_mcu_bbp_write(sc, 3, bbp3); 3790 3791 /* disable non-existing Tx chains */ 3792 bbp1 = rt2860_mcu_bbp_read(sc, 1); 3793 if (sc->ntxchains == 1) 3794 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 3795 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 3796 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 3797 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 3798 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 3799 rt2860_mcu_bbp_write(sc, 1, bbp1); 3800 3801 if (sc->mac_ver >= 0x3071) 3802 rt3090_rf_setup(sc); 3803 3804 /* select default channel */ 3805 rt2860_switch_chan(sc, ic->ic_curchan); 3806 3807 /* reset RF from MCU */ 3808 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3809 3810 /* set RTS threshold */ 3811 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 3812 tmp &= ~0xffff00; 3813 tmp |= IEEE80211_RTS_DEFAULT << 8; 3814 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 3815 3816 /* setup initial protection mode */ 3817 rt2860_updateprot(ifp); 3818 3819 /* turn radio LED on */ 3820 rt2860_set_leds(sc, RT2860_LED_RADIO); 3821 3822 /* enable Tx/Rx DMA engine */ 3823 if ((error = rt2860_txrx_enable(sc)) != 0) { 3824 rt2860_stop_locked(sc); 3825 return; 3826 } 3827 3828 /* clear pending interrupts */ 3829 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 3830 /* enable interrupts */ 3831 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 3832 3833 if (sc->sc_flags & RT2860_ADVANCED_PS) 3834 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 3835 3836 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3837 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3838 3839 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 3840#undef N 3841} 3842 3843static void 3844rt2860_stop(void *arg) 3845{ 3846 struct rt2860_softc *sc = arg; 3847 3848 RAL_LOCK(sc); 3849 rt2860_stop_locked(sc); 3850 RAL_UNLOCK(sc); 3851} 3852 3853static void 3854rt2860_stop_locked(struct rt2860_softc *sc) 3855{ 3856 struct ifnet *ifp = sc->sc_ifp; 3857 uint32_t tmp; 3858 int qid; 3859 3860 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3861 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 3862 3863 callout_stop(&sc->watchdog_ch); 3864 sc->sc_tx_timer = 0; 3865 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3866 3867 /* disable interrupts */ 3868 RAL_WRITE(sc, RT2860_INT_MASK, 0); 3869 3870 /* disable GP timer */ 3871 rt2860_set_gp_timer(sc, 0); 3872 3873 /* disable Rx */ 3874 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 3875 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3876 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 3877 3878 /* reset adapter */ 3879 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3880 RAL_BARRIER_WRITE(sc); 3881 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3882 3883 /* reset Tx and Rx rings (and reclaim TXWIs) */ 3884 sc->qfullmsk = 0; 3885 for (qid = 0; qid < 6; qid++) 3886 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 3887 rt2860_reset_rx_ring(sc, &sc->rxq); 3888} 3889 3890int 3891rt2860_load_microcode(struct rt2860_softc *sc) 3892{ 3893 const struct firmware *fp; 3894 int ntries, error; 3895 3896 RAL_LOCK_ASSERT(sc); 3897 3898 RAL_UNLOCK(sc); 3899 fp = firmware_get("rt2860fw"); 3900 RAL_LOCK(sc); 3901 if (fp == NULL) { 3902 device_printf(sc->sc_dev, 3903 "unable to receive rt2860fw firmware image\n"); 3904 return EINVAL; 3905 } 3906 3907 /* set "host program ram write selection" bit */ 3908 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 3909 /* write microcode image */ 3910 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, fp->data, fp->datasize); 3911 /* kick microcontroller unit */ 3912 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 3913 RAL_BARRIER_WRITE(sc); 3914 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 3915 3916 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3917 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3918 3919 /* wait until microcontroller is ready */ 3920 RAL_BARRIER_READ_WRITE(sc); 3921 for (ntries = 0; ntries < 1000; ntries++) { 3922 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 3923 break; 3924 DELAY(1000); 3925 } 3926 if (ntries == 1000) { 3927 device_printf(sc->sc_dev, 3928 "timeout waiting for MCU to initialize\n"); 3929 error = ETIMEDOUT; 3930 } else 3931 error = 0; 3932 3933 firmware_put(fp, FIRMWARE_UNLOAD); 3934 return error; 3935} 3936 3937/* 3938 * This function is called periodically to adjust Tx power based on 3939 * temperature variation. 3940 */ 3941#ifdef NOT_YET 3942static void 3943rt2860_calib(struct rt2860_softc *sc) 3944{ 3945 struct ieee80211com *ic = &sc->sc_ic; 3946 const uint8_t *tssi; 3947 uint8_t step, bbp49; 3948 int8_t ridx, d; 3949 3950 /* read current temperature */ 3951 bbp49 = rt2860_mcu_bbp_read(sc, 49); 3952 3953 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 3954 tssi = &sc->tssi_2ghz[4]; 3955 step = sc->step_2ghz; 3956 } else { 3957 tssi = &sc->tssi_5ghz[4]; 3958 step = sc->step_5ghz; 3959 } 3960 3961 if (bbp49 < tssi[0]) { /* lower than reference */ 3962 /* use higher Tx power than default */ 3963 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 3964 } else if (bbp49 > tssi[0]) { /* greater than reference */ 3965 /* use lower Tx power than default */ 3966 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 3967 } else { 3968 /* use default Tx power */ 3969 d = 0; 3970 } 3971 d *= step; 3972 3973 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 3974 3975 /* write adjusted Tx power values for each Tx rate */ 3976 for (ridx = 0; ridx < 5; ridx++) { 3977 if (sc->txpow20mhz[ridx] == 0xffffffff) 3978 continue; 3979 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 3980 b4inc(sc->txpow20mhz[ridx], d)); 3981 } 3982} 3983#endif 3984 3985static void 3986rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 3987{ 3988 uint32_t tmp; 3989 3990 if (aux) { 3991 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 3992 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C); 3993 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 3994 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 3995 } else { 3996 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 3997 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C); 3998 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 3999 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 4000 } 4001} 4002 4003static void 4004rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 4005{ 4006 struct ifnet *ifp = sc->sc_ifp; 4007 struct ieee80211com *ic = ifp->if_l2com; 4008 u_int chan, group; 4009 4010 chan = ieee80211_chan2ieee(ic, c); 4011 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 4012 return; 4013 4014 if (sc->mac_ver >= 0x3071) 4015 rt3090_set_chan(sc, chan); 4016 else 4017 rt2860_set_chan(sc, chan); 4018 4019 /* determine channel group */ 4020 if (chan <= 14) 4021 group = 0; 4022 else if (chan <= 64) 4023 group = 1; 4024 else if (chan <= 128) 4025 group = 2; 4026 else 4027 group = 3; 4028 4029 /* XXX necessary only when group has changed! */ 4030 rt2860_select_chan_group(sc, group); 4031 4032 DELAY(1000); 4033} 4034 4035static int 4036rt2860_setup_beacon(struct rt2860_softc *sc, struct ieee80211vap *vap) 4037{ 4038 struct ieee80211com *ic = vap->iv_ic; 4039 struct ieee80211_beacon_offsets bo; 4040 struct rt2860_txwi txwi; 4041 struct mbuf *m; 4042 int ridx; 4043 4044 if ((m = ieee80211_beacon_alloc(vap->iv_bss, &bo)) == NULL) 4045 return ENOBUFS; 4046 4047 memset(&txwi, 0, sizeof txwi); 4048 txwi.wcid = 0xff; 4049 txwi.len = htole16(m->m_pkthdr.len); 4050 /* send beacons at the lowest available rate */ 4051 ridx = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 4052 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4053 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4054 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4055 txwi.phy |= htole16(RT2860_PHY_OFDM); 4056 txwi.txop = RT2860_TX_TXOP_HT; 4057 txwi.flags = RT2860_TX_TS; 4058 txwi.xflags = RT2860_TX_NSEQ; 4059 4060 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 4061 (uint8_t *)&txwi, sizeof txwi); 4062 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 4063 mtod(m, uint8_t *), m->m_pkthdr.len); 4064 4065 m_freem(m); 4066 4067 return 0; 4068} 4069 4070static void 4071rt2860_enable_tsf_sync(struct rt2860_softc *sc) 4072{ 4073 struct ifnet *ifp = sc->sc_ifp; 4074 struct ieee80211com *ic = ifp->if_l2com; 4075 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4076 uint32_t tmp; 4077 4078 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 4079 4080 tmp &= ~0x1fffff; 4081 tmp |= vap->iv_bss->ni_intval * 16; 4082 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 4083 if (vap->iv_opmode == IEEE80211_M_STA) { 4084 /* 4085 * Local TSF is always updated with remote TSF on beacon 4086 * reception. 4087 */ 4088 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 4089 } 4090 else if (vap->iv_opmode == IEEE80211_M_IBSS || 4091 vap->iv_opmode == IEEE80211_M_MBSS) { 4092 tmp |= RT2860_BCN_TX_EN; 4093 /* 4094 * Local TSF is updated with remote TSF on beacon reception 4095 * only if the remote TSF is greater than local TSF. 4096 */ 4097 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 4098 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) { 4099 tmp |= RT2860_BCN_TX_EN; 4100 /* SYNC with nobody */ 4101 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 4102 } 4103 4104 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 4105} 4106