rt2661.c revision 192468
1/* $FreeBSD: head/sys/dev/ral/rt2661.c 192468 2009-05-20 20:00:40Z sam $ */ 2 3/*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/ral/rt2661.c 192468 2009-05-20 20:00:40Z sam $"); 22 23/*- 24 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28#include <sys/param.h> 29#include <sys/sysctl.h> 30#include <sys/sockio.h> 31#include <sys/mbuf.h> 32#include <sys/kernel.h> 33#include <sys/socket.h> 34#include <sys/systm.h> 35#include <sys/malloc.h> 36#include <sys/lock.h> 37#include <sys/mutex.h> 38#include <sys/module.h> 39#include <sys/bus.h> 40#include <sys/endian.h> 41#include <sys/firmware.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <sys/rman.h> 46 47#include <net/bpf.h> 48#include <net/if.h> 49#include <net/if_arp.h> 50#include <net/ethernet.h> 51#include <net/if_dl.h> 52#include <net/if_media.h> 53#include <net/if_types.h> 54 55#include <net80211/ieee80211_var.h> 56#include <net80211/ieee80211_radiotap.h> 57#include <net80211/ieee80211_regdomain.h> 58#include <net80211/ieee80211_amrr.h> 59 60#include <netinet/in.h> 61#include <netinet/in_systm.h> 62#include <netinet/in_var.h> 63#include <netinet/ip.h> 64#include <netinet/if_ether.h> 65 66#include <dev/ral/rt2661reg.h> 67#include <dev/ral/rt2661var.h> 68 69#define RAL_DEBUG 70#ifdef RAL_DEBUG 71#define DPRINTF(sc, fmt, ...) do { \ 72 if (sc->sc_debug > 0) \ 73 printf(fmt, __VA_ARGS__); \ 74} while (0) 75#define DPRINTFN(sc, n, fmt, ...) do { \ 76 if (sc->sc_debug >= (n)) \ 77 printf(fmt, __VA_ARGS__); \ 78} while (0) 79#else 80#define DPRINTF(sc, fmt, ...) 81#define DPRINTFN(sc, n, fmt, ...) 82#endif 83 84static struct ieee80211vap *rt2661_vap_create(struct ieee80211com *, 85 const char name[IFNAMSIZ], int unit, int opmode, 86 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 87 const uint8_t mac[IEEE80211_ADDR_LEN]); 88static void rt2661_vap_delete(struct ieee80211vap *); 89static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int, 90 int); 91static int rt2661_alloc_tx_ring(struct rt2661_softc *, 92 struct rt2661_tx_ring *, int); 93static void rt2661_reset_tx_ring(struct rt2661_softc *, 94 struct rt2661_tx_ring *); 95static void rt2661_free_tx_ring(struct rt2661_softc *, 96 struct rt2661_tx_ring *); 97static int rt2661_alloc_rx_ring(struct rt2661_softc *, 98 struct rt2661_rx_ring *, int); 99static void rt2661_reset_rx_ring(struct rt2661_softc *, 100 struct rt2661_rx_ring *); 101static void rt2661_free_rx_ring(struct rt2661_softc *, 102 struct rt2661_rx_ring *); 103static struct ieee80211_node *rt2661_node_alloc(struct ieee80211vap *, 104 const uint8_t [IEEE80211_ADDR_LEN]); 105static void rt2661_newassoc(struct ieee80211_node *, int); 106static int rt2661_newstate(struct ieee80211vap *, 107 enum ieee80211_state, int); 108static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 109static void rt2661_rx_intr(struct rt2661_softc *); 110static void rt2661_tx_intr(struct rt2661_softc *); 111static void rt2661_tx_dma_intr(struct rt2661_softc *, 112 struct rt2661_tx_ring *); 113static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 114static void rt2661_mcu_wakeup(struct rt2661_softc *); 115static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 116static void rt2661_scan_start(struct ieee80211com *); 117static void rt2661_scan_end(struct ieee80211com *); 118static void rt2661_set_channel(struct ieee80211com *); 119static void rt2661_setup_tx_desc(struct rt2661_softc *, 120 struct rt2661_tx_desc *, uint32_t, uint16_t, int, 121 int, const bus_dma_segment_t *, int, int); 122static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 123 struct ieee80211_node *, int); 124static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 125 struct ieee80211_node *); 126static void rt2661_start_locked(struct ifnet *); 127static void rt2661_start(struct ifnet *); 128static int rt2661_raw_xmit(struct ieee80211_node *, struct mbuf *, 129 const struct ieee80211_bpf_params *); 130static void rt2661_watchdog(void *); 131static int rt2661_ioctl(struct ifnet *, u_long, caddr_t); 132static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, 133 uint8_t); 134static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 135static void rt2661_rf_write(struct rt2661_softc *, uint8_t, 136 uint32_t); 137static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, 138 uint16_t); 139static void rt2661_select_antenna(struct rt2661_softc *); 140static void rt2661_enable_mrr(struct rt2661_softc *); 141static void rt2661_set_txpreamble(struct rt2661_softc *); 142static void rt2661_set_basicrates(struct rt2661_softc *, 143 const struct ieee80211_rateset *); 144static void rt2661_select_band(struct rt2661_softc *, 145 struct ieee80211_channel *); 146static void rt2661_set_chan(struct rt2661_softc *, 147 struct ieee80211_channel *); 148static void rt2661_set_bssid(struct rt2661_softc *, 149 const uint8_t *); 150static void rt2661_set_macaddr(struct rt2661_softc *, 151 const uint8_t *); 152static void rt2661_update_promisc(struct ifnet *); 153static int rt2661_wme_update(struct ieee80211com *) __unused; 154static void rt2661_update_slot(struct ifnet *); 155static const char *rt2661_get_rf(int); 156static void rt2661_read_eeprom(struct rt2661_softc *, 157 uint8_t macaddr[IEEE80211_ADDR_LEN]); 158static int rt2661_bbp_init(struct rt2661_softc *); 159static void rt2661_init_locked(struct rt2661_softc *); 160static void rt2661_init(void *); 161static void rt2661_stop_locked(struct rt2661_softc *); 162static void rt2661_stop(void *); 163static int rt2661_load_microcode(struct rt2661_softc *); 164#ifdef notyet 165static void rt2661_rx_tune(struct rt2661_softc *); 166static void rt2661_radar_start(struct rt2661_softc *); 167static int rt2661_radar_stop(struct rt2661_softc *); 168#endif 169static int rt2661_prepare_beacon(struct rt2661_softc *, 170 struct ieee80211vap *); 171static void rt2661_enable_tsf_sync(struct rt2661_softc *); 172static void rt2661_enable_tsf(struct rt2661_softc *); 173static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 174 175static const struct { 176 uint32_t reg; 177 uint32_t val; 178} rt2661_def_mac[] = { 179 RT2661_DEF_MAC 180}; 181 182static const struct { 183 uint8_t reg; 184 uint8_t val; 185} rt2661_def_bbp[] = { 186 RT2661_DEF_BBP 187}; 188 189static const struct rfprog { 190 uint8_t chan; 191 uint32_t r1, r2, r3, r4; 192} rt2661_rf5225_1[] = { 193 RT2661_RF5225_1 194}, rt2661_rf5225_2[] = { 195 RT2661_RF5225_2 196}; 197 198int 199rt2661_attach(device_t dev, int id) 200{ 201 struct rt2661_softc *sc = device_get_softc(dev); 202 struct ieee80211com *ic; 203 struct ifnet *ifp; 204 uint32_t val; 205 int error, ac, ntries; 206 uint8_t bands; 207 uint8_t macaddr[IEEE80211_ADDR_LEN]; 208 209 sc->sc_id = id; 210 sc->sc_dev = dev; 211 212 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 213 if (ifp == NULL) { 214 device_printf(sc->sc_dev, "can not if_alloc()\n"); 215 return ENOMEM; 216 } 217 ic = ifp->if_l2com; 218 219 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 220 MTX_DEF | MTX_RECURSE); 221 222 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 223 224 /* wait for NIC to initialize */ 225 for (ntries = 0; ntries < 1000; ntries++) { 226 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 227 break; 228 DELAY(1000); 229 } 230 if (ntries == 1000) { 231 device_printf(sc->sc_dev, 232 "timeout waiting for NIC to initialize\n"); 233 error = EIO; 234 goto fail1; 235 } 236 237 /* retrieve RF rev. no and various other things from EEPROM */ 238 rt2661_read_eeprom(sc, macaddr); 239 240 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val, 241 rt2661_get_rf(sc->rf_rev)); 242 243 /* 244 * Allocate Tx and Rx rings. 245 */ 246 for (ac = 0; ac < 4; ac++) { 247 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 248 RT2661_TX_RING_COUNT); 249 if (error != 0) { 250 device_printf(sc->sc_dev, 251 "could not allocate Tx ring %d\n", ac); 252 goto fail2; 253 } 254 } 255 256 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 257 if (error != 0) { 258 device_printf(sc->sc_dev, "could not allocate Mgt ring\n"); 259 goto fail2; 260 } 261 262 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 263 if (error != 0) { 264 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 265 goto fail3; 266 } 267 268 ifp->if_softc = sc; 269 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 270 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 271 ifp->if_init = rt2661_init; 272 ifp->if_ioctl = rt2661_ioctl; 273 ifp->if_start = rt2661_start; 274 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 275 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 276 IFQ_SET_READY(&ifp->if_snd); 277 278 ic->ic_ifp = ifp; 279 ic->ic_opmode = IEEE80211_M_STA; 280 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 281 282 /* set device capabilities */ 283 ic->ic_caps = 284 IEEE80211_C_STA /* station mode */ 285 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 286 | IEEE80211_C_HOSTAP /* hostap mode */ 287 | IEEE80211_C_MONITOR /* monitor mode */ 288 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 289 | IEEE80211_C_WDS /* 4-address traffic works */ 290 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 291 | IEEE80211_C_SHSLOT /* short slot time supported */ 292 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 293 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 294#ifdef notyet 295 | IEEE80211_C_TXFRAG /* handle tx frags */ 296 | IEEE80211_C_WME /* 802.11e */ 297#endif 298 ; 299 300 bands = 0; 301 setbit(&bands, IEEE80211_MODE_11B); 302 setbit(&bands, IEEE80211_MODE_11G); 303 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) 304 setbit(&bands, IEEE80211_MODE_11A); 305 ieee80211_init_channels(ic, NULL, &bands); 306 307 ieee80211_ifattach(ic, macaddr); 308 ic->ic_newassoc = rt2661_newassoc; 309 ic->ic_node_alloc = rt2661_node_alloc; 310#if 0 311 ic->ic_wme.wme_update = rt2661_wme_update; 312#endif 313 ic->ic_scan_start = rt2661_scan_start; 314 ic->ic_scan_end = rt2661_scan_end; 315 ic->ic_set_channel = rt2661_set_channel; 316 ic->ic_updateslot = rt2661_update_slot; 317 ic->ic_update_promisc = rt2661_update_promisc; 318 ic->ic_raw_xmit = rt2661_raw_xmit; 319 320 ic->ic_vap_create = rt2661_vap_create; 321 ic->ic_vap_delete = rt2661_vap_delete; 322 323 ieee80211_radiotap_attach(ic, 324 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 325 RT2661_TX_RADIOTAP_PRESENT, 326 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 327 RT2661_RX_RADIOTAP_PRESENT); 328 329#ifdef RAL_DEBUG 330 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 331 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 332 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 333#endif 334 if (bootverbose) 335 ieee80211_announce(ic); 336 337 return 0; 338 339fail3: rt2661_free_tx_ring(sc, &sc->mgtq); 340fail2: while (--ac >= 0) 341 rt2661_free_tx_ring(sc, &sc->txq[ac]); 342fail1: mtx_destroy(&sc->sc_mtx); 343 if_free(ifp); 344 return error; 345} 346 347int 348rt2661_detach(void *xsc) 349{ 350 struct rt2661_softc *sc = xsc; 351 struct ifnet *ifp = sc->sc_ifp; 352 struct ieee80211com *ic = ifp->if_l2com; 353 354 RAL_LOCK(sc); 355 rt2661_stop_locked(sc); 356 RAL_UNLOCK(sc); 357 358 ieee80211_ifdetach(ic); 359 360 rt2661_free_tx_ring(sc, &sc->txq[0]); 361 rt2661_free_tx_ring(sc, &sc->txq[1]); 362 rt2661_free_tx_ring(sc, &sc->txq[2]); 363 rt2661_free_tx_ring(sc, &sc->txq[3]); 364 rt2661_free_tx_ring(sc, &sc->mgtq); 365 rt2661_free_rx_ring(sc, &sc->rxq); 366 367 if_free(ifp); 368 369 mtx_destroy(&sc->sc_mtx); 370 371 return 0; 372} 373 374static struct ieee80211vap * 375rt2661_vap_create(struct ieee80211com *ic, 376 const char name[IFNAMSIZ], int unit, int opmode, int flags, 377 const uint8_t bssid[IEEE80211_ADDR_LEN], 378 const uint8_t mac[IEEE80211_ADDR_LEN]) 379{ 380 struct ifnet *ifp = ic->ic_ifp; 381 struct rt2661_vap *rvp; 382 struct ieee80211vap *vap; 383 384 switch (opmode) { 385 case IEEE80211_M_STA: 386 case IEEE80211_M_IBSS: 387 case IEEE80211_M_AHDEMO: 388 case IEEE80211_M_MONITOR: 389 case IEEE80211_M_HOSTAP: 390 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 391 if_printf(ifp, "only 1 vap supported\n"); 392 return NULL; 393 } 394 if (opmode == IEEE80211_M_STA) 395 flags |= IEEE80211_CLONE_NOBEACONS; 396 break; 397 case IEEE80211_M_WDS: 398 if (TAILQ_EMPTY(&ic->ic_vaps) || 399 ic->ic_opmode != IEEE80211_M_HOSTAP) { 400 if_printf(ifp, "wds only supported in ap mode\n"); 401 return NULL; 402 } 403 /* 404 * Silently remove any request for a unique 405 * bssid; WDS vap's always share the local 406 * mac address. 407 */ 408 flags &= ~IEEE80211_CLONE_BSSID; 409 break; 410 default: 411 if_printf(ifp, "unknown opmode %d\n", opmode); 412 return NULL; 413 } 414 rvp = (struct rt2661_vap *) malloc(sizeof(struct rt2661_vap), 415 M_80211_VAP, M_NOWAIT | M_ZERO); 416 if (rvp == NULL) 417 return NULL; 418 vap = &rvp->ral_vap; 419 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 420 421 /* override state transition machine */ 422 rvp->ral_newstate = vap->iv_newstate; 423 vap->iv_newstate = rt2661_newstate; 424#if 0 425 vap->iv_update_beacon = rt2661_beacon_update; 426#endif 427 428 ieee80211_amrr_init(&rvp->amrr, vap, 429 IEEE80211_AMRR_MIN_SUCCESS_THRESHOLD, 430 IEEE80211_AMRR_MAX_SUCCESS_THRESHOLD, 431 500 /* ms */); 432 433 /* complete setup */ 434 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); 435 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 436 ic->ic_opmode = opmode; 437 return vap; 438} 439 440static void 441rt2661_vap_delete(struct ieee80211vap *vap) 442{ 443 struct rt2661_vap *rvp = RT2661_VAP(vap); 444 445 ieee80211_amrr_cleanup(&rvp->amrr); 446 ieee80211_vap_detach(vap); 447 free(rvp, M_80211_VAP); 448} 449 450void 451rt2661_shutdown(void *xsc) 452{ 453 struct rt2661_softc *sc = xsc; 454 455 rt2661_stop(sc); 456} 457 458void 459rt2661_suspend(void *xsc) 460{ 461 struct rt2661_softc *sc = xsc; 462 463 rt2661_stop(sc); 464} 465 466void 467rt2661_resume(void *xsc) 468{ 469 struct rt2661_softc *sc = xsc; 470 struct ifnet *ifp = sc->sc_ifp; 471 472 if (ifp->if_flags & IFF_UP) 473 rt2661_init(sc); 474} 475 476static void 477rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 478{ 479 if (error != 0) 480 return; 481 482 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 483 484 *(bus_addr_t *)arg = segs[0].ds_addr; 485} 486 487static int 488rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 489 int count) 490{ 491 int i, error; 492 493 ring->count = count; 494 ring->queued = 0; 495 ring->cur = ring->next = ring->stat = 0; 496 497 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 498 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 499 count * RT2661_TX_DESC_SIZE, 1, count * RT2661_TX_DESC_SIZE, 500 0, NULL, NULL, &ring->desc_dmat); 501 if (error != 0) { 502 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 503 goto fail; 504 } 505 506 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 507 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 508 if (error != 0) { 509 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 510 goto fail; 511 } 512 513 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 514 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 515 0); 516 if (error != 0) { 517 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 518 goto fail; 519 } 520 521 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 522 M_NOWAIT | M_ZERO); 523 if (ring->data == NULL) { 524 device_printf(sc->sc_dev, "could not allocate soft data\n"); 525 error = ENOMEM; 526 goto fail; 527 } 528 529 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 530 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 531 RT2661_MAX_SCATTER, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 532 if (error != 0) { 533 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 534 goto fail; 535 } 536 537 for (i = 0; i < count; i++) { 538 error = bus_dmamap_create(ring->data_dmat, 0, 539 &ring->data[i].map); 540 if (error != 0) { 541 device_printf(sc->sc_dev, "could not create DMA map\n"); 542 goto fail; 543 } 544 } 545 546 return 0; 547 548fail: rt2661_free_tx_ring(sc, ring); 549 return error; 550} 551 552static void 553rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 554{ 555 struct rt2661_tx_desc *desc; 556 struct rt2661_tx_data *data; 557 int i; 558 559 for (i = 0; i < ring->count; i++) { 560 desc = &ring->desc[i]; 561 data = &ring->data[i]; 562 563 if (data->m != NULL) { 564 bus_dmamap_sync(ring->data_dmat, data->map, 565 BUS_DMASYNC_POSTWRITE); 566 bus_dmamap_unload(ring->data_dmat, data->map); 567 m_freem(data->m); 568 data->m = NULL; 569 } 570 571 if (data->ni != NULL) { 572 ieee80211_free_node(data->ni); 573 data->ni = NULL; 574 } 575 576 desc->flags = 0; 577 } 578 579 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 580 581 ring->queued = 0; 582 ring->cur = ring->next = ring->stat = 0; 583} 584 585static void 586rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 587{ 588 struct rt2661_tx_data *data; 589 int i; 590 591 if (ring->desc != NULL) { 592 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 593 BUS_DMASYNC_POSTWRITE); 594 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 595 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 596 } 597 598 if (ring->desc_dmat != NULL) 599 bus_dma_tag_destroy(ring->desc_dmat); 600 601 if (ring->data != NULL) { 602 for (i = 0; i < ring->count; i++) { 603 data = &ring->data[i]; 604 605 if (data->m != NULL) { 606 bus_dmamap_sync(ring->data_dmat, data->map, 607 BUS_DMASYNC_POSTWRITE); 608 bus_dmamap_unload(ring->data_dmat, data->map); 609 m_freem(data->m); 610 } 611 612 if (data->ni != NULL) 613 ieee80211_free_node(data->ni); 614 615 if (data->map != NULL) 616 bus_dmamap_destroy(ring->data_dmat, data->map); 617 } 618 619 free(ring->data, M_DEVBUF); 620 } 621 622 if (ring->data_dmat != NULL) 623 bus_dma_tag_destroy(ring->data_dmat); 624} 625 626static int 627rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 628 int count) 629{ 630 struct rt2661_rx_desc *desc; 631 struct rt2661_rx_data *data; 632 bus_addr_t physaddr; 633 int i, error; 634 635 ring->count = count; 636 ring->cur = ring->next = 0; 637 638 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 639 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 640 count * RT2661_RX_DESC_SIZE, 1, count * RT2661_RX_DESC_SIZE, 641 0, NULL, NULL, &ring->desc_dmat); 642 if (error != 0) { 643 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 644 goto fail; 645 } 646 647 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 648 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 649 if (error != 0) { 650 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 651 goto fail; 652 } 653 654 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 655 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 656 0); 657 if (error != 0) { 658 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 659 goto fail; 660 } 661 662 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 663 M_NOWAIT | M_ZERO); 664 if (ring->data == NULL) { 665 device_printf(sc->sc_dev, "could not allocate soft data\n"); 666 error = ENOMEM; 667 goto fail; 668 } 669 670 /* 671 * Pre-allocate Rx buffers and populate Rx ring. 672 */ 673 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 674 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 675 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 676 if (error != 0) { 677 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 678 goto fail; 679 } 680 681 for (i = 0; i < count; i++) { 682 desc = &sc->rxq.desc[i]; 683 data = &sc->rxq.data[i]; 684 685 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 686 if (error != 0) { 687 device_printf(sc->sc_dev, "could not create DMA map\n"); 688 goto fail; 689 } 690 691 data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 692 if (data->m == NULL) { 693 device_printf(sc->sc_dev, 694 "could not allocate rx mbuf\n"); 695 error = ENOMEM; 696 goto fail; 697 } 698 699 error = bus_dmamap_load(ring->data_dmat, data->map, 700 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr, 701 &physaddr, 0); 702 if (error != 0) { 703 device_printf(sc->sc_dev, 704 "could not load rx buf DMA map"); 705 goto fail; 706 } 707 708 desc->flags = htole32(RT2661_RX_BUSY); 709 desc->physaddr = htole32(physaddr); 710 } 711 712 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 713 714 return 0; 715 716fail: rt2661_free_rx_ring(sc, ring); 717 return error; 718} 719 720static void 721rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 722{ 723 int i; 724 725 for (i = 0; i < ring->count; i++) 726 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 727 728 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 729 730 ring->cur = ring->next = 0; 731} 732 733static void 734rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 735{ 736 struct rt2661_rx_data *data; 737 int i; 738 739 if (ring->desc != NULL) { 740 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 741 BUS_DMASYNC_POSTWRITE); 742 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 743 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 744 } 745 746 if (ring->desc_dmat != NULL) 747 bus_dma_tag_destroy(ring->desc_dmat); 748 749 if (ring->data != NULL) { 750 for (i = 0; i < ring->count; i++) { 751 data = &ring->data[i]; 752 753 if (data->m != NULL) { 754 bus_dmamap_sync(ring->data_dmat, data->map, 755 BUS_DMASYNC_POSTREAD); 756 bus_dmamap_unload(ring->data_dmat, data->map); 757 m_freem(data->m); 758 } 759 760 if (data->map != NULL) 761 bus_dmamap_destroy(ring->data_dmat, data->map); 762 } 763 764 free(ring->data, M_DEVBUF); 765 } 766 767 if (ring->data_dmat != NULL) 768 bus_dma_tag_destroy(ring->data_dmat); 769} 770 771static struct ieee80211_node * 772rt2661_node_alloc(struct ieee80211vap *vap, 773 const uint8_t mac[IEEE80211_ADDR_LEN]) 774{ 775 struct rt2661_node *rn; 776 777 rn = malloc(sizeof (struct rt2661_node), M_80211_NODE, 778 M_NOWAIT | M_ZERO); 779 780 return (rn != NULL) ? &rn->ni : NULL; 781} 782 783static void 784rt2661_newassoc(struct ieee80211_node *ni, int isnew) 785{ 786 struct ieee80211vap *vap = ni->ni_vap; 787 788 ieee80211_amrr_node_init(&RT2661_VAP(vap)->amrr, 789 &RT2661_NODE(ni)->amrr, ni); 790} 791 792static int 793rt2661_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 794{ 795 struct rt2661_vap *rvp = RT2661_VAP(vap); 796 struct ieee80211com *ic = vap->iv_ic; 797 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 798 int error; 799 800 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 801 uint32_t tmp; 802 803 /* abort TSF synchronization */ 804 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 805 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 806 } 807 808 error = rvp->ral_newstate(vap, nstate, arg); 809 810 if (error == 0 && nstate == IEEE80211_S_RUN) { 811 struct ieee80211_node *ni = vap->iv_bss; 812 813 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 814 rt2661_enable_mrr(sc); 815 rt2661_set_txpreamble(sc); 816 rt2661_set_basicrates(sc, &ni->ni_rates); 817 rt2661_set_bssid(sc, ni->ni_bssid); 818 } 819 820 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 821 vap->iv_opmode == IEEE80211_M_IBSS) { 822 error = rt2661_prepare_beacon(sc, vap); 823 if (error != 0) 824 return error; 825 } 826 if (vap->iv_opmode != IEEE80211_M_MONITOR) 827 rt2661_enable_tsf_sync(sc); 828 else 829 rt2661_enable_tsf(sc); 830 } 831 return error; 832} 833 834/* 835 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 836 * 93C66). 837 */ 838static uint16_t 839rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 840{ 841 uint32_t tmp; 842 uint16_t val; 843 int n; 844 845 /* clock C once before the first command */ 846 RT2661_EEPROM_CTL(sc, 0); 847 848 RT2661_EEPROM_CTL(sc, RT2661_S); 849 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 850 RT2661_EEPROM_CTL(sc, RT2661_S); 851 852 /* write start bit (1) */ 853 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 854 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 855 856 /* write READ opcode (10) */ 857 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 858 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 859 RT2661_EEPROM_CTL(sc, RT2661_S); 860 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 861 862 /* write address (A5-A0 or A7-A0) */ 863 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 864 for (; n >= 0; n--) { 865 RT2661_EEPROM_CTL(sc, RT2661_S | 866 (((addr >> n) & 1) << RT2661_SHIFT_D)); 867 RT2661_EEPROM_CTL(sc, RT2661_S | 868 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 869 } 870 871 RT2661_EEPROM_CTL(sc, RT2661_S); 872 873 /* read data Q15-Q0 */ 874 val = 0; 875 for (n = 15; n >= 0; n--) { 876 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 877 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 878 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 879 RT2661_EEPROM_CTL(sc, RT2661_S); 880 } 881 882 RT2661_EEPROM_CTL(sc, 0); 883 884 /* clear Chip Select and clock C */ 885 RT2661_EEPROM_CTL(sc, RT2661_S); 886 RT2661_EEPROM_CTL(sc, 0); 887 RT2661_EEPROM_CTL(sc, RT2661_C); 888 889 return val; 890} 891 892static void 893rt2661_tx_intr(struct rt2661_softc *sc) 894{ 895 struct ifnet *ifp = sc->sc_ifp; 896 struct rt2661_tx_ring *txq; 897 struct rt2661_tx_data *data; 898 struct rt2661_node *rn; 899 uint32_t val; 900 int qid, retrycnt; 901 902 for (;;) { 903 struct ieee80211_node *ni; 904 struct mbuf *m; 905 906 val = RAL_READ(sc, RT2661_STA_CSR4); 907 if (!(val & RT2661_TX_STAT_VALID)) 908 break; 909 910 /* retrieve the queue in which this frame was sent */ 911 qid = RT2661_TX_QID(val); 912 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 913 914 /* retrieve rate control algorithm context */ 915 data = &txq->data[txq->stat]; 916 m = data->m; 917 data->m = NULL; 918 ni = data->ni; 919 data->ni = NULL; 920 921 /* if no frame has been sent, ignore */ 922 if (ni == NULL) 923 continue; 924 925 rn = RT2661_NODE(ni); 926 927 switch (RT2661_TX_RESULT(val)) { 928 case RT2661_TX_SUCCESS: 929 retrycnt = RT2661_TX_RETRYCNT(val); 930 931 DPRINTFN(sc, 10, "data frame sent successfully after " 932 "%d retries\n", retrycnt); 933 if (data->rix != IEEE80211_FIXED_RATE_NONE) 934 ieee80211_amrr_tx_complete(&rn->amrr, 935 IEEE80211_AMRR_SUCCESS, retrycnt); 936 ifp->if_opackets++; 937 break; 938 939 case RT2661_TX_RETRY_FAIL: 940 retrycnt = RT2661_TX_RETRYCNT(val); 941 942 DPRINTFN(sc, 9, "%s\n", 943 "sending data frame failed (too much retries)"); 944 if (data->rix != IEEE80211_FIXED_RATE_NONE) 945 ieee80211_amrr_tx_complete(&rn->amrr, 946 IEEE80211_AMRR_FAILURE, retrycnt); 947 ifp->if_oerrors++; 948 break; 949 950 default: 951 /* other failure */ 952 device_printf(sc->sc_dev, 953 "sending data frame failed 0x%08x\n", val); 954 ifp->if_oerrors++; 955 } 956 957 DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat); 958 959 txq->queued--; 960 if (++txq->stat >= txq->count) /* faster than % count */ 961 txq->stat = 0; 962 963 if (m->m_flags & M_TXCB) 964 ieee80211_process_callback(ni, m, 965 RT2661_TX_RESULT(val) != RT2661_TX_SUCCESS); 966 m_freem(m); 967 ieee80211_free_node(ni); 968 } 969 970 sc->sc_tx_timer = 0; 971 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 972 973 rt2661_start_locked(ifp); 974} 975 976static void 977rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 978{ 979 struct rt2661_tx_desc *desc; 980 struct rt2661_tx_data *data; 981 982 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD); 983 984 for (;;) { 985 desc = &txq->desc[txq->next]; 986 data = &txq->data[txq->next]; 987 988 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 989 !(le32toh(desc->flags) & RT2661_TX_VALID)) 990 break; 991 992 bus_dmamap_sync(txq->data_dmat, data->map, 993 BUS_DMASYNC_POSTWRITE); 994 bus_dmamap_unload(txq->data_dmat, data->map); 995 996 /* descriptor is no longer valid */ 997 desc->flags &= ~htole32(RT2661_TX_VALID); 998 999 DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next); 1000 1001 if (++txq->next >= txq->count) /* faster than % count */ 1002 txq->next = 0; 1003 } 1004 1005 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1006} 1007 1008static void 1009rt2661_rx_intr(struct rt2661_softc *sc) 1010{ 1011 struct ifnet *ifp = sc->sc_ifp; 1012 struct ieee80211com *ic = ifp->if_l2com; 1013 struct rt2661_rx_desc *desc; 1014 struct rt2661_rx_data *data; 1015 bus_addr_t physaddr; 1016 struct ieee80211_frame *wh; 1017 struct ieee80211_node *ni; 1018 struct mbuf *mnew, *m; 1019 int error; 1020 1021 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1022 BUS_DMASYNC_POSTREAD); 1023 1024 for (;;) { 1025 int8_t rssi, nf; 1026 1027 desc = &sc->rxq.desc[sc->rxq.cur]; 1028 data = &sc->rxq.data[sc->rxq.cur]; 1029 1030 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1031 break; 1032 1033 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1034 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1035 /* 1036 * This should not happen since we did not request 1037 * to receive those frames when we filled TXRX_CSR0. 1038 */ 1039 DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n", 1040 le32toh(desc->flags)); 1041 ifp->if_ierrors++; 1042 goto skip; 1043 } 1044 1045 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1046 ifp->if_ierrors++; 1047 goto skip; 1048 } 1049 1050 /* 1051 * Try to allocate a new mbuf for this ring element and load it 1052 * before processing the current mbuf. If the ring element 1053 * cannot be loaded, drop the received packet and reuse the old 1054 * mbuf. In the unlikely case that the old mbuf can't be 1055 * reloaded either, explicitly panic. 1056 */ 1057 mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1058 if (mnew == NULL) { 1059 ifp->if_ierrors++; 1060 goto skip; 1061 } 1062 1063 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1064 BUS_DMASYNC_POSTREAD); 1065 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1066 1067 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1068 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr, 1069 &physaddr, 0); 1070 if (error != 0) { 1071 m_freem(mnew); 1072 1073 /* try to reload the old mbuf */ 1074 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1075 mtod(data->m, void *), MCLBYTES, 1076 rt2661_dma_map_addr, &physaddr, 0); 1077 if (error != 0) { 1078 /* very unlikely that it will fail... */ 1079 panic("%s: could not load old rx mbuf", 1080 device_get_name(sc->sc_dev)); 1081 } 1082 ifp->if_ierrors++; 1083 goto skip; 1084 } 1085 1086 /* 1087 * New mbuf successfully loaded, update Rx ring and continue 1088 * processing. 1089 */ 1090 m = data->m; 1091 data->m = mnew; 1092 desc->physaddr = htole32(physaddr); 1093 1094 /* finalize mbuf */ 1095 m->m_pkthdr.rcvif = ifp; 1096 m->m_pkthdr.len = m->m_len = 1097 (le32toh(desc->flags) >> 16) & 0xfff; 1098 1099 rssi = rt2661_get_rssi(sc, desc->rssi); 1100 /* Error happened during RSSI conversion. */ 1101 if (rssi < 0) 1102 rssi = -30; /* XXX ignored by net80211 */ 1103 nf = RT2661_NOISE_FLOOR; 1104 1105 if (ieee80211_radiotap_active(ic)) { 1106 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1107 uint32_t tsf_lo, tsf_hi; 1108 1109 /* get timestamp (low and high 32 bits) */ 1110 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1111 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1112 1113 tap->wr_tsf = 1114 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1115 tap->wr_flags = 0; 1116 tap->wr_rate = ieee80211_plcp2rate(desc->rate, 1117 (desc->flags & htole32(RT2661_RX_OFDM)) ? 1118 IEEE80211_T_OFDM : IEEE80211_T_CCK); 1119 tap->wr_antsignal = nf + rssi; 1120 tap->wr_antnoise = nf; 1121 } 1122 sc->sc_flags |= RAL_INPUT_RUNNING; 1123 RAL_UNLOCK(sc); 1124 wh = mtod(m, struct ieee80211_frame *); 1125 1126 /* send the frame to the 802.11 layer */ 1127 ni = ieee80211_find_rxnode(ic, 1128 (struct ieee80211_frame_min *)wh); 1129 if (ni != NULL) { 1130 (void) ieee80211_input(ni, m, rssi, nf); 1131 ieee80211_free_node(ni); 1132 } else 1133 (void) ieee80211_input_all(ic, m, rssi, nf); 1134 1135 RAL_LOCK(sc); 1136 sc->sc_flags &= ~RAL_INPUT_RUNNING; 1137 1138skip: desc->flags |= htole32(RT2661_RX_BUSY); 1139 1140 DPRINTFN(sc, 15, "rx intr idx=%u\n", sc->rxq.cur); 1141 1142 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1143 } 1144 1145 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1146 BUS_DMASYNC_PREWRITE); 1147} 1148 1149/* ARGSUSED */ 1150static void 1151rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1152{ 1153 /* do nothing */ 1154} 1155 1156static void 1157rt2661_mcu_wakeup(struct rt2661_softc *sc) 1158{ 1159 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1160 1161 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1162 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1163 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1164 1165 /* send wakeup command to MCU */ 1166 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1167} 1168 1169static void 1170rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1171{ 1172 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1173 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1174} 1175 1176void 1177rt2661_intr(void *arg) 1178{ 1179 struct rt2661_softc *sc = arg; 1180 struct ifnet *ifp = sc->sc_ifp; 1181 uint32_t r1, r2; 1182 1183 RAL_LOCK(sc); 1184 1185 /* disable MAC and MCU interrupts */ 1186 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1187 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1188 1189 /* don't re-enable interrupts if we're shutting down */ 1190 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1191 RAL_UNLOCK(sc); 1192 return; 1193 } 1194 1195 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1196 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1197 1198 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1199 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1200 1201 if (r1 & RT2661_MGT_DONE) 1202 rt2661_tx_dma_intr(sc, &sc->mgtq); 1203 1204 if (r1 & RT2661_RX_DONE) 1205 rt2661_rx_intr(sc); 1206 1207 if (r1 & RT2661_TX0_DMA_DONE) 1208 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1209 1210 if (r1 & RT2661_TX1_DMA_DONE) 1211 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1212 1213 if (r1 & RT2661_TX2_DMA_DONE) 1214 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1215 1216 if (r1 & RT2661_TX3_DMA_DONE) 1217 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1218 1219 if (r1 & RT2661_TX_DONE) 1220 rt2661_tx_intr(sc); 1221 1222 if (r2 & RT2661_MCU_CMD_DONE) 1223 rt2661_mcu_cmd_intr(sc); 1224 1225 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1226 rt2661_mcu_beacon_expire(sc); 1227 1228 if (r2 & RT2661_MCU_WAKEUP) 1229 rt2661_mcu_wakeup(sc); 1230 1231 /* re-enable MAC and MCU interrupts */ 1232 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1233 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1234 1235 RAL_UNLOCK(sc); 1236} 1237 1238static uint8_t 1239rt2661_plcp_signal(int rate) 1240{ 1241 switch (rate) { 1242 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1243 case 12: return 0xb; 1244 case 18: return 0xf; 1245 case 24: return 0xa; 1246 case 36: return 0xe; 1247 case 48: return 0x9; 1248 case 72: return 0xd; 1249 case 96: return 0x8; 1250 case 108: return 0xc; 1251 1252 /* CCK rates (NB: not IEEE std, device-specific) */ 1253 case 2: return 0x0; 1254 case 4: return 0x1; 1255 case 11: return 0x2; 1256 case 22: return 0x3; 1257 } 1258 return 0xff; /* XXX unsupported/unknown rate */ 1259} 1260 1261static void 1262rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1263 uint32_t flags, uint16_t xflags, int len, int rate, 1264 const bus_dma_segment_t *segs, int nsegs, int ac) 1265{ 1266 struct ifnet *ifp = sc->sc_ifp; 1267 struct ieee80211com *ic = ifp->if_l2com; 1268 uint16_t plcp_length; 1269 int i, remainder; 1270 1271 desc->flags = htole32(flags); 1272 desc->flags |= htole32(len << 16); 1273 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1274 1275 desc->xflags = htole16(xflags); 1276 desc->xflags |= htole16(nsegs << 13); 1277 1278 desc->wme = htole16( 1279 RT2661_QID(ac) | 1280 RT2661_AIFSN(2) | 1281 RT2661_LOGCWMIN(4) | 1282 RT2661_LOGCWMAX(10)); 1283 1284 /* 1285 * Remember in which queue this frame was sent. This field is driver 1286 * private data only. It will be made available by the NIC in STA_CSR4 1287 * on Tx interrupts. 1288 */ 1289 desc->qid = ac; 1290 1291 /* setup PLCP fields */ 1292 desc->plcp_signal = rt2661_plcp_signal(rate); 1293 desc->plcp_service = 4; 1294 1295 len += IEEE80211_CRC_LEN; 1296 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { 1297 desc->flags |= htole32(RT2661_TX_OFDM); 1298 1299 plcp_length = len & 0xfff; 1300 desc->plcp_length_hi = plcp_length >> 6; 1301 desc->plcp_length_lo = plcp_length & 0x3f; 1302 } else { 1303 plcp_length = (16 * len + rate - 1) / rate; 1304 if (rate == 22) { 1305 remainder = (16 * len) % 22; 1306 if (remainder != 0 && remainder < 7) 1307 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1308 } 1309 desc->plcp_length_hi = plcp_length >> 8; 1310 desc->plcp_length_lo = plcp_length & 0xff; 1311 1312 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1313 desc->plcp_signal |= 0x08; 1314 } 1315 1316 /* RT2x61 supports scatter with up to 5 segments */ 1317 for (i = 0; i < nsegs; i++) { 1318 desc->addr[i] = htole32(segs[i].ds_addr); 1319 desc->len [i] = htole16(segs[i].ds_len); 1320 } 1321} 1322 1323static int 1324rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1325 struct ieee80211_node *ni) 1326{ 1327 struct ieee80211vap *vap = ni->ni_vap; 1328 struct ieee80211com *ic = ni->ni_ic; 1329 struct rt2661_tx_desc *desc; 1330 struct rt2661_tx_data *data; 1331 struct ieee80211_frame *wh; 1332 struct ieee80211_key *k; 1333 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1334 uint16_t dur; 1335 uint32_t flags = 0; /* XXX HWSEQ */ 1336 int nsegs, rate, error; 1337 1338 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1339 data = &sc->mgtq.data[sc->mgtq.cur]; 1340 1341 rate = vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)].mgmtrate; 1342 1343 wh = mtod(m0, struct ieee80211_frame *); 1344 1345 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1346 k = ieee80211_crypto_encap(ni, m0); 1347 if (k == NULL) { 1348 m_freem(m0); 1349 return ENOBUFS; 1350 } 1351 } 1352 1353 error = bus_dmamap_load_mbuf_sg(sc->mgtq.data_dmat, data->map, m0, 1354 segs, &nsegs, 0); 1355 if (error != 0) { 1356 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1357 error); 1358 m_freem(m0); 1359 return error; 1360 } 1361 1362 if (ieee80211_radiotap_active_vap(vap)) { 1363 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1364 1365 tap->wt_flags = 0; 1366 tap->wt_rate = rate; 1367 1368 ieee80211_radiotap_tx(vap, m0); 1369 } 1370 1371 data->m = m0; 1372 data->ni = ni; 1373 /* management frames are not taken into account for amrr */ 1374 data->rix = IEEE80211_FIXED_RATE_NONE; 1375 1376 wh = mtod(m0, struct ieee80211_frame *); 1377 1378 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1379 flags |= RT2661_TX_NEED_ACK; 1380 1381 dur = ieee80211_ack_duration(ic->ic_rt, 1382 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1383 *(uint16_t *)wh->i_dur = htole16(dur); 1384 1385 /* tell hardware to add timestamp in probe responses */ 1386 if ((wh->i_fc[0] & 1387 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1388 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1389 flags |= RT2661_TX_TIMESTAMP; 1390 } 1391 1392 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1393 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT); 1394 1395 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1396 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map, 1397 BUS_DMASYNC_PREWRITE); 1398 1399 DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n", 1400 m0->m_pkthdr.len, sc->mgtq.cur, rate); 1401 1402 /* kick mgt */ 1403 sc->mgtq.queued++; 1404 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1405 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1406 1407 return 0; 1408} 1409 1410static int 1411rt2661_sendprot(struct rt2661_softc *sc, int ac, 1412 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1413{ 1414 struct ieee80211com *ic = ni->ni_ic; 1415 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1416 const struct ieee80211_frame *wh; 1417 struct rt2661_tx_desc *desc; 1418 struct rt2661_tx_data *data; 1419 struct mbuf *mprot; 1420 int protrate, ackrate, pktlen, flags, isshort, error; 1421 uint16_t dur; 1422 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1423 int nsegs; 1424 1425 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1426 ("protection %d", prot)); 1427 1428 wh = mtod(m, const struct ieee80211_frame *); 1429 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1430 1431 protrate = ieee80211_ctl_rate(ic->ic_rt, rate); 1432 ackrate = ieee80211_ack_rate(ic->ic_rt, rate); 1433 1434 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1435 dur = ieee80211_compute_duration(ic->ic_rt, pktlen, rate, isshort) 1436 + ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1437 flags = RT2661_TX_MORE_FRAG; 1438 if (prot == IEEE80211_PROT_RTSCTS) { 1439 /* NB: CTS is the same size as an ACK */ 1440 dur += ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1441 flags |= RT2661_TX_NEED_ACK; 1442 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1443 } else { 1444 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1445 } 1446 if (mprot == NULL) { 1447 /* XXX stat + msg */ 1448 return ENOBUFS; 1449 } 1450 1451 data = &txq->data[txq->cur]; 1452 desc = &txq->desc[txq->cur]; 1453 1454 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, mprot, segs, 1455 &nsegs, 0); 1456 if (error != 0) { 1457 device_printf(sc->sc_dev, 1458 "could not map mbuf (error %d)\n", error); 1459 m_freem(mprot); 1460 return error; 1461 } 1462 1463 data->m = mprot; 1464 data->ni = ieee80211_ref_node(ni); 1465 /* ctl frames are not taken into account for amrr */ 1466 data->rix = IEEE80211_FIXED_RATE_NONE; 1467 1468 rt2661_setup_tx_desc(sc, desc, flags, 0, mprot->m_pkthdr.len, 1469 protrate, segs, 1, ac); 1470 1471 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1472 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1473 1474 txq->queued++; 1475 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1476 1477 return 0; 1478} 1479 1480static int 1481rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1482 struct ieee80211_node *ni, int ac) 1483{ 1484 struct ieee80211vap *vap = ni->ni_vap; 1485 struct ifnet *ifp = sc->sc_ifp; 1486 struct ieee80211com *ic = ifp->if_l2com; 1487 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1488 struct rt2661_tx_desc *desc; 1489 struct rt2661_tx_data *data; 1490 struct ieee80211_frame *wh; 1491 const struct ieee80211_txparam *tp; 1492 struct ieee80211_key *k; 1493 const struct chanAccParams *cap; 1494 struct mbuf *mnew; 1495 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1496 uint16_t dur; 1497 uint32_t flags; 1498 int error, nsegs, rate, noack = 0; 1499 1500 wh = mtod(m0, struct ieee80211_frame *); 1501 1502 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1503 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1504 rate = tp->mcastrate; 1505 } else if (m0->m_flags & M_EAPOL) { 1506 rate = tp->mgmtrate; 1507 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1508 rate = tp->ucastrate; 1509 } else { 1510 (void) ieee80211_amrr_choose(ni, &RT2661_NODE(ni)->amrr); 1511 rate = ni->ni_txrate; 1512 } 1513 rate &= IEEE80211_RATE_VAL; 1514 1515 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 1516 cap = &ic->ic_wme.wme_chanParams; 1517 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 1518 } 1519 1520 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1521 k = ieee80211_crypto_encap(ni, m0); 1522 if (k == NULL) { 1523 m_freem(m0); 1524 return ENOBUFS; 1525 } 1526 1527 /* packet header may have moved, reset our local pointer */ 1528 wh = mtod(m0, struct ieee80211_frame *); 1529 } 1530 1531 flags = 0; 1532 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1533 int prot = IEEE80211_PROT_NONE; 1534 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1535 prot = IEEE80211_PROT_RTSCTS; 1536 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1537 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) 1538 prot = ic->ic_protmode; 1539 if (prot != IEEE80211_PROT_NONE) { 1540 error = rt2661_sendprot(sc, ac, m0, ni, prot, rate); 1541 if (error) { 1542 m_freem(m0); 1543 return error; 1544 } 1545 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1546 } 1547 } 1548 1549 data = &txq->data[txq->cur]; 1550 desc = &txq->desc[txq->cur]; 1551 1552 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs, 1553 &nsegs, 0); 1554 if (error != 0 && error != EFBIG) { 1555 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1556 error); 1557 m_freem(m0); 1558 return error; 1559 } 1560 if (error != 0) { 1561 mnew = m_defrag(m0, M_DONTWAIT); 1562 if (mnew == NULL) { 1563 device_printf(sc->sc_dev, 1564 "could not defragment mbuf\n"); 1565 m_freem(m0); 1566 return ENOBUFS; 1567 } 1568 m0 = mnew; 1569 1570 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, 1571 segs, &nsegs, 0); 1572 if (error != 0) { 1573 device_printf(sc->sc_dev, 1574 "could not map mbuf (error %d)\n", error); 1575 m_freem(m0); 1576 return error; 1577 } 1578 1579 /* packet header have moved, reset our local pointer */ 1580 wh = mtod(m0, struct ieee80211_frame *); 1581 } 1582 1583 if (ieee80211_radiotap_active_vap(vap)) { 1584 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1585 1586 tap->wt_flags = 0; 1587 tap->wt_rate = rate; 1588 1589 ieee80211_radiotap_tx(vap, m0); 1590 } 1591 1592 data->m = m0; 1593 data->ni = ni; 1594 1595 /* remember link conditions for rate adaptation algorithm */ 1596 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) { 1597 data->rix = ni->ni_txrate; 1598 /* XXX probably need last rssi value and not avg */ 1599 data->rssi = ic->ic_node_getrssi(ni); 1600 } else 1601 data->rix = IEEE80211_FIXED_RATE_NONE; 1602 1603 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1604 flags |= RT2661_TX_NEED_ACK; 1605 1606 dur = ieee80211_ack_duration(ic->ic_rt, 1607 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1608 *(uint16_t *)wh->i_dur = htole16(dur); 1609 } 1610 1611 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs, 1612 nsegs, ac); 1613 1614 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1615 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1616 1617 DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n", 1618 m0->m_pkthdr.len, txq->cur, rate); 1619 1620 /* kick Tx */ 1621 txq->queued++; 1622 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1623 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac); 1624 1625 return 0; 1626} 1627 1628static void 1629rt2661_start_locked(struct ifnet *ifp) 1630{ 1631 struct rt2661_softc *sc = ifp->if_softc; 1632 struct mbuf *m; 1633 struct ieee80211_node *ni; 1634 int ac; 1635 1636 RAL_LOCK_ASSERT(sc); 1637 1638 /* prevent management frames from being sent if we're not ready */ 1639 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING) || sc->sc_invalid) 1640 return; 1641 1642 for (;;) { 1643 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1644 if (m == NULL) 1645 break; 1646 1647 ac = M_WME_GETAC(m); 1648 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) { 1649 /* there is no place left in this ring */ 1650 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1651 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1652 break; 1653 } 1654 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1655 if (rt2661_tx_data(sc, m, ni, ac) != 0) { 1656 ieee80211_free_node(ni); 1657 ifp->if_oerrors++; 1658 break; 1659 } 1660 1661 sc->sc_tx_timer = 5; 1662 } 1663} 1664 1665static void 1666rt2661_start(struct ifnet *ifp) 1667{ 1668 struct rt2661_softc *sc = ifp->if_softc; 1669 1670 RAL_LOCK(sc); 1671 rt2661_start_locked(ifp); 1672 RAL_UNLOCK(sc); 1673} 1674 1675static int 1676rt2661_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1677 const struct ieee80211_bpf_params *params) 1678{ 1679 struct ieee80211com *ic = ni->ni_ic; 1680 struct ifnet *ifp = ic->ic_ifp; 1681 struct rt2661_softc *sc = ifp->if_softc; 1682 1683 RAL_LOCK(sc); 1684 1685 /* prevent management frames from being sent if we're not ready */ 1686 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1687 RAL_UNLOCK(sc); 1688 m_freem(m); 1689 ieee80211_free_node(ni); 1690 return ENETDOWN; 1691 } 1692 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1693 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1694 RAL_UNLOCK(sc); 1695 m_freem(m); 1696 ieee80211_free_node(ni); 1697 return ENOBUFS; /* XXX */ 1698 } 1699 1700 ifp->if_opackets++; 1701 1702 /* 1703 * Legacy path; interpret frame contents to decide 1704 * precisely how to send the frame. 1705 * XXX raw path 1706 */ 1707 if (rt2661_tx_mgt(sc, m, ni) != 0) 1708 goto bad; 1709 sc->sc_tx_timer = 5; 1710 1711 RAL_UNLOCK(sc); 1712 1713 return 0; 1714bad: 1715 ifp->if_oerrors++; 1716 ieee80211_free_node(ni); 1717 RAL_UNLOCK(sc); 1718 return EIO; /* XXX */ 1719} 1720 1721static void 1722rt2661_watchdog(void *arg) 1723{ 1724 struct rt2661_softc *sc = (struct rt2661_softc *)arg; 1725 struct ifnet *ifp = sc->sc_ifp; 1726 1727 RAL_LOCK_ASSERT(sc); 1728 1729 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running")); 1730 1731 if (sc->sc_invalid) /* card ejected */ 1732 return; 1733 1734 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1735 if_printf(ifp, "device timeout\n"); 1736 rt2661_init_locked(sc); 1737 ifp->if_oerrors++; 1738 /* NB: callout is reset in rt2661_init() */ 1739 return; 1740 } 1741 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 1742} 1743 1744static int 1745rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1746{ 1747 struct rt2661_softc *sc = ifp->if_softc; 1748 struct ieee80211com *ic = ifp->if_l2com; 1749 struct ifreq *ifr = (struct ifreq *) data; 1750 int error = 0, startall = 0; 1751 1752 switch (cmd) { 1753 case SIOCSIFFLAGS: 1754 RAL_LOCK(sc); 1755 if (ifp->if_flags & IFF_UP) { 1756 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1757 rt2661_init_locked(sc); 1758 startall = 1; 1759 } else 1760 rt2661_update_promisc(ifp); 1761 } else { 1762 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1763 rt2661_stop_locked(sc); 1764 } 1765 RAL_UNLOCK(sc); 1766 if (startall) 1767 ieee80211_start_all(ic); 1768 break; 1769 case SIOCGIFMEDIA: 1770 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1771 break; 1772 case SIOCGIFADDR: 1773 error = ether_ioctl(ifp, cmd, data); 1774 break; 1775 default: 1776 error = EINVAL; 1777 break; 1778 } 1779 return error; 1780} 1781 1782static void 1783rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1784{ 1785 uint32_t tmp; 1786 int ntries; 1787 1788 for (ntries = 0; ntries < 100; ntries++) { 1789 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1790 break; 1791 DELAY(1); 1792 } 1793 if (ntries == 100) { 1794 device_printf(sc->sc_dev, "could not write to BBP\n"); 1795 return; 1796 } 1797 1798 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 1799 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 1800 1801 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val); 1802} 1803 1804static uint8_t 1805rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 1806{ 1807 uint32_t val; 1808 int ntries; 1809 1810 for (ntries = 0; ntries < 100; ntries++) { 1811 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1812 break; 1813 DELAY(1); 1814 } 1815 if (ntries == 100) { 1816 device_printf(sc->sc_dev, "could not read from BBP\n"); 1817 return 0; 1818 } 1819 1820 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 1821 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 1822 1823 for (ntries = 0; ntries < 100; ntries++) { 1824 val = RAL_READ(sc, RT2661_PHY_CSR3); 1825 if (!(val & RT2661_BBP_BUSY)) 1826 return val & 0xff; 1827 DELAY(1); 1828 } 1829 1830 device_printf(sc->sc_dev, "could not read from BBP\n"); 1831 return 0; 1832} 1833 1834static void 1835rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 1836{ 1837 uint32_t tmp; 1838 int ntries; 1839 1840 for (ntries = 0; ntries < 100; ntries++) { 1841 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 1842 break; 1843 DELAY(1); 1844 } 1845 if (ntries == 100) { 1846 device_printf(sc->sc_dev, "could not write to RF\n"); 1847 return; 1848 } 1849 1850 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 1851 (reg & 3); 1852 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 1853 1854 /* remember last written value in sc */ 1855 sc->rf_regs[reg] = val; 1856 1857 DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff); 1858} 1859 1860static int 1861rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 1862{ 1863 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 1864 return EIO; /* there is already a command pending */ 1865 1866 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 1867 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 1868 1869 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 1870 1871 return 0; 1872} 1873 1874static void 1875rt2661_select_antenna(struct rt2661_softc *sc) 1876{ 1877 uint8_t bbp4, bbp77; 1878 uint32_t tmp; 1879 1880 bbp4 = rt2661_bbp_read(sc, 4); 1881 bbp77 = rt2661_bbp_read(sc, 77); 1882 1883 /* TBD */ 1884 1885 /* make sure Rx is disabled before switching antenna */ 1886 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 1887 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 1888 1889 rt2661_bbp_write(sc, 4, bbp4); 1890 rt2661_bbp_write(sc, 77, bbp77); 1891 1892 /* restore Rx filter */ 1893 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 1894} 1895 1896/* 1897 * Enable multi-rate retries for frames sent at OFDM rates. 1898 * In 802.11b/g mode, allow fallback to CCK rates. 1899 */ 1900static void 1901rt2661_enable_mrr(struct rt2661_softc *sc) 1902{ 1903 struct ifnet *ifp = sc->sc_ifp; 1904 struct ieee80211com *ic = ifp->if_l2com; 1905 uint32_t tmp; 1906 1907 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1908 1909 tmp &= ~RT2661_MRR_CCK_FALLBACK; 1910 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan)) 1911 tmp |= RT2661_MRR_CCK_FALLBACK; 1912 tmp |= RT2661_MRR_ENABLED; 1913 1914 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1915} 1916 1917static void 1918rt2661_set_txpreamble(struct rt2661_softc *sc) 1919{ 1920 struct ifnet *ifp = sc->sc_ifp; 1921 struct ieee80211com *ic = ifp->if_l2com; 1922 uint32_t tmp; 1923 1924 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1925 1926 tmp &= ~RT2661_SHORT_PREAMBLE; 1927 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1928 tmp |= RT2661_SHORT_PREAMBLE; 1929 1930 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1931} 1932 1933static void 1934rt2661_set_basicrates(struct rt2661_softc *sc, 1935 const struct ieee80211_rateset *rs) 1936{ 1937#define RV(r) ((r) & IEEE80211_RATE_VAL) 1938 struct ifnet *ifp = sc->sc_ifp; 1939 struct ieee80211com *ic = ifp->if_l2com; 1940 uint32_t mask = 0; 1941 uint8_t rate; 1942 int i, j; 1943 1944 for (i = 0; i < rs->rs_nrates; i++) { 1945 rate = rs->rs_rates[i]; 1946 1947 if (!(rate & IEEE80211_RATE_BASIC)) 1948 continue; 1949 1950 /* 1951 * Find h/w rate index. We know it exists because the rate 1952 * set has already been negotiated. 1953 */ 1954 for (j = 0; ic->ic_sup_rates[IEEE80211_MODE_11G].rs_rates[j] != RV(rate); j++); 1955 1956 mask |= 1 << j; 1957 } 1958 1959 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 1960 1961 DPRINTF(sc, "Setting basic rate mask to 0x%x\n", mask); 1962#undef RV 1963} 1964 1965/* 1966 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 1967 * driver. 1968 */ 1969static void 1970rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 1971{ 1972 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 1973 uint32_t tmp; 1974 1975 /* update all BBP registers that depend on the band */ 1976 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 1977 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 1978 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1979 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 1980 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 1981 } 1982 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1983 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1984 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 1985 } 1986 1987 rt2661_bbp_write(sc, 17, bbp17); 1988 rt2661_bbp_write(sc, 96, bbp96); 1989 rt2661_bbp_write(sc, 104, bbp104); 1990 1991 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1992 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1993 rt2661_bbp_write(sc, 75, 0x80); 1994 rt2661_bbp_write(sc, 86, 0x80); 1995 rt2661_bbp_write(sc, 88, 0x80); 1996 } 1997 1998 rt2661_bbp_write(sc, 35, bbp35); 1999 rt2661_bbp_write(sc, 97, bbp97); 2000 rt2661_bbp_write(sc, 98, bbp98); 2001 2002 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2003 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2004 if (IEEE80211_IS_CHAN_2GHZ(c)) 2005 tmp |= RT2661_PA_PE_2GHZ; 2006 else 2007 tmp |= RT2661_PA_PE_5GHZ; 2008 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2009} 2010 2011static void 2012rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2013{ 2014 struct ifnet *ifp = sc->sc_ifp; 2015 struct ieee80211com *ic = ifp->if_l2com; 2016 const struct rfprog *rfprog; 2017 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2018 int8_t power; 2019 u_int i, chan; 2020 2021 chan = ieee80211_chan2ieee(ic, c); 2022 KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan)); 2023 2024 /* select the appropriate RF settings based on what EEPROM says */ 2025 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2026 2027 /* find the settings for this channel (we know it exists) */ 2028 for (i = 0; rfprog[i].chan != chan; i++); 2029 2030 power = sc->txpow[i]; 2031 if (power < 0) { 2032 bbp94 += power; 2033 power = 0; 2034 } else if (power > 31) { 2035 bbp94 += power - 31; 2036 power = 31; 2037 } 2038 2039 /* 2040 * If we are switching from the 2GHz band to the 5GHz band or 2041 * vice-versa, BBP registers need to be reprogrammed. 2042 */ 2043 if (c->ic_flags != sc->sc_curchan->ic_flags) { 2044 rt2661_select_band(sc, c); 2045 rt2661_select_antenna(sc); 2046 } 2047 sc->sc_curchan = c; 2048 2049 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2050 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2051 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2052 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2053 2054 DELAY(200); 2055 2056 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2057 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2058 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2059 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2060 2061 DELAY(200); 2062 2063 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2064 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2065 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2066 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2067 2068 /* enable smart mode for MIMO-capable RFs */ 2069 bbp3 = rt2661_bbp_read(sc, 3); 2070 2071 bbp3 &= ~RT2661_SMART_MODE; 2072 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2073 bbp3 |= RT2661_SMART_MODE; 2074 2075 rt2661_bbp_write(sc, 3, bbp3); 2076 2077 if (bbp94 != RT2661_BBPR94_DEFAULT) 2078 rt2661_bbp_write(sc, 94, bbp94); 2079 2080 /* 5GHz radio needs a 1ms delay here */ 2081 if (IEEE80211_IS_CHAN_5GHZ(c)) 2082 DELAY(1000); 2083} 2084 2085static void 2086rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2087{ 2088 uint32_t tmp; 2089 2090 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2091 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2092 2093 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2094 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2095} 2096 2097static void 2098rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2099{ 2100 uint32_t tmp; 2101 2102 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2103 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2104 2105 tmp = addr[4] | addr[5] << 8; 2106 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2107} 2108 2109static void 2110rt2661_update_promisc(struct ifnet *ifp) 2111{ 2112 struct rt2661_softc *sc = ifp->if_softc; 2113 uint32_t tmp; 2114 2115 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2116 2117 tmp &= ~RT2661_DROP_NOT_TO_ME; 2118 if (!(ifp->if_flags & IFF_PROMISC)) 2119 tmp |= RT2661_DROP_NOT_TO_ME; 2120 2121 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2122 2123 DPRINTF(sc, "%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2124 "entering" : "leaving"); 2125} 2126 2127/* 2128 * Update QoS (802.11e) settings for each h/w Tx ring. 2129 */ 2130static int 2131rt2661_wme_update(struct ieee80211com *ic) 2132{ 2133 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2134 const struct wmeParams *wmep; 2135 2136 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2137 2138 /* XXX: not sure about shifts. */ 2139 /* XXX: the reference driver plays with AC_VI settings too. */ 2140 2141 /* update TxOp */ 2142 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2143 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2144 wmep[WME_AC_BK].wmep_txopLimit); 2145 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2146 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2147 wmep[WME_AC_VO].wmep_txopLimit); 2148 2149 /* update CWmin */ 2150 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2151 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2152 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2153 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2154 wmep[WME_AC_VO].wmep_logcwmin); 2155 2156 /* update CWmax */ 2157 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2158 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2159 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2160 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2161 wmep[WME_AC_VO].wmep_logcwmax); 2162 2163 /* update Aifsn */ 2164 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2165 wmep[WME_AC_BE].wmep_aifsn << 12 | 2166 wmep[WME_AC_BK].wmep_aifsn << 8 | 2167 wmep[WME_AC_VI].wmep_aifsn << 4 | 2168 wmep[WME_AC_VO].wmep_aifsn); 2169 2170 return 0; 2171} 2172 2173static void 2174rt2661_update_slot(struct ifnet *ifp) 2175{ 2176 struct rt2661_softc *sc = ifp->if_softc; 2177 struct ieee80211com *ic = ifp->if_l2com; 2178 uint8_t slottime; 2179 uint32_t tmp; 2180 2181 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2182 2183 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2184 tmp = (tmp & ~0xff) | slottime; 2185 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2186} 2187 2188static const char * 2189rt2661_get_rf(int rev) 2190{ 2191 switch (rev) { 2192 case RT2661_RF_5225: return "RT5225"; 2193 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2194 case RT2661_RF_2527: return "RT2527"; 2195 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2196 default: return "unknown"; 2197 } 2198} 2199 2200static void 2201rt2661_read_eeprom(struct rt2661_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 2202{ 2203 uint16_t val; 2204 int i; 2205 2206 /* read MAC address */ 2207 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2208 macaddr[0] = val & 0xff; 2209 macaddr[1] = val >> 8; 2210 2211 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2212 macaddr[2] = val & 0xff; 2213 macaddr[3] = val >> 8; 2214 2215 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2216 macaddr[4] = val & 0xff; 2217 macaddr[5] = val >> 8; 2218 2219 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2220 /* XXX: test if different from 0xffff? */ 2221 sc->rf_rev = (val >> 11) & 0x1f; 2222 sc->hw_radio = (val >> 10) & 0x1; 2223 sc->rx_ant = (val >> 4) & 0x3; 2224 sc->tx_ant = (val >> 2) & 0x3; 2225 sc->nb_ant = val & 0x3; 2226 2227 DPRINTF(sc, "RF revision=%d\n", sc->rf_rev); 2228 2229 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2230 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2231 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2232 2233 DPRINTF(sc, "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2234 sc->ext_2ghz_lna, sc->ext_5ghz_lna); 2235 2236 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2237 if ((val & 0xff) != 0xff) 2238 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2239 2240 /* Only [-10, 10] is valid */ 2241 if (sc->rssi_2ghz_corr < -10 || sc->rssi_2ghz_corr > 10) 2242 sc->rssi_2ghz_corr = 0; 2243 2244 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2245 if ((val & 0xff) != 0xff) 2246 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2247 2248 /* Only [-10, 10] is valid */ 2249 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10) 2250 sc->rssi_5ghz_corr = 0; 2251 2252 /* adjust RSSI correction for external low-noise amplifier */ 2253 if (sc->ext_2ghz_lna) 2254 sc->rssi_2ghz_corr -= 14; 2255 if (sc->ext_5ghz_lna) 2256 sc->rssi_5ghz_corr -= 14; 2257 2258 DPRINTF(sc, "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2259 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr); 2260 2261 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2262 if ((val >> 8) != 0xff) 2263 sc->rfprog = (val >> 8) & 0x3; 2264 if ((val & 0xff) != 0xff) 2265 sc->rffreq = val & 0xff; 2266 2267 DPRINTF(sc, "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq); 2268 2269 /* read Tx power for all a/b/g channels */ 2270 for (i = 0; i < 19; i++) { 2271 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2272 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2273 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2274 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]); 2275 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2276 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2277 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]); 2278 } 2279 2280 /* read vendor-specific BBP values */ 2281 for (i = 0; i < 16; i++) { 2282 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2283 if (val == 0 || val == 0xffff) 2284 continue; /* skip invalid entries */ 2285 sc->bbp_prom[i].reg = val >> 8; 2286 sc->bbp_prom[i].val = val & 0xff; 2287 DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2288 sc->bbp_prom[i].val); 2289 } 2290} 2291 2292static int 2293rt2661_bbp_init(struct rt2661_softc *sc) 2294{ 2295#define N(a) (sizeof (a) / sizeof ((a)[0])) 2296 int i, ntries; 2297 uint8_t val; 2298 2299 /* wait for BBP to be ready */ 2300 for (ntries = 0; ntries < 100; ntries++) { 2301 val = rt2661_bbp_read(sc, 0); 2302 if (val != 0 && val != 0xff) 2303 break; 2304 DELAY(100); 2305 } 2306 if (ntries == 100) { 2307 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2308 return EIO; 2309 } 2310 2311 /* initialize BBP registers to default values */ 2312 for (i = 0; i < N(rt2661_def_bbp); i++) { 2313 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2314 rt2661_def_bbp[i].val); 2315 } 2316 2317 /* write vendor-specific BBP values (from EEPROM) */ 2318 for (i = 0; i < 16; i++) { 2319 if (sc->bbp_prom[i].reg == 0) 2320 continue; 2321 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2322 } 2323 2324 return 0; 2325#undef N 2326} 2327 2328static void 2329rt2661_init_locked(struct rt2661_softc *sc) 2330{ 2331#define N(a) (sizeof (a) / sizeof ((a)[0])) 2332 struct ifnet *ifp = sc->sc_ifp; 2333 struct ieee80211com *ic = ifp->if_l2com; 2334 uint32_t tmp, sta[3]; 2335 int i, error, ntries; 2336 2337 RAL_LOCK_ASSERT(sc); 2338 2339 if ((sc->sc_flags & RAL_FW_LOADED) == 0) { 2340 error = rt2661_load_microcode(sc); 2341 if (error != 0) { 2342 if_printf(ifp, 2343 "%s: could not load 8051 microcode, error %d\n", 2344 __func__, error); 2345 return; 2346 } 2347 sc->sc_flags |= RAL_FW_LOADED; 2348 } 2349 2350 rt2661_stop_locked(sc); 2351 2352 /* initialize Tx rings */ 2353 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2354 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2355 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2356 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2357 2358 /* initialize Mgt ring */ 2359 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2360 2361 /* initialize Rx ring */ 2362 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2363 2364 /* initialize Tx rings sizes */ 2365 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2366 RT2661_TX_RING_COUNT << 24 | 2367 RT2661_TX_RING_COUNT << 16 | 2368 RT2661_TX_RING_COUNT << 8 | 2369 RT2661_TX_RING_COUNT); 2370 2371 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2372 RT2661_TX_DESC_WSIZE << 16 | 2373 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2374 RT2661_MGT_RING_COUNT); 2375 2376 /* initialize Rx rings */ 2377 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2378 RT2661_RX_DESC_BACK << 16 | 2379 RT2661_RX_DESC_WSIZE << 8 | 2380 RT2661_RX_RING_COUNT); 2381 2382 /* XXX: some magic here */ 2383 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2384 2385 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2386 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2387 2388 /* load base address of Rx ring */ 2389 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2390 2391 /* initialize MAC registers to default values */ 2392 for (i = 0; i < N(rt2661_def_mac); i++) 2393 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2394 2395 rt2661_set_macaddr(sc, IF_LLADDR(ifp)); 2396 2397 /* set host ready */ 2398 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2399 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2400 2401 /* wait for BBP/RF to wakeup */ 2402 for (ntries = 0; ntries < 1000; ntries++) { 2403 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2404 break; 2405 DELAY(1000); 2406 } 2407 if (ntries == 1000) { 2408 printf("timeout waiting for BBP/RF to wakeup\n"); 2409 rt2661_stop_locked(sc); 2410 return; 2411 } 2412 2413 if (rt2661_bbp_init(sc) != 0) { 2414 rt2661_stop_locked(sc); 2415 return; 2416 } 2417 2418 /* select default channel */ 2419 sc->sc_curchan = ic->ic_curchan; 2420 rt2661_select_band(sc, sc->sc_curchan); 2421 rt2661_select_antenna(sc); 2422 rt2661_set_chan(sc, sc->sc_curchan); 2423 2424 /* update Rx filter */ 2425 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2426 2427 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2428 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2429 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2430 RT2661_DROP_ACKCTS; 2431 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2432 tmp |= RT2661_DROP_TODS; 2433 if (!(ifp->if_flags & IFF_PROMISC)) 2434 tmp |= RT2661_DROP_NOT_TO_ME; 2435 } 2436 2437 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2438 2439 /* clear STA registers */ 2440 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta)); 2441 2442 /* initialize ASIC */ 2443 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2444 2445 /* clear any pending interrupt */ 2446 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2447 2448 /* enable interrupts */ 2449 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2450 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2451 2452 /* kick Rx */ 2453 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2454 2455 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2456 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2457 2458 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 2459#undef N 2460} 2461 2462static void 2463rt2661_init(void *priv) 2464{ 2465 struct rt2661_softc *sc = priv; 2466 struct ifnet *ifp = sc->sc_ifp; 2467 struct ieee80211com *ic = ifp->if_l2com; 2468 2469 RAL_LOCK(sc); 2470 rt2661_init_locked(sc); 2471 RAL_UNLOCK(sc); 2472 2473 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2474 ieee80211_start_all(ic); /* start all vap's */ 2475} 2476 2477void 2478rt2661_stop_locked(struct rt2661_softc *sc) 2479{ 2480 struct ifnet *ifp = sc->sc_ifp; 2481 uint32_t tmp; 2482 volatile int *flags = &sc->sc_flags; 2483 2484 while (*flags & RAL_INPUT_RUNNING) 2485 msleep(sc, &sc->sc_mtx, 0, "ralrunning", hz/10); 2486 2487 callout_stop(&sc->watchdog_ch); 2488 sc->sc_tx_timer = 0; 2489 2490 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2491 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2492 2493 /* abort Tx (for all 5 Tx rings) */ 2494 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2495 2496 /* disable Rx (value remains after reset!) */ 2497 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2498 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2499 2500 /* reset ASIC */ 2501 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2502 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2503 2504 /* disable interrupts */ 2505 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff); 2506 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2507 2508 /* clear any pending interrupt */ 2509 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2510 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2511 2512 /* reset Tx and Rx rings */ 2513 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2514 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2515 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2516 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2517 rt2661_reset_tx_ring(sc, &sc->mgtq); 2518 rt2661_reset_rx_ring(sc, &sc->rxq); 2519 } 2520} 2521 2522void 2523rt2661_stop(void *priv) 2524{ 2525 struct rt2661_softc *sc = priv; 2526 2527 RAL_LOCK(sc); 2528 rt2661_stop_locked(sc); 2529 RAL_UNLOCK(sc); 2530} 2531 2532static int 2533rt2661_load_microcode(struct rt2661_softc *sc) 2534{ 2535 struct ifnet *ifp = sc->sc_ifp; 2536 const struct firmware *fp; 2537 const char *imagename; 2538 int ntries, error; 2539 2540 RAL_LOCK_ASSERT(sc); 2541 2542 switch (sc->sc_id) { 2543 case 0x0301: imagename = "rt2561sfw"; break; 2544 case 0x0302: imagename = "rt2561fw"; break; 2545 case 0x0401: imagename = "rt2661fw"; break; 2546 default: 2547 if_printf(ifp, "%s: unexpected pci device id 0x%x, " 2548 "don't know how to retrieve firmware\n", 2549 __func__, sc->sc_id); 2550 return EINVAL; 2551 } 2552 RAL_UNLOCK(sc); 2553 fp = firmware_get(imagename); 2554 RAL_LOCK(sc); 2555 if (fp == NULL) { 2556 if_printf(ifp, "%s: unable to retrieve firmware image %s\n", 2557 __func__, imagename); 2558 return EINVAL; 2559 } 2560 2561 /* 2562 * Load 8051 microcode into NIC. 2563 */ 2564 /* reset 8051 */ 2565 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2566 2567 /* cancel any pending Host to MCU command */ 2568 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2569 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2570 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2571 2572 /* write 8051's microcode */ 2573 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2574 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, fp->data, fp->datasize); 2575 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2576 2577 /* kick 8051's ass */ 2578 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2579 2580 /* wait for 8051 to initialize */ 2581 for (ntries = 0; ntries < 500; ntries++) { 2582 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2583 break; 2584 DELAY(100); 2585 } 2586 if (ntries == 500) { 2587 if_printf(ifp, "%s: timeout waiting for MCU to initialize\n", 2588 __func__); 2589 error = EIO; 2590 } else 2591 error = 0; 2592 2593 firmware_put(fp, FIRMWARE_UNLOAD); 2594 return error; 2595} 2596 2597#ifdef notyet 2598/* 2599 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2600 * false CCA count. This function is called periodically (every seconds) when 2601 * in the RUN state. Values taken from the reference driver. 2602 */ 2603static void 2604rt2661_rx_tune(struct rt2661_softc *sc) 2605{ 2606 uint8_t bbp17; 2607 uint16_t cca; 2608 int lo, hi, dbm; 2609 2610 /* 2611 * Tuning range depends on operating band and on the presence of an 2612 * external low-noise amplifier. 2613 */ 2614 lo = 0x20; 2615 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2616 lo += 0x08; 2617 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2618 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2619 lo += 0x10; 2620 hi = lo + 0x20; 2621 2622 /* retrieve false CCA count since last call (clear on read) */ 2623 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2624 2625 if (dbm >= -35) { 2626 bbp17 = 0x60; 2627 } else if (dbm >= -58) { 2628 bbp17 = hi; 2629 } else if (dbm >= -66) { 2630 bbp17 = lo + 0x10; 2631 } else if (dbm >= -74) { 2632 bbp17 = lo + 0x08; 2633 } else { 2634 /* RSSI < -74dBm, tune using false CCA count */ 2635 2636 bbp17 = sc->bbp17; /* current value */ 2637 2638 hi -= 2 * (-74 - dbm); 2639 if (hi < lo) 2640 hi = lo; 2641 2642 if (bbp17 > hi) { 2643 bbp17 = hi; 2644 2645 } else if (cca > 512) { 2646 if (++bbp17 > hi) 2647 bbp17 = hi; 2648 } else if (cca < 100) { 2649 if (--bbp17 < lo) 2650 bbp17 = lo; 2651 } 2652 } 2653 2654 if (bbp17 != sc->bbp17) { 2655 rt2661_bbp_write(sc, 17, bbp17); 2656 sc->bbp17 = bbp17; 2657 } 2658} 2659 2660/* 2661 * Enter/Leave radar detection mode. 2662 * This is for 802.11h additional regulatory domains. 2663 */ 2664static void 2665rt2661_radar_start(struct rt2661_softc *sc) 2666{ 2667 uint32_t tmp; 2668 2669 /* disable Rx */ 2670 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2671 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2672 2673 rt2661_bbp_write(sc, 82, 0x20); 2674 rt2661_bbp_write(sc, 83, 0x00); 2675 rt2661_bbp_write(sc, 84, 0x40); 2676 2677 /* save current BBP registers values */ 2678 sc->bbp18 = rt2661_bbp_read(sc, 18); 2679 sc->bbp21 = rt2661_bbp_read(sc, 21); 2680 sc->bbp22 = rt2661_bbp_read(sc, 22); 2681 sc->bbp16 = rt2661_bbp_read(sc, 16); 2682 sc->bbp17 = rt2661_bbp_read(sc, 17); 2683 sc->bbp64 = rt2661_bbp_read(sc, 64); 2684 2685 rt2661_bbp_write(sc, 18, 0xff); 2686 rt2661_bbp_write(sc, 21, 0x3f); 2687 rt2661_bbp_write(sc, 22, 0x3f); 2688 rt2661_bbp_write(sc, 16, 0xbd); 2689 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2690 rt2661_bbp_write(sc, 64, 0x21); 2691 2692 /* restore Rx filter */ 2693 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2694} 2695 2696static int 2697rt2661_radar_stop(struct rt2661_softc *sc) 2698{ 2699 uint8_t bbp66; 2700 2701 /* read radar detection result */ 2702 bbp66 = rt2661_bbp_read(sc, 66); 2703 2704 /* restore BBP registers values */ 2705 rt2661_bbp_write(sc, 16, sc->bbp16); 2706 rt2661_bbp_write(sc, 17, sc->bbp17); 2707 rt2661_bbp_write(sc, 18, sc->bbp18); 2708 rt2661_bbp_write(sc, 21, sc->bbp21); 2709 rt2661_bbp_write(sc, 22, sc->bbp22); 2710 rt2661_bbp_write(sc, 64, sc->bbp64); 2711 2712 return bbp66 == 1; 2713} 2714#endif 2715 2716static int 2717rt2661_prepare_beacon(struct rt2661_softc *sc, struct ieee80211vap *vap) 2718{ 2719 struct ieee80211com *ic = vap->iv_ic; 2720 struct ieee80211_beacon_offsets bo; 2721 struct rt2661_tx_desc desc; 2722 struct mbuf *m0; 2723 int rate; 2724 2725 m0 = ieee80211_beacon_alloc(vap->iv_bss, &bo); 2726 if (m0 == NULL) { 2727 device_printf(sc->sc_dev, "could not allocate beacon frame\n"); 2728 return ENOBUFS; 2729 } 2730 2731 /* send beacons at the lowest available rate */ 2732 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 12 : 2; 2733 2734 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2735 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2736 2737 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2738 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2739 2740 /* copy beacon header and payload into NIC memory */ 2741 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2742 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2743 2744 m_freem(m0); 2745 2746 return 0; 2747} 2748 2749/* 2750 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2751 * and HostAP operating modes. 2752 */ 2753static void 2754rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2755{ 2756 struct ifnet *ifp = sc->sc_ifp; 2757 struct ieee80211com *ic = ifp->if_l2com; 2758 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2759 uint32_t tmp; 2760 2761 if (vap->iv_opmode != IEEE80211_M_STA) { 2762 /* 2763 * Change default 16ms TBTT adjustment to 8ms. 2764 * Must be done before enabling beacon generation. 2765 */ 2766 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2767 } 2768 2769 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2770 2771 /* set beacon interval (in 1/16ms unit) */ 2772 tmp |= vap->iv_bss->ni_intval * 16; 2773 2774 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2775 if (vap->iv_opmode == IEEE80211_M_STA) 2776 tmp |= RT2661_TSF_MODE(1); 2777 else 2778 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2779 2780 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2781} 2782 2783static void 2784rt2661_enable_tsf(struct rt2661_softc *sc) 2785{ 2786 RAL_WRITE(sc, RT2661_TXRX_CSR9, 2787 (RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000) 2788 | RT2661_TSF_TICKING | RT2661_TSF_MODE(2)); 2789} 2790 2791/* 2792 * Retrieve the "Received Signal Strength Indicator" from the raw values 2793 * contained in Rx descriptors. The computation depends on which band the 2794 * frame was received. Correction values taken from the reference driver. 2795 */ 2796static int 2797rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 2798{ 2799 int lna, agc, rssi; 2800 2801 lna = (raw >> 5) & 0x3; 2802 agc = raw & 0x1f; 2803 2804 if (lna == 0) { 2805 /* 2806 * No mapping available. 2807 * 2808 * NB: Since RSSI is relative to noise floor, -1 is 2809 * adequate for caller to know error happened. 2810 */ 2811 return -1; 2812 } 2813 2814 rssi = (2 * agc) - RT2661_NOISE_FLOOR; 2815 2816 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 2817 rssi += sc->rssi_2ghz_corr; 2818 2819 if (lna == 1) 2820 rssi -= 64; 2821 else if (lna == 2) 2822 rssi -= 74; 2823 else if (lna == 3) 2824 rssi -= 90; 2825 } else { 2826 rssi += sc->rssi_5ghz_corr; 2827 2828 if (lna == 1) 2829 rssi -= 64; 2830 else if (lna == 2) 2831 rssi -= 86; 2832 else if (lna == 3) 2833 rssi -= 100; 2834 } 2835 return rssi; 2836} 2837 2838static void 2839rt2661_scan_start(struct ieee80211com *ic) 2840{ 2841 struct ifnet *ifp = ic->ic_ifp; 2842 struct rt2661_softc *sc = ifp->if_softc; 2843 uint32_t tmp; 2844 2845 /* abort TSF synchronization */ 2846 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 2847 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0xffffff); 2848 rt2661_set_bssid(sc, ifp->if_broadcastaddr); 2849} 2850 2851static void 2852rt2661_scan_end(struct ieee80211com *ic) 2853{ 2854 struct ifnet *ifp = ic->ic_ifp; 2855 struct rt2661_softc *sc = ifp->if_softc; 2856 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2857 2858 rt2661_enable_tsf_sync(sc); 2859 /* XXX keep local copy */ 2860 rt2661_set_bssid(sc, vap->iv_bss->ni_bssid); 2861} 2862 2863static void 2864rt2661_set_channel(struct ieee80211com *ic) 2865{ 2866 struct ifnet *ifp = ic->ic_ifp; 2867 struct rt2661_softc *sc = ifp->if_softc; 2868 2869 RAL_LOCK(sc); 2870 rt2661_set_chan(sc, ic->ic_curchan); 2871 RAL_UNLOCK(sc); 2872 2873} 2874