1252206Sdavidcs/* 2252206Sdavidcs * Copyright (c) 2013-2014 Qlogic Corporation 3252206Sdavidcs * All rights reserved. 4252206Sdavidcs * 5252206Sdavidcs * Redistribution and use in source and binary forms, with or without 6252206Sdavidcs * modification, are permitted provided that the following conditions 7252206Sdavidcs * are met: 8252206Sdavidcs * 9252206Sdavidcs * 1. Redistributions of source code must retain the above copyright 10252206Sdavidcs * notice, this list of conditions and the following disclaimer. 11252206Sdavidcs * 2. Redistributions in binary form must reproduce the above copyright 12252206Sdavidcs * notice, this list of conditions and the following disclaimer in the 13252206Sdavidcs * documentation and/or other materials provided with the distribution. 14252206Sdavidcs * 15252206Sdavidcs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16252206Sdavidcs * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17252206Sdavidcs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18252206Sdavidcs * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19252206Sdavidcs * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20252206Sdavidcs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21252206Sdavidcs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22252206Sdavidcs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23252206Sdavidcs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24252206Sdavidcs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25252206Sdavidcs * POSSIBILITY OF SUCH DAMAGE. 26252206Sdavidcs * 27252206Sdavidcs * $FreeBSD: releng/11.0/sys/dev/qlxge/qls_dump.h 252206 2013-06-25 17:50:22Z davidcs $ 28252206Sdavidcs */ 29252206Sdavidcs 30252206Sdavidcs/* 31252206Sdavidcs * File: qls_dump.h 32252206Sdavidcs */ 33252206Sdavidcs 34252206Sdavidcs#ifndef _QLS_DUMP_H_ 35252206Sdavidcs#define _QLS_DUMP_H_ 36252206Sdavidcs 37252206Sdavidcs#define Q81_MPID_COOKIE 0x5555aaaa 38252206Sdavidcs 39252206Sdavidcstypedef struct qls_mpid_glbl_hdr 40252206Sdavidcs{ 41252206Sdavidcs uint32_t cookie; 42252206Sdavidcs uint8_t id[16]; 43252206Sdavidcs uint32_t time_lo; 44252206Sdavidcs uint32_t time_hi; 45252206Sdavidcs uint32_t img_size; 46252206Sdavidcs uint32_t hdr_size; 47252206Sdavidcs uint8_t info[220]; 48252206Sdavidcs} qls_mpid_glbl_hdr_t; 49252206Sdavidcs 50252206Sdavidcstypedef struct qls_mpid_seg_hdr 51252206Sdavidcs{ 52252206Sdavidcs uint32_t cookie; 53252206Sdavidcs uint32_t seg_num; 54252206Sdavidcs uint32_t seg_size; 55252206Sdavidcs uint32_t extra; 56252206Sdavidcs uint8_t desc[16]; 57252206Sdavidcs} qls_mpid_seg_hdr_t; 58252206Sdavidcs 59252206Sdavidcsenum 60252206Sdavidcs{ 61252206Sdavidcs Q81_MPI_CORE_REGS_ADDR = 0x00030000, 62252206Sdavidcs Q81_MPI_CORE_REGS_CNT = 127, 63252206Sdavidcs Q81_MPI_CORE_SH_REGS_CNT = 16, 64252206Sdavidcs Q81_TEST_REGS_ADDR = 0x00001000, 65252206Sdavidcs Q81_TEST_REGS_CNT = 23, 66252206Sdavidcs Q81_RMII_REGS_ADDR = 0x00001040, 67252206Sdavidcs Q81_RMII_REGS_CNT = 64, 68252206Sdavidcs Q81_FCMAC1_REGS_ADDR = 0x00001080, 69252206Sdavidcs Q81_FCMAC2_REGS_ADDR = 0x000010c0, 70252206Sdavidcs Q81_FCMAC_REGS_CNT = 64, 71252206Sdavidcs Q81_FC1_MBX_REGS_ADDR = 0x00001100, 72252206Sdavidcs Q81_FC2_MBX_REGS_ADDR = 0x00001240, 73252206Sdavidcs Q81_FC_MBX_REGS_CNT = 64, 74252206Sdavidcs Q81_IDE_REGS_ADDR = 0x00001140, 75252206Sdavidcs Q81_IDE_REGS_CNT = 64, 76252206Sdavidcs Q81_NIC1_MBX_REGS_ADDR = 0x00001180, 77252206Sdavidcs Q81_NIC2_MBX_REGS_ADDR = 0x00001280, 78252206Sdavidcs Q81_NIC_MBX_REGS_CNT = 64, 79252206Sdavidcs Q81_SMBUS_REGS_ADDR = 0x00001200, 80252206Sdavidcs Q81_SMBUS_REGS_CNT = 64, 81252206Sdavidcs Q81_I2C_REGS_ADDR = 0x00001fc0, 82252206Sdavidcs Q81_I2C_REGS_CNT = 64, 83252206Sdavidcs Q81_MEMC_REGS_ADDR = 0x00003000, 84252206Sdavidcs Q81_MEMC_REGS_CNT = 256, 85252206Sdavidcs Q81_PBUS_REGS_ADDR = 0x00007c00, 86252206Sdavidcs Q81_PBUS_REGS_CNT = 256, 87252206Sdavidcs Q81_MDE_REGS_ADDR = 0x00010000, 88252206Sdavidcs Q81_MDE_REGS_CNT = 6, 89252206Sdavidcs Q81_CODE_RAM_ADDR = 0x00020000, 90252206Sdavidcs Q81_CODE_RAM_CNT = 0x2000, 91252206Sdavidcs Q81_MEMC_RAM_ADDR = 0x00100000, 92252206Sdavidcs Q81_MEMC_RAM_CNT = 0x2000, 93252206Sdavidcs Q81_XGMAC_REGISTER_END = 0x740, 94252206Sdavidcs}; 95252206Sdavidcs 96252206Sdavidcs#define Q81_PROBE_DATA_LENGTH_WORDS ((64*2) + 1) 97252206Sdavidcs#define Q81_NUMBER_OF_PROBES 34 98252206Sdavidcs 99252206Sdavidcs#define Q81_PROBE_SIZE \ 100252206Sdavidcs (Q81_PROBE_DATA_LENGTH_WORDS * Q81_NUMBER_OF_PROBES) 101252206Sdavidcs 102252206Sdavidcs#define Q81_NUMBER_ROUTING_REG_ENTRIES 48 103252206Sdavidcs#define Q81_WORDS_PER_ROUTING_REG_ENTRY 4 104252206Sdavidcs 105252206Sdavidcs#define Q81_ROUT_REG_SIZE \ 106252206Sdavidcs (Q81_NUMBER_ROUTING_REG_ENTRIES * Q81_WORDS_PER_ROUTING_REG_ENTRY) 107252206Sdavidcs 108252206Sdavidcs#define Q81_MAC_PROTOCOL_REGISTER_WORDS ((512 * 3) + (32 * 2) + (4096 * 1) +\ 109252206Sdavidcs (4096 * 1) + (4 * 2) +\ 110252206Sdavidcs (8 * 2) + (16 * 1) +\ 111252206Sdavidcs (4 * 1) + (4 * 4) + (4 * 1)) 112252206Sdavidcs 113252206Sdavidcs#define Q81_WORDS_PER_MAC_PROT_ENTRY 2 114252206Sdavidcs#define Q81_MAC_REG_SIZE \ 115252206Sdavidcs (Q81_MAC_PROTOCOL_REGISTER_WORDS * Q81_WORDS_PER_MAC_PROT_ENTRY) 116252206Sdavidcs 117252206Sdavidcs#define Q81_MAX_SEMAPHORE_FUNCTIONS 5 118252206Sdavidcs 119252206Sdavidcs#define Q81_WQC_WORD_SIZE 6 120252206Sdavidcs#define Q81_NUMBER_OF_WQCS 128 121252206Sdavidcs#define Q81_WQ_SIZE (Q81_WQC_WORD_SIZE * Q81_NUMBER_OF_WQCS) 122252206Sdavidcs 123252206Sdavidcs#define Q81_CQC_WORD_SIZE 13 124252206Sdavidcs#define Q81_NUMBER_OF_CQCS 128 125252206Sdavidcs#define Q81_CQ_SIZE (Q81_CQC_WORD_SIZE * Q81_NUMBER_OF_CQCS) 126252206Sdavidcs 127252206Sdavidcsstruct qls_mpi_coredump { 128252206Sdavidcs qls_mpid_glbl_hdr_t mpi_global_header; 129252206Sdavidcs 130252206Sdavidcs qls_mpid_seg_hdr_t core_regs_seg_hdr; 131252206Sdavidcs uint32_t mpi_core_regs[Q81_MPI_CORE_REGS_CNT]; 132252206Sdavidcs uint32_t mpi_core_sh_regs[Q81_MPI_CORE_SH_REGS_CNT]; 133252206Sdavidcs 134252206Sdavidcs qls_mpid_seg_hdr_t test_logic_regs_seg_hdr; 135252206Sdavidcs uint32_t test_logic_regs[Q81_TEST_REGS_CNT]; 136252206Sdavidcs 137252206Sdavidcs qls_mpid_seg_hdr_t rmii_regs_seg_hdr; 138252206Sdavidcs uint32_t rmii_regs[Q81_RMII_REGS_CNT]; 139252206Sdavidcs 140252206Sdavidcs qls_mpid_seg_hdr_t fcmac1_regs_seg_hdr; 141252206Sdavidcs uint32_t fcmac1_regs[Q81_FCMAC_REGS_CNT]; 142252206Sdavidcs 143252206Sdavidcs qls_mpid_seg_hdr_t fcmac2_regs_seg_hdr; 144252206Sdavidcs uint32_t fcmac2_regs[Q81_FCMAC_REGS_CNT]; 145252206Sdavidcs 146252206Sdavidcs qls_mpid_seg_hdr_t fc1_mbx_regs_seg_hdr; 147252206Sdavidcs uint32_t fc1_mbx_regs[Q81_FC_MBX_REGS_CNT]; 148252206Sdavidcs 149252206Sdavidcs qls_mpid_seg_hdr_t ide_regs_seg_hdr; 150252206Sdavidcs uint32_t ide_regs[Q81_IDE_REGS_CNT]; 151252206Sdavidcs 152252206Sdavidcs qls_mpid_seg_hdr_t nic1_mbx_regs_seg_hdr; 153252206Sdavidcs uint32_t nic1_mbx_regs[Q81_NIC_MBX_REGS_CNT]; 154252206Sdavidcs 155252206Sdavidcs qls_mpid_seg_hdr_t smbus_regs_seg_hdr; 156252206Sdavidcs uint32_t smbus_regs[Q81_SMBUS_REGS_CNT]; 157252206Sdavidcs 158252206Sdavidcs qls_mpid_seg_hdr_t fc2_mbx_regs_seg_hdr; 159252206Sdavidcs uint32_t fc2_mbx_regs[Q81_FC_MBX_REGS_CNT]; 160252206Sdavidcs 161252206Sdavidcs qls_mpid_seg_hdr_t nic2_mbx_regs_seg_hdr; 162252206Sdavidcs uint32_t nic2_mbx_regs[Q81_NIC_MBX_REGS_CNT]; 163252206Sdavidcs 164252206Sdavidcs qls_mpid_seg_hdr_t i2c_regs_seg_hdr; 165252206Sdavidcs uint32_t i2c_regs[Q81_I2C_REGS_CNT]; 166252206Sdavidcs 167252206Sdavidcs qls_mpid_seg_hdr_t memc_regs_seg_hdr; 168252206Sdavidcs uint32_t memc_regs[Q81_MEMC_REGS_CNT]; 169252206Sdavidcs 170252206Sdavidcs qls_mpid_seg_hdr_t pbus_regs_seg_hdr; 171252206Sdavidcs uint32_t pbus_regs[Q81_PBUS_REGS_CNT]; 172252206Sdavidcs 173252206Sdavidcs qls_mpid_seg_hdr_t mde_regs_seg_hdr; 174252206Sdavidcs uint32_t mde_regs[Q81_MDE_REGS_CNT]; 175252206Sdavidcs 176252206Sdavidcs qls_mpid_seg_hdr_t xaui1_an_hdr; 177252206Sdavidcs uint32_t serdes1_xaui_an[14]; 178252206Sdavidcs 179252206Sdavidcs qls_mpid_seg_hdr_t xaui1_hss_pcs_hdr; 180252206Sdavidcs uint32_t serdes1_xaui_hss_pcs[33]; 181252206Sdavidcs 182252206Sdavidcs qls_mpid_seg_hdr_t xfi1_an_hdr; 183252206Sdavidcs uint32_t serdes1_xfi_an[14]; 184252206Sdavidcs 185252206Sdavidcs qls_mpid_seg_hdr_t xfi1_train_hdr; 186252206Sdavidcs uint32_t serdes1_xfi_train[12]; 187252206Sdavidcs 188252206Sdavidcs qls_mpid_seg_hdr_t xfi1_hss_pcs_hdr; 189252206Sdavidcs uint32_t serdes1_xfi_hss_pcs[15]; 190252206Sdavidcs 191252206Sdavidcs qls_mpid_seg_hdr_t xfi1_hss_tx_hdr; 192252206Sdavidcs uint32_t serdes1_xfi_hss_tx[32]; 193252206Sdavidcs 194252206Sdavidcs qls_mpid_seg_hdr_t xfi1_hss_rx_hdr; 195252206Sdavidcs uint32_t serdes1_xfi_hss_rx[32]; 196252206Sdavidcs 197252206Sdavidcs qls_mpid_seg_hdr_t xfi1_hss_pll_hdr; 198252206Sdavidcs uint32_t serdes1_xfi_hss_pll[32]; 199252206Sdavidcs 200252206Sdavidcs qls_mpid_seg_hdr_t xaui2_an_hdr; 201252206Sdavidcs uint32_t serdes2_xaui_an[14]; 202252206Sdavidcs 203252206Sdavidcs qls_mpid_seg_hdr_t xaui2_hss_pcs_hdr; 204252206Sdavidcs uint32_t serdes2_xaui_hss_pcs[33]; 205252206Sdavidcs 206252206Sdavidcs qls_mpid_seg_hdr_t xfi2_an_hdr; 207252206Sdavidcs uint32_t serdes2_xfi_an[14]; 208252206Sdavidcs 209252206Sdavidcs qls_mpid_seg_hdr_t xfi2_train_hdr; 210252206Sdavidcs uint32_t serdes2_xfi_train[12]; 211252206Sdavidcs 212252206Sdavidcs qls_mpid_seg_hdr_t xfi2_hss_pcs_hdr; 213252206Sdavidcs uint32_t serdes2_xfi_hss_pcs[15]; 214252206Sdavidcs 215252206Sdavidcs qls_mpid_seg_hdr_t xfi2_hss_tx_hdr; 216252206Sdavidcs uint32_t serdes2_xfi_hss_tx[32]; 217252206Sdavidcs 218252206Sdavidcs qls_mpid_seg_hdr_t xfi2_hss_rx_hdr; 219252206Sdavidcs uint32_t serdes2_xfi_hss_rx[32]; 220252206Sdavidcs 221252206Sdavidcs qls_mpid_seg_hdr_t xfi2_hss_pll_hdr; 222252206Sdavidcs uint32_t serdes2_xfi_hss_pll[32]; 223252206Sdavidcs 224252206Sdavidcs qls_mpid_seg_hdr_t nic1_regs_seg_hdr; 225252206Sdavidcs uint32_t nic1_regs[64]; 226252206Sdavidcs 227252206Sdavidcs qls_mpid_seg_hdr_t nic2_regs_seg_hdr; 228252206Sdavidcs uint32_t nic2_regs[64]; 229252206Sdavidcs 230252206Sdavidcs qls_mpid_seg_hdr_t intr_states_seg_hdr; 231252206Sdavidcs uint32_t intr_states[MAX_RX_RINGS]; 232252206Sdavidcs 233252206Sdavidcs qls_mpid_seg_hdr_t xgmac1_seg_hdr; 234252206Sdavidcs uint32_t xgmac1[Q81_XGMAC_REGISTER_END]; 235252206Sdavidcs 236252206Sdavidcs qls_mpid_seg_hdr_t xgmac2_seg_hdr; 237252206Sdavidcs uint32_t xgmac2[Q81_XGMAC_REGISTER_END]; 238252206Sdavidcs 239252206Sdavidcs qls_mpid_seg_hdr_t probe_dump_seg_hdr; 240252206Sdavidcs uint32_t probe_dump[Q81_PROBE_SIZE]; 241252206Sdavidcs 242252206Sdavidcs qls_mpid_seg_hdr_t routing_reg_seg_hdr; 243252206Sdavidcs uint32_t routing_regs[Q81_ROUT_REG_SIZE]; 244252206Sdavidcs 245252206Sdavidcs qls_mpid_seg_hdr_t mac_prot_reg_seg_hdr; 246252206Sdavidcs uint32_t mac_prot_regs[Q81_MAC_REG_SIZE]; 247252206Sdavidcs 248252206Sdavidcs qls_mpid_seg_hdr_t sem_regs_seg_hdr; 249252206Sdavidcs uint32_t sem_regs[Q81_MAX_SEMAPHORE_FUNCTIONS]; 250252206Sdavidcs 251252206Sdavidcs qls_mpid_seg_hdr_t ets_seg_hdr; 252252206Sdavidcs uint32_t ets[8+2]; 253252206Sdavidcs 254252206Sdavidcs qls_mpid_seg_hdr_t wqc1_seg_hdr; 255252206Sdavidcs uint32_t wqc1[Q81_WQ_SIZE]; 256252206Sdavidcs 257252206Sdavidcs qls_mpid_seg_hdr_t cqc1_seg_hdr; 258252206Sdavidcs uint32_t cqc1[Q81_CQ_SIZE]; 259252206Sdavidcs 260252206Sdavidcs qls_mpid_seg_hdr_t wqc2_seg_hdr; 261252206Sdavidcs uint32_t wqc2[Q81_WQ_SIZE]; 262252206Sdavidcs 263252206Sdavidcs qls_mpid_seg_hdr_t cqc2_seg_hdr; 264252206Sdavidcs uint32_t cqc2[Q81_CQ_SIZE]; 265252206Sdavidcs 266252206Sdavidcs qls_mpid_seg_hdr_t code_ram_seg_hdr; 267252206Sdavidcs uint32_t code_ram[Q81_CODE_RAM_CNT]; 268252206Sdavidcs 269252206Sdavidcs qls_mpid_seg_hdr_t memc_ram_seg_hdr; 270252206Sdavidcs uint32_t memc_ram[Q81_MEMC_RAM_CNT]; 271252206Sdavidcs}; 272252206Sdavidcstypedef struct qls_mpi_coredump qls_mpi_coredump_t; 273252206Sdavidcs 274252206Sdavidcs#define Q81_BAD_DATA 0xDEADBEEF 275252206Sdavidcs 276252206Sdavidcs#endif /* #ifndef _QLS_DUMP_H_ */ 277252206Sdavidcs 278