1252206Sdavidcs/* 2252206Sdavidcs * Copyright (c) 2013-2014 Qlogic Corporation 3252206Sdavidcs * All rights reserved. 4252206Sdavidcs * 5252206Sdavidcs * Redistribution and use in source and binary forms, with or without 6252206Sdavidcs * modification, are permitted provided that the following conditions 7252206Sdavidcs * are met: 8252206Sdavidcs * 9252206Sdavidcs * 1. Redistributions of source code must retain the above copyright 10252206Sdavidcs * notice, this list of conditions and the following disclaimer. 11252206Sdavidcs * 2. Redistributions in binary form must reproduce the above copyright 12252206Sdavidcs * notice, this list of conditions and the following disclaimer in the 13252206Sdavidcs * documentation and/or other materials provided with the distribution. 14252206Sdavidcs * 15252206Sdavidcs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16252206Sdavidcs * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17252206Sdavidcs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18252206Sdavidcs * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19252206Sdavidcs * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20252206Sdavidcs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21252206Sdavidcs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22252206Sdavidcs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23252206Sdavidcs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24252206Sdavidcs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25252206Sdavidcs * POSSIBILITY OF SUCH DAMAGE. 26252206Sdavidcs */ 27252206Sdavidcs 28252206Sdavidcs/* 29252206Sdavidcs * File: qls_dump.c 30252206Sdavidcs */ 31252206Sdavidcs#include <sys/cdefs.h> 32252206Sdavidcs__FBSDID("$FreeBSD: releng/11.0/sys/dev/qlxge/qls_dump.c 258780 2013-11-30 22:17:27Z eadler $"); 33252206Sdavidcs 34252206Sdavidcs 35252206Sdavidcs#include "qls_os.h" 36252206Sdavidcs#include "qls_hw.h" 37252206Sdavidcs#include "qls_def.h" 38252206Sdavidcs#include "qls_glbl.h" 39252206Sdavidcs#include "qls_dump.h" 40252206Sdavidcs 41252206Sdavidcsqls_mpi_coredump_t ql_mpi_coredump; 42252206Sdavidcs 43252206Sdavidcs#define Q81_CORE_SEG_NUM 1 44252206Sdavidcs#define Q81_TEST_LOGIC_SEG_NUM 2 45252206Sdavidcs#define Q81_RMII_SEG_NUM 3 46252206Sdavidcs#define Q81_FCMAC1_SEG_NUM 4 47252206Sdavidcs#define Q81_FCMAC2_SEG_NUM 5 48252206Sdavidcs#define Q81_FC1_MBOX_SEG_NUM 6 49252206Sdavidcs#define Q81_IDE_SEG_NUM 7 50252206Sdavidcs#define Q81_NIC1_MBOX_SEG_NUM 8 51252206Sdavidcs#define Q81_SMBUS_SEG_NUM 9 52252206Sdavidcs#define Q81_FC2_MBOX_SEG_NUM 10 53252206Sdavidcs#define Q81_NIC2_MBOX_SEG_NUM 11 54252206Sdavidcs#define Q81_I2C_SEG_NUM 12 55252206Sdavidcs#define Q81_MEMC_SEG_NUM 13 56252206Sdavidcs#define Q81_PBUS_SEG_NUM 14 57252206Sdavidcs#define Q81_MDE_SEG_NUM 15 58252206Sdavidcs#define Q81_NIC1_CONTROL_SEG_NUM 16 59252206Sdavidcs#define Q81_NIC2_CONTROL_SEG_NUM 17 60252206Sdavidcs#define Q81_NIC1_XGMAC_SEG_NUM 18 61252206Sdavidcs#define Q81_NIC2_XGMAC_SEG_NUM 19 62252206Sdavidcs#define Q81_WCS_RAM_SEG_NUM 20 63252206Sdavidcs#define Q81_MEMC_RAM_SEG_NUM 21 64252206Sdavidcs#define Q81_XAUI1_AN_SEG_NUM 22 65252206Sdavidcs#define Q81_XAUI1_HSS_PCS_SEG_NUM 23 66252206Sdavidcs#define Q81_XFI1_AN_SEG_NUM 24 67252206Sdavidcs#define Q81_XFI1_TRAIN_SEG_NUM 25 68252206Sdavidcs#define Q81_XFI1_HSS_PCS_SEG_NUM 26 69252206Sdavidcs#define Q81_XFI1_HSS_TX_SEG_NUM 27 70252206Sdavidcs#define Q81_XFI1_HSS_RX_SEG_NUM 28 71252206Sdavidcs#define Q81_XFI1_HSS_PLL_SEG_NUM 29 72252206Sdavidcs#define Q81_INTR_STATES_SEG_NUM 31 73252206Sdavidcs#define Q81_ETS_SEG_NUM 34 74252206Sdavidcs#define Q81_PROBE_DUMP_SEG_NUM 35 75252206Sdavidcs#define Q81_ROUTING_INDEX_SEG_NUM 36 76252206Sdavidcs#define Q81_MAC_PROTOCOL_SEG_NUM 37 77252206Sdavidcs#define Q81_XAUI2_AN_SEG_NUM 38 78252206Sdavidcs#define Q81_XAUI2_HSS_PCS_SEG_NUM 39 79252206Sdavidcs#define Q81_XFI2_AN_SEG_NUM 40 80252206Sdavidcs#define Q81_XFI2_TRAIN_SEG_NUM 41 81252206Sdavidcs#define Q81_XFI2_HSS_PCS_SEG_NUM 42 82252206Sdavidcs#define Q81_XFI2_HSS_TX_SEG_NUM 43 83252206Sdavidcs#define Q81_XFI2_HSS_RX_SEG_NUM 44 84252206Sdavidcs#define Q81_XFI2_HSS_PLL_SEG_NUM 45 85252206Sdavidcs#define Q81_WQC1_SEG_NUM 46 86252206Sdavidcs#define Q81_CQC1_SEG_NUM 47 87252206Sdavidcs#define Q81_WQC2_SEG_NUM 48 88252206Sdavidcs#define Q81_CQC2_SEG_NUM 49 89252206Sdavidcs#define Q81_SEM_REGS_SEG_NUM 50 90252206Sdavidcs 91252206Sdavidcsenum 92252206Sdavidcs{ 93252206Sdavidcs Q81_PAUSE_SRC_LO = 0x00000100, 94252206Sdavidcs Q81_PAUSE_SRC_HI = 0x00000104, 95252206Sdavidcs Q81_GLOBAL_CFG = 0x00000108, 96252206Sdavidcs Q81_GLOBAL_CFG_RESET = (1 << 0), /*Control*/ 97252206Sdavidcs Q81_GLOBAL_CFG_JUMBO = (1 << 6), /*Control*/ 98252206Sdavidcs Q81_GLOBAL_CFG_TX_STAT_EN = (1 << 10), /*Control*/ 99252206Sdavidcs Q81_GLOBAL_CFG_RX_STAT_EN = (1 << 11), /*Control*/ 100252206Sdavidcs Q81_TX_CFG = 0x0000010c, 101252206Sdavidcs Q81_TX_CFG_RESET = (1 << 0), /*Control*/ 102252206Sdavidcs Q81_TX_CFG_EN = (1 << 1), /*Control*/ 103252206Sdavidcs Q81_TX_CFG_PREAM = (1 << 2), /*Control*/ 104252206Sdavidcs Q81_RX_CFG = 0x00000110, 105252206Sdavidcs Q81_RX_CFG_RESET = (1 << 0), /*Control*/ 106252206Sdavidcs Q81_RX_CFG_EN = (1 << 1), /*Control*/ 107252206Sdavidcs Q81_RX_CFG_PREAM = (1 << 2), /*Control*/ 108252206Sdavidcs Q81_FLOW_CTL = 0x0000011c, 109252206Sdavidcs Q81_PAUSE_OPCODE = 0x00000120, 110252206Sdavidcs Q81_PAUSE_TIMER = 0x00000124, 111252206Sdavidcs Q81_PAUSE_FRM_DEST_LO = 0x00000128, 112252206Sdavidcs Q81_PAUSE_FRM_DEST_HI = 0x0000012c, 113252206Sdavidcs Q81_MAC_TX_PARAMS = 0x00000134, 114258780Seadler Q81_MAC_TX_PARAMS_JUMBO = (1U << 31), /*Control*/ 115252206Sdavidcs Q81_MAC_TX_PARAMS_SIZE_SHIFT = 16, /*Control*/ 116252206Sdavidcs Q81_MAC_RX_PARAMS = 0x00000138, 117252206Sdavidcs Q81_MAC_SYS_INT = 0x00000144, 118252206Sdavidcs Q81_MAC_SYS_INT_MASK = 0x00000148, 119252206Sdavidcs Q81_MAC_MGMT_INT = 0x0000014c, 120252206Sdavidcs Q81_MAC_MGMT_IN_MASK = 0x00000150, 121252206Sdavidcs Q81_EXT_ARB_MODE = 0x000001fc, 122252206Sdavidcs Q81_TX_PKTS = 0x00000200, 123252206Sdavidcs Q81_TX_PKTS_LO = 0x00000204, 124252206Sdavidcs Q81_TX_BYTES = 0x00000208, 125252206Sdavidcs Q81_TX_BYTES_LO = 0x0000020C, 126252206Sdavidcs Q81_TX_MCAST_PKTS = 0x00000210, 127252206Sdavidcs Q81_TX_MCAST_PKTS_LO = 0x00000214, 128252206Sdavidcs Q81_TX_BCAST_PKTS = 0x00000218, 129252206Sdavidcs Q81_TX_BCAST_PKTS_LO = 0x0000021C, 130252206Sdavidcs Q81_TX_UCAST_PKTS = 0x00000220, 131252206Sdavidcs Q81_TX_UCAST_PKTS_LO = 0x00000224, 132252206Sdavidcs Q81_TX_CTL_PKTS = 0x00000228, 133252206Sdavidcs Q81_TX_CTL_PKTS_LO = 0x0000022c, 134252206Sdavidcs Q81_TX_PAUSE_PKTS = 0x00000230, 135252206Sdavidcs Q81_TX_PAUSE_PKTS_LO = 0x00000234, 136252206Sdavidcs Q81_TX_64_PKT = 0x00000238, 137252206Sdavidcs Q81_TX_64_PKT_LO = 0x0000023c, 138252206Sdavidcs Q81_TX_65_TO_127_PKT = 0x00000240, 139252206Sdavidcs Q81_TX_65_TO_127_PKT_LO = 0x00000244, 140252206Sdavidcs Q81_TX_128_TO_255_PKT = 0x00000248, 141252206Sdavidcs Q81_TX_128_TO_255_PKT_LO = 0x0000024c, 142252206Sdavidcs Q81_TX_256_511_PKT = 0x00000250, 143252206Sdavidcs Q81_TX_256_511_PKT_LO = 0x00000254, 144252206Sdavidcs Q81_TX_512_TO_1023_PKT = 0x00000258, 145252206Sdavidcs Q81_TX_512_TO_1023_PKT_LO = 0x0000025c, 146252206Sdavidcs Q81_TX_1024_TO_1518_PKT = 0x00000260, 147252206Sdavidcs Q81_TX_1024_TO_1518_PKT_LO = 0x00000264, 148252206Sdavidcs Q81_TX_1519_TO_MAX_PKT = 0x00000268, 149252206Sdavidcs Q81_TX_1519_TO_MAX_PKT_LO = 0x0000026c, 150252206Sdavidcs Q81_TX_UNDERSIZE_PKT = 0x00000270, 151252206Sdavidcs Q81_TX_UNDERSIZE_PKT_LO = 0x00000274, 152252206Sdavidcs Q81_TX_OVERSIZE_PKT = 0x00000278, 153252206Sdavidcs Q81_TX_OVERSIZE_PKT_LO = 0x0000027c, 154252206Sdavidcs Q81_RX_HALF_FULL_DET = 0x000002a0, 155252206Sdavidcs Q81_TX_HALF_FULL_DET_LO = 0x000002a4, 156252206Sdavidcs Q81_RX_OVERFLOW_DET = 0x000002a8, 157252206Sdavidcs Q81_TX_OVERFLOW_DET_LO = 0x000002ac, 158252206Sdavidcs Q81_RX_HALF_FULL_MASK = 0x000002b0, 159252206Sdavidcs Q81_TX_HALF_FULL_MASK_LO = 0x000002b4, 160252206Sdavidcs Q81_RX_OVERFLOW_MASK = 0x000002b8, 161252206Sdavidcs Q81_TX_OVERFLOW_MASK_LO = 0x000002bc, 162252206Sdavidcs Q81_STAT_CNT_CTL = 0x000002c0, 163252206Sdavidcs Q81_STAT_CNT_CTL_CLEAR_TX = (1 << 0), /*Control*/ 164252206Sdavidcs Q81_STAT_CNT_CTL_CLEAR_RX = (1 << 1), /*Control*/ 165252206Sdavidcs Q81_AUX_RX_HALF_FULL_DET = 0x000002d0, 166252206Sdavidcs Q81_AUX_TX_HALF_FULL_DET = 0x000002d4, 167252206Sdavidcs Q81_AUX_RX_OVERFLOW_DET = 0x000002d8, 168252206Sdavidcs Q81_AUX_TX_OVERFLOW_DET = 0x000002dc, 169252206Sdavidcs Q81_AUX_RX_HALF_FULL_MASK = 0x000002f0, 170252206Sdavidcs Q81_AUX_TX_HALF_FULL_MASK = 0x000002f4, 171252206Sdavidcs Q81_AUX_RX_OVERFLOW_MASK = 0x000002f8, 172252206Sdavidcs Q81_AUX_TX_OVERFLOW_MASK = 0x000002fc, 173252206Sdavidcs Q81_RX_BYTES = 0x00000300, 174252206Sdavidcs Q81_RX_BYTES_LO = 0x00000304, 175252206Sdavidcs Q81_RX_BYTES_OK = 0x00000308, 176252206Sdavidcs Q81_RX_BYTES_OK_LO = 0x0000030c, 177252206Sdavidcs Q81_RX_PKTS = 0x00000310, 178252206Sdavidcs Q81_RX_PKTS_LO = 0x00000314, 179252206Sdavidcs Q81_RX_PKTS_OK = 0x00000318, 180252206Sdavidcs Q81_RX_PKTS_OK_LO = 0x0000031c, 181252206Sdavidcs Q81_RX_BCAST_PKTS = 0x00000320, 182252206Sdavidcs Q81_RX_BCAST_PKTS_LO = 0x00000324, 183252206Sdavidcs Q81_RX_MCAST_PKTS = 0x00000328, 184252206Sdavidcs Q81_RX_MCAST_PKTS_LO = 0x0000032c, 185252206Sdavidcs Q81_RX_UCAST_PKTS = 0x00000330, 186252206Sdavidcs Q81_RX_UCAST_PKTS_LO = 0x00000334, 187252206Sdavidcs Q81_RX_UNDERSIZE_PKTS = 0x00000338, 188252206Sdavidcs Q81_RX_UNDERSIZE_PKTS_LO = 0x0000033c, 189252206Sdavidcs Q81_RX_OVERSIZE_PKTS = 0x00000340, 190252206Sdavidcs Q81_RX_OVERSIZE_PKTS_LO = 0x00000344, 191252206Sdavidcs Q81_RX_JABBER_PKTS = 0x00000348, 192252206Sdavidcs Q81_RX_JABBER_PKTS_LO = 0x0000034c, 193252206Sdavidcs Q81_RX_UNDERSIZE_FCERR_PKTS = 0x00000350, 194252206Sdavidcs Q81_RX_UNDERSIZE_FCERR_PKTS_LO = 0x00000354, 195252206Sdavidcs Q81_RX_DROP_EVENTS = 0x00000358, 196252206Sdavidcs Q81_RX_DROP_EVENTS_LO = 0x0000035c, 197252206Sdavidcs Q81_RX_FCERR_PKTS = 0x00000360, 198252206Sdavidcs Q81_RX_FCERR_PKTS_LO = 0x00000364, 199252206Sdavidcs Q81_RX_ALIGN_ERR = 0x00000368, 200252206Sdavidcs Q81_RX_ALIGN_ERR_LO = 0x0000036c, 201252206Sdavidcs Q81_RX_SYMBOL_ERR = 0x00000370, 202252206Sdavidcs Q81_RX_SYMBOL_ERR_LO = 0x00000374, 203252206Sdavidcs Q81_RX_MAC_ERR = 0x00000378, 204252206Sdavidcs Q81_RX_MAC_ERR_LO = 0x0000037c, 205252206Sdavidcs Q81_RX_CTL_PKTS = 0x00000380, 206252206Sdavidcs Q81_RX_CTL_PKTS_LO = 0x00000384, 207252206Sdavidcs Q81_RX_PAUSE_PKTS = 0x00000388, 208252206Sdavidcs Q81_RX_PAUSE_PKTS_LO = 0x0000038c, 209252206Sdavidcs Q81_RX_64_PKTS = 0x00000390, 210252206Sdavidcs Q81_RX_64_PKTS_LO = 0x00000394, 211252206Sdavidcs Q81_RX_65_TO_127_PKTS = 0x00000398, 212252206Sdavidcs Q81_RX_65_TO_127_PKTS_LO = 0x0000039c, 213252206Sdavidcs Q81_RX_128_255_PKTS = 0x000003a0, 214252206Sdavidcs Q81_RX_128_255_PKTS_LO = 0x000003a4, 215252206Sdavidcs Q81_RX_256_511_PKTS = 0x000003a8, 216252206Sdavidcs Q81_RX_256_511_PKTS_LO = 0x000003ac, 217252206Sdavidcs Q81_RX_512_TO_1023_PKTS = 0x000003b0, 218252206Sdavidcs Q81_RX_512_TO_1023_PKTS_LO = 0x000003b4, 219252206Sdavidcs Q81_RX_1024_TO_1518_PKTS = 0x000003b8, 220252206Sdavidcs Q81_RX_1024_TO_1518_PKTS_LO = 0x000003bc, 221252206Sdavidcs Q81_RX_1519_TO_MAX_PKTS = 0x000003c0, 222252206Sdavidcs Q81_RX_1519_TO_MAX_PKTS_LO = 0x000003c4, 223252206Sdavidcs Q81_RX_LEN_ERR_PKTS = 0x000003c8, 224252206Sdavidcs Q81_RX_LEN_ERR_PKTS_LO = 0x000003cc, 225252206Sdavidcs Q81_MDIO_TX_DATA = 0x00000400, 226252206Sdavidcs Q81_MDIO_RX_DATA = 0x00000410, 227252206Sdavidcs Q81_MDIO_CMD = 0x00000420, 228252206Sdavidcs Q81_MDIO_PHY_ADDR = 0x00000430, 229252206Sdavidcs Q81_MDIO_PORT = 0x00000440, 230252206Sdavidcs Q81_MDIO_STATUS = 0x00000450, 231252206Sdavidcs Q81_TX_CBFC_PAUSE_FRAMES0 = 0x00000500, 232252206Sdavidcs Q81_TX_CBFC_PAUSE_FRAMES0_LO = 0x00000504, 233252206Sdavidcs Q81_TX_CBFC_PAUSE_FRAMES1 = 0x00000508, 234252206Sdavidcs Q81_TX_CBFC_PAUSE_FRAMES1_LO = 0x0000050C, 235252206Sdavidcs Q81_TX_CBFC_PAUSE_FRAMES2 = 0x00000510, 236252206Sdavidcs Q81_TX_CBFC_PAUSE_FRAMES2_LO = 0x00000514, 237252206Sdavidcs Q81_TX_CBFC_PAUSE_FRAMES3 = 0x00000518, 238252206Sdavidcs Q81_TX_CBFC_PAUSE_FRAMES3_LO = 0x0000051C, 239252206Sdavidcs Q81_TX_CBFC_PAUSE_FRAMES4 = 0x00000520, 240252206Sdavidcs Q81_TX_CBFC_PAUSE_FRAMES4_LO = 0x00000524, 241252206Sdavidcs Q81_TX_CBFC_PAUSE_FRAMES5 = 0x00000528, 242252206Sdavidcs Q81_TX_CBFC_PAUSE_FRAMES5_LO = 0x0000052C, 243252206Sdavidcs Q81_TX_CBFC_PAUSE_FRAMES6 = 0x00000530, 244252206Sdavidcs Q81_TX_CBFC_PAUSE_FRAMES6_LO = 0x00000534, 245252206Sdavidcs Q81_TX_CBFC_PAUSE_FRAMES7 = 0x00000538, 246252206Sdavidcs Q81_TX_CBFC_PAUSE_FRAMES7_LO = 0x0000053C, 247252206Sdavidcs Q81_TX_FCOE_PKTS = 0x00000540, 248252206Sdavidcs Q81_TX_FCOE_PKTS_LO = 0x00000544, 249252206Sdavidcs Q81_TX_MGMT_PKTS = 0x00000548, 250252206Sdavidcs Q81_TX_MGMT_PKTS_LO = 0x0000054C, 251252206Sdavidcs Q81_RX_CBFC_PAUSE_FRAMES0 = 0x00000568, 252252206Sdavidcs Q81_RX_CBFC_PAUSE_FRAMES0_LO = 0x0000056C, 253252206Sdavidcs Q81_RX_CBFC_PAUSE_FRAMES1 = 0x00000570, 254252206Sdavidcs Q81_RX_CBFC_PAUSE_FRAMES1_LO = 0x00000574, 255252206Sdavidcs Q81_RX_CBFC_PAUSE_FRAMES2 = 0x00000578, 256252206Sdavidcs Q81_RX_CBFC_PAUSE_FRAMES2_LO = 0x0000057C, 257252206Sdavidcs Q81_RX_CBFC_PAUSE_FRAMES3 = 0x00000580, 258252206Sdavidcs Q81_RX_CBFC_PAUSE_FRAMES3_LO = 0x00000584, 259252206Sdavidcs Q81_RX_CBFC_PAUSE_FRAMES4 = 0x00000588, 260252206Sdavidcs Q81_RX_CBFC_PAUSE_FRAMES4_LO = 0x0000058C, 261252206Sdavidcs Q81_RX_CBFC_PAUSE_FRAMES5 = 0x00000590, 262252206Sdavidcs Q81_RX_CBFC_PAUSE_FRAMES5_LO = 0x00000594, 263252206Sdavidcs Q81_RX_CBFC_PAUSE_FRAMES6 = 0x00000598, 264252206Sdavidcs Q81_RX_CBFC_PAUSE_FRAMES6_LO = 0x0000059C, 265252206Sdavidcs Q81_RX_CBFC_PAUSE_FRAMES7 = 0x000005A0, 266252206Sdavidcs Q81_RX_CBFC_PAUSE_FRAMES7_LO = 0x000005A4, 267252206Sdavidcs Q81_RX_FCOE_PKTS = 0x000005A8, 268252206Sdavidcs Q81_RX_FCOE_PKTS_LO = 0x000005AC, 269252206Sdavidcs Q81_RX_MGMT_PKTS = 0x000005B0, 270252206Sdavidcs Q81_RX_MGMT_PKTS_LO = 0x000005B4, 271252206Sdavidcs Q81_RX_NIC_FIFO_DROP = 0x000005B8, 272252206Sdavidcs Q81_RX_NIC_FIFO_DROP_LO = 0x000005BC, 273252206Sdavidcs Q81_RX_FCOE_FIFO_DROP = 0x000005C0, 274252206Sdavidcs Q81_RX_FCOE_FIFO_DROP_LO = 0x000005C4, 275252206Sdavidcs Q81_RX_MGMT_FIFO_DROP = 0x000005C8, 276252206Sdavidcs Q81_RX_MGMT_FIFO_DROP_LO = 0x000005CC, 277252206Sdavidcs Q81_RX_PKTS_PRIORITY0 = 0x00000600, 278252206Sdavidcs Q81_RX_PKTS_PRIORITY0_LO = 0x00000604, 279252206Sdavidcs Q81_RX_PKTS_PRIORITY1 = 0x00000608, 280252206Sdavidcs Q81_RX_PKTS_PRIORITY1_LO = 0x0000060C, 281252206Sdavidcs Q81_RX_PKTS_PRIORITY2 = 0x00000610, 282252206Sdavidcs Q81_RX_PKTS_PRIORITY2_LO = 0x00000614, 283252206Sdavidcs Q81_RX_PKTS_PRIORITY3 = 0x00000618, 284252206Sdavidcs Q81_RX_PKTS_PRIORITY3_LO = 0x0000061C, 285252206Sdavidcs Q81_RX_PKTS_PRIORITY4 = 0x00000620, 286252206Sdavidcs Q81_RX_PKTS_PRIORITY4_LO = 0x00000624, 287252206Sdavidcs Q81_RX_PKTS_PRIORITY5 = 0x00000628, 288252206Sdavidcs Q81_RX_PKTS_PRIORITY5_LO = 0x0000062C, 289252206Sdavidcs Q81_RX_PKTS_PRIORITY6 = 0x00000630, 290252206Sdavidcs Q81_RX_PKTS_PRIORITY6_LO = 0x00000634, 291252206Sdavidcs Q81_RX_PKTS_PRIORITY7 = 0x00000638, 292252206Sdavidcs Q81_RX_PKTS_PRIORITY7_LO = 0x0000063C, 293252206Sdavidcs Q81_RX_OCTETS_PRIORITY0 = 0x00000640, 294252206Sdavidcs Q81_RX_OCTETS_PRIORITY0_LO = 0x00000644, 295252206Sdavidcs Q81_RX_OCTETS_PRIORITY1 = 0x00000648, 296252206Sdavidcs Q81_RX_OCTETS_PRIORITY1_LO = 0x0000064C, 297252206Sdavidcs Q81_RX_OCTETS_PRIORITY2 = 0x00000650, 298252206Sdavidcs Q81_RX_OCTETS_PRIORITY2_LO = 0x00000654, 299252206Sdavidcs Q81_RX_OCTETS_PRIORITY3 = 0x00000658, 300252206Sdavidcs Q81_RX_OCTETS_PRIORITY3_LO = 0x0000065C, 301252206Sdavidcs Q81_RX_OCTETS_PRIORITY4 = 0x00000660, 302252206Sdavidcs Q81_RX_OCTETS_PRIORITY4_LO = 0x00000664, 303252206Sdavidcs Q81_RX_OCTETS_PRIORITY5 = 0x00000668, 304252206Sdavidcs Q81_RX_OCTETS_PRIORITY5_LO = 0x0000066C, 305252206Sdavidcs Q81_RX_OCTETS_PRIORITY6 = 0x00000670, 306252206Sdavidcs Q81_RX_OCTETS_PRIORITY6_LO = 0x00000674, 307252206Sdavidcs Q81_RX_OCTETS_PRIORITY7 = 0x00000678, 308252206Sdavidcs Q81_RX_OCTETS_PRIORITY7_LO = 0x0000067C, 309252206Sdavidcs Q81_TX_PKTS_PRIORITY0 = 0x00000680, 310252206Sdavidcs Q81_TX_PKTS_PRIORITY0_LO = 0x00000684, 311252206Sdavidcs Q81_TX_PKTS_PRIORITY1 = 0x00000688, 312252206Sdavidcs Q81_TX_PKTS_PRIORITY1_LO = 0x0000068C, 313252206Sdavidcs Q81_TX_PKTS_PRIORITY2 = 0x00000690, 314252206Sdavidcs Q81_TX_PKTS_PRIORITY2_LO = 0x00000694, 315252206Sdavidcs Q81_TX_PKTS_PRIORITY3 = 0x00000698, 316252206Sdavidcs Q81_TX_PKTS_PRIORITY3_LO = 0x0000069C, 317252206Sdavidcs Q81_TX_PKTS_PRIORITY4 = 0x000006A0, 318252206Sdavidcs Q81_TX_PKTS_PRIORITY4_LO = 0x000006A4, 319252206Sdavidcs Q81_TX_PKTS_PRIORITY5 = 0x000006A8, 320252206Sdavidcs Q81_TX_PKTS_PRIORITY5_LO = 0x000006AC, 321252206Sdavidcs Q81_TX_PKTS_PRIORITY6 = 0x000006B0, 322252206Sdavidcs Q81_TX_PKTS_PRIORITY6_LO = 0x000006B4, 323252206Sdavidcs Q81_TX_PKTS_PRIORITY7 = 0x000006B8, 324252206Sdavidcs Q81_TX_PKTS_PRIORITY7_LO = 0x000006BC, 325252206Sdavidcs Q81_TX_OCTETS_PRIORITY0 = 0x000006C0, 326252206Sdavidcs Q81_TX_OCTETS_PRIORITY0_LO = 0x000006C4, 327252206Sdavidcs Q81_TX_OCTETS_PRIORITY1 = 0x000006C8, 328252206Sdavidcs Q81_TX_OCTETS_PRIORITY1_LO = 0x000006CC, 329252206Sdavidcs Q81_TX_OCTETS_PRIORITY2 = 0x000006D0, 330252206Sdavidcs Q81_TX_OCTETS_PRIORITY2_LO = 0x000006D4, 331252206Sdavidcs Q81_TX_OCTETS_PRIORITY3 = 0x000006D8, 332252206Sdavidcs Q81_TX_OCTETS_PRIORITY3_LO = 0x000006DC, 333252206Sdavidcs Q81_TX_OCTETS_PRIORITY4 = 0x000006E0, 334252206Sdavidcs Q81_TX_OCTETS_PRIORITY4_LO = 0x000006E4, 335252206Sdavidcs Q81_TX_OCTETS_PRIORITY5 = 0x000006E8, 336252206Sdavidcs Q81_TX_OCTETS_PRIORITY5_LO = 0x000006EC, 337252206Sdavidcs Q81_TX_OCTETS_PRIORITY6 = 0x000006F0, 338252206Sdavidcs Q81_TX_OCTETS_PRIORITY6_LO = 0x000006F4, 339252206Sdavidcs Q81_TX_OCTETS_PRIORITY7 = 0x000006F8, 340252206Sdavidcs Q81_TX_OCTETS_PRIORITY7_LO = 0x000006FC, 341252206Sdavidcs Q81_RX_DISCARD_PRIORITY0 = 0x00000700, 342252206Sdavidcs Q81_RX_DISCARD_PRIORITY0_LO = 0x00000704, 343252206Sdavidcs Q81_RX_DISCARD_PRIORITY1 = 0x00000708, 344252206Sdavidcs Q81_RX_DISCARD_PRIORITY1_LO = 0x0000070C, 345252206Sdavidcs Q81_RX_DISCARD_PRIORITY2 = 0x00000710, 346252206Sdavidcs Q81_RX_DISCARD_PRIORITY2_LO = 0x00000714, 347252206Sdavidcs Q81_RX_DISCARD_PRIORITY3 = 0x00000718, 348252206Sdavidcs Q81_RX_DISCARD_PRIORITY3_LO = 0x0000071C, 349252206Sdavidcs Q81_RX_DISCARD_PRIORITY4 = 0x00000720, 350252206Sdavidcs Q81_RX_DISCARD_PRIORITY4_LO = 0x00000724, 351252206Sdavidcs Q81_RX_DISCARD_PRIORITY5 = 0x00000728, 352252206Sdavidcs Q81_RX_DISCARD_PRIORITY5_LO = 0x0000072C, 353252206Sdavidcs Q81_RX_DISCARD_PRIORITY6 = 0x00000730, 354252206Sdavidcs Q81_RX_DISCARD_PRIORITY6_LO = 0x00000734, 355252206Sdavidcs Q81_RX_DISCARD_PRIORITY7 = 0x00000738, 356252206Sdavidcs Q81_RX_DISCARD_PRIORITY7_LO = 0x0000073C 357252206Sdavidcs}; 358252206Sdavidcs 359252206Sdavidcsstatic void 360252206Sdavidcsqls_mpid_seg_hdr(qls_mpid_seg_hdr_t *seg_hdr, uint32_t seg_num, 361252206Sdavidcs uint32_t seg_size, unsigned char *desc) 362252206Sdavidcs{ 363252206Sdavidcs memset(seg_hdr, 0, sizeof(qls_mpid_seg_hdr_t)); 364252206Sdavidcs 365252206Sdavidcs seg_hdr->cookie = Q81_MPID_COOKIE; 366252206Sdavidcs seg_hdr->seg_num = seg_num; 367252206Sdavidcs seg_hdr->seg_size = seg_size; 368252206Sdavidcs 369252206Sdavidcs memcpy(seg_hdr->desc, desc, (sizeof(seg_hdr->desc))-1); 370252206Sdavidcs 371252206Sdavidcs return; 372252206Sdavidcs} 373252206Sdavidcs 374252206Sdavidcsstatic int 375252206Sdavidcsqls_wait_reg_rdy(qla_host_t *ha , uint32_t reg, uint32_t bit, uint32_t err_bit) 376252206Sdavidcs{ 377252206Sdavidcs uint32_t data; 378252206Sdavidcs int count = 10; 379252206Sdavidcs 380252206Sdavidcs while (count) { 381252206Sdavidcs 382252206Sdavidcs data = READ_REG32(ha, reg); 383252206Sdavidcs 384252206Sdavidcs if (data & err_bit) 385252206Sdavidcs return (-1); 386252206Sdavidcs else if (data & bit) 387252206Sdavidcs return (0); 388252206Sdavidcs 389252206Sdavidcs qls_mdelay(__func__, 10); 390252206Sdavidcs count--; 391252206Sdavidcs } 392252206Sdavidcs return (-1); 393252206Sdavidcs} 394252206Sdavidcs 395252206Sdavidcsstatic int 396252206Sdavidcsqls_rd_mpi_reg(qla_host_t *ha, uint32_t reg, uint32_t *data) 397252206Sdavidcs{ 398252206Sdavidcs int ret; 399252206Sdavidcs 400252206Sdavidcs ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY, 401252206Sdavidcs Q81_CTL_PROC_ADDR_ERR); 402252206Sdavidcs 403252206Sdavidcs if (ret) 404252206Sdavidcs goto exit_qls_rd_mpi_reg; 405252206Sdavidcs 406252206Sdavidcs WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg | Q81_CTL_PROC_ADDR_READ); 407252206Sdavidcs 408252206Sdavidcs ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY, 409252206Sdavidcs Q81_CTL_PROC_ADDR_ERR); 410252206Sdavidcs 411252206Sdavidcs if (ret) 412252206Sdavidcs goto exit_qls_rd_mpi_reg; 413252206Sdavidcs 414252206Sdavidcs *data = READ_REG32(ha, Q81_CTL_PROC_DATA); 415252206Sdavidcs 416252206Sdavidcsexit_qls_rd_mpi_reg: 417252206Sdavidcs return (ret); 418252206Sdavidcs} 419252206Sdavidcs 420252206Sdavidcsstatic int 421252206Sdavidcsqls_wr_mpi_reg(qla_host_t *ha, uint32_t reg, uint32_t data) 422252206Sdavidcs{ 423252206Sdavidcs int ret = 0; 424252206Sdavidcs 425252206Sdavidcs ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY, 426252206Sdavidcs Q81_CTL_PROC_ADDR_ERR); 427252206Sdavidcs if (ret) 428252206Sdavidcs goto exit_qls_wr_mpi_reg; 429252206Sdavidcs 430252206Sdavidcs WRITE_REG32(ha, Q81_CTL_PROC_DATA, data); 431252206Sdavidcs 432252206Sdavidcs WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg); 433252206Sdavidcs 434252206Sdavidcs ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY, 435252206Sdavidcs Q81_CTL_PROC_ADDR_ERR); 436252206Sdavidcsexit_qls_wr_mpi_reg: 437252206Sdavidcs return (ret); 438252206Sdavidcs} 439252206Sdavidcs 440252206Sdavidcs 441252206Sdavidcs#define Q81_TEST_LOGIC_FUNC_PORT_CONFIG 0x1002 442252206Sdavidcs#define Q81_INVALID_NUM 0xFFFFFFFF 443252206Sdavidcs 444252206Sdavidcs#define Q81_NIC1_FUNC_ENABLE 0x00000001 445252206Sdavidcs#define Q81_NIC1_FUNC_MASK 0x0000000e 446252206Sdavidcs#define Q81_NIC1_FUNC_SHIFT 1 447252206Sdavidcs#define Q81_NIC2_FUNC_ENABLE 0x00000010 448252206Sdavidcs#define Q81_NIC2_FUNC_MASK 0x000000e0 449252206Sdavidcs#define Q81_NIC2_FUNC_SHIFT 5 450252206Sdavidcs#define Q81_FUNCTION_SHIFT 6 451252206Sdavidcs 452252206Sdavidcsstatic uint32_t 453252206Sdavidcsqls_get_other_fnum(qla_host_t *ha) 454252206Sdavidcs{ 455252206Sdavidcs int ret; 456252206Sdavidcs uint32_t o_func; 457252206Sdavidcs uint32_t test_logic; 458252206Sdavidcs uint32_t nic1_fnum = Q81_INVALID_NUM; 459252206Sdavidcs uint32_t nic2_fnum = Q81_INVALID_NUM; 460252206Sdavidcs 461252206Sdavidcs ret = qls_rd_mpi_reg(ha, Q81_TEST_LOGIC_FUNC_PORT_CONFIG, &test_logic); 462252206Sdavidcs if (ret) 463252206Sdavidcs return(Q81_INVALID_NUM); 464252206Sdavidcs 465252206Sdavidcs if (test_logic & Q81_NIC1_FUNC_ENABLE) 466252206Sdavidcs nic1_fnum = (test_logic & Q81_NIC1_FUNC_MASK) >> 467252206Sdavidcs Q81_NIC1_FUNC_SHIFT; 468252206Sdavidcs 469252206Sdavidcs if (test_logic & Q81_NIC2_FUNC_ENABLE) 470252206Sdavidcs nic2_fnum = (test_logic & Q81_NIC2_FUNC_MASK) >> 471252206Sdavidcs Q81_NIC2_FUNC_SHIFT; 472252206Sdavidcs 473252206Sdavidcs if (ha->pci_func == 0) 474252206Sdavidcs o_func = nic2_fnum; 475252206Sdavidcs else 476252206Sdavidcs o_func = nic1_fnum; 477252206Sdavidcs 478252206Sdavidcs return(o_func); 479252206Sdavidcs} 480252206Sdavidcs 481252206Sdavidcsstatic uint32_t 482252206Sdavidcsqls_rd_ofunc_reg(qla_host_t *ha, uint32_t reg) 483252206Sdavidcs{ 484252206Sdavidcs uint32_t ofunc; 485252206Sdavidcs uint32_t data; 486252206Sdavidcs int ret = 0; 487252206Sdavidcs 488252206Sdavidcs ofunc = qls_get_other_fnum(ha); 489252206Sdavidcs 490252206Sdavidcs if (ofunc == Q81_INVALID_NUM) 491252206Sdavidcs return(Q81_INVALID_NUM); 492252206Sdavidcs 493252206Sdavidcs reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (ofunc << Q81_FUNCTION_SHIFT) | reg; 494252206Sdavidcs 495252206Sdavidcs ret = qls_rd_mpi_reg(ha, reg, &data); 496252206Sdavidcs 497252206Sdavidcs if (ret != 0) 498252206Sdavidcs return(Q81_INVALID_NUM); 499252206Sdavidcs 500252206Sdavidcs return(data); 501252206Sdavidcs} 502252206Sdavidcs 503252206Sdavidcsstatic void 504252206Sdavidcsqls_wr_ofunc_reg(qla_host_t *ha, uint32_t reg, uint32_t value) 505252206Sdavidcs{ 506252206Sdavidcs uint32_t ofunc; 507252206Sdavidcs int ret = 0; 508252206Sdavidcs 509252206Sdavidcs ofunc = qls_get_other_fnum(ha); 510252206Sdavidcs 511252206Sdavidcs if (ofunc == Q81_INVALID_NUM) 512252206Sdavidcs return; 513252206Sdavidcs 514252206Sdavidcs reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (ofunc << Q81_FUNCTION_SHIFT) | reg; 515252206Sdavidcs 516252206Sdavidcs ret = qls_wr_mpi_reg(ha, reg, value); 517252206Sdavidcs 518252206Sdavidcs return; 519252206Sdavidcs} 520252206Sdavidcs 521252206Sdavidcsstatic int 522252206Sdavidcsqls_wait_ofunc_reg_rdy(qla_host_t *ha , uint32_t reg, uint32_t bit, 523252206Sdavidcs uint32_t err_bit) 524252206Sdavidcs{ 525252206Sdavidcs uint32_t data; 526252206Sdavidcs int count = 10; 527252206Sdavidcs 528252206Sdavidcs while (count) { 529252206Sdavidcs 530252206Sdavidcs data = qls_rd_ofunc_reg(ha, reg); 531252206Sdavidcs 532252206Sdavidcs if (data & err_bit) 533252206Sdavidcs return (-1); 534252206Sdavidcs else if (data & bit) 535252206Sdavidcs return (0); 536252206Sdavidcs 537252206Sdavidcs qls_mdelay(__func__, 10); 538252206Sdavidcs count--; 539252206Sdavidcs } 540252206Sdavidcs return (-1); 541252206Sdavidcs} 542252206Sdavidcs 543252206Sdavidcs#define Q81_XG_SERDES_ADDR_RDY BIT_31 544252206Sdavidcs#define Q81_XG_SERDES_ADDR_READ BIT_30 545252206Sdavidcs 546252206Sdavidcsstatic int 547252206Sdavidcsqls_rd_ofunc_serdes_reg(qla_host_t *ha, uint32_t reg, uint32_t *data) 548252206Sdavidcs{ 549252206Sdavidcs int ret; 550252206Sdavidcs 551252206Sdavidcs /* wait for reg to come ready */ 552252206Sdavidcs ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XG_SERDES_ADDR >> 2), 553252206Sdavidcs Q81_XG_SERDES_ADDR_RDY, 0); 554252206Sdavidcs if (ret) 555252206Sdavidcs goto exit_qls_rd_ofunc_serdes_reg; 556252206Sdavidcs 557252206Sdavidcs /* set up for reg read */ 558252206Sdavidcs qls_wr_ofunc_reg(ha, (Q81_CTL_XG_SERDES_ADDR >> 2), 559252206Sdavidcs (reg | Q81_XG_SERDES_ADDR_READ)); 560252206Sdavidcs 561252206Sdavidcs /* wait for reg to come ready */ 562252206Sdavidcs ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XG_SERDES_ADDR >> 2), 563252206Sdavidcs Q81_XG_SERDES_ADDR_RDY, 0); 564252206Sdavidcs if (ret) 565252206Sdavidcs goto exit_qls_rd_ofunc_serdes_reg; 566252206Sdavidcs 567252206Sdavidcs /* get the data */ 568252206Sdavidcs *data = qls_rd_ofunc_reg(ha, (Q81_CTL_XG_SERDES_DATA >> 2)); 569252206Sdavidcs 570252206Sdavidcsexit_qls_rd_ofunc_serdes_reg: 571252206Sdavidcs return ret; 572252206Sdavidcs} 573252206Sdavidcs 574252206Sdavidcs#define Q81_XGMAC_ADDR_RDY BIT_31 575252206Sdavidcs#define Q81_XGMAC_ADDR_R BIT_30 576252206Sdavidcs#define Q81_XGMAC_ADDR_XME BIT_29 577252206Sdavidcs 578252206Sdavidcsstatic int 579252206Sdavidcsqls_rd_ofunc_xgmac_reg(qla_host_t *ha, uint32_t reg, uint32_t *data) 580252206Sdavidcs{ 581252206Sdavidcs int ret = 0; 582252206Sdavidcs 583252206Sdavidcs ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XGMAC_ADDR >> 2), 584252206Sdavidcs Q81_XGMAC_ADDR_RDY, Q81_XGMAC_ADDR_XME); 585252206Sdavidcs 586252206Sdavidcs if (ret) 587252206Sdavidcs goto exit_qls_rd_ofunc_xgmac_reg; 588252206Sdavidcs 589252206Sdavidcs qls_wr_ofunc_reg(ha, (Q81_XGMAC_ADDR_RDY >> 2), 590252206Sdavidcs (reg | Q81_XGMAC_ADDR_R)); 591252206Sdavidcs 592252206Sdavidcs ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XGMAC_ADDR >> 2), 593252206Sdavidcs Q81_XGMAC_ADDR_RDY, Q81_XGMAC_ADDR_XME); 594252206Sdavidcs if (ret) 595252206Sdavidcs goto exit_qls_rd_ofunc_xgmac_reg; 596252206Sdavidcs 597252206Sdavidcs *data = qls_rd_ofunc_reg(ha, Q81_CTL_XGMAC_DATA); 598252206Sdavidcs 599252206Sdavidcsexit_qls_rd_ofunc_xgmac_reg: 600252206Sdavidcs return ret; 601252206Sdavidcs} 602252206Sdavidcs 603252206Sdavidcsstatic int 604252206Sdavidcsqls_rd_serdes_reg(qla_host_t *ha, uint32_t reg, uint32_t *data) 605252206Sdavidcs{ 606252206Sdavidcs int ret; 607252206Sdavidcs 608252206Sdavidcs ret = qls_wait_reg_rdy(ha, Q81_CTL_XG_SERDES_ADDR, 609252206Sdavidcs Q81_XG_SERDES_ADDR_RDY, 0); 610252206Sdavidcs 611252206Sdavidcs if (ret) 612252206Sdavidcs goto exit_qls_rd_serdes_reg; 613252206Sdavidcs 614252206Sdavidcs WRITE_REG32(ha, Q81_CTL_XG_SERDES_ADDR, \ 615252206Sdavidcs (reg | Q81_XG_SERDES_ADDR_READ)); 616252206Sdavidcs 617252206Sdavidcs ret = qls_wait_reg_rdy(ha, Q81_CTL_XG_SERDES_ADDR, 618252206Sdavidcs Q81_XG_SERDES_ADDR_RDY, 0); 619252206Sdavidcs 620252206Sdavidcs if (ret) 621252206Sdavidcs goto exit_qls_rd_serdes_reg; 622252206Sdavidcs 623252206Sdavidcs *data = READ_REG32(ha, Q81_CTL_XG_SERDES_DATA); 624252206Sdavidcs 625252206Sdavidcsexit_qls_rd_serdes_reg: 626252206Sdavidcs 627252206Sdavidcs return ret; 628252206Sdavidcs} 629252206Sdavidcs 630252206Sdavidcsstatic void 631252206Sdavidcsqls_get_both_serdes(qla_host_t *ha, uint32_t addr, uint32_t *dptr, 632252206Sdavidcs uint32_t *ind_ptr, uint32_t dvalid, uint32_t ind_valid) 633252206Sdavidcs{ 634252206Sdavidcs int ret = -1; 635252206Sdavidcs 636252206Sdavidcs if (dvalid) 637252206Sdavidcs ret = qls_rd_serdes_reg(ha, addr, dptr); 638252206Sdavidcs 639252206Sdavidcs if (ret) 640252206Sdavidcs *dptr = Q81_BAD_DATA; 641252206Sdavidcs 642252206Sdavidcs ret = -1; 643252206Sdavidcs 644252206Sdavidcs if(ind_valid) 645252206Sdavidcs ret = qls_rd_ofunc_serdes_reg(ha, addr, ind_ptr); 646252206Sdavidcs 647252206Sdavidcs if (ret) 648252206Sdavidcs *ind_ptr = Q81_BAD_DATA; 649252206Sdavidcs} 650252206Sdavidcs 651252206Sdavidcs#define Q81_XFI1_POWERED_UP 0x00000005 652252206Sdavidcs#define Q81_XFI2_POWERED_UP 0x0000000A 653252206Sdavidcs#define Q81_XAUI_POWERED_UP 0x00000001 654252206Sdavidcs 655252206Sdavidcsstatic int 656252206Sdavidcsqls_rd_serdes_regs(qla_host_t *ha, qls_mpi_coredump_t *mpi_dump) 657252206Sdavidcs{ 658252206Sdavidcs int ret; 659252206Sdavidcs uint32_t xfi_d_valid, xfi_ind_valid, xaui_d_valid, xaui_ind_valid; 660252206Sdavidcs uint32_t temp, xaui_reg, i; 661252206Sdavidcs uint32_t *dptr, *indptr; 662252206Sdavidcs 663252206Sdavidcs xfi_d_valid = xfi_ind_valid = xaui_d_valid = xaui_ind_valid = 0; 664252206Sdavidcs 665252206Sdavidcs xaui_reg = 0x800; 666252206Sdavidcs 667252206Sdavidcs ret = qls_rd_ofunc_serdes_reg(ha, xaui_reg, &temp); 668252206Sdavidcs if (ret) 669252206Sdavidcs temp = 0; 670252206Sdavidcs 671252206Sdavidcs if ((temp & Q81_XAUI_POWERED_UP) == Q81_XAUI_POWERED_UP) 672252206Sdavidcs xaui_ind_valid = 1; 673252206Sdavidcs 674252206Sdavidcs ret = qls_rd_serdes_reg(ha, xaui_reg, &temp); 675252206Sdavidcs if (ret) 676252206Sdavidcs temp = 0; 677252206Sdavidcs 678252206Sdavidcs if ((temp & Q81_XAUI_POWERED_UP) == Q81_XAUI_POWERED_UP) 679252206Sdavidcs xaui_d_valid = 1; 680252206Sdavidcs 681252206Sdavidcs ret = qls_rd_serdes_reg(ha, 0x1E06, &temp); 682252206Sdavidcs if (ret) 683252206Sdavidcs temp = 0; 684252206Sdavidcs 685252206Sdavidcs if ((temp & Q81_XFI1_POWERED_UP) == Q81_XFI1_POWERED_UP) { 686252206Sdavidcs 687252206Sdavidcs if (ha->pci_func & 1) 688252206Sdavidcs xfi_ind_valid = 1; /* NIC 2, so the indirect 689252206Sdavidcs (NIC1) xfi is up*/ 690252206Sdavidcs else 691252206Sdavidcs xfi_d_valid = 1; 692252206Sdavidcs } 693252206Sdavidcs 694252206Sdavidcs if((temp & Q81_XFI2_POWERED_UP) == Q81_XFI2_POWERED_UP) { 695252206Sdavidcs 696252206Sdavidcs if(ha->pci_func & 1) 697252206Sdavidcs xfi_d_valid = 1; /* NIC 2, so the indirect (NIC1) 698252206Sdavidcs xfi is up */ 699252206Sdavidcs else 700252206Sdavidcs xfi_ind_valid = 1; 701252206Sdavidcs } 702252206Sdavidcs 703252206Sdavidcs if (ha->pci_func & 1) { 704252206Sdavidcs dptr = (uint32_t *)(&mpi_dump->serdes2_xaui_an); 705252206Sdavidcs indptr = (uint32_t *)(&mpi_dump->serdes1_xaui_an); 706252206Sdavidcs } else { 707252206Sdavidcs dptr = (uint32_t *)(&mpi_dump->serdes1_xaui_an); 708252206Sdavidcs indptr = (uint32_t *)(&mpi_dump->serdes2_xaui_an); 709252206Sdavidcs } 710252206Sdavidcs 711252206Sdavidcs for (i = 0; i <= 0x000000034; i += 4, dptr ++, indptr ++) { 712252206Sdavidcs qls_get_both_serdes(ha, i, dptr, indptr, 713252206Sdavidcs xaui_d_valid, xaui_ind_valid); 714252206Sdavidcs } 715252206Sdavidcs 716252206Sdavidcs if (ha->pci_func & 1) { 717252206Sdavidcs dptr = (uint32_t *)(&mpi_dump->serdes2_xaui_hss_pcs); 718252206Sdavidcs indptr = (uint32_t *)(&mpi_dump->serdes1_xaui_hss_pcs); 719252206Sdavidcs } else { 720252206Sdavidcs dptr = (uint32_t *)(&mpi_dump->serdes1_xaui_hss_pcs); 721252206Sdavidcs indptr = (uint32_t *)(&mpi_dump->serdes2_xaui_hss_pcs); 722252206Sdavidcs } 723252206Sdavidcs 724252206Sdavidcs for (i = 0x800; i <= 0x880; i += 4, dptr ++, indptr ++) { 725252206Sdavidcs qls_get_both_serdes(ha, i, dptr, indptr, 726252206Sdavidcs xaui_d_valid, xaui_ind_valid); 727252206Sdavidcs } 728252206Sdavidcs 729252206Sdavidcs if (ha->pci_func & 1) { 730252206Sdavidcs dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_an); 731252206Sdavidcs indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_an); 732252206Sdavidcs } else { 733252206Sdavidcs dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_an); 734252206Sdavidcs indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_an); 735252206Sdavidcs } 736252206Sdavidcs 737252206Sdavidcs for (i = 0x1000; i <= 0x1034; i += 4, dptr ++, indptr ++) { 738252206Sdavidcs qls_get_both_serdes(ha, i, dptr, indptr, 739252206Sdavidcs xfi_d_valid, xfi_ind_valid); 740252206Sdavidcs } 741252206Sdavidcs 742252206Sdavidcs if (ha->pci_func & 1) { 743252206Sdavidcs dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_train); 744252206Sdavidcs indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_train); 745252206Sdavidcs } else { 746252206Sdavidcs dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_train); 747252206Sdavidcs indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_train); 748252206Sdavidcs } 749252206Sdavidcs 750252206Sdavidcs for (i = 0x1050; i <= 0x107c; i += 4, dptr ++, indptr ++) { 751252206Sdavidcs qls_get_both_serdes(ha, i, dptr, indptr, 752252206Sdavidcs xfi_d_valid, xfi_ind_valid); 753252206Sdavidcs } 754252206Sdavidcs 755252206Sdavidcs if (ha->pci_func & 1) { 756252206Sdavidcs dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pcs); 757252206Sdavidcs indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pcs); 758252206Sdavidcs } else { 759252206Sdavidcs dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pcs); 760252206Sdavidcs indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pcs); 761252206Sdavidcs } 762252206Sdavidcs 763252206Sdavidcs for (i = 0x1800; i <= 0x1838; i += 4, dptr++, indptr ++) { 764252206Sdavidcs qls_get_both_serdes(ha, i, dptr, indptr, 765252206Sdavidcs xfi_d_valid, xfi_ind_valid); 766252206Sdavidcs } 767252206Sdavidcs 768252206Sdavidcs if (ha->pci_func & 1) { 769252206Sdavidcs dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_tx); 770252206Sdavidcs indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_tx); 771252206Sdavidcs } else { 772252206Sdavidcs dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_tx); 773252206Sdavidcs indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_tx); 774252206Sdavidcs } 775252206Sdavidcs 776252206Sdavidcs for (i = 0x1c00; i <= 0x1c1f; i++, dptr ++, indptr ++) { 777252206Sdavidcs qls_get_both_serdes(ha, i, dptr, indptr, 778252206Sdavidcs xfi_d_valid, xfi_ind_valid); 779252206Sdavidcs } 780252206Sdavidcs 781252206Sdavidcs if (ha->pci_func & 1) { 782252206Sdavidcs dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_rx); 783252206Sdavidcs indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_rx); 784252206Sdavidcs } else { 785252206Sdavidcs dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_rx); 786252206Sdavidcs indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_rx); 787252206Sdavidcs } 788252206Sdavidcs 789252206Sdavidcs for (i = 0x1c40; i <= 0x1c5f; i++, dptr ++, indptr ++) { 790252206Sdavidcs qls_get_both_serdes(ha, i, dptr, indptr, 791252206Sdavidcs xfi_d_valid, xfi_ind_valid); 792252206Sdavidcs } 793252206Sdavidcs 794252206Sdavidcs if (ha->pci_func & 1) { 795252206Sdavidcs dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pll); 796252206Sdavidcs indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pll); 797252206Sdavidcs } else { 798252206Sdavidcs dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pll); 799252206Sdavidcs indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pll); 800252206Sdavidcs } 801252206Sdavidcs 802252206Sdavidcs for (i = 0x1e00; i <= 0x1e1f; i++, dptr ++, indptr ++) { 803252206Sdavidcs qls_get_both_serdes(ha, i, dptr, indptr, 804252206Sdavidcs xfi_d_valid, xfi_ind_valid); 805252206Sdavidcs } 806252206Sdavidcs 807252206Sdavidcs return(0); 808252206Sdavidcs} 809252206Sdavidcs 810252206Sdavidcsstatic int 811252206Sdavidcsqls_unpause_mpi_risc(qla_host_t *ha) 812252206Sdavidcs{ 813252206Sdavidcs uint32_t data; 814252206Sdavidcs 815252206Sdavidcs data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS); 816252206Sdavidcs 817252206Sdavidcs if (!(data & Q81_CTL_HCS_RISC_PAUSED)) 818252206Sdavidcs return -1; 819252206Sdavidcs 820252206Sdavidcs WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \ 821252206Sdavidcs Q81_CTL_HCS_CMD_CLR_RISC_PAUSE); 822252206Sdavidcs 823252206Sdavidcs return 0; 824252206Sdavidcs} 825252206Sdavidcs 826252206Sdavidcsstatic int 827252206Sdavidcsqls_pause_mpi_risc(qla_host_t *ha) 828252206Sdavidcs{ 829252206Sdavidcs uint32_t data; 830252206Sdavidcs int count = 10; 831252206Sdavidcs 832252206Sdavidcs WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \ 833252206Sdavidcs Q81_CTL_HCS_CMD_SET_RISC_PAUSE); 834252206Sdavidcs 835252206Sdavidcs do { 836252206Sdavidcs data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS); 837252206Sdavidcs 838252206Sdavidcs if (data & Q81_CTL_HCS_RISC_PAUSED) 839252206Sdavidcs break; 840252206Sdavidcs 841252206Sdavidcs qls_mdelay(__func__, 10); 842252206Sdavidcs 843252206Sdavidcs count--; 844252206Sdavidcs 845252206Sdavidcs } while (count); 846252206Sdavidcs 847252206Sdavidcs return ((count == 0) ? -1 : 0); 848252206Sdavidcs} 849252206Sdavidcs 850252206Sdavidcsstatic void 851252206Sdavidcsqls_get_intr_states(qla_host_t *ha, uint32_t *buf) 852252206Sdavidcs{ 853252206Sdavidcs int i; 854252206Sdavidcs 855252206Sdavidcs for (i = 0; i < MAX_RX_RINGS; i++, buf++) { 856252206Sdavidcs 857252206Sdavidcs WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (0x037f0300 + i)); 858252206Sdavidcs 859252206Sdavidcs *buf = READ_REG32(ha, Q81_CTL_INTR_ENABLE); 860252206Sdavidcs } 861252206Sdavidcs} 862252206Sdavidcs 863252206Sdavidcsstatic int 864252206Sdavidcsqls_rd_xgmac_reg(qla_host_t *ha, uint32_t reg, uint32_t*data) 865252206Sdavidcs{ 866252206Sdavidcs int ret = 0; 867252206Sdavidcs 868252206Sdavidcs ret = qls_wait_reg_rdy(ha, Q81_CTL_XGMAC_ADDR, Q81_XGMAC_ADDR_RDY, 869252206Sdavidcs Q81_XGMAC_ADDR_XME); 870252206Sdavidcs if (ret) 871252206Sdavidcs goto exit_qls_rd_xgmac_reg; 872252206Sdavidcs 873252206Sdavidcs WRITE_REG32(ha, Q81_CTL_XGMAC_ADDR, (reg | Q81_XGMAC_ADDR_R)); 874252206Sdavidcs 875252206Sdavidcs ret = qls_wait_reg_rdy(ha, Q81_CTL_XGMAC_ADDR, Q81_XGMAC_ADDR_RDY, 876252206Sdavidcs Q81_XGMAC_ADDR_XME); 877252206Sdavidcs if (ret) 878252206Sdavidcs goto exit_qls_rd_xgmac_reg; 879252206Sdavidcs 880252206Sdavidcs *data = READ_REG32(ha, Q81_CTL_XGMAC_DATA); 881252206Sdavidcs 882252206Sdavidcsexit_qls_rd_xgmac_reg: 883252206Sdavidcs return ret; 884252206Sdavidcs} 885252206Sdavidcs 886252206Sdavidcsstatic int 887252206Sdavidcsqls_rd_xgmac_regs(qla_host_t *ha, uint32_t *buf, uint32_t o_func) 888252206Sdavidcs{ 889252206Sdavidcs int ret = 0; 890252206Sdavidcs int i; 891252206Sdavidcs 892252206Sdavidcs for (i = 0; i < Q81_XGMAC_REGISTER_END; i += 4, buf ++) { 893252206Sdavidcs 894252206Sdavidcs switch (i) { 895252206Sdavidcs case Q81_PAUSE_SRC_LO : 896252206Sdavidcs case Q81_PAUSE_SRC_HI : 897252206Sdavidcs case Q81_GLOBAL_CFG : 898252206Sdavidcs case Q81_TX_CFG : 899252206Sdavidcs case Q81_RX_CFG : 900252206Sdavidcs case Q81_FLOW_CTL : 901252206Sdavidcs case Q81_PAUSE_OPCODE : 902252206Sdavidcs case Q81_PAUSE_TIMER : 903252206Sdavidcs case Q81_PAUSE_FRM_DEST_LO : 904252206Sdavidcs case Q81_PAUSE_FRM_DEST_HI : 905252206Sdavidcs case Q81_MAC_TX_PARAMS : 906252206Sdavidcs case Q81_MAC_RX_PARAMS : 907252206Sdavidcs case Q81_MAC_SYS_INT : 908252206Sdavidcs case Q81_MAC_SYS_INT_MASK : 909252206Sdavidcs case Q81_MAC_MGMT_INT : 910252206Sdavidcs case Q81_MAC_MGMT_IN_MASK : 911252206Sdavidcs case Q81_EXT_ARB_MODE : 912252206Sdavidcs case Q81_TX_PKTS : 913252206Sdavidcs case Q81_TX_PKTS_LO : 914252206Sdavidcs case Q81_TX_BYTES : 915252206Sdavidcs case Q81_TX_BYTES_LO : 916252206Sdavidcs case Q81_TX_MCAST_PKTS : 917252206Sdavidcs case Q81_TX_MCAST_PKTS_LO : 918252206Sdavidcs case Q81_TX_BCAST_PKTS : 919252206Sdavidcs case Q81_TX_BCAST_PKTS_LO : 920252206Sdavidcs case Q81_TX_UCAST_PKTS : 921252206Sdavidcs case Q81_TX_UCAST_PKTS_LO : 922252206Sdavidcs case Q81_TX_CTL_PKTS : 923252206Sdavidcs case Q81_TX_CTL_PKTS_LO : 924252206Sdavidcs case Q81_TX_PAUSE_PKTS : 925252206Sdavidcs case Q81_TX_PAUSE_PKTS_LO : 926252206Sdavidcs case Q81_TX_64_PKT : 927252206Sdavidcs case Q81_TX_64_PKT_LO : 928252206Sdavidcs case Q81_TX_65_TO_127_PKT : 929252206Sdavidcs case Q81_TX_65_TO_127_PKT_LO : 930252206Sdavidcs case Q81_TX_128_TO_255_PKT : 931252206Sdavidcs case Q81_TX_128_TO_255_PKT_LO : 932252206Sdavidcs case Q81_TX_256_511_PKT : 933252206Sdavidcs case Q81_TX_256_511_PKT_LO : 934252206Sdavidcs case Q81_TX_512_TO_1023_PKT : 935252206Sdavidcs case Q81_TX_512_TO_1023_PKT_LO : 936252206Sdavidcs case Q81_TX_1024_TO_1518_PKT : 937252206Sdavidcs case Q81_TX_1024_TO_1518_PKT_LO : 938252206Sdavidcs case Q81_TX_1519_TO_MAX_PKT : 939252206Sdavidcs case Q81_TX_1519_TO_MAX_PKT_LO : 940252206Sdavidcs case Q81_TX_UNDERSIZE_PKT : 941252206Sdavidcs case Q81_TX_UNDERSIZE_PKT_LO : 942252206Sdavidcs case Q81_TX_OVERSIZE_PKT : 943252206Sdavidcs case Q81_TX_OVERSIZE_PKT_LO : 944252206Sdavidcs case Q81_RX_HALF_FULL_DET : 945252206Sdavidcs case Q81_TX_HALF_FULL_DET_LO : 946252206Sdavidcs case Q81_RX_OVERFLOW_DET : 947252206Sdavidcs case Q81_TX_OVERFLOW_DET_LO : 948252206Sdavidcs case Q81_RX_HALF_FULL_MASK : 949252206Sdavidcs case Q81_TX_HALF_FULL_MASK_LO : 950252206Sdavidcs case Q81_RX_OVERFLOW_MASK : 951252206Sdavidcs case Q81_TX_OVERFLOW_MASK_LO : 952252206Sdavidcs case Q81_STAT_CNT_CTL : 953252206Sdavidcs case Q81_AUX_RX_HALF_FULL_DET : 954252206Sdavidcs case Q81_AUX_TX_HALF_FULL_DET : 955252206Sdavidcs case Q81_AUX_RX_OVERFLOW_DET : 956252206Sdavidcs case Q81_AUX_TX_OVERFLOW_DET : 957252206Sdavidcs case Q81_AUX_RX_HALF_FULL_MASK : 958252206Sdavidcs case Q81_AUX_TX_HALF_FULL_MASK : 959252206Sdavidcs case Q81_AUX_RX_OVERFLOW_MASK : 960252206Sdavidcs case Q81_AUX_TX_OVERFLOW_MASK : 961252206Sdavidcs case Q81_RX_BYTES : 962252206Sdavidcs case Q81_RX_BYTES_LO : 963252206Sdavidcs case Q81_RX_BYTES_OK : 964252206Sdavidcs case Q81_RX_BYTES_OK_LO : 965252206Sdavidcs case Q81_RX_PKTS : 966252206Sdavidcs case Q81_RX_PKTS_LO : 967252206Sdavidcs case Q81_RX_PKTS_OK : 968252206Sdavidcs case Q81_RX_PKTS_OK_LO : 969252206Sdavidcs case Q81_RX_BCAST_PKTS : 970252206Sdavidcs case Q81_RX_BCAST_PKTS_LO : 971252206Sdavidcs case Q81_RX_MCAST_PKTS : 972252206Sdavidcs case Q81_RX_MCAST_PKTS_LO : 973252206Sdavidcs case Q81_RX_UCAST_PKTS : 974252206Sdavidcs case Q81_RX_UCAST_PKTS_LO : 975252206Sdavidcs case Q81_RX_UNDERSIZE_PKTS : 976252206Sdavidcs case Q81_RX_UNDERSIZE_PKTS_LO : 977252206Sdavidcs case Q81_RX_OVERSIZE_PKTS : 978252206Sdavidcs case Q81_RX_OVERSIZE_PKTS_LO : 979252206Sdavidcs case Q81_RX_JABBER_PKTS : 980252206Sdavidcs case Q81_RX_JABBER_PKTS_LO : 981252206Sdavidcs case Q81_RX_UNDERSIZE_FCERR_PKTS : 982252206Sdavidcs case Q81_RX_UNDERSIZE_FCERR_PKTS_LO : 983252206Sdavidcs case Q81_RX_DROP_EVENTS : 984252206Sdavidcs case Q81_RX_DROP_EVENTS_LO : 985252206Sdavidcs case Q81_RX_FCERR_PKTS : 986252206Sdavidcs case Q81_RX_FCERR_PKTS_LO : 987252206Sdavidcs case Q81_RX_ALIGN_ERR : 988252206Sdavidcs case Q81_RX_ALIGN_ERR_LO : 989252206Sdavidcs case Q81_RX_SYMBOL_ERR : 990252206Sdavidcs case Q81_RX_SYMBOL_ERR_LO : 991252206Sdavidcs case Q81_RX_MAC_ERR : 992252206Sdavidcs case Q81_RX_MAC_ERR_LO : 993252206Sdavidcs case Q81_RX_CTL_PKTS : 994252206Sdavidcs case Q81_RX_CTL_PKTS_LO : 995252206Sdavidcs case Q81_RX_PAUSE_PKTS : 996252206Sdavidcs case Q81_RX_PAUSE_PKTS_LO : 997252206Sdavidcs case Q81_RX_64_PKTS : 998252206Sdavidcs case Q81_RX_64_PKTS_LO : 999252206Sdavidcs case Q81_RX_65_TO_127_PKTS : 1000252206Sdavidcs case Q81_RX_65_TO_127_PKTS_LO : 1001252206Sdavidcs case Q81_RX_128_255_PKTS : 1002252206Sdavidcs case Q81_RX_128_255_PKTS_LO : 1003252206Sdavidcs case Q81_RX_256_511_PKTS : 1004252206Sdavidcs case Q81_RX_256_511_PKTS_LO : 1005252206Sdavidcs case Q81_RX_512_TO_1023_PKTS : 1006252206Sdavidcs case Q81_RX_512_TO_1023_PKTS_LO : 1007252206Sdavidcs case Q81_RX_1024_TO_1518_PKTS : 1008252206Sdavidcs case Q81_RX_1024_TO_1518_PKTS_LO : 1009252206Sdavidcs case Q81_RX_1519_TO_MAX_PKTS : 1010252206Sdavidcs case Q81_RX_1519_TO_MAX_PKTS_LO : 1011252206Sdavidcs case Q81_RX_LEN_ERR_PKTS : 1012252206Sdavidcs case Q81_RX_LEN_ERR_PKTS_LO : 1013252206Sdavidcs case Q81_MDIO_TX_DATA : 1014252206Sdavidcs case Q81_MDIO_RX_DATA : 1015252206Sdavidcs case Q81_MDIO_CMD : 1016252206Sdavidcs case Q81_MDIO_PHY_ADDR : 1017252206Sdavidcs case Q81_MDIO_PORT : 1018252206Sdavidcs case Q81_MDIO_STATUS : 1019252206Sdavidcs case Q81_TX_CBFC_PAUSE_FRAMES0 : 1020252206Sdavidcs case Q81_TX_CBFC_PAUSE_FRAMES0_LO : 1021252206Sdavidcs case Q81_TX_CBFC_PAUSE_FRAMES1 : 1022252206Sdavidcs case Q81_TX_CBFC_PAUSE_FRAMES1_LO : 1023252206Sdavidcs case Q81_TX_CBFC_PAUSE_FRAMES2 : 1024252206Sdavidcs case Q81_TX_CBFC_PAUSE_FRAMES2_LO : 1025252206Sdavidcs case Q81_TX_CBFC_PAUSE_FRAMES3 : 1026252206Sdavidcs case Q81_TX_CBFC_PAUSE_FRAMES3_LO : 1027252206Sdavidcs case Q81_TX_CBFC_PAUSE_FRAMES4 : 1028252206Sdavidcs case Q81_TX_CBFC_PAUSE_FRAMES4_LO : 1029252206Sdavidcs case Q81_TX_CBFC_PAUSE_FRAMES5 : 1030252206Sdavidcs case Q81_TX_CBFC_PAUSE_FRAMES5_LO : 1031252206Sdavidcs case Q81_TX_CBFC_PAUSE_FRAMES6 : 1032252206Sdavidcs case Q81_TX_CBFC_PAUSE_FRAMES6_LO : 1033252206Sdavidcs case Q81_TX_CBFC_PAUSE_FRAMES7 : 1034252206Sdavidcs case Q81_TX_CBFC_PAUSE_FRAMES7_LO : 1035252206Sdavidcs case Q81_TX_FCOE_PKTS : 1036252206Sdavidcs case Q81_TX_FCOE_PKTS_LO : 1037252206Sdavidcs case Q81_TX_MGMT_PKTS : 1038252206Sdavidcs case Q81_TX_MGMT_PKTS_LO : 1039252206Sdavidcs case Q81_RX_CBFC_PAUSE_FRAMES0 : 1040252206Sdavidcs case Q81_RX_CBFC_PAUSE_FRAMES0_LO : 1041252206Sdavidcs case Q81_RX_CBFC_PAUSE_FRAMES1 : 1042252206Sdavidcs case Q81_RX_CBFC_PAUSE_FRAMES1_LO : 1043252206Sdavidcs case Q81_RX_CBFC_PAUSE_FRAMES2 : 1044252206Sdavidcs case Q81_RX_CBFC_PAUSE_FRAMES2_LO : 1045252206Sdavidcs case Q81_RX_CBFC_PAUSE_FRAMES3 : 1046252206Sdavidcs case Q81_RX_CBFC_PAUSE_FRAMES3_LO : 1047252206Sdavidcs case Q81_RX_CBFC_PAUSE_FRAMES4 : 1048252206Sdavidcs case Q81_RX_CBFC_PAUSE_FRAMES4_LO : 1049252206Sdavidcs case Q81_RX_CBFC_PAUSE_FRAMES5 : 1050252206Sdavidcs case Q81_RX_CBFC_PAUSE_FRAMES5_LO : 1051252206Sdavidcs case Q81_RX_CBFC_PAUSE_FRAMES6 : 1052252206Sdavidcs case Q81_RX_CBFC_PAUSE_FRAMES6_LO : 1053252206Sdavidcs case Q81_RX_CBFC_PAUSE_FRAMES7 : 1054252206Sdavidcs case Q81_RX_CBFC_PAUSE_FRAMES7_LO : 1055252206Sdavidcs case Q81_RX_FCOE_PKTS : 1056252206Sdavidcs case Q81_RX_FCOE_PKTS_LO : 1057252206Sdavidcs case Q81_RX_MGMT_PKTS : 1058252206Sdavidcs case Q81_RX_MGMT_PKTS_LO : 1059252206Sdavidcs case Q81_RX_NIC_FIFO_DROP : 1060252206Sdavidcs case Q81_RX_NIC_FIFO_DROP_LO : 1061252206Sdavidcs case Q81_RX_FCOE_FIFO_DROP : 1062252206Sdavidcs case Q81_RX_FCOE_FIFO_DROP_LO : 1063252206Sdavidcs case Q81_RX_MGMT_FIFO_DROP : 1064252206Sdavidcs case Q81_RX_MGMT_FIFO_DROP_LO : 1065252206Sdavidcs case Q81_RX_PKTS_PRIORITY0 : 1066252206Sdavidcs case Q81_RX_PKTS_PRIORITY0_LO : 1067252206Sdavidcs case Q81_RX_PKTS_PRIORITY1 : 1068252206Sdavidcs case Q81_RX_PKTS_PRIORITY1_LO : 1069252206Sdavidcs case Q81_RX_PKTS_PRIORITY2 : 1070252206Sdavidcs case Q81_RX_PKTS_PRIORITY2_LO : 1071252206Sdavidcs case Q81_RX_PKTS_PRIORITY3 : 1072252206Sdavidcs case Q81_RX_PKTS_PRIORITY3_LO : 1073252206Sdavidcs case Q81_RX_PKTS_PRIORITY4 : 1074252206Sdavidcs case Q81_RX_PKTS_PRIORITY4_LO : 1075252206Sdavidcs case Q81_RX_PKTS_PRIORITY5 : 1076252206Sdavidcs case Q81_RX_PKTS_PRIORITY5_LO : 1077252206Sdavidcs case Q81_RX_PKTS_PRIORITY6 : 1078252206Sdavidcs case Q81_RX_PKTS_PRIORITY6_LO : 1079252206Sdavidcs case Q81_RX_PKTS_PRIORITY7 : 1080252206Sdavidcs case Q81_RX_PKTS_PRIORITY7_LO : 1081252206Sdavidcs case Q81_RX_OCTETS_PRIORITY0 : 1082252206Sdavidcs case Q81_RX_OCTETS_PRIORITY0_LO : 1083252206Sdavidcs case Q81_RX_OCTETS_PRIORITY1 : 1084252206Sdavidcs case Q81_RX_OCTETS_PRIORITY1_LO : 1085252206Sdavidcs case Q81_RX_OCTETS_PRIORITY2 : 1086252206Sdavidcs case Q81_RX_OCTETS_PRIORITY2_LO : 1087252206Sdavidcs case Q81_RX_OCTETS_PRIORITY3 : 1088252206Sdavidcs case Q81_RX_OCTETS_PRIORITY3_LO : 1089252206Sdavidcs case Q81_RX_OCTETS_PRIORITY4 : 1090252206Sdavidcs case Q81_RX_OCTETS_PRIORITY4_LO : 1091252206Sdavidcs case Q81_RX_OCTETS_PRIORITY5 : 1092252206Sdavidcs case Q81_RX_OCTETS_PRIORITY5_LO : 1093252206Sdavidcs case Q81_RX_OCTETS_PRIORITY6 : 1094252206Sdavidcs case Q81_RX_OCTETS_PRIORITY6_LO : 1095252206Sdavidcs case Q81_RX_OCTETS_PRIORITY7 : 1096252206Sdavidcs case Q81_RX_OCTETS_PRIORITY7_LO : 1097252206Sdavidcs case Q81_TX_PKTS_PRIORITY0 : 1098252206Sdavidcs case Q81_TX_PKTS_PRIORITY0_LO : 1099252206Sdavidcs case Q81_TX_PKTS_PRIORITY1 : 1100252206Sdavidcs case Q81_TX_PKTS_PRIORITY1_LO : 1101252206Sdavidcs case Q81_TX_PKTS_PRIORITY2 : 1102252206Sdavidcs case Q81_TX_PKTS_PRIORITY2_LO : 1103252206Sdavidcs case Q81_TX_PKTS_PRIORITY3 : 1104252206Sdavidcs case Q81_TX_PKTS_PRIORITY3_LO : 1105252206Sdavidcs case Q81_TX_PKTS_PRIORITY4 : 1106252206Sdavidcs case Q81_TX_PKTS_PRIORITY4_LO : 1107252206Sdavidcs case Q81_TX_PKTS_PRIORITY5 : 1108252206Sdavidcs case Q81_TX_PKTS_PRIORITY5_LO : 1109252206Sdavidcs case Q81_TX_PKTS_PRIORITY6 : 1110252206Sdavidcs case Q81_TX_PKTS_PRIORITY6_LO : 1111252206Sdavidcs case Q81_TX_PKTS_PRIORITY7 : 1112252206Sdavidcs case Q81_TX_PKTS_PRIORITY7_LO : 1113252206Sdavidcs case Q81_TX_OCTETS_PRIORITY0 : 1114252206Sdavidcs case Q81_TX_OCTETS_PRIORITY0_LO : 1115252206Sdavidcs case Q81_TX_OCTETS_PRIORITY1 : 1116252206Sdavidcs case Q81_TX_OCTETS_PRIORITY1_LO : 1117252206Sdavidcs case Q81_TX_OCTETS_PRIORITY2 : 1118252206Sdavidcs case Q81_TX_OCTETS_PRIORITY2_LO : 1119252206Sdavidcs case Q81_TX_OCTETS_PRIORITY3 : 1120252206Sdavidcs case Q81_TX_OCTETS_PRIORITY3_LO : 1121252206Sdavidcs case Q81_TX_OCTETS_PRIORITY4 : 1122252206Sdavidcs case Q81_TX_OCTETS_PRIORITY4_LO : 1123252206Sdavidcs case Q81_TX_OCTETS_PRIORITY5 : 1124252206Sdavidcs case Q81_TX_OCTETS_PRIORITY5_LO : 1125252206Sdavidcs case Q81_TX_OCTETS_PRIORITY6 : 1126252206Sdavidcs case Q81_TX_OCTETS_PRIORITY6_LO : 1127252206Sdavidcs case Q81_TX_OCTETS_PRIORITY7 : 1128252206Sdavidcs case Q81_TX_OCTETS_PRIORITY7_LO : 1129252206Sdavidcs case Q81_RX_DISCARD_PRIORITY0 : 1130252206Sdavidcs case Q81_RX_DISCARD_PRIORITY0_LO : 1131252206Sdavidcs case Q81_RX_DISCARD_PRIORITY1 : 1132252206Sdavidcs case Q81_RX_DISCARD_PRIORITY1_LO : 1133252206Sdavidcs case Q81_RX_DISCARD_PRIORITY2 : 1134252206Sdavidcs case Q81_RX_DISCARD_PRIORITY2_LO : 1135252206Sdavidcs case Q81_RX_DISCARD_PRIORITY3 : 1136252206Sdavidcs case Q81_RX_DISCARD_PRIORITY3_LO : 1137252206Sdavidcs case Q81_RX_DISCARD_PRIORITY4 : 1138252206Sdavidcs case Q81_RX_DISCARD_PRIORITY4_LO : 1139252206Sdavidcs case Q81_RX_DISCARD_PRIORITY5 : 1140252206Sdavidcs case Q81_RX_DISCARD_PRIORITY5_LO : 1141252206Sdavidcs case Q81_RX_DISCARD_PRIORITY6 : 1142252206Sdavidcs case Q81_RX_DISCARD_PRIORITY6_LO : 1143252206Sdavidcs case Q81_RX_DISCARD_PRIORITY7 : 1144252206Sdavidcs case Q81_RX_DISCARD_PRIORITY7_LO : 1145252206Sdavidcs 1146252206Sdavidcs if (o_func) 1147252206Sdavidcs ret = qls_rd_ofunc_xgmac_reg(ha, 1148252206Sdavidcs i, buf); 1149252206Sdavidcs else 1150252206Sdavidcs ret = qls_rd_xgmac_reg(ha, i, buf); 1151252206Sdavidcs 1152252206Sdavidcs if (ret) 1153252206Sdavidcs *buf = Q81_BAD_DATA; 1154252206Sdavidcs 1155252206Sdavidcs break; 1156252206Sdavidcs 1157252206Sdavidcs default: 1158252206Sdavidcs break; 1159252206Sdavidcs 1160252206Sdavidcs } 1161252206Sdavidcs } 1162252206Sdavidcs return 0; 1163252206Sdavidcs} 1164252206Sdavidcs 1165252206Sdavidcsstatic int 1166252206Sdavidcsqls_get_mpi_regs(qla_host_t *ha, uint32_t *buf, uint32_t offset, uint32_t count) 1167252206Sdavidcs{ 1168252206Sdavidcs int i, ret = 0; 1169252206Sdavidcs 1170252206Sdavidcs for (i = 0; i < count; i++, buf++) { 1171252206Sdavidcs 1172252206Sdavidcs ret = qls_rd_mpi_reg(ha, (offset + i), buf); 1173252206Sdavidcs 1174252206Sdavidcs if (ret) 1175252206Sdavidcs return ret; 1176252206Sdavidcs } 1177252206Sdavidcs 1178252206Sdavidcs return (ret); 1179252206Sdavidcs} 1180252206Sdavidcs 1181252206Sdavidcsstatic int 1182252206Sdavidcsqls_get_mpi_shadow_regs(qla_host_t *ha, uint32_t *buf) 1183252206Sdavidcs{ 1184252206Sdavidcs uint32_t i; 1185252206Sdavidcs int ret; 1186252206Sdavidcs 1187252206Sdavidcs#define Q81_RISC_124 0x0000007c 1188252206Sdavidcs#define Q81_RISC_127 0x0000007f 1189252206Sdavidcs#define Q81_SHADOW_OFFSET 0xb0000000 1190252206Sdavidcs 1191252206Sdavidcs for (i = 0; i < Q81_MPI_CORE_SH_REGS_CNT; i++, buf++) { 1192252206Sdavidcs 1193252206Sdavidcs ret = qls_wr_mpi_reg(ha, 1194252206Sdavidcs (Q81_CTL_PROC_ADDR_RISC_INT_REG | Q81_RISC_124), 1195252206Sdavidcs (Q81_SHADOW_OFFSET | i << 20)); 1196252206Sdavidcs if (ret) 1197252206Sdavidcs goto exit_qls_get_mpi_shadow_regs; 1198252206Sdavidcs 1199252206Sdavidcs ret = qls_mpi_risc_rd_reg(ha, 1200252206Sdavidcs (Q81_CTL_PROC_ADDR_RISC_INT_REG | Q81_RISC_127), 1201252206Sdavidcs buf); 1202252206Sdavidcs if (ret) 1203252206Sdavidcs goto exit_qls_get_mpi_shadow_regs; 1204252206Sdavidcs } 1205252206Sdavidcs 1206252206Sdavidcsexit_qls_get_mpi_shadow_regs: 1207252206Sdavidcs return ret; 1208252206Sdavidcs} 1209252206Sdavidcs 1210252206Sdavidcs#define SYS_CLOCK (0x00) 1211252206Sdavidcs#define PCI_CLOCK (0x80) 1212252206Sdavidcs#define FC_CLOCK (0x140) 1213252206Sdavidcs#define XGM_CLOCK (0x180) 1214252206Sdavidcs 1215252206Sdavidcs#define Q81_ADDRESS_REGISTER_ENABLE 0x00010000 1216252206Sdavidcs#define Q81_UP 0x00008000 1217252206Sdavidcs#define Q81_MAX_MUX 0x40 1218252206Sdavidcs#define Q81_MAX_MODULES 0x1F 1219252206Sdavidcs 1220252206Sdavidcsstatic uint32_t * 1221252206Sdavidcsqls_get_probe(qla_host_t *ha, uint32_t clock, uint8_t *valid, uint32_t *buf) 1222252206Sdavidcs{ 1223252206Sdavidcs uint32_t module, mux_sel, probe, lo_val, hi_val; 1224252206Sdavidcs 1225252206Sdavidcs for (module = 0; module < Q81_MAX_MODULES; module ++) { 1226252206Sdavidcs 1227252206Sdavidcs if (valid[module]) { 1228252206Sdavidcs 1229252206Sdavidcs for (mux_sel = 0; mux_sel < Q81_MAX_MUX; mux_sel++) { 1230252206Sdavidcs 1231252206Sdavidcs probe = clock | Q81_ADDRESS_REGISTER_ENABLE | 1232252206Sdavidcs mux_sel | (module << 9); 1233252206Sdavidcs WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\ 1234252206Sdavidcs probe); 1235252206Sdavidcs 1236252206Sdavidcs lo_val = READ_REG32(ha,\ 1237252206Sdavidcs Q81_CTL_XG_PROBE_MUX_DATA); 1238252206Sdavidcs 1239252206Sdavidcs if (mux_sel == 0) { 1240252206Sdavidcs *buf = probe; 1241252206Sdavidcs buf ++; 1242252206Sdavidcs } 1243252206Sdavidcs 1244252206Sdavidcs probe |= Q81_UP; 1245252206Sdavidcs 1246252206Sdavidcs WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\ 1247252206Sdavidcs probe); 1248252206Sdavidcs hi_val = READ_REG32(ha,\ 1249252206Sdavidcs Q81_CTL_XG_PROBE_MUX_DATA); 1250252206Sdavidcs 1251252206Sdavidcs *buf = lo_val; 1252252206Sdavidcs buf++; 1253252206Sdavidcs *buf = hi_val; 1254252206Sdavidcs buf++; 1255252206Sdavidcs } 1256252206Sdavidcs } 1257252206Sdavidcs } 1258252206Sdavidcs 1259252206Sdavidcs return(buf); 1260252206Sdavidcs} 1261252206Sdavidcs 1262252206Sdavidcsstatic int 1263252206Sdavidcsqls_get_probe_dump(qla_host_t *ha, uint32_t *buf) 1264252206Sdavidcs{ 1265252206Sdavidcs 1266252206Sdavidcs uint8_t sys_clock_valid_modules[0x20] = { 1267252206Sdavidcs 1, // 0x00 1268252206Sdavidcs 1, // 0x01 1269252206Sdavidcs 1, // 0x02 1270252206Sdavidcs 0, // 0x03 1271252206Sdavidcs 1, // 0x04 1272252206Sdavidcs 1, // 0x05 1273252206Sdavidcs 1, // 0x06 1274252206Sdavidcs 1, // 0x07 1275252206Sdavidcs 1, // 0x08 1276252206Sdavidcs 1, // 0x09 1277252206Sdavidcs 1, // 0x0A 1278252206Sdavidcs 1, // 0x0B 1279252206Sdavidcs 1, // 0x0C 1280252206Sdavidcs 1, // 0x0D 1281252206Sdavidcs 1, // 0x0E 1282252206Sdavidcs 0, // 0x0F 1283252206Sdavidcs 1, // 0x10 1284252206Sdavidcs 1, // 0x11 1285252206Sdavidcs 1, // 0x12 1286252206Sdavidcs 1, // 0x13 1287252206Sdavidcs 0, // 0x14 1288252206Sdavidcs 0, // 0x15 1289252206Sdavidcs 0, // 0x16 1290252206Sdavidcs 0, // 0x17 1291252206Sdavidcs 0, // 0x18 1292252206Sdavidcs 0, // 0x19 1293252206Sdavidcs 0, // 0x1A 1294252206Sdavidcs 0, // 0x1B 1295252206Sdavidcs 0, // 0x1C 1296252206Sdavidcs 0, // 0x1D 1297252206Sdavidcs 0, // 0x1E 1298252206Sdavidcs 0 // 0x1F 1299252206Sdavidcs }; 1300252206Sdavidcs 1301252206Sdavidcs 1302252206Sdavidcs uint8_t pci_clock_valid_modules[0x20] = { 1303252206Sdavidcs 1, // 0x00 1304252206Sdavidcs 0, // 0x01 1305252206Sdavidcs 0, // 0x02 1306252206Sdavidcs 0, // 0x03 1307252206Sdavidcs 0, // 0x04 1308252206Sdavidcs 0, // 0x05 1309252206Sdavidcs 1, // 0x06 1310252206Sdavidcs 1, // 0x07 1311252206Sdavidcs 0, // 0x08 1312252206Sdavidcs 0, // 0x09 1313252206Sdavidcs 0, // 0x0A 1314252206Sdavidcs 0, // 0x0B 1315252206Sdavidcs 0, // 0x0C 1316252206Sdavidcs 0, // 0x0D 1317252206Sdavidcs 1, // 0x0E 1318252206Sdavidcs 0, // 0x0F 1319252206Sdavidcs 0, // 0x10 1320252206Sdavidcs 0, // 0x11 1321252206Sdavidcs 0, // 0x12 1322252206Sdavidcs 0, // 0x13 1323252206Sdavidcs 0, // 0x14 1324252206Sdavidcs 0, // 0x15 1325252206Sdavidcs 0, // 0x16 1326252206Sdavidcs 0, // 0x17 1327252206Sdavidcs 0, // 0x18 1328252206Sdavidcs 0, // 0x19 1329252206Sdavidcs 0, // 0x1A 1330252206Sdavidcs 0, // 0x1B 1331252206Sdavidcs 0, // 0x1C 1332252206Sdavidcs 0, // 0x1D 1333252206Sdavidcs 0, // 0x1E 1334252206Sdavidcs 0 // 0x1F 1335252206Sdavidcs }; 1336252206Sdavidcs 1337252206Sdavidcs 1338252206Sdavidcs uint8_t xgm_clock_valid_modules[0x20] = { 1339252206Sdavidcs 1, // 0x00 1340252206Sdavidcs 0, // 0x01 1341252206Sdavidcs 0, // 0x02 1342252206Sdavidcs 1, // 0x03 1343252206Sdavidcs 0, // 0x04 1344252206Sdavidcs 0, // 0x05 1345252206Sdavidcs 0, // 0x06 1346252206Sdavidcs 0, // 0x07 1347252206Sdavidcs 1, // 0x08 1348252206Sdavidcs 1, // 0x09 1349252206Sdavidcs 0, // 0x0A 1350252206Sdavidcs 0, // 0x0B 1351252206Sdavidcs 1, // 0x0C 1352252206Sdavidcs 1, // 0x0D 1353252206Sdavidcs 1, // 0x0E 1354252206Sdavidcs 0, // 0x0F 1355252206Sdavidcs 1, // 0x10 1356252206Sdavidcs 1, // 0x11 1357252206Sdavidcs 0, // 0x12 1358252206Sdavidcs 0, // 0x13 1359252206Sdavidcs 0, // 0x14 1360252206Sdavidcs 0, // 0x15 1361252206Sdavidcs 0, // 0x16 1362252206Sdavidcs 0, // 0x17 1363252206Sdavidcs 0, // 0x18 1364252206Sdavidcs 0, // 0x19 1365252206Sdavidcs 0, // 0x1A 1366252206Sdavidcs 0, // 0x1B 1367252206Sdavidcs 0, // 0x1C 1368252206Sdavidcs 0, // 0x1D 1369252206Sdavidcs 0, // 0x1E 1370252206Sdavidcs 0 // 0x1F 1371252206Sdavidcs }; 1372252206Sdavidcs 1373252206Sdavidcs uint8_t fc_clock_valid_modules[0x20] = { 1374252206Sdavidcs 1, // 0x00 1375252206Sdavidcs 0, // 0x01 1376252206Sdavidcs 0, // 0x02 1377252206Sdavidcs 0, // 0x03 1378252206Sdavidcs 0, // 0x04 1379252206Sdavidcs 0, // 0x05 1380252206Sdavidcs 0, // 0x06 1381252206Sdavidcs 0, // 0x07 1382252206Sdavidcs 0, // 0x08 1383252206Sdavidcs 0, // 0x09 1384252206Sdavidcs 0, // 0x0A 1385252206Sdavidcs 0, // 0x0B 1386252206Sdavidcs 1, // 0x0C 1387252206Sdavidcs 1, // 0x0D 1388252206Sdavidcs 0, // 0x0E 1389252206Sdavidcs 0, // 0x0F 1390252206Sdavidcs 0, // 0x10 1391252206Sdavidcs 0, // 0x11 1392252206Sdavidcs 0, // 0x12 1393252206Sdavidcs 0, // 0x13 1394252206Sdavidcs 0, // 0x14 1395252206Sdavidcs 0, // 0x15 1396252206Sdavidcs 0, // 0x16 1397252206Sdavidcs 0, // 0x17 1398252206Sdavidcs 0, // 0x18 1399252206Sdavidcs 0, // 0x19 1400252206Sdavidcs 0, // 0x1A 1401252206Sdavidcs 0, // 0x1B 1402252206Sdavidcs 0, // 0x1C 1403252206Sdavidcs 0, // 0x1D 1404252206Sdavidcs 0, // 0x1E 1405252206Sdavidcs 0 // 0x1F 1406252206Sdavidcs }; 1407252206Sdavidcs 1408252206Sdavidcs qls_wr_mpi_reg(ha, 0x100e, 0x18a20000); 1409252206Sdavidcs 1410252206Sdavidcs buf = qls_get_probe(ha, SYS_CLOCK, sys_clock_valid_modules, buf); 1411252206Sdavidcs 1412252206Sdavidcs buf = qls_get_probe(ha, PCI_CLOCK, pci_clock_valid_modules, buf); 1413252206Sdavidcs 1414252206Sdavidcs buf = qls_get_probe(ha, XGM_CLOCK, xgm_clock_valid_modules, buf); 1415252206Sdavidcs 1416252206Sdavidcs buf = qls_get_probe(ha, FC_CLOCK, fc_clock_valid_modules, buf); 1417252206Sdavidcs 1418252206Sdavidcs return(0); 1419252206Sdavidcs} 1420252206Sdavidcs 1421252206Sdavidcsstatic void 1422252206Sdavidcsqls_get_ridx_registers(qla_host_t *ha, uint32_t *buf) 1423252206Sdavidcs{ 1424252206Sdavidcs uint32_t type, idx, idx_max; 1425252206Sdavidcs uint32_t r_idx; 1426252206Sdavidcs uint32_t r_data; 1427252206Sdavidcs uint32_t val; 1428252206Sdavidcs 1429252206Sdavidcs for (type = 0; type < 4; type ++) { 1430252206Sdavidcs if (type < 2) 1431252206Sdavidcs idx_max = 8; 1432252206Sdavidcs else 1433252206Sdavidcs idx_max = 16; 1434252206Sdavidcs 1435252206Sdavidcs for (idx = 0; idx < idx_max; idx ++) { 1436252206Sdavidcs 1437252206Sdavidcs val = 0x04000000 | (type << 16) | (idx << 8); 1438252206Sdavidcs WRITE_REG32(ha, Q81_CTL_ROUTING_INDEX, val); 1439252206Sdavidcs 1440252206Sdavidcs r_idx = 0; 1441252206Sdavidcs while ((r_idx & 0x40000000) == 0) 1442252206Sdavidcs r_idx = READ_REG32(ha, Q81_CTL_ROUTING_INDEX); 1443252206Sdavidcs 1444252206Sdavidcs r_data = READ_REG32(ha, Q81_CTL_ROUTING_DATA); 1445252206Sdavidcs 1446252206Sdavidcs *buf = type; 1447252206Sdavidcs buf ++; 1448252206Sdavidcs *buf = idx; 1449252206Sdavidcs buf ++; 1450252206Sdavidcs *buf = r_idx; 1451252206Sdavidcs buf ++; 1452252206Sdavidcs *buf = r_data; 1453252206Sdavidcs buf ++; 1454252206Sdavidcs } 1455252206Sdavidcs } 1456252206Sdavidcs} 1457252206Sdavidcs 1458252206Sdavidcsstatic void 1459252206Sdavidcsqls_get_mac_proto_regs(qla_host_t *ha, uint32_t* buf) 1460252206Sdavidcs{ 1461252206Sdavidcs 1462252206Sdavidcs#define Q81_RS_AND_ADR 0x06000000 1463252206Sdavidcs#define Q81_RS_ONLY 0x04000000 1464252206Sdavidcs#define Q81_NUM_TYPES 10 1465252206Sdavidcs 1466252206Sdavidcs uint32_t result_index, result_data; 1467252206Sdavidcs uint32_t type; 1468252206Sdavidcs uint32_t index; 1469252206Sdavidcs uint32_t offset; 1470252206Sdavidcs uint32_t val; 1471252206Sdavidcs uint32_t initial_val; 1472252206Sdavidcs uint32_t max_index; 1473252206Sdavidcs uint32_t max_offset; 1474252206Sdavidcs 1475252206Sdavidcs for (type = 0; type < Q81_NUM_TYPES; type ++) { 1476252206Sdavidcs switch (type) { 1477252206Sdavidcs 1478252206Sdavidcs case 0: // CAM 1479252206Sdavidcs initial_val = Q81_RS_AND_ADR; 1480252206Sdavidcs max_index = 512; 1481252206Sdavidcs max_offset = 3; 1482252206Sdavidcs break; 1483252206Sdavidcs 1484252206Sdavidcs case 1: // Multicast MAC Address 1485252206Sdavidcs initial_val = Q81_RS_ONLY; 1486252206Sdavidcs max_index = 32; 1487252206Sdavidcs max_offset = 2; 1488252206Sdavidcs break; 1489252206Sdavidcs 1490252206Sdavidcs case 2: // VLAN filter mask 1491252206Sdavidcs case 3: // MC filter mask 1492252206Sdavidcs initial_val = Q81_RS_ONLY; 1493252206Sdavidcs max_index = 4096; 1494252206Sdavidcs max_offset = 1; 1495252206Sdavidcs break; 1496252206Sdavidcs 1497252206Sdavidcs case 4: // FC MAC addresses 1498252206Sdavidcs initial_val = Q81_RS_ONLY; 1499252206Sdavidcs max_index = 4; 1500252206Sdavidcs max_offset = 2; 1501252206Sdavidcs break; 1502252206Sdavidcs 1503252206Sdavidcs case 5: // Mgmt MAC addresses 1504252206Sdavidcs initial_val = Q81_RS_ONLY; 1505252206Sdavidcs max_index = 8; 1506252206Sdavidcs max_offset = 2; 1507252206Sdavidcs break; 1508252206Sdavidcs 1509252206Sdavidcs case 6: // Mgmt VLAN addresses 1510252206Sdavidcs initial_val = Q81_RS_ONLY; 1511252206Sdavidcs max_index = 16; 1512252206Sdavidcs max_offset = 1; 1513252206Sdavidcs break; 1514252206Sdavidcs 1515252206Sdavidcs case 7: // Mgmt IPv4 address 1516252206Sdavidcs initial_val = Q81_RS_ONLY; 1517252206Sdavidcs max_index = 4; 1518252206Sdavidcs max_offset = 1; 1519252206Sdavidcs break; 1520252206Sdavidcs 1521252206Sdavidcs case 8: // Mgmt IPv6 address 1522252206Sdavidcs initial_val = Q81_RS_ONLY; 1523252206Sdavidcs max_index = 4; 1524252206Sdavidcs max_offset = 4; 1525252206Sdavidcs break; 1526252206Sdavidcs 1527252206Sdavidcs case 9: // Mgmt TCP/UDP Dest port 1528252206Sdavidcs initial_val = Q81_RS_ONLY; 1529252206Sdavidcs max_index = 4; 1530252206Sdavidcs max_offset = 1; 1531252206Sdavidcs break; 1532252206Sdavidcs 1533252206Sdavidcs default: 1534252206Sdavidcs printf("Bad type!!! 0x%08x\n", type); 1535252206Sdavidcs max_index = 0; 1536252206Sdavidcs max_offset = 0; 1537252206Sdavidcs break; 1538252206Sdavidcs } 1539252206Sdavidcs 1540252206Sdavidcs for (index = 0; index < max_index; index ++) { 1541252206Sdavidcs 1542252206Sdavidcs for (offset = 0; offset < max_offset; offset ++) { 1543252206Sdavidcs 1544252206Sdavidcs val = initial_val | (type << 16) | 1545252206Sdavidcs (index << 4) | (offset); 1546252206Sdavidcs 1547252206Sdavidcs WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX,\ 1548252206Sdavidcs val); 1549252206Sdavidcs 1550252206Sdavidcs result_index = 0; 1551252206Sdavidcs 1552252206Sdavidcs while ((result_index & 0x40000000) == 0) 1553252206Sdavidcs result_index = 1554252206Sdavidcs READ_REG32(ha, \ 1555252206Sdavidcs Q81_CTL_MAC_PROTO_ADDR_INDEX); 1556252206Sdavidcs 1557252206Sdavidcs result_data = READ_REG32(ha,\ 1558252206Sdavidcs Q81_CTL_MAC_PROTO_ADDR_DATA); 1559252206Sdavidcs 1560252206Sdavidcs *buf = result_index; 1561252206Sdavidcs buf ++; 1562252206Sdavidcs 1563252206Sdavidcs *buf = result_data; 1564252206Sdavidcs buf ++; 1565252206Sdavidcs } 1566252206Sdavidcs } 1567252206Sdavidcs } 1568252206Sdavidcs} 1569252206Sdavidcs 1570252206Sdavidcsstatic int 1571252206Sdavidcsqls_get_ets_regs(qla_host_t *ha, uint32_t *buf) 1572252206Sdavidcs{ 1573252206Sdavidcs int ret = 0; 1574252206Sdavidcs int i; 1575252206Sdavidcs 1576252206Sdavidcs for(i = 0; i < 8; i ++, buf ++) { 1577252206Sdavidcs WRITE_REG32(ha, Q81_CTL_NIC_ENH_TX_SCHD, \ 1578252206Sdavidcs ((i << 29) | 0x08000000)); 1579252206Sdavidcs *buf = READ_REG32(ha, Q81_CTL_NIC_ENH_TX_SCHD); 1580252206Sdavidcs } 1581252206Sdavidcs 1582252206Sdavidcs for(i = 0; i < 2; i ++, buf ++) { 1583252206Sdavidcs WRITE_REG32(ha, Q81_CTL_CNA_ENH_TX_SCHD, \ 1584252206Sdavidcs ((i << 29) | 0x08000000)); 1585252206Sdavidcs *buf = READ_REG32(ha, Q81_CTL_CNA_ENH_TX_SCHD); 1586252206Sdavidcs } 1587252206Sdavidcs 1588252206Sdavidcs return ret; 1589252206Sdavidcs} 1590252206Sdavidcs 1591252206Sdavidcsint 1592252206Sdavidcsqls_mpi_core_dump(qla_host_t *ha) 1593252206Sdavidcs{ 1594252206Sdavidcs int ret; 1595252206Sdavidcs int i; 1596252206Sdavidcs uint32_t reg, reg_val; 1597252206Sdavidcs 1598252206Sdavidcs qls_mpi_coredump_t *mpi_dump = &ql_mpi_coredump; 1599252206Sdavidcs 1600252206Sdavidcs ret = qls_pause_mpi_risc(ha); 1601252206Sdavidcs if (ret) { 1602252206Sdavidcs printf("Failed RISC pause. Status = 0x%.08x\n",ret); 1603252206Sdavidcs return(-1); 1604252206Sdavidcs } 1605252206Sdavidcs 1606252206Sdavidcs memset(&(mpi_dump->mpi_global_header), 0, 1607252206Sdavidcs sizeof(qls_mpid_glbl_hdr_t)); 1608252206Sdavidcs 1609252206Sdavidcs mpi_dump->mpi_global_header.cookie = Q81_MPID_COOKIE; 1610252206Sdavidcs mpi_dump->mpi_global_header.hdr_size = 1611252206Sdavidcs sizeof(qls_mpid_glbl_hdr_t); 1612252206Sdavidcs mpi_dump->mpi_global_header.img_size = 1613252206Sdavidcs sizeof(qls_mpi_coredump_t); 1614252206Sdavidcs 1615252206Sdavidcs memcpy(mpi_dump->mpi_global_header.id, "MPI Coredump", 1616252206Sdavidcs sizeof(mpi_dump->mpi_global_header.id)); 1617252206Sdavidcs 1618252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->nic1_regs_seg_hdr, 1619252206Sdavidcs Q81_NIC1_CONTROL_SEG_NUM, 1620252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic1_regs)), 1621252206Sdavidcs "NIC1 Registers"); 1622252206Sdavidcs 1623252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->nic2_regs_seg_hdr, 1624252206Sdavidcs Q81_NIC2_CONTROL_SEG_NUM, 1625252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic2_regs)), 1626252206Sdavidcs "NIC2 Registers"); 1627252206Sdavidcs 1628252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->xgmac1_seg_hdr, 1629252206Sdavidcs Q81_NIC1_XGMAC_SEG_NUM, 1630252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->xgmac1)), 1631252206Sdavidcs "NIC1 XGMac Registers"); 1632252206Sdavidcs 1633252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->xgmac2_seg_hdr, 1634252206Sdavidcs Q81_NIC2_XGMAC_SEG_NUM, 1635252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->xgmac2)), 1636252206Sdavidcs "NIC2 XGMac Registers"); 1637252206Sdavidcs 1638252206Sdavidcs if (ha->pci_func & 1) { 1639252206Sdavidcs for (i = 0; i < 64; i++) 1640252206Sdavidcs mpi_dump->nic2_regs[i] = 1641252206Sdavidcs READ_REG32(ha, i * sizeof(uint32_t)); 1642252206Sdavidcs 1643252206Sdavidcs for (i = 0; i < 64; i++) 1644252206Sdavidcs mpi_dump->nic1_regs[i] = 1645252206Sdavidcs qls_rd_ofunc_reg(ha, 1646252206Sdavidcs (i * sizeof(uint32_t)) / 4); 1647252206Sdavidcs 1648252206Sdavidcs qls_rd_xgmac_regs(ha, &mpi_dump->xgmac2[0], 0); 1649252206Sdavidcs qls_rd_xgmac_regs(ha, &mpi_dump->xgmac1[0], 1); 1650252206Sdavidcs } else { 1651252206Sdavidcs for (i = 0; i < 64; i++) 1652252206Sdavidcs mpi_dump->nic1_regs[i] = 1653252206Sdavidcs READ_REG32(ha, i * sizeof(uint32_t)); 1654252206Sdavidcs 1655252206Sdavidcs for (i = 0; i < 64; i++) 1656252206Sdavidcs mpi_dump->nic2_regs[i] = 1657252206Sdavidcs qls_rd_ofunc_reg(ha, 1658252206Sdavidcs (i * sizeof(uint32_t)) / 4); 1659252206Sdavidcs 1660252206Sdavidcs qls_rd_xgmac_regs(ha, &mpi_dump->xgmac1[0], 0); 1661252206Sdavidcs qls_rd_xgmac_regs(ha, &mpi_dump->xgmac2[0], 1); 1662252206Sdavidcs } 1663252206Sdavidcs 1664252206Sdavidcs 1665252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->xaui1_an_hdr, 1666252206Sdavidcs Q81_XAUI1_AN_SEG_NUM, 1667252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + 1668252206Sdavidcs sizeof(mpi_dump->serdes1_xaui_an)), 1669252206Sdavidcs "XAUI1 AN Registers"); 1670252206Sdavidcs 1671252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->xaui1_hss_pcs_hdr, 1672252206Sdavidcs Q81_XAUI1_HSS_PCS_SEG_NUM, 1673252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + 1674252206Sdavidcs sizeof(mpi_dump->serdes1_xaui_hss_pcs)), 1675252206Sdavidcs "XAUI1 HSS PCS Registers"); 1676252206Sdavidcs 1677252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->xfi1_an_hdr, 1678252206Sdavidcs Q81_XFI1_AN_SEG_NUM, 1679252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->serdes1_xfi_an)), 1680252206Sdavidcs "XFI1 AN Registers"); 1681252206Sdavidcs 1682252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->xfi1_train_hdr, 1683252206Sdavidcs Q81_XFI1_TRAIN_SEG_NUM, 1684252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + 1685252206Sdavidcs sizeof(mpi_dump->serdes1_xfi_train)), 1686252206Sdavidcs "XFI1 TRAIN Registers"); 1687252206Sdavidcs 1688252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_pcs_hdr, 1689252206Sdavidcs Q81_XFI1_HSS_PCS_SEG_NUM, 1690252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + 1691252206Sdavidcs sizeof(mpi_dump->serdes1_xfi_hss_pcs)), 1692252206Sdavidcs "XFI1 HSS PCS Registers"); 1693252206Sdavidcs 1694252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_tx_hdr, 1695252206Sdavidcs Q81_XFI1_HSS_TX_SEG_NUM, 1696252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + 1697252206Sdavidcs sizeof(mpi_dump->serdes1_xfi_hss_tx)), 1698252206Sdavidcs "XFI1 HSS TX Registers"); 1699252206Sdavidcs 1700252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_rx_hdr, 1701252206Sdavidcs Q81_XFI1_HSS_RX_SEG_NUM, 1702252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + 1703252206Sdavidcs sizeof(mpi_dump->serdes1_xfi_hss_rx)), 1704252206Sdavidcs "XFI1 HSS RX Registers"); 1705252206Sdavidcs 1706252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_pll_hdr, 1707252206Sdavidcs Q81_XFI1_HSS_PLL_SEG_NUM, 1708252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + 1709252206Sdavidcs sizeof(mpi_dump->serdes1_xfi_hss_pll)), 1710252206Sdavidcs "XFI1 HSS PLL Registers"); 1711252206Sdavidcs 1712252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->xaui2_an_hdr, 1713252206Sdavidcs Q81_XAUI2_AN_SEG_NUM, 1714252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + 1715252206Sdavidcs sizeof(mpi_dump->serdes2_xaui_an)), 1716252206Sdavidcs "XAUI2 AN Registers"); 1717252206Sdavidcs 1718252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->xaui2_hss_pcs_hdr, 1719252206Sdavidcs Q81_XAUI2_HSS_PCS_SEG_NUM, 1720252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + 1721252206Sdavidcs sizeof(mpi_dump->serdes2_xaui_hss_pcs)), 1722252206Sdavidcs "XAUI2 HSS PCS Registers"); 1723252206Sdavidcs 1724252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->xfi2_an_hdr, 1725252206Sdavidcs Q81_XFI2_AN_SEG_NUM, 1726252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->serdes2_xfi_an)), 1727252206Sdavidcs "XFI2 AN Registers"); 1728252206Sdavidcs 1729252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->xfi2_train_hdr, 1730252206Sdavidcs Q81_XFI2_TRAIN_SEG_NUM, 1731252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + 1732252206Sdavidcs sizeof(mpi_dump->serdes2_xfi_train)), 1733252206Sdavidcs "XFI2 TRAIN Registers"); 1734252206Sdavidcs 1735252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_pcs_hdr, 1736252206Sdavidcs Q81_XFI2_HSS_PCS_SEG_NUM, 1737252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + 1738252206Sdavidcs sizeof(mpi_dump->serdes2_xfi_hss_pcs)), 1739252206Sdavidcs "XFI2 HSS PCS Registers"); 1740252206Sdavidcs 1741252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_tx_hdr, 1742252206Sdavidcs Q81_XFI2_HSS_TX_SEG_NUM, 1743252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + 1744252206Sdavidcs sizeof(mpi_dump->serdes2_xfi_hss_tx)), 1745252206Sdavidcs "XFI2 HSS TX Registers"); 1746252206Sdavidcs 1747252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_rx_hdr, 1748252206Sdavidcs Q81_XFI2_HSS_RX_SEG_NUM, 1749252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + 1750252206Sdavidcs sizeof(mpi_dump->serdes2_xfi_hss_rx)), 1751252206Sdavidcs "XFI2 HSS RX Registers"); 1752252206Sdavidcs 1753252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_pll_hdr, 1754252206Sdavidcs Q81_XFI2_HSS_PLL_SEG_NUM, 1755252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + 1756252206Sdavidcs sizeof(mpi_dump->serdes2_xfi_hss_pll)), 1757252206Sdavidcs "XFI2 HSS PLL Registers"); 1758252206Sdavidcs 1759252206Sdavidcs qls_rd_serdes_regs(ha, mpi_dump); 1760252206Sdavidcs 1761252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->core_regs_seg_hdr, 1762252206Sdavidcs Q81_CORE_SEG_NUM, 1763252206Sdavidcs (sizeof(mpi_dump->core_regs_seg_hdr) + 1764252206Sdavidcs sizeof(mpi_dump->mpi_core_regs) + 1765252206Sdavidcs sizeof(mpi_dump->mpi_core_sh_regs)), 1766252206Sdavidcs "Core Registers"); 1767252206Sdavidcs 1768252206Sdavidcs ret = qls_get_mpi_regs(ha, &mpi_dump->mpi_core_regs[0], 1769252206Sdavidcs Q81_MPI_CORE_REGS_ADDR, Q81_MPI_CORE_REGS_CNT); 1770252206Sdavidcs 1771252206Sdavidcs ret = qls_get_mpi_shadow_regs(ha, 1772252206Sdavidcs &mpi_dump->mpi_core_sh_regs[0]); 1773252206Sdavidcs 1774252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->test_logic_regs_seg_hdr, 1775252206Sdavidcs Q81_TEST_LOGIC_SEG_NUM, 1776252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + 1777252206Sdavidcs sizeof(mpi_dump->test_logic_regs)), 1778252206Sdavidcs "Test Logic Regs"); 1779252206Sdavidcs 1780252206Sdavidcs ret = qls_get_mpi_regs(ha, &mpi_dump->test_logic_regs[0], 1781252206Sdavidcs Q81_TEST_REGS_ADDR, Q81_TEST_REGS_CNT); 1782252206Sdavidcs 1783252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->rmii_regs_seg_hdr, 1784252206Sdavidcs Q81_RMII_SEG_NUM, 1785252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->rmii_regs)), 1786252206Sdavidcs "RMII Registers"); 1787252206Sdavidcs 1788252206Sdavidcs ret = qls_get_mpi_regs(ha, &mpi_dump->rmii_regs[0], 1789252206Sdavidcs Q81_RMII_REGS_ADDR, Q81_RMII_REGS_CNT); 1790252206Sdavidcs 1791252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->fcmac1_regs_seg_hdr, 1792252206Sdavidcs Q81_FCMAC1_SEG_NUM, 1793252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fcmac1_regs)), 1794252206Sdavidcs "FCMAC1 Registers"); 1795252206Sdavidcs 1796252206Sdavidcs ret = qls_get_mpi_regs(ha, &mpi_dump->fcmac1_regs[0], 1797252206Sdavidcs Q81_FCMAC1_REGS_ADDR, Q81_FCMAC_REGS_CNT); 1798252206Sdavidcs 1799252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->fcmac2_regs_seg_hdr, 1800252206Sdavidcs Q81_FCMAC2_SEG_NUM, 1801252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fcmac2_regs)), 1802252206Sdavidcs "FCMAC2 Registers"); 1803252206Sdavidcs 1804252206Sdavidcs ret = qls_get_mpi_regs(ha, &mpi_dump->fcmac2_regs[0], 1805252206Sdavidcs Q81_FCMAC2_REGS_ADDR, Q81_FCMAC_REGS_CNT); 1806252206Sdavidcs 1807252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->fc1_mbx_regs_seg_hdr, 1808252206Sdavidcs Q81_FC1_MBOX_SEG_NUM, 1809252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fc1_mbx_regs)), 1810252206Sdavidcs "FC1 MBox Regs"); 1811252206Sdavidcs 1812252206Sdavidcs ret = qls_get_mpi_regs(ha, &mpi_dump->fc1_mbx_regs[0], 1813252206Sdavidcs Q81_FC1_MBX_REGS_ADDR, Q81_FC_MBX_REGS_CNT); 1814252206Sdavidcs 1815252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->ide_regs_seg_hdr, 1816252206Sdavidcs Q81_IDE_SEG_NUM, 1817252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->ide_regs)), 1818252206Sdavidcs "IDE Registers"); 1819252206Sdavidcs 1820252206Sdavidcs ret = qls_get_mpi_regs(ha, &mpi_dump->ide_regs[0], 1821252206Sdavidcs Q81_IDE_REGS_ADDR, Q81_IDE_REGS_CNT); 1822252206Sdavidcs 1823252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->nic1_mbx_regs_seg_hdr, 1824252206Sdavidcs Q81_NIC1_MBOX_SEG_NUM, 1825252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic1_mbx_regs)), 1826252206Sdavidcs "NIC1 MBox Regs"); 1827252206Sdavidcs 1828252206Sdavidcs ret = qls_get_mpi_regs(ha, &mpi_dump->nic1_mbx_regs[0], 1829252206Sdavidcs Q81_NIC1_MBX_REGS_ADDR, Q81_NIC_MBX_REGS_CNT); 1830252206Sdavidcs 1831252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->smbus_regs_seg_hdr, 1832252206Sdavidcs Q81_SMBUS_SEG_NUM, 1833252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->smbus_regs)), 1834252206Sdavidcs "SMBus Registers"); 1835252206Sdavidcs 1836252206Sdavidcs ret = qls_get_mpi_regs(ha, &mpi_dump->smbus_regs[0], 1837252206Sdavidcs Q81_SMBUS_REGS_ADDR, Q81_SMBUS_REGS_CNT); 1838252206Sdavidcs 1839252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->fc2_mbx_regs_seg_hdr, 1840252206Sdavidcs Q81_FC2_MBOX_SEG_NUM, 1841252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fc2_mbx_regs)), 1842252206Sdavidcs "FC2 MBox Regs"); 1843252206Sdavidcs 1844252206Sdavidcs ret = qls_get_mpi_regs(ha, &mpi_dump->fc2_mbx_regs[0], 1845252206Sdavidcs Q81_FC2_MBX_REGS_ADDR, Q81_FC_MBX_REGS_CNT); 1846252206Sdavidcs 1847252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->nic2_mbx_regs_seg_hdr, 1848252206Sdavidcs Q81_NIC2_MBOX_SEG_NUM, 1849252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic2_mbx_regs)), 1850252206Sdavidcs "NIC2 MBox Regs"); 1851252206Sdavidcs 1852252206Sdavidcs ret = qls_get_mpi_regs(ha, &mpi_dump->nic2_mbx_regs[0], 1853252206Sdavidcs Q81_NIC2_MBX_REGS_ADDR, Q81_NIC_MBX_REGS_CNT); 1854252206Sdavidcs 1855252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->i2c_regs_seg_hdr, 1856252206Sdavidcs Q81_I2C_SEG_NUM, 1857252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + 1858252206Sdavidcs sizeof(mpi_dump->i2c_regs)), 1859252206Sdavidcs "I2C Registers"); 1860252206Sdavidcs 1861252206Sdavidcs ret = qls_get_mpi_regs(ha, &mpi_dump->i2c_regs[0], 1862252206Sdavidcs Q81_I2C_REGS_ADDR, Q81_I2C_REGS_CNT); 1863252206Sdavidcs 1864252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->memc_regs_seg_hdr, 1865252206Sdavidcs Q81_MEMC_SEG_NUM, 1866252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->memc_regs)), 1867252206Sdavidcs "MEMC Registers"); 1868252206Sdavidcs 1869252206Sdavidcs ret = qls_get_mpi_regs(ha, &mpi_dump->memc_regs[0], 1870252206Sdavidcs Q81_MEMC_REGS_ADDR, Q81_MEMC_REGS_CNT); 1871252206Sdavidcs 1872252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->pbus_regs_seg_hdr, 1873252206Sdavidcs Q81_PBUS_SEG_NUM, 1874252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->pbus_regs)), 1875252206Sdavidcs "PBUS Registers"); 1876252206Sdavidcs 1877252206Sdavidcs ret = qls_get_mpi_regs(ha, &mpi_dump->pbus_regs[0], 1878252206Sdavidcs Q81_PBUS_REGS_ADDR, Q81_PBUS_REGS_CNT); 1879252206Sdavidcs 1880252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->mde_regs_seg_hdr, 1881252206Sdavidcs Q81_MDE_SEG_NUM, 1882252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->mde_regs)), 1883252206Sdavidcs "MDE Registers"); 1884252206Sdavidcs 1885252206Sdavidcs ret = qls_get_mpi_regs(ha, &mpi_dump->mde_regs[0], 1886252206Sdavidcs Q81_MDE_REGS_ADDR, Q81_MDE_REGS_CNT); 1887252206Sdavidcs 1888252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->intr_states_seg_hdr, 1889252206Sdavidcs Q81_INTR_STATES_SEG_NUM, 1890252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->intr_states)), 1891252206Sdavidcs "INTR States"); 1892252206Sdavidcs 1893252206Sdavidcs qls_get_intr_states(ha, &mpi_dump->intr_states[0]); 1894252206Sdavidcs 1895252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->probe_dump_seg_hdr, 1896252206Sdavidcs Q81_PROBE_DUMP_SEG_NUM, 1897252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->probe_dump)), 1898252206Sdavidcs "Probe Dump"); 1899252206Sdavidcs 1900252206Sdavidcs qls_get_probe_dump(ha, &mpi_dump->probe_dump[0]); 1901252206Sdavidcs 1902252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->routing_reg_seg_hdr, 1903252206Sdavidcs Q81_ROUTING_INDEX_SEG_NUM, 1904252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->routing_regs)), 1905252206Sdavidcs "Routing Regs"); 1906252206Sdavidcs 1907252206Sdavidcs qls_get_ridx_registers(ha, &mpi_dump->routing_regs[0]); 1908252206Sdavidcs 1909252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->mac_prot_reg_seg_hdr, 1910252206Sdavidcs Q81_MAC_PROTOCOL_SEG_NUM, 1911252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->mac_prot_regs)), 1912252206Sdavidcs "MAC Prot Regs"); 1913252206Sdavidcs 1914252206Sdavidcs qls_get_mac_proto_regs(ha, &mpi_dump->mac_prot_regs[0]); 1915252206Sdavidcs 1916252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->ets_seg_hdr, 1917252206Sdavidcs Q81_ETS_SEG_NUM, 1918252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->ets)), 1919252206Sdavidcs "ETS Registers"); 1920252206Sdavidcs 1921252206Sdavidcs ret = qls_get_ets_regs(ha, &mpi_dump->ets[0]); 1922252206Sdavidcs 1923252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->sem_regs_seg_hdr, 1924252206Sdavidcs Q81_SEM_REGS_SEG_NUM, 1925252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->sem_regs)), 1926252206Sdavidcs "Sem Registers"); 1927252206Sdavidcs 1928252206Sdavidcs for(i = 0; i < Q81_MAX_SEMAPHORE_FUNCTIONS ; i ++) { 1929252206Sdavidcs 1930252206Sdavidcs reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (i << Q81_FUNCTION_SHIFT) | 1931252206Sdavidcs (Q81_CTL_SEMAPHORE >> 2); 1932252206Sdavidcs 1933252206Sdavidcs ret = qls_mpi_risc_rd_reg(ha, reg, ®_val); 1934252206Sdavidcs mpi_dump->sem_regs[i] = reg_val; 1935252206Sdavidcs 1936252206Sdavidcs if (ret != 0) 1937252206Sdavidcs mpi_dump->sem_regs[i] = Q81_BAD_DATA; 1938252206Sdavidcs } 1939252206Sdavidcs 1940252206Sdavidcs ret = qls_unpause_mpi_risc(ha); 1941252206Sdavidcs if (ret) 1942252206Sdavidcs printf("Failed RISC unpause. Status = 0x%.08x\n",ret); 1943252206Sdavidcs 1944252206Sdavidcs ret = qls_mpi_reset(ha); 1945252206Sdavidcs if (ret) 1946252206Sdavidcs printf("Failed RISC reset. Status = 0x%.08x\n",ret); 1947252206Sdavidcs 1948252206Sdavidcs WRITE_REG32(ha, Q81_CTL_FUNC_SPECIFIC, 0x80008000); 1949252206Sdavidcs 1950252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->memc_ram_seg_hdr, 1951252206Sdavidcs Q81_MEMC_RAM_SEG_NUM, 1952252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->memc_ram)), 1953252206Sdavidcs "MEMC RAM"); 1954252206Sdavidcs 1955252206Sdavidcs ret = qls_mbx_dump_risc_ram(ha, &mpi_dump->memc_ram[0], 1956252206Sdavidcs Q81_MEMC_RAM_ADDR, Q81_MEMC_RAM_CNT); 1957252206Sdavidcs if (ret) 1958252206Sdavidcs printf("Failed Dump of MEMC RAM. Status = 0x%.08x\n",ret); 1959252206Sdavidcs 1960252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->code_ram_seg_hdr, 1961252206Sdavidcs Q81_WCS_RAM_SEG_NUM, 1962252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->code_ram)), 1963252206Sdavidcs "WCS RAM"); 1964252206Sdavidcs 1965252206Sdavidcs ret = qls_mbx_dump_risc_ram(ha, &mpi_dump->memc_ram[0], 1966252206Sdavidcs Q81_CODE_RAM_ADDR, Q81_CODE_RAM_CNT); 1967252206Sdavidcs if (ret) 1968252206Sdavidcs printf("Failed Dump of CODE RAM. Status = 0x%.08x\n",ret); 1969252206Sdavidcs 1970252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->wqc1_seg_hdr, 1971252206Sdavidcs Q81_WQC1_SEG_NUM, 1972252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->wqc1)), 1973252206Sdavidcs "WQC 1"); 1974252206Sdavidcs 1975252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->wqc2_seg_hdr, 1976252206Sdavidcs Q81_WQC2_SEG_NUM, 1977252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->wqc2)), 1978252206Sdavidcs "WQC 2"); 1979252206Sdavidcs 1980252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->cqc1_seg_hdr, 1981252206Sdavidcs Q81_CQC1_SEG_NUM, 1982252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->cqc1)), 1983252206Sdavidcs "CQC 1"); 1984252206Sdavidcs 1985252206Sdavidcs qls_mpid_seg_hdr(&mpi_dump->cqc2_seg_hdr, 1986252206Sdavidcs Q81_CQC2_SEG_NUM, 1987252206Sdavidcs (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->cqc2)), 1988252206Sdavidcs "CQC 2"); 1989252206Sdavidcs 1990252206Sdavidcs return 0; 1991252206Sdavidcs} 1992252206Sdavidcs 1993