1285242Sachim/******************************************************************************* 2285242Sachim*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3285242Sachim* 4285242Sachim*Redistribution and use in source and binary forms, with or without modification, are permitted provided 5285242Sachim*that the following conditions are met: 6285242Sachim*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7285242Sachim*following disclaimer. 8285242Sachim*2. Redistributions in binary form must reproduce the above copyright notice, 9285242Sachim*this list of conditions and the following disclaimer in the documentation and/or other materials provided 10285242Sachim*with the distribution. 11285242Sachim* 12285242Sachim*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13285242Sachim*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14285242Sachim*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15285242Sachim*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16285242Sachim*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17285242Sachim*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18285242Sachim*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19285242Sachim*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20285242Sachim* 21285242Sachim* $FreeBSD: releng/11.0/sys/dev/pms/freebsd/driver/common/lxcommon.h 299081 2016-05-04 17:52:53Z pfg $ 22285242Sachim* 23285242Sachim*******************************************************************************/ 24285242Sachim/****************************************************************************** 25285242Sachim 26285242SachimModule Name: 27285242Sachim lxcommon.h 28285242SachimAbstract: 29285242Sachim TISA Initiator/target driver module constant define header file 30285242SachimEnvironment: 31285242Sachim Kernel or loadable module 32285242Sachim 33285242Sachim******************************************************************************/ 34285242Sachim 35285242Sachim 36285242Sachim#include <dev/pms/RefTisa/tisa/api/titypes.h> 37285242Sachim 38285242Sachim 39285242Sachim#define LINUX_DMA_MEM_MAX 0x1ffe0 /* 128k - 32, real 128k - 24 */ 40285242Sachim#define DEK_MAX_TABLE_ITEMS DEK_MAX_TABLE_ENTRIES // from tisa/api/titypes.h 41285242Sachim 42285242Sachim/* 43285242Sachim** IP address length based on character. 44285242Sachim*/ 45285242Sachim#ifdef AGTIAPI_IP6_SUPPORT 46285242Sachim# define IP_ADDR_CHAR_LEN 64 47285242Sachim#else 48285242Sachim# define IP_ADDR_CHAR_LEN 16 49285242Sachim#endif 50285242Sachim 51285242Sachim#define MSEC_PER_TICK (1000/hz) /* milisecond per tick */ 52285242Sachim#define USEC_PER_TICK (1000000/hz) /* microsecond per tick */ 53285242Sachim#define AGTIAPI_64BIT_ALIGN 8 /* 64 bit environment alignment */ 54285242Sachim 55285242Sachim/* 56285242Sachim** Max device supported 57285242Sachim*/ 58285242Sachim#define AGTIAPI_MAX_CARDS 4 /* card supported up to system limit */ 59285242Sachim#define AGTIAPI_TOO_MANY_CARDS -1 /* beyond defined max support */ 60285242Sachim#define AGTIAPI_MAX_PORTALS 16 /* max portal per card */ 61285242Sachim/* max device per portal */ 62285242Sachim 63285242Sachim/* 64285242Sachim** Adjustable Parameter Options 65285242Sachim*/ 66285242Sachim#define AGTIAPI_OPTION_ON 1 /* adjustable parameter available */ 67285242Sachim#define AGTIAPI_KEY_MAX 64 /* max number of keys */ 68285242Sachim#define AGTIAPI_STRING_MAX 512 /* max length for string */ 69285242Sachim#define AGTIAPI_PARAM_MAX 256 /* max number of parameters */ 70285242Sachim#ifdef TARGET_DRIVER 71285242Sachim#define AGTIAPI_DMA_MEM_LIST_MAX 4096 /* max number of DMA memory list */ 72285242Sachim#define AGTIAPI_CACHE_MEM_LIST_MAX 24 /* max number of CACHE memory list */ 73285242Sachim#else /* INITIATOR_DRIVER */ 74285242Sachim#define AGTIAPI_DMA_MEM_LIST_MAX 1024 /* max number of DMA memory list */ 75285242Sachim#define AGTIAPI_CACHE_MEM_LIST_MAX 1024 /* max number of CACHE memory list */ 76285242Sachim#endif 77285242Sachim#ifndef AGTIAPI_DYNAMIC_MAX 78285242Sachim#define AGTIAPI_DYNAMIC_MAX 4096 /* max unreleased dynamic memory */ 79285242Sachim#endif 80285242Sachim#define AGTIAPI_LOOP_MAX 4 /* max loop for init process */ 81285242Sachim 82285242Sachim#define AGTIAPI_MAX_NAME 70 // Max string name length 83285242Sachim#define AGTIAPI_MIN_NAME 10 // minimum space for SAS name string 84285242Sachim#define AGTIAPI_MAX_ID 8 // Max string id length 85285242Sachim 86285242Sachim/* 87285242Sachim** Card-port status definitions 88285242Sachim*/ 89285242Sachim#define AGTIAPI_INIT_TIME 0x00000001 90285242Sachim#define AGTIAPI_SOFT_RESET 0x00000002 91285242Sachim#define AGTIAPI_HAD_RESET 0x00000004 // ### 92285242Sachim#define AGTIAPI_DISC_DONE 0x00000008 93285242Sachim#define AGTIAPI_INSTALLED 0x00000010 94285242Sachim#define AGTIAPI_RESET 0x00000020 95285242Sachim#define AGTIAPI_FLAG_UP 0x00000040 96285242Sachim#define AGTIAPI_CB_DONE 0x00000080 97285242Sachim#define AGTIAPI_DISC_COMPLETE 0x00000100 98285242Sachim#define AGTIAPI_IOREGION_REQUESTED 0x00000200 99285242Sachim#define AGTIAPI_IRQ_REQUESTED 0x00000400 100285242Sachim#define AGTIAPI_SCSI_REGISTERED 0x00000800 101285242Sachim#define AGTIAPI_NAME_SERVER_UP 0x00001000 102285242Sachim#define AGTIAPI_PORT_INITIALIZED 0x00002000 103285242Sachim#define AGTIAPI_PORT_LINK_UP 0x00004000 104285242Sachim#define AGTIAPI_LGN_LINK_UP 0x00008000 105285242Sachim#define AGTIAPI_PORT_PANIC 0x00010000 106285242Sachim#define AGTIAPI_RESET_SUCCESS 0x00020000 107285242Sachim#define AGTIAPI_PORT_START 0x00040000 108285242Sachim#define AGTIAPI_PORT_STOPPED 0x00080000 109285242Sachim#define AGTIAPI_PORT_SHUTDOWN 0x00100000 110285242Sachim#define AGTIAPI_IN_USE 0x00200000 111285242Sachim#define AGTIAPI_SYS_INTR_ON 0x00400000 112285242Sachim#define AGTIAPI_PORT_DISC_READY 0x00800000 113285242Sachim#define AGTIAPI_SIG_DOWN 0x01000000 114285242Sachim#define AGTIAPI_SIG_UP 0x02000000 115285242Sachim#define AGTIAPI_TASK 0x04000000 116285242Sachim#define AGTIAPI_INITIATOR 0x08000000 117285242Sachim#define AGTIAPI_TARGET 0x10000000 118285242Sachim#define AGTIAPI_TIMER_ON 0x20000000 119285242Sachim#define AGTIAPI_SHUT_DOWN 0x40000000 120285242Sachim/* reserved for ccb flag TASK_MANAGEMENT 121285242Sachim#define AGTIAPI_RESERVED 0x80000000 122285242Sachim*/ 123285242Sachim#define AGTIAPI_RESET_ALL 0xFFFFFFFF 124285242Sachim 125285242Sachim/* 126285242Sachim** PCI defines 127285242Sachim*/ 128285242Sachim#ifndef PCI_VENDOR_ID_HP 129285242Sachim#define PCI_VENDOR_ID_HP 0x103c 130285242Sachim#endif 131285242Sachim 132285242Sachim#ifndef PCI_VENDOR_ID_PMC_SIERRA 133285242Sachim#define PCI_VENDOR_ID_PMC_SIERRA 0x11F8 134285242Sachim#endif 135285242Sachim 136285242Sachim#ifndef PCI_VENDOR_ID_AGILENT 137285242Sachim#define PCI_VENDOR_ID_AGILENT 0x15bc 138285242Sachim#endif 139285242Sachim 140285242Sachim#ifndef PCI_VENDOR_ID_CYCLONE 141285242Sachim#define PCI_VENDOR_ID_CYCLONE 0x113C 142285242Sachim#endif 143285242Sachim 144285242Sachim#ifndef PCI_VENDOR_ID_SPCV_FPGA 145285242Sachim#define PCI_VENDOR_ID_SPCV_FPGA 0x1855 146285242Sachim#endif 147285242Sachim 148285242Sachim#ifndef PCI_VENDOR_ID_HIALEAH 149285242Sachim#define PCI_VENDOR_ID_HIALEAH 0x9005 150285242Sachim#endif 151285242Sachim 152285242Sachim#define PCI_DEVICE_ID_HP_TS 0x102a 153285242Sachim#define PCI_DEVICE_ID_HP_TL 0x1028 154285242Sachim#define PCI_DEVICE_ID_HP_XL2 0x1029 155285242Sachim#define PCI_DEVICE_ID_AG_DX2 0x0100 156285242Sachim#define PCI_DEVICE_ID_AG_DX2PLUS 0x0101 157285242Sachim#define PCI_DEVICE_ID_AG_QX2 0x0102 158285242Sachim#define PCI_DEVICE_ID_AG_QX4 0x0103 159285242Sachim#define PCI_DEVICE_ID_AG_QE4 0x1200 160285242Sachim#define PCI_DEVICE_ID_AG_DE4 0x1203 161285242Sachim#define PCI_DEVICE_ID_AG_XL10 0x0104 162285242Sachim#define PCI_DEVICE_ID_AG_DX4PLUS 0x0105 163285242Sachim#define PCI_DEVICE_ID_AG_DIXL 0x0110 164285242Sachim#define PCI_DEVICE_ID_AG_IDX1 0x050A 165285242Sachim#define PCI_DEVICE_ID_PMC_SIERRA_SPC 0x8001 166285242Sachim#define PCI_DEVICE_ID_PMC_SIERRA_SPCV 0x8008 167285242Sachim#define PCI_DEVICE_ID_PMC_SIERRA_SPCVE 0x8009 168285242Sachim#define PCI_DEVICE_ID_PMC_SIERRA_SPCVPLUS 0x8018 169285242Sachim#define PCI_DEVICE_ID_PMC_SIERRA_SPCVE_16 0x8019 170285242Sachim#define PCI_DEVICE_ID_SPCV_FPGA 0xabcd 171285242Sachim#define PCI_DEVICE_ID_PMC_SIERRA_SPCV12G 0x8070 172285242Sachim#define PCI_DEVICE_ID_PMC_SIERRA_SPCVE12G 0x8071 173285242Sachim#define PCI_DEVICE_ID_PMC_SIERRA_SPCV12G_16 0x8072 174285242Sachim#define PCI_DEVICE_ID_PMC_SIERRA_SPCVE12G_16 0x8073 175285242Sachim#define PCI_DEVICE_ID_HIALEAH_HBA_SPC 0x8081 176285242Sachim#define PCI_DEVICE_ID_HIALEAH_RAID_SPC 0x8091 177285242Sachim#define PCI_DEVICE_ID_HIALEAH_HBA_SPCV 0x8088 178285242Sachim#define PCI_DEVICE_ID_HIALEAH_RAID_SPCV 0x8098 179285242Sachim#define PCI_DEVICE_ID_HIALEAH_HBA_SPCVE 0x8089 180285242Sachim#define PCI_DEVICE_ID_HIALEAH_RAID_SPCVE 0x8099 181285242Sachim#define PCI_DEVICE_ID_DELRAY_HBA_8PORTS_SPCV 0x8074 182285242Sachim#define PCI_DEVICE_ID_DELRAY_HBA_8PORTS_SPCVE 0x8075 183285242Sachim#define PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCV 0x8076 184285242Sachim#define PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCVE 0x8077 185285242Sachim#define PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCV_SATA 0x8006 186285242Sachim 187285242Sachim 188285242Sachim#define PCI_SUB_VENDOR_ID_HP PCI_VENDOR_ID_HP 189285242Sachim#define PCI_SUB_VENDOR_ID_AG PCI_VENDOR_ID_AGILENT 190285242Sachim#define PCI_SUB_VENDOR_ID_MASK 0xFFFF 191285242Sachim#define PCI_SUB_SYSTEM_ID_AG 0x0001 192285242Sachim#define PCI_BASE_MEM_MASK (~0x0F) 193285242Sachim 194285242Sachim#define PCI_DEVICE_ID_CYCLONE 0xB555 195285242Sachim#define PCI_ENABLE_VALUE 0x0157 196285242Sachim#ifdef PMC_SPC 197285242Sachim#define PCI_NUMBER_BARS 6 198285242Sachim#endif 199285242Sachim#define IOCTL_MN_GET_CARD_INFO 0x11 200285242Sachim/* 201285242Sachim** Constant defines 202285242Sachim*/ 203285242Sachim#define _08B 8 204285242Sachim#define _16B 16 205285242Sachim#define _24B 24 206285242Sachim#define _32B 32 207285242Sachim#define _64B 64 208285242Sachim#define _128B 128 209285242Sachim#define _256B 256 210285242Sachim#define _512B 512 211285242Sachim 212285242Sachim#define _1K 1024 213285242Sachim#define _2K 2048 214285242Sachim#define _4K 4096 215285242Sachim#define _128K (128*(_1K)) 216285242Sachim 217285242Sachim// Card property related info. 218285242Sachimtypedef struct _ag_card_id { 219285242Sachim U16 vendorId; /* pci vendor id */ 220285242Sachim U16 deviceId; /* pci device id */ 221285242Sachim S32 cardNameIndex; /* structure index */ 222285242Sachim U16 membar; /* pci memory bar offset */ 223285242Sachim U16 iobar1; /* pci io bar 1 offset */ 224285242Sachim U16 iobar2; /* pci io bar 2 offest */ 225285242Sachim U16 reg; /* pci memory bar number */ 226285242Sachim} ag_card_id_t; 227285242Sachim 228285242Sachim 229285242Sachim#define PCI_BASE_ADDRESS_0 PCIR_BAR(0) 230285242Sachim#define PCI_BASE_ADDRESS_1 PCIR_BAR(1) 231285242Sachim#define PCI_BASE_ADDRESS_2 PCIR_BAR(2) 232285242Sachim#define PCI_BASE_ADDRESS_3 PCIR_BAR(3) 233285242Sachim#define PCI_BASE_ADDRESS_4 PCIR_BAR(4) 234285242Sachim 235285242Sachim 236285242Sachimag_card_id_t ag_card_type[] = { 237285242Sachim#ifdef AGTIAPI_ISCSI 238285242Sachim {PCI_VENDOR_ID_AGILENTj, PCI_DEVICE_ID_AG_DIXL, 1, 239285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_0, 0}, 240285242Sachim {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_IDX1, 2, 241285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_0, 0}, 242285242Sachim#endif 243285242Sachim#ifdef AGTIAPI_FC 244285242Sachim {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_TS, 3, 245285242Sachim PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2, 3}, 246285242Sachim {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_TL, 4, 247285242Sachim PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2, 3}, 248285242Sachim {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_XL2, 5, 249285242Sachim PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2, 3}, 250285242Sachim {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_DX2, 6, 251285242Sachim PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, 252285242Sachim {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_DX2PLUS, 7, 253285242Sachim PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, 254285242Sachim {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_DX4PLUS, 8, 255285242Sachim PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, 256285242Sachim {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_QX2, 9, 257285242Sachim PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, 258285242Sachim {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_QX4, 10, 259285242Sachim PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, 260285242Sachim {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_DE4, 11, 261285242Sachim PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, 262285242Sachim {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_QE4, 12, 263285242Sachim PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, 264285242Sachim {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_XL10, 13, 265285242Sachim PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4}, 266285242Sachim#endif 267285242Sachim#ifdef AGTIAPI_SA 268285242Sachim#ifdef PMC_SPC 269285242Sachim {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPC, 14, 270285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 271285242Sachim {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCV, 15, 272285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 273285242Sachim {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVE, 16, 274285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 275285242Sachim {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVPLUS, 17, 276285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 277285242Sachim {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVE_16, 18, 278285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 279285242Sachim {PCI_VENDOR_ID_SPCV_FPGA, PCI_DEVICE_ID_SPCV_FPGA, 19, 280285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 281285242Sachim {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCV12G, 20, 282285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 283285242Sachim {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVE12G, 21, 284285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 285285242Sachim {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCV12G_16, 22, 286285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 287285242Sachim {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVE12G_16, 23, 288285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 289285242Sachim {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_HBA_SPC, 24, 290285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 291285242Sachim {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_RAID_SPC, 25, 292285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 293285242Sachim {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_HBA_SPCV, 26, 294285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 295285242Sachim {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_RAID_SPCV, 27, 296285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 297285242Sachim {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_HBA_SPCVE, 28, 298285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 299285242Sachim {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_RAID_SPCVE, 29, 300285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 301285242Sachim {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_8PORTS_SPCV, 30, 302285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 303285242Sachim {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_8PORTS_SPCVE, 31, 304285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 305285242Sachim {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCV, 32, 306285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 307285242Sachim {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCVE, 33, 308285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 309285242Sachim {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCV_SATA, 34, 310285242Sachim PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0}, 311285242Sachim 312285242Sachim#endif 313285242Sachim#endif //AGTIAPI_SA 314285242Sachim}; 315285242Sachim 316285242Sachimstatic const char *ag_card_names[] = { 317285242Sachim "Unknown", 318285242Sachim "iSCSI DiXL Card", 319285242Sachim "iSCSI iDX1 Card", 320285242Sachim "Tachyon TS Fibre Channel Card", 321285242Sachim "Tachyon TL Fibre Channel Card", 322285242Sachim "Tachyon XL2 Fibre Channel Card", 323285242Sachim "Tachyon DX2 Fibre Channel Card", 324285242Sachim "Tachyon DX2+ Fibre Channel Card", 325285242Sachim "Tachyon DX4+ Fibre Channel Card", 326285242Sachim "Tachyon QX2 Fibre Channel Card", 327285242Sachim "Tachyon QX4 Fibre Channel Card", 328285242Sachim "Tachyon DE4 Fibre Channel Card", 329285242Sachim "Tachyon QE4 Fibre Channel Card", 330285242Sachim "Tachyon XL10 Fibre Channel Card", 331285242Sachim#ifdef AGTIAPI_SA 332285242Sachim#ifdef PMC_SPC 333285242Sachim "PMC Sierra SPC SAS-SATA Card", 334285242Sachim "PMC Sierra SPC-V SAS-SATA Card", 335285242Sachim "PMC Sierra SPC-VE SAS-SATA Card", 336285242Sachim "PMC Sierra SPC-V 16 Port SAS-SATA Card", 337285242Sachim "PMC Sierra SPC-VE 16 Port SAS-SATA Card", 338285242Sachim "PMC Sierra FPGA", 339285242Sachim "PMC Sierra SPC-V SAS-SATA Card 12Gig", 340285242Sachim "PMC Sierra SPC-VE SAS-SATA Card 12Gig", 341285242Sachim "PMC Sierra SPC-V 16 Port SAS-SATA Card 12Gig", 342285242Sachim "PMC Sierra SPC-VE 16 Port SAS-SATA Card 12Gig", 343285242Sachim "Adaptec Hialeah 4/8 Port SAS-SATA HBA Card 6Gig", 344285242Sachim "Adaptec Hialeah 4/8 Port SAS-SATA RAID Card 6Gig", 345285242Sachim "Adaptec Hialeah 8/16 Port SAS-SATA HBA Card 6Gig", 346285242Sachim "Adaptec Hialeah 8/16 Port SAS-SATA RAID Card 6Gig", 347285242Sachim "Adaptec Hialeah 8/16 Port SAS-SATA HBA Encryption Card 6Gig", 348285242Sachim "Adaptec Hialeah 8/16 Port SAS-SATA RAID Encryption Card 6Gig", 349285242Sachim "Adaptec Delray 8 Port SAS-SATA HBA Card 12Gig", 350285242Sachim "Adaptec Delray 8 Port SAS-SATA HBA Encryption Card 12Gig", 351285242Sachim "Adaptec Delray 16 Port SAS-SATA HBA Card 12Gig", 352285242Sachim "Adaptec Delray 16 Port SAS-SATA HBA Encryption Card 12Gig", 353285242Sachim "Adaptec SATA Adapter", 354285242Sachim 355285242Sachim#endif 356285242Sachim#endif 357285242Sachim}; 358285242Sachim 359285242Sachim 360285242Sachim 361285242Sachim/* 362285242Sachim** Resource Info Structure 363285242Sachim*/ 364285242Sachimtypedef struct _ag_resource_info { 365285242Sachim tiLoLevelResource_t tiLoLevelResource; // Low level resource required 366285242Sachim tiInitiatorResource_t tiInitiatorResource; // Initiator resource required 367285242Sachim tiTargetResource_t tiTargetResource; // Target resource required 368285242Sachim tiTdSharedMem_t tiSharedMem; // Shared memory by ti and td 369285242Sachim} ag_resource_info_t; 370285242Sachim 371285242Sachim 372285242Sachim// DMA memory address pair 373285242Sachimtypedef struct _ag_dma_addr { 374285242Sachim void *dmaVirtAddr; 375285242Sachim vm_paddr_t dmaPhysAddr; 376285242Sachim U32 memSize; 377285242Sachim bit32 type; 378285242Sachim bus_addr_t nocache_busaddr; 379285242Sachim void *nocache_mem; 380285242Sachim} ag_dma_addr_t; 381285242Sachim 382285242Sachim 383285242Sachimtypedef struct _CardInfo 384285242Sachim{ 385285242Sachim U32 pciIOAddrLow; /* PCI IOBASE lower */ 386285242Sachim U32 pciIOAddrUp; /* PCI IOBASE Upper */ 387285242Sachim U32_64 pciMemBase; /* PCI MEMBASE, physical */ 388285242Sachim U32_64 pciMemBaseSpc[PCI_NUMBER_BARS]; // PCI MEMBASE, physical 389285242Sachim U16 deviceId; // PCI device id 390285242Sachim U16 vendorId; // PCI Vendor id 391285242Sachim U32 busNum; 392285242Sachim U32 deviceNum; 393285242Sachim}CardInfo_t; 394285242Sachim 395285242Sachim// Card info. for all cards and drivers 396285242Sachimtypedef struct _ag_card_info { 397285242Sachim struct mtx pmIOLock; 398285242Sachim device_t pPCIDev; // PCI device pointer 399285242Sachim void *pCard; // pointer to per card data structure 400285242Sachim S32 cardNameIndex; 401285242Sachim U32 cardID; // card system ID 402285242Sachim U32 cardIdIndex; 403285242Sachim U32 pciIOAddrLow; // PCI IOBASE lower 404285242Sachim U32 pciIOAddrUp; // PCI IOBASE Upper 405285242Sachim U32_64 pciMemBase; // PCI MEMBASE, physical 406285242Sachim caddr_t pciMemVirtAddr; // PCI MEMBASE, virtual ptr 407285242Sachim U32 pciMemSize; // PCI MEMBASE memory size 408285242Sachim#ifdef AGTIAPI_SA 409285242Sachim#ifdef FPGA_CARD 410285242Sachim U32_64 pciMemBase0; // PCI MEMBASE, physical 411285242Sachim caddr_t pciMemVirtAddr0; // PCI MEMBASE, virtual ptr 412285242Sachim U32 pciMemSize0; // PCI MEMBASE memory size 413285242Sachim#endif 414285242Sachim#ifdef PMC_SPC 415285242Sachim struct resource *pciMemBaseRscSpc[PCI_NUMBER_BARS]; 416285242Sachim int pciMemBaseRIDSpc[PCI_NUMBER_BARS]; 417285242Sachim U32_64 pciMemBaseSpc[PCI_NUMBER_BARS]; // PCI MEMBASE, physical 418285242Sachim caddr_t pciMemVirtAddrSpc[PCI_NUMBER_BARS];//PCI MEMBASE, virt ptr 419285242Sachim U32 pciMemSizeSpc[PCI_NUMBER_BARS]; // PCI MEMBASE memory size 420285242Sachim#endif 421285242Sachim#endif 422285242Sachim U16 memBar; 423285242Sachim U16 memReg; 424285242Sachim U32 cacheIndex; 425285242Sachim U32 dmaIndex; 426285242Sachim ag_dma_addr_t tiDmaMem[AGTIAPI_DMA_MEM_LIST_MAX]; // dma addr list 427285242Sachim 428285242Sachim // all (free and allocated) mem slots 429285242Sachim ag_dma_addr_t dynamicMem[AGTIAPI_DYNAMIC_MAX]; 430285242Sachim 431285242Sachim // ptr to free mem slots 432285242Sachim ag_dma_addr_t *freeDynamicMem[AGTIAPI_DYNAMIC_MAX]; 433285242Sachim 434285242Sachim U16 topOfFreeDynamicMem; // idx to the first free slot ptr 435285242Sachim 436285242Sachim void *tiCachedMem[AGTIAPI_CACHE_MEM_LIST_MAX];// cached mem list 437285242Sachim ag_resource_info_t tiRscInfo; /* low level resource requirement */ 438285242Sachim U08 WWN[AGTIAPI_MAX_NAME]; /* WWN for this card */ 439285242Sachim U08 WWNLen; 440285242Sachim 441285242Sachim// #define MAX_MSIX_NUM_VECTOR 64 ## 442285242Sachim#define MAX_MSIX_NUM_VECTOR 16 // 1 then 16 just for testing; 443285242Sachim#define MAX_MSIX_NUM_DPC 64 // 16 444285242Sachim#define MAX_MSIX_NUM_ISR 64 // 16 445285242Sachim#ifdef SPC_MSIX_INTR 446285242Sachim 447285242Sachim // ## use as a map instead of presirq 448285242Sachim struct resource *msix_entries[MAX_MSIX_NUM_VECTOR]; 449285242Sachim#endif 450285242Sachim U32 maxInterruptVectors; 451285242Sachim} ag_card_info_t; 452285242Sachim 453285242Sachim/* 454285242Sachim** Optional Adjustable Parameters Structures. 455299081Spfg** Not using pointer structure for easy read and access tree structure. 456285242Sachim** In the future if more layer of key tree involved, it might be a good 457285242Sachim** idea to change the structure and program. 458285242Sachim*/ 459285242Sachimtypedef struct _ag_param_value{ 460285242Sachim char valueName[AGTIAPI_MAX_NAME]; 461285242Sachim char valueString[AGTIAPI_STRING_MAX]; 462285242Sachim struct _ag_param_value *next; 463285242Sachim} ag_value_t; 464285242Sachim 465285242Sachimtypedef struct _ag_param_key{ 466285242Sachim char keyName[AGTIAPI_MAX_NAME]; 467285242Sachim ag_value_t *pValueHead; 468285242Sachim ag_value_t *pValueTail; 469285242Sachim struct _ag_param_key *pSubkeyHead; 470285242Sachim struct _ag_param_key *pSubkeyTail; 471285242Sachim struct _ag_param_key *next; 472285242Sachim} ag_key_t; 473285242Sachim 474285242Sachim/* 475285242Sachim** Portal info data structure 476285242Sachim*/ 477285242Sachimtypedef struct _ag_portal_info { 478285242Sachim U32 portID; 479285242Sachim U32 portStatus; 480285242Sachim U32 devTotal; 481285242Sachim U32 devPrev; 482285242Sachim tiPortInfo_t tiPortInfo; 483285242Sachim tiPortalContext_t tiPortalContext; 484285242Sachim#ifdef INITIATOR_DRIVER 485285242Sachim void *pDevList[AGTIAPI_HW_LIMIT_DEVICE]; 486285242Sachim#endif 487285242Sachim} ag_portal_info_t; 488285242Sachim 489285242Sachim#define MAP_TABLE_ENTRY(pC, c, d, l) (pC->encrypt_map + \ 490285242Sachim (c * pC->devDiscover * AGTIAPI_MAX_LUN) + \ 491285242Sachim (d * AGTIAPI_MAX_LUN) + \ 492285242Sachim (l)) 493285242Sachim 494285242Sachim#ifdef CHAR_DEVICE 495285242Sachim/************************************************************************* 496285242SachimPurpose: Payload Wraper for ioctl commands 497285242Sachim***********************************************************************/ 498285242Sachimtypedef struct datatosendt{ 499285242Sachimbit32 datasize; //buffer size 500285242Sachimbit8 *data; //buffer 501285242Sachim}datatosend; 502285242Sachim/***********************************************************************/ 503285242Sachim#define AGTIAPI_IOCTL_BASE 'x' 504285242Sachim#define AGTIAPI_IOCTL _IOWR(AGTIAPI_IOCTL_BASE, 0,datatosend ) //receiving payload here// 505285242Sachim#define AGTIAPI_IOCTL_MAX 1 506285242Sachim#endif 507285242Sachim 508285242Sachim#ifdef AGTIAPI_FLOW_DEBUG 509285242Sachim#define AGTIAPI_FLOW(format, a...) printf(format, ## a) 510285242Sachim#else 511285242Sachim#define AGTIAPI_FLOW(format, a...) 512285242Sachim#endif 513285242Sachim 514285242Sachim#ifdef AGTIAPI_DEBUG 515285242Sachim#define AGTIAPI_PRINTK(format, a...) printf(format, ## a) 516285242Sachim#else 517285242Sachim#define AGTIAPI_PRINTK(format, a...) 518285242Sachim#endif 519285242Sachim 520285242Sachim#ifdef AGTIAPI_INIT_DEBUG 521285242Sachim#define AGTIAPI_INIT(format, a...) printf(format, ## a) 522285242Sachim/* to avoid losing the logs */ 523285242Sachim#define AGTIAPI_INIT_MDELAY(dly) mdelay(dly) 524285242Sachim#else 525285242Sachim#define AGTIAPI_INIT(format, a...) 526285242Sachim#define AGTIAPI_INIT_MDELAY(dly) 527285242Sachim#endif 528285242Sachim 529285242Sachim#ifdef AGTIAPI_INIT2_DEBUG 530285242Sachim#define AGTIAPI_INIT2(format, a...) printf(format, ## a) 531285242Sachim#else 532285242Sachim#define AGTIAPI_INIT2(format, a...) 533285242Sachim#endif 534285242Sachim 535285242Sachim#ifdef AGTIAPI_INIT_MEM_DEBUG 536285242Sachim#define AGTIAPI_INITMEM(format, a...) printf(format, ## a) 537285242Sachim#else 538285242Sachim#define AGTIAPI_INITMEM(format, a...) 539285242Sachim#endif 540285242Sachim 541285242Sachim#ifdef AGTIAPI_IO_DEBUG 542285242Sachim#define AGTIAPI_IO(format, a...) printf(format, ## a) 543285242Sachim#else 544285242Sachim#define AGTIAPI_IO(format, a...) 545285242Sachim#endif 546285242Sachim 547285242Sachim#ifdef AGTIAPI_LOAD_DELAY 548285242Sachim#define AGTIAPI_INIT_DELAY(delay_time) \ 549285242Sachim { \ 550285242Sachim agtiapi_DelayMSec(delay_time); \ 551285242Sachim } 552285242Sachim#else 553285242Sachim#define AGTIAPI_INIT_DELAY(delay_time) 554285242Sachim#endif 555285242Sachim 556285242Sachim/* 557285242Sachim * AGTIAPI_KDB() will be used to drop into kernel debugger 558285242Sachim * from driver code if kdb is involved. 559285242Sachim */ 560285242Sachim#ifdef AGTIAPI_KDB_ENABLE 561285242Sachim#define AGTIAPI_KDB() KDB_ENTER() 562285242Sachim#else 563285242Sachim#define AGTIAPI_KDB() 564285242Sachim#endif 565285242Sachim 566285242Sachim#if (BITS_PER_LONG == 64) 567285242Sachim//#if 1 568285242Sachim#define LOW_32_BITS(addr) (U32)(addr & 0xffffffff) 569285242Sachim#define HIGH_32_BITS(addr) (U32)((addr >> 32) & 0xffffffff) 570285242Sachim#else 571285242Sachim#define LOW_32_BITS(addr) (U32)addr 572285242Sachim#define HIGH_32_BITS(addr) 0 573285242Sachim#endif 574285242Sachim 575285242Sachim#define AG_SWAP16(data) (((data<<8) & 0xFF00) | (data>>8)) 576285242Sachim#define AG_SWAP24(data) (((data<<16) & 0xFF0000) | \ 577285242Sachim ((data>>16) & 0xFF) | (data & 0xFF00)) 578285242Sachim#define AG_SWAP32(data) ((data<<24) | ((data<<8) & 0xFF0000) | \ 579285242Sachim ((data>>8) & 0xFF00) | (data>>24)) 580285242Sachim 581285242Sachim#define AG_PCI_DEV_INFO(pdev) ( \ 582285242Sachim AGTIAPI_PRINTK("vendor id 0x%x device id 0x%x, slot %d, function %d\n", \ 583285242Sachim pdev->vendor, pdev->device, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)) \ 584285242Sachim ) 585285242Sachim 586285242Sachim#define COUNT(arr) (sizeof(arr) / sizeof(arr[0])) 587285242Sachim 588285242Sachim#define PORTAL_CONTEXT_TO_PORTALDATA(pPortalContext) \ 589285242Sachim ((ag_portal_data_t *)(((tiPortalContext_t *)pPortalContext)->osData)) 590285242Sachim#define PORTAL_STATUS(pPortalData) (pPortalData->portalInfo.portStatus) 591285242Sachim 592285242Sachim#if (defined(DEFINE_OSTI_PORT_EVENT_IN_IBE)) || \ 593285242Sachim (defined(DEFINE_OSTI_PORT_EVENT_IN_TFE)) 594285242Sachim#define TIROOT_TO_CARD(ptiRoot) \ 595285242Sachim ((ag_card_t *)(((appRoot_t *)(ptiRoot->osData))->oscData)) 596285242Sachim#define TIROOT_TO_CARDINFO(ptiRoot) (TIROOT_TO_CARD(ptiRoot)->pCardInfo) 597285242Sachim#define TIROOT_TO_PCIDEV(ptiRoot) (TIROOT_TO_CARDINFO(ptiRoot)->pPCIDev) 598285242Sachim#else 599285242Sachim 600285242Sachim#define TIROOT_TO_CARD(ptiRoot) ((struct agtiapi_softc *)(ptiRoot->osData)) 601285242Sachim#define TIROOT_TO_CARDINFO(ptiRoot) (TIROOT_TO_CARD(ptiRoot)->pCardInfo) 602285242Sachim#define TIROOT_TO_PCIDEV(ptiRoot) (TIROOT_TO_CARD(ptiRoot)->my_dev) 603285242Sachim 604285242Sachim#endif 605285242Sachim 606285242Sachim 607285242Sachim#define Is_ADP7H(pmsc) ((0x90058088 == (pmsc->VidDid))?1:\ 608285242Sachim (0x90058089 == (pmsc->VidDid))?1:0) 609285242Sachim#define Is_ADP8H(pmsc) ((0x90058074 == (pmsc->VidDid))?1:\ 610285242Sachim (0x90058076 == (pmsc->VidDid))?1:0) 611285242Sachim 612285242Sachim 613285242Sachim#define __cacheline_aligned __attribute__((__aligned__(CACHE_LINE_SIZE))) 614285242Sachim 615285242Sachim/* 616285242Sachim** link data, need to be included at the start (offset 0) 617285242Sachim** of any strutures that are to be stored in the link list 618285242Sachim*/ 619285242Sachimtypedef struct _LINK_NODE 620285242Sachim{ 621285242Sachim struct _LINK_NODE *pNext; 622285242Sachim struct _LINK_NODE *pPrev; 623285242Sachim 624285242Sachim /* 625285242Sachim ** for assertion purpose only 626285242Sachim */ 627285242Sachim struct _LINK_NODE * pHead; // track the link list the link is a member of 628285242Sachim void * pad; 629285242Sachim 630285242Sachim} LINK_NODE, * PLINK_NODE __cacheline_aligned; 631285242Sachim 632285242Sachim 633285242Sachim/* 634285242Sachim** link list basic pointers 635285242Sachim*/ 636285242Sachimtypedef struct _LINK_LIST 637285242Sachim{ 638285242Sachim PLINK_NODE pHead; 639285242Sachim bit32 Count; 640299081Spfg LINK_NODE Head __cacheline_aligned; // always one link to speed up insert&rm 641285242Sachim} LINK_LIST, * PLINK_LIST __cacheline_aligned; 642285242Sachim 643285242Sachim 644285242Sachim/******************************************************************** 645285242Sachim** MACROS 646285242Sachim********************************************************************/ 647285242Sachim/******************************************************************************* 648285242Sachim** 649285242Sachim** MODULE NAME: comListInitialize 650285242Sachim** 651285242Sachim** PURPOSE: Initialize a link list. 652285242Sachim** 653285242Sachim** PARAMETERS: PLINK_LIST OUT - Link list definition. 654285242Sachim** 655285242Sachim** SIDE EFFECTS & CAVEATS: 656285242Sachim** 657285242Sachim** ALGORITHM: 658285242Sachim** 659285242Sachim*******************************************************************************/ 660285242Sachim#define comListInitialize(pList) {(pList)->pHead = &((pList)->Head); \ 661285242Sachim (pList)->pHead->pNext = (pList)->pHead; \ 662285242Sachim (pList)->pHead->pPrev = (pList)->pHead; \ 663285242Sachim (pList)->Count = 0; \ 664285242Sachim } 665285242Sachim 666285242Sachim/******************************************************************************* 667285242Sachim** 668285242Sachim** MODULE NAME: comLinkInitialize 669285242Sachim** 670285242Sachim** PURPOSE: Initialize a link. 671285242Sachim** This function should be used to initialize a new link before it 672285242Sachim** is used in the linked list. This will initialize the link so 673285242Sachim** the assertion will work 674285242Sachim** 675285242Sachim** PARAMETERS: PLINK_NODE IN - Link to be initialized. 676285242Sachim** 677285242Sachim** SIDE EFFECTS & CAVEATS: 678285242Sachim** 679285242Sachim** ALGORITHM: 680285242Sachim** 681285242Sachim*******************************************************************************/ 682285242Sachim 683285242Sachim#define comLinkInitialize(pLink) { (pLink)->pHead = NULL; \ 684285242Sachim (pLink)->pNext = NULL; \ 685285242Sachim (pLink)->pPrev = NULL; \ 686285242Sachim } 687285242Sachim 688285242Sachim/******************************************************************************* 689285242Sachim** 690285242Sachim** MODULE NAME: comListAdd 691285242Sachim** 692285242Sachim** PURPOSE: add a link at the tail of the list 693285242Sachim** 694285242Sachim** PARAMETERS: PLINK_LIST OUT - Link list definition. 695285242Sachim** PLINK_NODE IN - Link to be inserted. 696285242Sachim** 697285242Sachim** SIDE EFFECTS & CAVEATS: 698285242Sachim** !!! assumes that fcllistInitialize has been called on the linklist 699285242Sachim** !!! if not, this function behavior is un-predictable 700285242Sachim** 701285242Sachim** ALGORITHM: 702285242Sachim** 703285242Sachim*******************************************************************************/ 704285242Sachim#define comListAdd(pList, pLink) { \ 705285242Sachim (pLink)->pNext = (pList)->pHead; \ 706285242Sachim (pLink)->pPrev = (pList)->pHead->pPrev; \ 707285242Sachim (pLink)->pPrev->pNext = (pLink); \ 708285242Sachim (pList)->pHead->pPrev = (pLink); \ 709285242Sachim (pList)->Count ++; \ 710285242Sachim (pLink)->pHead = (pList)->pHead; \ 711285242Sachim } 712285242Sachim 713285242Sachim/******************************************************************************* 714285242Sachim** 715285242Sachim** MODULE NAME: comListInsert 716285242Sachim** 717285242Sachim** PURPOSE: insert a link preceding the given one 718285242Sachim** 719285242Sachim** PARAMETERS: PLINK_LIST OUT - Link list definition. 720285242Sachim** PLINK_NODE IN - Link to be inserted after. 721285242Sachim** PLINK_NODE IN - Link to be inserted. 722285242Sachim** 723285242Sachim** SIDE EFFECTS & CAVEATS: 724285242Sachim** !!! assumes that fcllistInitialize has been called on the linklist 725285242Sachim** !!! if not, this function behavior is un-predictable 726285242Sachim** 727285242Sachim** ALGORITHM: 728285242Sachim** 729285242Sachim*******************************************************************************/ 730285242Sachim 731285242Sachim#define comListInsert(pList, pLink, pNew) { \ 732285242Sachim (pNew)->pNext = (pLink); \ 733285242Sachim (pNew)->pPrev = (pLink)->pPrev; \ 734285242Sachim (pNew)->pPrev->pNext = (pNew); \ 735285242Sachim (pLink)->pPrev = (pNew); \ 736285242Sachim (pList)->Count ++; \ 737285242Sachim (pNew)->pHead = (pList)->pHead; \ 738285242Sachim } 739285242Sachim 740285242Sachim/******************************************************************************* 741285242Sachim** 742285242Sachim** MODULE NAME: comListRemove 743285242Sachim** 744285242Sachim** PURPOSE: remove the link from the list. 745285242Sachim** 746285242Sachim** PARAMETERS: PLINK_LIST OUT - Link list definition. 747285242Sachim** PLINK_NODE IN - Link to delet from list 748285242Sachim** 749285242Sachim** SIDE EFFECTS & CAVEATS: 750285242Sachim** !!! assumes that fcllistInitialize has been called on the linklist 751285242Sachim** !!! if not, this function behavior is un-predictable 752285242Sachim** 753285242Sachim** !!! No validation is made on the list or the validity of the link 754285242Sachim** !!! the caller must make sure that the link is in the list 755285242Sachim** 756285242Sachim** 757285242Sachim** ALGORITHM: 758285242Sachim** 759285242Sachim*******************************************************************************/ 760285242Sachim#define comListRemove(pList, pLink) { \ 761285242Sachim (pLink)->pPrev->pNext = (pLink)->pNext; \ 762285242Sachim (pLink)->pNext->pPrev = (pLink)->pPrev; \ 763285242Sachim (pLink)->pHead = NULL; \ 764285242Sachim (pList)->Count --; \ 765285242Sachim } 766285242Sachim 767285242Sachim/******************************************************************************* 768285242Sachim** 769285242Sachim** MODULE NAME: comListGetHead 770285242Sachim** 771285242Sachim** PURPOSE: get the link following the head link. 772285242Sachim** 773285242Sachim** PARAMETERS: PLINK_LIST OUT - Link list definition. 774285242Sachim** RETURNS - PLINK_NODE the link following the head 775285242Sachim** NULL if the following link is the head 776285242Sachim** 777285242Sachim** SIDE EFFECTS & CAVEATS: 778285242Sachim** !!! assumes that fcllistInitialize has been called on the linklist 779285242Sachim** !!! if not, this function behavior is un-predictable 780285242Sachim** 781285242Sachim** ALGORITHM: 782285242Sachim** 783285242Sachim*******************************************************************************/ 784285242Sachim#define comListGetHead(pList) comListGetNext(pList,(pList)->pHead) 785285242Sachim 786285242Sachim/******************************************************************************* 787285242Sachim** 788285242Sachim** MODULE NAME: comListGetTail 789285242Sachim** 790285242Sachim** PURPOSE: get the link preceding the tail link. 791285242Sachim** 792285242Sachim** PARAMETERS: PLINK_LIST OUT - Link list definition. 793285242Sachim** RETURNS - PLINK_NODE the link preceding the head 794285242Sachim** NULL if the preceding link is the head 795285242Sachim** 796285242Sachim** SIDE EFFECTS & CAVEATS: 797285242Sachim** 798285242Sachim** ALGORITHM: 799285242Sachim** 800285242Sachim*******************************************************************************/ 801285242Sachim#define comListGetTail(pList) comListGetPrev((pList), (pList)->pHead) 802285242Sachim 803285242Sachim/******************************************************************************* 804285242Sachim** 805285242Sachim** MODULE NAME: comListGetCount 806285242Sachim** 807285242Sachim** PURPOSE: get the number of links in the list excluding head and tail. 808285242Sachim** 809285242Sachim** PARAMETERS: LINK_LIST OUT - Link list definition. 810285242Sachim** 811285242Sachim** SIDE EFFECTS & CAVEATS: 812285242Sachim** !!! assumes that fcllistInitialize has been called on the linklist 813285242Sachim** !!! if not, this function behavior is un-predictable 814285242Sachim** 815285242Sachim** ALGORITHM: 816285242Sachim** 817285242Sachim*******************************************************************************/ 818285242Sachim 819285242Sachim#define comListGetCount(pList) ((pList)->Count) 820285242Sachim 821285242Sachim 822285242Sachim 823285242Sachim/******************************************************************************* 824285242Sachim** 825285242Sachim** MODULE NAME: comListGetNext 826285242Sachim** 827285242Sachim** PURPOSE: get the next link in the list. (one toward tail) 828285242Sachim** 829285242Sachim** PARAMETERS: PLINK_LIST OUT - Link list definition. 830285242Sachim** PLINK_NODE IN - Link to get next to 831285242Sachim** 832285242Sachim** return PLINK - points to next link 833285242Sachim** NULL if next link is head 834285242Sachim** 835285242Sachim** SIDE EFFECTS & CAVEATS: 836285242Sachim** !!! assumes that fcllistInitialize has been called on the linklist 837285242Sachim** !!! if not, this function behavior is un-predictable 838285242Sachim** 839285242Sachim** !!! No validation is made on the list or the validity of the link 840285242Sachim** !!! the caller must make sure that the link is in the list 841285242Sachim** 842285242Sachim** ALGORITHM: 843285242Sachim** 844285242Sachim*******************************************************************************/ 845285242Sachim 846285242Sachim#define comListGetNext(pList, pLink) (((pLink)->pNext == (pList)->pHead) ? \ 847285242Sachim NULL : (pLink)->pNext) 848285242Sachim 849285242Sachim 850285242Sachim/******************************************************************************* 851285242Sachim** 852285242Sachim** MODULE NAME: comListGetPrev 853285242Sachim** 854285242Sachim** PURPOSE: get the previous link in the list. (one toward head) 855285242Sachim** 856285242Sachim** PARAMETERS: PLINK_LIST OUT - Link list definition. 857285242Sachim** PLINK_NODE IN - Link to get prev to 858285242Sachim** 859285242Sachim** return PLINK - points to previous link 860285242Sachim** NULL if previous link is head 861285242Sachim** 862285242Sachim** SIDE EFFECTS & CAVEATS: 863285242Sachim** !!! assumes that fcllistInitialize has been called on the linklist 864285242Sachim** !!! if not, this function behavior is un-predictable 865285242Sachim** 866285242Sachim** !!! No validation is made on the list or the validity of the link 867285242Sachim** !!! the caller must make sure that the link is in the list 868285242Sachim** 869285242Sachim** ALGORITHM: 870285242Sachim** 871285242Sachim*******************************************************************************/ 872285242Sachim 873285242Sachim/*lint -emacro(613,fiLlistGetPrev) */ 874285242Sachim 875285242Sachim#define comListGetPrev(pList, pLink) (((pLink)->pPrev == (pList)->pHead) ? \ 876285242Sachim NULL : (pLink)->pPrev) 877285242Sachim 878285242Sachim#define AGT_INTERRUPT IRQF_DISABLED 879285242Sachim#define AGT_SAMPLE_RANDOM IRQF_SAMPLE_RANDOM 880285242Sachim#define AGT_SHIRQ IRQF_SHARED 881285242Sachim#define AGT_PROBEIRQ IRQF_PROBE_SHARED 882285242Sachim#define AGT_PERCPU IRQF_PERCPU 883285242Sachim 884285242Sachim 885285242Sachim#include "lxproto.h" 886285242Sachim 887