1285242Sachim/******************************************************************************* 2285242Sachim*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3285242Sachim* 4285242Sachim*Redistribution and use in source and binary forms, with or without modification, are permitted provided 5285242Sachim*that the following conditions are met: 6285242Sachim*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7285242Sachim*following disclaimer. 8285242Sachim*2. Redistributions in binary form must reproduce the above copyright notice, 9285242Sachim*this list of conditions and the following disclaimer in the documentation and/or other materials provided 10285242Sachim*with the distribution. 11285242Sachim* 12285242Sachim*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13285242Sachim*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14285242Sachim*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15285242Sachim*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16285242Sachim*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17285242Sachim*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18285242Sachim*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19285242Sachim*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20285242Sachim* 21285242Sachim* $FreeBSD: releng/11.0/sys/dev/pms/RefTisa/sallsdk/spc/spcdefs.h 285242 2015-07-07 13:17:02Z achim $ 22285242Sachim* 23285242Sachim********************************************************************************/ 24285242Sachim/*******************************************************************************/ 25285242Sachim/*! \file spcdefs.h 26285242Sachim * \brief The file defines the MPI Application Programming Interface (API) 27285242Sachim * 28285242Sachim * The file defines the MPI Application Programming Interfacde (API) 29285242Sachim * 30285242Sachim */ 31285242Sachim/*******************************************************************************/ 32285242Sachim#ifndef __SPCDEFS_H__ 33285242Sachim#define __SPCDEFS_H__ 34285242Sachim 35285242Sachim/*******************************************************************************/ 36285242Sachim/*******************************************************************************/ 37285242Sachim/* CONSTANTS */ 38285242Sachim/*******************************************************************************/ 39285242Sachim/*******************************************************************************/ 40285242Sachim/*******************************************************************************/ 41285242Sachim/* MSGU CONFIGURATION TABLE */ 42285242Sachim/*******************************************************************************/ 43285242Sachim#define SPC_MSGU_CFG_TABLE_UPDATE 0x001 /* Inbound doorbell bit0 */ 44285242Sachim#define SPC_MSGU_CFG_TABLE_RESET 0x002 /* Inbound doorbell bit1 */ 45285242Sachim#define SPC_MSGU_CFG_TABLE_FREEZE 0x004 /* Inbound doorbell bit2 */ 46285242Sachim#define SPC_MSGU_CFG_TABLE_UNFREEZE 0x008 /* Inbound doorbell bit4 */ 47285242Sachim#define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO 0x080 /* Inbound doorbell bit7 SPCV */ 48285242Sachim#define SPCV_MSGU_HALT_CPUS 0x100 /* Inbound doorbell bit8 SPCV */ 49285242Sachim 50285242Sachim/***** Notes *****/ 51285242Sachim/* The firmware side is using Little Endian (MIPs). */ 52285242Sachim/* So anything sending or receiving from FW must be in Little Endian */ 53285242Sachim/*******************************************************************************/ 54285242Sachim/** \struct mpiMsgHeader_s 55285242Sachim * \brief MPI message header 56285242Sachim * 57285242Sachim * The mpiMsgHeader_s defines the fields in the header of every message 58285242Sachim */ 59285242Sachim/*******************************************************************************/ 60285242Sachim/* This structire defines the fields in the header of every message */ 61285242Sachim 62285242Sachim 63285242Sachimstruct mpiMsgHeader_s 64285242Sachim{ 65285242Sachim bit32 Header; /* Bits [11:0] - Message operation code */ 66285242Sachim /* Bits [15:12] - Message Category */ 67285242Sachim /* Bits [21:16] - Outboundqueue ID for the operation completion message */ 68285242Sachim /* Bits [23:22] - Reserved */ 69285242Sachim /* Bits [28:24] - Buffer Count, indicates how many buffer are allocated for the massage */ 70285242Sachim /* Bits [30:29] - Reserved */ 71285242Sachim /* Bits [31] - Message Valid bit */ 72285242Sachim}; 73285242Sachim 74285242Sachimtypedef struct mpiMsgHeader_s mpiMsgHeader_t; 75285242Sachim 76285242Sachim#define V_BIT 0x1 77285242Sachim 78285242Sachim#define V_MASK 0x1 79285242Sachim#define BC_MASK 0x1F 80285242Sachim#define OBID_MASK 0x3F 81285242Sachim#define CAT_MASK 0x0F 82285242Sachim#define OPCODE_MASK 0xFFF 83285242Sachim#define HEADER_V_MASK 0x80000000 84285242Sachim#define HEADER_BC_MASK 0x1f000000 85285242Sachim 86285242Sachim#ifndef SPC_CONFIG 87285242Sachim/*******************************************************************************/ 88285242Sachim/** \struct spc_ConfigMainDescriptor_s 89285242Sachim * \brief This structure is used to configure main part of Configuration Table 90285242Sachim * 91285242Sachim * This structure specifies all required attributes to configuration table 92285242Sachim */ 93285242Sachim/*******************************************************************************/ 94285242Sachim/* new MPI configuration main table */ 95285242Sachimstruct spc_configMainDescriptor_s 96285242Sachim{ 97285242Sachim bit8 Signature[4]; /**< DW0 signature - Indicate coherent table */ 98285242Sachim bit32 InterfaceRev; /**< DW1 Revsion of Interface */ 99285242Sachim bit32 FWRevision; /**< DW2 Revsion of FW */ 100285242Sachim bit32 MaxOutstandingIO; /**< DW3 Max outstanding IO */ 101285242Sachim bit32 MDevMaxSGL; /**< DW4 Maximum SGL elements & Max Devices */ 102285242Sachim /* bit0-15 Maximum SGL */ 103285242Sachim /* bit16-31 Maximum Devices */ 104285242Sachim bit32 ContrlCapFlag; /**< DW5 Controller Capability */ 105285242Sachim /* bit0-7 Max number of inbound queue */ 106285242Sachim /* bit8-15 Max number of outbound queue */ 107285242Sachim /* bit16 high priority of inbound queue is supported */ 108285242Sachim /* bit17 reserved */ 109285242Sachim /* bit18 interrupt coalescing is supported, SPCV-reserved */ 110285242Sachim /* bit19-24 Maximum number of valid phys */ 111285242Sachim /* bit25-31 SAS Revision SPecification */ 112285242Sachim bit32 GSTOffset; /**< DW6 General Status Table */ 113285242Sachim bit32 inboundQueueOffset; /**< DW7 inbound configuration table offset */ 114285242Sachim /* bit23-0 inbound queue table offset */ 115285242Sachim /* bit31-24 entry size, new in SPCV */ 116285242Sachim bit32 outboundQueueOffset; /**< DW8 outbound configuration table offset */ 117285242Sachim /* bit23-0 outbound queue table offset */ 118285242Sachim /* bit31-24 entry size, new in SPCV */ 119285242Sachim bit32 iQNPPD_HPPD_GEvent; /**< DW9 inbound Queue Process depth and General Event */ 120285242Sachim /* bit0-7 inbound normal priority process depth */ 121285242Sachim /* bit8-15 inbound high priority process depth */ 122285242Sachim /* bit16-23 OQ number to receive GENERAL_EVENT Notification */ 123285242Sachim /* bit24-31 OQ number to receive DEVICE_HANDLE_REMOVAL Notification */ 124285242Sachim bit32 outboundHWEventPID0_3; /**< DWA outbound HW event for PortId 0 to 3, SPCV-reserved */ 125285242Sachim /* bit0-7 outbound queue number of SAS_HW event for PhyId 0 */ 126285242Sachim /* bit8-15 outbound queue number of SAS_HW event for PhyId 1 */ 127285242Sachim /* bit16-23 outbound queue number of SAS_HW event for PhyId 2 */ 128285242Sachim /* bit24-31 outbound queue number of SAS_HW event for PhyId 3 */ 129285242Sachim bit32 outboundHWEventPID4_7; /**< DWB outbound HW event for PortId 4 to 7, SPCV-reserved */ 130285242Sachim /* bit0-7 outbound queue number of SAS_HW event for PhyId 4 */ 131285242Sachim /* bit8-15 outbound queue number of SAS_HW event for PhyId 5 */ 132285242Sachim /* bit16-23 outbound queue number of SAS_HW event for PhyId 6 */ 133285242Sachim /* bit24-31 outbound queue number of SAS_HW event for PhyId 7 */ 134285242Sachim bit32 outboundNCQEventPID0_3; /**< DWC outbound NCQ event for PortId 0 to 3, SPCV-reserved */ 135285242Sachim /* bit0-7 outbound queue number of SATA_NCQ event for PhyId 0 */ 136285242Sachim /* bit8-15 outbound queue number of SATA_NCQ event for PhyId 1 */ 137285242Sachim /* bit16-23 outbound queue number of SATA_NCQ event for PhyId 2 */ 138285242Sachim /* bit24-31 outbound queue number of SATA_NCQ event for PortId 3 */ 139285242Sachim bit32 outboundNCQEventPID4_7; /**< DWD outbound NCQ event for PortId 4 to 7, SPCV-reserved*/ 140285242Sachim /* bit0-7 outbound queue number of SATA_NCQ event for PhyId 4 */ 141285242Sachim /* bit8-15 outbound queue number of SATA_NCQ event for PhyId 5 */ 142285242Sachim /* bit16-23 outbound queue number of SATA_NCQ event for PhyId 6 */ 143285242Sachim /* bit24-31 outbound queue number of SATA_NCQ event for PhyId 7 */ 144285242Sachim bit32 outboundTargetITNexusEventPID0_3; /**< DWE outbound target ITNexus Event for PortId 0 to 3, SPCV-reserved */ 145285242Sachim /* bit0-7 outbound queue number of ITNexus event for PhyId 0 */ 146285242Sachim /* bit8-15 outbound queue number of ITNexus event for PhyId 1 */ 147285242Sachim /* bit16-23 outbound queue number of ITNexus event for PhyId 2 */ 148285242Sachim /* bit24-31 outbound queue number of ITNexus event for PhyId 3 */ 149285242Sachim bit32 outboundTargetITNexusEventPID4_7; /**< DWF outbound target ITNexus Event for PortId 4 to 7, SPCV-reserved */ 150285242Sachim /* bit0-7 outbound queue number of ITNexus event for PhyId 4 */ 151285242Sachim /* bit8-15 outbound queue number of ITNexus event for PhyId 5 */ 152285242Sachim /* bit16-23 outbound queue number of ITNexus event for PhyId 6 */ 153285242Sachim /* bit24-31 outbound queue number of ITNexus event for PhyId 7 */ 154285242Sachim bit32 outboundTargetSSPEventPID0_3; /**< DW10 outbound target SSP event for PordId 0 to 3, SPCV-reserved */ 155285242Sachim /* bit0-7 outbound queue number of SSP event for PhyId 0 */ 156285242Sachim /* bit8-15 outbound queue number of SSP event for PhyId 1 */ 157285242Sachim /* bit16-23 outbound queue number of SSP event for PhyId 2 */ 158285242Sachim /* bit24-31 outbound queue number of SSP event for PhyId 3 */ 159285242Sachim bit32 outboundTargetSSPEventPID4_7; /**< DW11 outbound target SSP event for PordId 4 to 7, SPCV-reserved */ 160285242Sachim /* bit0-7 outbound queue number of SSP event for PhyId 4 */ 161285242Sachim /* bit8-15 outbound queue number of SSP event for PhyId 5 */ 162285242Sachim /* bit16-23 outbound queue number of SSP event for PhyId 6 */ 163285242Sachim /* bit24-31 outbound queue number of SSP event for PhyId 7 */ 164285242Sachim bit32 ioAbortDelay; /**< DW12 IO Abort Delay (bit15:0) MPI_TABLE_CHANGE*/ 165285242Sachim bit32 custset; /**< DW13 custset */ 166285242Sachim bit32 upperEventLogAddress; /**< DW14 Upper physical MSGU Event log address */ 167285242Sachim bit32 lowerEventLogAddress; /**< DW15 Lower physical MSGU Event log address */ 168285242Sachim bit32 eventLogSize; /**< DW16 Size of MSGU Event log, 0 means log disable */ 169285242Sachim bit32 eventLogOption; /**< DW17 Option of MSGU Event log */ 170285242Sachim /* bit3-0 log severity, 0x0 Disable Logging */ 171285242Sachim /* 0x1 Critical Error */ 172285242Sachim /* 0x2 Minor Error */ 173285242Sachim /* 0x3 Warning */ 174285242Sachim /* 0x4 Information */ 175285242Sachim /* 0x5 Debugging */ 176285242Sachim /* 0x6 - 0xF Reserved */ 177285242Sachim bit32 upperIOPeventLogAddress; /**< DW18 Upper physical IOP Event log address */ 178285242Sachim bit32 lowerIOPeventLogAddress; /**< DW19 Lower physical IOP Event log address */ 179285242Sachim bit32 IOPeventLogSize; /**< DW1A Size of IOP Event log, 0 means log disable */ 180285242Sachim bit32 IOPeventLogOption; /**< DW1B Option of IOP Event log */ 181285242Sachim /* bit3-0 log severity, 0x0 Critical Error */ 182285242Sachim /* 0x1 Minor Error */ 183285242Sachim /* 0x2 Warning */ 184285242Sachim /* 0x3 Information */ 185285242Sachim /* 0x4 Unknown */ 186285242Sachim /* 0x5 - 0xF Reserved */ 187285242Sachim bit32 FatalErrorInterrupt; /**< DW1C Fatal Error Interrupt enable and vector */ 188285242Sachim /* bit0 Fatal Error Interrupt Enable */ 189285242Sachim /* bit1 PI/CI 64bit address */ 190285242Sachim /* bit2 SGPIO IOMB support */ 191285242Sachim /* bit6-2 Reserved */ 192285242Sachim /* bit7 OQ NP/HPriority Path enable */ 193285242Sachim /* bit15-8 Fatal Error Interrupt Vector */ 194285242Sachim /* bit16 Enable IQ/OQ 64 */ 195285242Sachim /* bit17 Interrupt Reassertion Enable */ 196285242Sachim /* bit18 Interrupt Reassertion Delay in ms */ 197285242Sachim /* bit31-19 Interrupt Reassertion delay, 0-default 1ms */ 198285242Sachim bit32 FatalErrorDumpOffset0; /**< DW1D FERDOMS-GU Fatal Error Register Dump Offset for MSGU */ 199285242Sachim bit32 FatalErrorDumpLength0; /**< DW1E FERDLMS-GU Fatal Error Register Dump Length for MSGU */ 200285242Sachim bit32 FatalErrorDumpOffset1; /**< DW1F FERDO-SSTRUCPCS Fatal Error Register Dump Offset for IOP */ 201285242Sachim bit32 FatalErrorDumpLength1; /**< DW20 FERDLSTRUCTTPCS Fatal Error Register Dump Length for IOP */ 202285242Sachim bit32 HDAModeFlags; /**< DW21 HDA Mode Flags, SPCV-reserved */ 203285242Sachim bit32 analogSetupTblOffset; /**< DW22 SPASTO Phy Calibration Table offset */ 204285242Sachim /* bit23-0 phy calib table offset */ 205285242Sachim /* bit31-24 entry size */ 206285242Sachim bit32 InterruptVecTblOffset; /**< DW23 Interrupt Vector Table MPI_TABLE_CHANG */ 207285242Sachim /* bit23-0 interrupt vector table offset */ 208285242Sachim /* bit31-24 entry size */ 209285242Sachim bit32 phyAttributeTblOffset; /**< DW24 SAS Phy Attribute Table Offset MPI_TABLE_CHANG*/ 210285242Sachim /* bit23-0 phy attribute table offset */ 211285242Sachim /* bit31-24 entry size */ 212285242Sachim bit32 portRecoveryResetTimer; /* Offset 0x25 [31:16] Port recovery timer default that is 0 213285242Sachim used for all SAS ports. Granularity of this timer is 100ms. The host can 214285242Sachim change the individual port recovery timer by using the PORT_CONTROL 215285242Sachim [15:0] Port reset timer default that is used 3 (i.e 300ms) for all 216285242Sachim SAS ports. Granularity of this timer is 100ms. Host can change the 217285242Sachim individual port recovery timer by using PORT_CONTROL Command */ 218285242Sachim bit32 interruptReassertionDelay; /* Offset 0x26 [23:0] Remind host of outbound completion 0 disabled 100usec per increment */ 219285242Sachim 220285242Sachim bit32 ilaRevision; /* Offset 0x27 */ 221285242Sachim}; 222285242Sachim 223285242Sachim/* main configuration offset - byte offset */ 224285242Sachim#define MAIN_SIGNATURE_OFFSET 0x00 /* DWORD 0x00 (R) */ 225285242Sachim#define MAIN_INTERFACE_REVISION 0x04 /* DWORD 0x01 (R) */ 226285242Sachim#define MAIN_FW_REVISION 0x08 /* DWORD 0x02 (R) */ 227285242Sachim#define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C /* DWORD 0x03 (R) */ 228285242Sachim#define MAIN_MAX_SGL_OFFSET 0x10 /* DWORD 0x04 (R) */ 229285242Sachim#define MAIN_CNTRL_CAP_OFFSET 0x14 /* DWORD 0x05 (R) */ 230285242Sachim#define MAIN_GST_OFFSET 0x18 /* DWORD 0x06 (R) */ 231285242Sachim#define MAIN_IBQ_OFFSET 0x1C /* DWORD 0x07 (R) */ 232285242Sachim#define MAIN_OBQ_OFFSET 0x20 /* DWORD 0x08 (R) */ 233285242Sachim#define MAIN_IQNPPD_HPPD_OFFSET 0x24 /* DWORD 0x09 (W) */ 234285242Sachim#define MAIN_OB_HW_EVENT_PID03_OFFSET 0x28 /* DWORD 0x0A (W) */ /* reserved for SPCV */ 235285242Sachim#define MAIN_OB_HW_EVENT_PID47_OFFSET 0x2C /* DWORD 0x0B (W) */ /* reserved for SPCV */ 236285242Sachim#define MAIN_OB_NCQ_EVENT_PID03_OFFSET 0x30 /* DWORD 0x0C (W) */ /* reserved for SPCV */ 237285242Sachim#define MAIN_OB_NCQ_EVENT_PID47_OFFSET 0x34 /* DWORD 0x0D (W) */ /* reserved for SPCV */ 238285242Sachim#define MAIN_TITNX_EVENT_PID03_OFFSET 0x38 /* DWORD 0x0E (W) */ /* reserved for SPCV */ 239285242Sachim#define MAIN_TITNX_EVENT_PID47_OFFSET 0x3C /* DWORD 0x0F (W) */ /* reserved for SPCV */ 240285242Sachim#define MAIN_OB_SSP_EVENT_PID03_OFFSET 0x40 /* DWORD 0x10 (W) */ /* reserved for SPCV */ 241285242Sachim#define MAIN_OB_SSP_EVENT_PID47_OFFSET 0x44 /* DWORD 0x11 (W) */ /* reserved for SPCV */ 242285242Sachim#define MAIN_IO_ABORT_DELAY 0x48 /* DWORD 0x12 (W) */ /* reserved for SPCV */ 243285242Sachim#define MAIN_CUSTOMER_SETTING 0x4C /* DWORD 0x13 (W) */ /* reserved for SPCV */ 244285242Sachim#define MAIN_EVENT_LOG_ADDR_HI 0x50 /* DWORD 0x14 (W) */ 245285242Sachim#define MAIN_EVENT_LOG_ADDR_LO 0x54 /* DWORD 0x15 (W) */ 246285242Sachim#define MAIN_EVENT_LOG_BUFF_SIZE 0x58 /* DWORD 0x16 (W) */ 247285242Sachim#define MAIN_EVENT_LOG_OPTION 0x5C /* DWORD 0x17 (W) */ 248285242Sachim#define MAIN_IOP_EVENT_LOG_ADDR_HI 0x60 /* DWORD 0x18 (W) */ 249285242Sachim#define MAIN_IOP_EVENT_LOG_ADDR_LO 0x64 /* DWORD 0x19 (W) */ 250285242Sachim#define MAIN_IOP_EVENT_LOG_BUFF_SIZE 0x68 /* DWORD 0x1A (W) */ 251285242Sachim#define MAIN_IOP_EVENT_LOG_OPTION 0x6C /* DWORD 0x1B (W) */ 252285242Sachim#define MAIN_FATAL_ERROR_INTERRUPT 0x70 /* DWORD 0x1C (W) */ 253285242Sachim#define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74 /* DWORD 0x1D (R) */ 254285242Sachim#define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78 /* DWORD 0x1E (R) */ 255285242Sachim#define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C /* DWORD 0x1F (R) */ 256285242Sachim#define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80 /* DWORD 0x20 (R) */ 257285242Sachim#define MAIN_HDA_FLAGS_OFFSET 0x84 /* DWORD 0x21 (R) */ /* reserved for SPCV */ 258285242Sachim#define MAIN_ANALOG_SETUP_OFFSET 0x88 /* DWORD 0x22 (R) */ 259285242Sachim#define MAIN_INT_VEC_TABLE_OFFSET 0x8C /* DWORD 0x23 (W) */ /* for SPCV */ 260285242Sachim#define MAIN_PHY_ATTRIBUTE_OFFSET 0x90 /* DWORD 0x24 (W) */ /* for SPCV */ 261285242Sachim#define MAIN_PRECTD_PRESETD 0x94 /* DWORD 0x25 (W) */ /* for SPCV */ 262285242Sachim#define MAIN_IRAD_RESERVED 0x98 /* DWORD 0x26 (W) */ /* for SPCV */ 263285242Sachim#define MAIN_MOQFOT_MOQFOES 0x9C /* DWORD 0x27 (W) */ /* for SPCV */ 264285242Sachim#define MAIN_MERRDCTO_MERRDCES 0xA0 /* DWORD 0x28 (W) */ /* for SPCV */ 265285242Sachim#define MAIN_ILAT_ILAV_ILASMRN_ILAMRN_ILAMJN 0xA4 /* DWORD 0x29 (W) */ /* for SPCV */ 266285242Sachim#define MAIN_INACTIVE_ILA_REVSION 0xA8 /* DWORD 0x2A (W) */ /* for SPCV V 3.02 */ 267285242Sachim#define MAIN_SEEPROM_REVSION 0xAC /* DWORD 0x2B (W) */ /* for SPCV V 3.02 */ 268285242Sachim#define MAIN_UNKNOWN1 0xB0 /* DWORD 0x2C (W) */ /* for SPCV V 3.03 */ 269285242Sachim#define MAIN_UNKNOWN2 0xB4 /* DWORD 0x2D (W) */ /* for SPCV V 3.03 */ 270285242Sachim#define MAIN_UNKNOWN3 0xB8 /* DWORD 0x2E (W) */ /* for SPCV V 3.03 */ 271285242Sachim#define MAIN_XCBI_REF_TAG_PAT 0xBC /* DWORD 0x2F (W) */ /* for SPCV V 3.03 */ 272285242Sachim#define MAIN_AWT_MIDRANGE 0xC0 /* DWORD 0x30 (W) */ /* for SPCV V 3.03 */ 273285242Sachim 274285242Sachim 275285242Sachimtypedef struct spc_configMainDescriptor_s spc_configMainDescriptor_t; 276285242Sachim#define SPC_CONFIG 277285242Sachim#endif 278285242Sachim 279285242Sachim/* bit to disable end to end crc checking ins SPCv */ 280285242Sachim#define MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE 0x00010000 281285242Sachim 282285242Sachim/* bit mask for field Controller Capability in main part */ 283285242Sachim#define MAIN_MAX_IB_MASK 0x000000ff /* bit7-0 */ 284285242Sachim#define MAIN_MAX_OB_MASK 0x0000ff00 /* bit15-8 */ 285285242Sachim#define MAIN_PHY_COUNT_MASK 0x01f80000 /* bit24-19 */ 286285242Sachim#define MAIN_QSUPPORT_BITS 0x0007ffff 287285242Sachim#define MAIN_SAS_SUPPORT_BITS 0xfe000000 288285242Sachim 289285242Sachim/* bit mask for field max sgl in main part */ 290285242Sachim#define MAIN_MAX_SGL_BITS 0xFFFF 291285242Sachim#define MAIN_MAX_DEV_BITS 0xFFFF0000 292285242Sachim 293285242Sachim/* bit mask for HDA flags field */ 294285242Sachim#define MAIN_HDA_FLAG_BITS 0x000000FF 295285242Sachim 296285242Sachim#define FATAL_ERROR_INT_BITS 0xFF 297285242Sachim#define INT_REASRT_ENABLE 0x00020000 298285242Sachim#define INT_REASRT_MS_ENABLE 0x00040000 299285242Sachim#define INT_REASRT_DELAY_BITS 0xFFF80000 300285242Sachim 301285242Sachim#define MAX_VALID_PHYS 8 302285242Sachim#define IB_QUEUE_CFGSIZE 64 303285242Sachim#define OB_QUEUE_CFGSIZE 64 304285242Sachim 305285242Sachim/* inbound queue configuration offset - byte offset */ 306285242Sachim#define IB_PROPERITY_OFFSET 0x00 307285242Sachim#define IB_BASE_ADDR_HI_OFFSET 0x04 308285242Sachim#define IB_BASE_ADDR_LO_OFFSET 0x08 309285242Sachim#define IB_CI_BASE_ADDR_HI_OFFSET 0x0C 310285242Sachim#define IB_CI_BASE_ADDR_LO_OFFSET 0x10 311285242Sachim#define IB_PIPCI_BAR 0x14 312285242Sachim#define IB_PIPCI_BAR_OFFSET 0x18 313285242Sachim#define IB_RESERVED_OFFSET 0x1C 314285242Sachim 315285242Sachim/* outbound queue configuration offset - byte offset */ 316285242Sachim#define OB_PROPERITY_OFFSET 0x00 317285242Sachim#define OB_BASE_ADDR_HI_OFFSET 0x04 318285242Sachim#define OB_BASE_ADDR_LO_OFFSET 0x08 319285242Sachim#define OB_PI_BASE_ADDR_HI_OFFSET 0x0C 320285242Sachim#define OB_PI_BASE_ADDR_LO_OFFSET 0x10 321285242Sachim#define OB_CIPCI_BAR 0x14 322285242Sachim#define OB_CIPCI_BAR_OFFSET 0x18 323285242Sachim#define OB_INTERRUPT_COALES_OFFSET 0x1C 324285242Sachim#define OB_DYNAMIC_COALES_OFFSET 0x20 325285242Sachim 326285242Sachim#define OB_PROPERTY_INT_ENABLE 0x40000000 327285242Sachim 328285242Sachim/* General Status Table offset - byte offset */ 329285242Sachim#define GST_GSTLEN_MPIS_OFFSET 0x00 330285242Sachim#define GST_IQ_FREEZE_STATE0_OFFSET 0x04 331285242Sachim#define GST_IQ_FREEZE_STATE1_OFFSET 0x08 332285242Sachim#define GST_MSGUTCNT_OFFSET 0x0C 333285242Sachim#define GST_IOPTCNT_OFFSET 0x10 334285242Sachim#define GST_IOP1TCNT_OFFSET 0x14 335285242Sachim#define GST_PHYSTATE_OFFSET 0x18 /* SPCV reserved */ 336285242Sachim#define GST_PHYSTATE0_OFFSET 0x18 /* SPCV reserved */ 337285242Sachim#define GST_PHYSTATE1_OFFSET 0x1C /* SPCV reserved */ 338285242Sachim#define GST_PHYSTATE2_OFFSET 0x20 /* SPCV reserved */ 339285242Sachim#define GST_PHYSTATE3_OFFSET 0x24 /* SPCV reserved */ 340285242Sachim#define GST_PHYSTATE4_OFFSET 0x28 /* SPCV reserved */ 341285242Sachim#define GST_PHYSTATE5_OFFSET 0x2C /* SPCV reserved */ 342285242Sachim#define GST_PHYSTATE6_OFFSET 0x30 /* SPCV reserved */ 343285242Sachim#define GST_PHYSTATE7_OFFSET 0x34 /* SPCV reserved */ 344285242Sachim#define GST_GPIO_PINS_OFFSET 0x38 345285242Sachim#define GST_RERRINFO_OFFSET 0x44 346285242Sachim 347285242Sachim/* General Status Table - MPI state */ 348285242Sachim#define GST_MPI_STATE_UNINIT 0x00 349285242Sachim#define GST_MPI_STATE_INIT 0x01 350285242Sachim#define GST_MPI_STATE_TERMINATION 0x02 351285242Sachim#define GST_MPI_STATE_ERROR 0x03 352285242Sachim#define GST_MPI_STATE_MASK 0x07 353285242Sachim 354285242Sachim#define GST_INF_STATE_BITS 0xfffe0007 355285242Sachim 356285242Sachim 357285242Sachim/* MPI fatal and non fatal offset mask */ 358285242Sachim#define MPI_FATAL_ERROR_TABLE_OFFSET_MASK 0xFFFFFF 359285242Sachim#define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24) /* for SPCV */ 360285242Sachim 361285242Sachim/* MPI fatal and non fatal Error dump capture table offset - byte offset */ 362285242Sachim#define MPI_FATAL_EDUMP_TABLE_LO_OFFSET 0x00 /* HNFBUFL */ 363285242Sachim#define MPI_FATAL_EDUMP_TABLE_HI_OFFSET 0x04 /* HNFBUFH */ 364285242Sachim#define MPI_FATAL_EDUMP_TABLE_LENGTH 0x08 /* HNFBLEN */ 365285242Sachim#define MPI_FATAL_EDUMP_TABLE_HANDSHAKE 0x0C /* FDDHSHK */ 366285242Sachim#define MPI_FATAL_EDUMP_TABLE_STATUS 0x10 /* FDDTSTAT */ 367285242Sachim#define MPI_FATAL_EDUMP_TABLE_ACCUM_LEN 0x14 /* ACCDDLEN */ 368285242Sachim/* */ 369285242Sachim#define MPI_FATAL_EDUMP_HANDSHAKE_RDY 0x1 370285242Sachim#define MPI_FATAL_EDUMP_HANDSHAKE_BUSY 0x0 371285242Sachim/* */ 372285242Sachim#define MPI_FATAL_EDUMP_TABLE_STAT_RSVD 0x0 373285242Sachim#define MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED 0x1 374285242Sachim#define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA 0x2 375285242Sachim#define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE 0x3 376285242Sachim 377285242Sachim#define IOCTL_ERROR_NO_FATAL_ERROR 0x77 378285242Sachim 379285242Sachim/*******************************************************************************/ 380285242Sachim/** \struct spc_GSTableDescriptor_s 381285242Sachim * \brief This structure is used for SPC MPI General Status Table 382285242Sachim * 383285242Sachim * This structure specifies all required attributes to Gereral Status Table 384285242Sachim */ 385285242Sachim/*******************************************************************************/ 386285242Sachimstruct spc_GSTableDescriptor_s 387285242Sachim{ 388285242Sachim bit32 GSTLenMPIS; /**< DW0 - GST Length, MPI State */ 389285242Sachim /**< bit02-00 MPI state */ 390285242Sachim /**< 000 - not initialized, 001 - initialized, 391285242Sachim 010 - Configuration termination in progress */ 392285242Sachim /**< bit3 - IQ Frozen */ 393285242Sachim /**< bit15-04 GST Length */ 394285242Sachim /**< bit31-16 MPI-S Initialize Error */ 395285242Sachim bit32 IQFreezeState0; /**< DW1 - Inbound Queue Freeze State0 */ 396285242Sachim bit32 IQFreezeState1; /**< DW2 - Inbound Qeue Freeze State1 */ 397285242Sachim bit32 MsguTcnt; /**< DW3 - MSGU Tick count */ 398285242Sachim bit32 IopTcnt; /**< DW4 - IOP Tick count */ 399285242Sachim bit32 Iop1Tcnt; /**< DW5 - IOP1 Tick count */ 400285242Sachim bit32 PhyState[MAX_VALID_PHYS]; /* SPCV = reserved */ 401285242Sachim /**< DW6 to DW 0D - Phy Link state 0 to 7, Phy Start State 0 to 7 */ 402285242Sachim /**< bit00 Phy Start state n, 0 not started, 1 started */ 403285242Sachim /**< bit01 Phy Link state n, 0 link down, 1 link up */ 404285242Sachim /**< bit31-2 Reserved */ 405285242Sachim bit32 GPIOpins; /**< DWE - GPIO pins */ 406285242Sachim bit32 reserved1; /**< DWF - reserved */ 407285242Sachim bit32 reserved2; /**< DW10 - reserved */ 408285242Sachim bit32 recoverErrInfo[8]; /**< DW11 to DW18 - Recoverable Error Information */ 409285242Sachim}; 410285242Sachim 411285242Sachimtypedef struct spc_GSTableDescriptor_s spc_GSTableDescriptor_t; 412285242Sachim 413285242Sachim/*******************************************************************************/ 414285242Sachim/** \struct spc_SPASTable_s 415285242Sachim * \brief SAS Phy Analog Setup Table 416285242Sachim * 417285242Sachim * The spc_SPASTable_s structure is used to set Phy Calibration 418285242Sachim * attributes 419285242Sachim */ 420285242Sachim/*******************************************************************************/ 421285242Sachimstruct spc_SPASTable_s 422285242Sachim{ 423285242Sachim bit32 spaReg0; /* transmitter per port configuration 1 SAS_SATA G1 */ 424285242Sachim bit32 spaReg1; /* transmitter per port configuration 2 SAS_SATA G1*/ 425285242Sachim bit32 spaReg2; /* transmitter per port configuration 3 SAS_SATA G1*/ 426285242Sachim bit32 spaReg3; /* transmitter configuration 1 */ 427285242Sachim bit32 spaReg4; /* reveiver per port configuration 1 SAS_SATA G1G2 */ 428285242Sachim bit32 spaReg5; /* reveiver per port configuration 2 SAS_SATA G3 */ 429285242Sachim bit32 spaReg6; /* reveiver per configuration 1 */ 430285242Sachim bit32 spaReg7; /* reveiver per configuration 2 */ 431285242Sachim bit32 reserved[2]; /* reserved */ 432285242Sachim}; 433285242Sachim 434285242Sachimtypedef struct spc_SPASTable_s spc_SPASTable_t; 435285242Sachim 436285242Sachim/*******************************************************************************/ 437285242Sachim/** \struct spc_inboundQueueDescriptor_s 438285242Sachim * \brief This structure is used to configure inbound queues 439285242Sachim * 440285242Sachim * This structure specifies all required attributes to configure inbound queues 441285242Sachim */ 442285242Sachim/*******************************************************************************/ 443285242Sachimstruct spc_inboundQueueDescriptor_s 444285242Sachim{ 445285242Sachim bit32 elementPriSizeCount; /**< Priority, Size, Count in the queue */ 446285242Sachim /**< bit00-15 Count */ 447285242Sachim /**< When set to 0, this queue is disabled */ 448285242Sachim /**< bit16-29 Size */ 449285242Sachim /**< bit30-31 Priority 00:Normal, 01:High Priority */ 450285242Sachim bit32 upperBaseAddress; /**< Upper address bits for the queue message buffer pool */ 451285242Sachim bit32 lowerBaseAddress; /**< Lower address bits for the queue message buffer pool */ 452285242Sachim bit32 ciUpperBaseAddress; /**< Upper physical address for inbound queue CI */ 453285242Sachim bit32 ciLowerBaseAddress; /**< Lower physical address for inbound queue CI */ 454285242Sachim bit32 PIPCIBar; /**< PCI BAR for PI Offset */ 455285242Sachim bit32 PIOffset; /**< Offset address for inbound queue PI */ 456285242Sachim bit32 reserved; /**< reserved */ 457285242Sachim}; 458285242Sachim 459285242Sachimtypedef struct spc_inboundQueueDescriptor_s spc_inboundQueueDescriptor_t; 460285242Sachim 461285242Sachim/*******************************************************************************/ 462285242Sachim/** \struct spc_outboundQueueDescriptor_s 463285242Sachim * \brief This structure is used to configure outbound queues 464285242Sachim * 465285242Sachim * This structure specifies all required attributes to configure outbound queues 466285242Sachim */ 467285242Sachim/*******************************************************************************/ 468285242Sachimstruct spc_outboundQueueDescriptor_s 469285242Sachim{ 470285242Sachim bit32 elementSizeCount; /**< Size & Count of each element (slot) in the queue) */ 471285242Sachim /**< bit00-15 Count */ 472285242Sachim /**< When set to 0, this queue is disabled */ 473285242Sachim /**< bit16-29 Size */ 474285242Sachim /**< bit30 Interrupt enable/disable */ 475285242Sachim /**< bit31 reserved */ 476285242Sachim bit32 upperBaseAddress; /**< Upper address bits for the queue message buffer pool */ 477285242Sachim bit32 lowerBaseAddress; /**< Lower address bits for the queue message buffer pool */ 478285242Sachim bit32 piUpperBaseAddress; /**< PI Upper Base Address for outbound queue */ 479285242Sachim bit32 piLowerBaseAddress; /**< PI Lower Base Address for outbound queue */ 480285242Sachim bit32 CIPCIBar; /**< PCI BAR for CI Offset */ 481285242Sachim bit32 CIOffset; /**< Offset address for outbound queue CI */ 482285242Sachim bit32 interruptVecCntDelay; /**< Delay in microseconds before the interrupt is asserted */ 483285242Sachim /**< if the interrupt threshold has not been reached */ 484285242Sachim /**< Number of interrupt events before the interrupt is asserted */ 485285242Sachim /**< If set to 0, interrupts for this queue are disable */ 486285242Sachim /**< Interrupt vector number for this queue */ 487285242Sachim /**< Note that the interrupt type can be MSI or MSI-X */ 488285242Sachim /**< depending on the system configuration */ 489285242Sachim /**< bit00-15 Delay */ 490285242Sachim /**< bit16-23 Count */ 491285242Sachim /**< bit24-31 Vector */ 492285242Sachim bit32 DInterruptTOPCIOffset; /**< Dynamic Interrupt Coalescing Timeout PCI Bar Offset */ 493285242Sachim}; 494285242Sachim 495285242Sachimtypedef struct spc_outboundQueueDescriptor_s spc_outboundQueueDescriptor_t; 496285242Sachim 497285242Sachimtypedef struct InterruptVT_s 498285242Sachim{ 499285242Sachim bit32 iccict; /**< DW0 - Interrupt Colescing Control and Timer */ 500285242Sachim bit32 iraeirad; /**< DW1 - Interrupt Reassertion Enable/Delay */ 501285242Sachim} InterruptVT_t; 502285242Sachim 503285242Sachimtypedef struct mpiInterruptVT_s 504285242Sachim{ 505285242Sachim InterruptVT_t IntVecTble[MAX_NUM_VECTOR << 1]; 506285242Sachim} mpiInterruptVT_t; 507285242Sachim 508285242Sachim#define INT_VT_Coal_CNT_TO 0 509285242Sachim#define INT_VT_Coal_ReAssert_Enab 4 510285242Sachim 511285242Sachimtypedef struct phyAttrb_s 512285242Sachim{ 513285242Sachim bit32 phyState; 514285242Sachim bit32 phyEventOQ; 515285242Sachim} phyAttrb_t; 516285242Sachim 517285242Sachimtypedef struct sasPhyAttribute_s 518285242Sachim{ 519285242Sachim phyAttrb_t phyAttribute[MAX_VALID_PHYS]; 520285242Sachim}sasPhyAttribute_t; 521285242Sachim 522285242Sachim 523285242Sachim#define PHY_STATE 0 524285242Sachim#define PHY_EVENT_OQ 4 525285242Sachim 526285242Sachim/*******************************************************************************/ 527285242Sachim/** \struct spcMSGUConfig_s 528285242Sachim * \brief This structure is used to configure controller's message unit 529285242Sachim * 530285242Sachim */ 531285242Sachim/*******************************************************************************/ 532285242Sachimtypedef struct fwMSGUConfig_s 533285242Sachim{ 534285242Sachim spc_configMainDescriptor_t mainConfiguration; /**< main part of Configuration Table */ 535285242Sachim spc_GSTableDescriptor_t GeneralStatusTable; /**< MPI general status table */ 536285242Sachim spc_inboundQueueDescriptor_t inboundQueue[IB_QUEUE_CFGSIZE]; /**< Inbound queue configuration array */ 537285242Sachim spc_outboundQueueDescriptor_t outboundQueue[OB_QUEUE_CFGSIZE]; /**< Outbound queue configuration array */ 538285242Sachim agsaPhyAnalogSetupTable_t phyAnalogConfig; 539285242Sachim mpiInterruptVT_t interruptVTable; 540285242Sachim sasPhyAttribute_t phyAttributeTable; 541285242Sachim}fwMSGUConfig_t; 542285242Sachim 543285242Sachim 544285242Sachimtypedef void (*EnadDisabHandler_t)( 545285242Sachim agsaRoot_t *agRoot, 546285242Sachim bit32 interruptVectorIndex 547285242Sachim ); 548285242Sachim 549285242Sachimtypedef bit32 (*InterruptOurs_t)( 550285242Sachim agsaRoot_t *agRoot, 551285242Sachim bit32 interruptVectorIndex 552285242Sachim ); 553285242Sachim#endif /* __SPC_DEFS__ */ 554