sa.h revision 285242
1285242Sachim/******************************************************************************* 2285242Sachim*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3285242Sachim* 4285242Sachim*Redistribution and use in source and binary forms, with or without modification, are permitted provided 5285242Sachim*that the following conditions are met: 6285242Sachim*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7285242Sachim*following disclaimer. 8285242Sachim*2. Redistributions in binary form must reproduce the above copyright notice, 9285242Sachim*this list of conditions and the following disclaimer in the documentation and/or other materials provided 10285242Sachim*with the distribution. 11285242Sachim* 12285242Sachim*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13285242Sachim*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14285242Sachim*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15285242Sachim*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16285242Sachim*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17285242Sachim*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18285242Sachim*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19285242Sachim*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20285242Sachim* 21285242Sachim* $FreeBSD: projects/pms/sys/dev/pms/RefTisa/sallsdk/api/sa.h 285242 2015-07-07 13:17:02Z achim $ 22285242Sachim* 23285242Sachim********************************************************************************/ 24285242Sachim/*******************************************************************************/ 25285242Sachim/*! \file sa.h 26285242Sachim * \brief The file defines the constants, data structure, and functions defined by LL API 27285242Sachim */ 28285242Sachim/******************************************************************************/ 29285242Sachim 30285242Sachim#ifndef __SA_H__ 31285242Sachim#define __SA_H__ 32285242Sachim 33285242Sachim#include <dev/pms/RefTisa/sallsdk/api/sa_spec.h> 34285242Sachim#include <dev/pms/RefTisa/sallsdk/api/sa_err.h> 35285242Sachim 36285242Sachim/* TestBase needed to have the 'Multi-Data fetch disable' feature */ 37285242Sachim#define SA_CONFIG_MDFD_REGISTRY 38285242Sachim 39285242Sachim#define OSSA_OFFSET_OF(STRUCT_TYPE, FEILD) \ 40285242Sachim (bitptr)&(((STRUCT_TYPE *)0)->FEILD) 41285242Sachim 42285242Sachim#if defined(SA_CPU_LITTLE_ENDIAN) 43285242Sachim 44285242Sachim#define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 45285242Sachim (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16); 46285242Sachim 47285242Sachim#define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 48285242Sachim (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32); 49285242Sachim 50285242Sachim#define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 51285242Sachim (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) 52285242Sachim 53285242Sachim#define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 54285242Sachim (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) 55285242Sachim 56285242Sachim#define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 57285242Sachim (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \ 58285242Sachim (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)(((bit16)VALUE16)&0xFF); 59285242Sachim 60285242Sachim#define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 61285242Sachim (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \ 62285242Sachim (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \ 63285242Sachim (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \ 64285242Sachim (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)(((bit32)VALUE32)&0xFF); 65285242Sachim 66285242Sachim#define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 67285242Sachim (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 68285242Sachim (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); 69285242Sachim 70285242Sachim#define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 71285242Sachim (*(bit8 *)(((bit8 *)ADDR32)+3)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 72285242Sachim (*(bit8 *)(((bit8 *)ADDR32)+2)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \ 73285242Sachim (*(bit8 *)(((bit8 *)ADDR32)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \ 74285242Sachim (*(bit8 *)(((bit8 *)ADDR32))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))); 75285242Sachim 76285242Sachim#define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \ 77285242Sachim si_memcpy(DEST_ADDR, SRC_ADDR, LEN); 78285242Sachim 79285242Sachim 80285242Sachim#elif defined(SA_CPU_BIG_ENDIAN) 81285242Sachim 82285242Sachim#define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 83285242Sachim (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \ 84285242Sachim (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit16)VALUE16)&0xFF); 85285242Sachim 86285242Sachim#define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 87285242Sachim (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \ 88285242Sachim (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \ 89285242Sachim (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \ 90285242Sachim (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit32)VALUE32)&0xFF); 91285242Sachim 92285242Sachim#define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 93285242Sachim (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 94285242Sachim (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); 95285242Sachim 96285242Sachim#define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 97285242Sachim (*((bit8 *)(((bit8 *)ADDR32)+3))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 98285242Sachim (*((bit8 *)(((bit8 *)ADDR32)+2))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \ 99285242Sachim (*((bit8 *)(((bit8 *)ADDR32)+1))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \ 100285242Sachim (*((bit8 *)(((bit8 *)ADDR32)))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))); 101285242Sachim 102285242Sachim#define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 103285242Sachim (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16); 104285242Sachim 105285242Sachim#define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 106285242Sachim (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32); 107285242Sachim 108285242Sachim#define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 109285242Sachim (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); 110285242Sachim 111285242Sachim#define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 112285242Sachim (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); 113285242Sachim 114285242Sachim#define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \ 115285242Sachim si_memcpy(DEST_ADDR, SRC_ADDR, LEN); 116285242Sachim 117285242Sachim#else 118285242Sachim 119285242Sachim#error (Host CPU endianess undefined!!) 120285242Sachim 121285242Sachim#endif 122285242Sachim 123285242Sachim#define AGSA_WRITE_SGL(sglDest, sgLower, sgUpper, len, extReserved) \ 124285242Sachim OSSA_WRITE_LE_32(agRoot, sglDest, 0, sgLower); \ 125285242Sachim OSSA_WRITE_LE_32(agRoot, sglDest, 4, sgUpper); \ 126285242Sachim OSSA_WRITE_LE_32(agRoot, sglDest, 8, len); \ 127285242Sachim OSSA_WRITE_LE_32(agRoot, sglDest, 12, extReserved); 128285242Sachim 129285242Sachim 130285242Sachim/************************************************************************** 131285242Sachim * define byte swap macro * 132285242Sachim **************************************************************************/ 133285242Sachim/*! \def AGSA_FLIP_2_BYTES(_x) 134285242Sachim* \brief AGSA_FLIP_2_BYTES macro 135285242Sachim* 136285242Sachim* use to flip two bytes 137285242Sachim*/ 138285242Sachim#define AGSA_FLIP_2_BYTES(_x) ((bit16)(((((bit16)(_x))&0x00FF)<<8)| \ 139285242Sachim ((((bit16)(_x))&0xFF00)>>8))) 140285242Sachim 141285242Sachim/*! \def AGSA_FLIP_4_BYTES(_x) 142285242Sachim* \brief AGSA_FLIP_4_BYTES macro 143285242Sachim* 144285242Sachim* use to flip four bytes 145285242Sachim*/ 146285242Sachim#define AGSA_FLIP_4_BYTES(_x) ((bit32)(((((bit32)(_x))&0x000000FF)<<24)| \ 147285242Sachim ((((bit32)(_x))&0x0000FF00)<<8)| \ 148285242Sachim ((((bit32)(_x))&0x00FF0000)>>8)| \ 149285242Sachim ((((bit32)(_x))&0xFF000000)>>24))) 150285242Sachim 151285242Sachim 152285242Sachim#if defined(SA_CPU_LITTLE_ENDIAN) 153285242Sachim 154285242Sachim/*! \def LEBIT16_TO_BIT16(_x) 155285242Sachim* \brief LEBIT16_TO_BIT16 macro 156285242Sachim* 157285242Sachim* use to convert little endian bit16 to host bit16 158285242Sachim*/ 159285242Sachim#ifndef LEBIT16_TO_BIT16 160285242Sachim#define LEBIT16_TO_BIT16(_x) (_x) 161285242Sachim#endif 162285242Sachim 163285242Sachim/*! \def BIT16_TO_LEBIT16(_x) 164285242Sachim* \brief BIT16_TO_LEBIT16 macro 165285242Sachim* 166285242Sachim* use to convert host bit16 to little endian bit16 167285242Sachim*/ 168285242Sachim#ifndef BIT16_TO_LEBIT16 169285242Sachim#define BIT16_TO_LEBIT16(_x) (_x) 170285242Sachim#endif 171285242Sachim 172285242Sachim/*! \def BEBIT16_TO_BIT16(_x) 173285242Sachim* \brief BEBIT16_TO_BIT16 macro 174285242Sachim* 175285242Sachim* use to convert big endian bit16 to host bit16 176285242Sachim*/ 177285242Sachim#ifndef BEBIT16_TO_BIT16 178285242Sachim#define BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) 179285242Sachim#endif 180285242Sachim 181285242Sachim/*! \def BIT16_TO_BEBIT16(_x) 182285242Sachim* \brief BIT16_TO_BEBIT16 macro 183285242Sachim* 184285242Sachim* use to convert host bit16 to big endian bit16 185285242Sachim*/ 186285242Sachim#ifndef BIT16_TO_BEBIT16 187285242Sachim#define BIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 188285242Sachim#endif 189285242Sachim 190285242Sachim/*! \def LEBIT32_TO_BIT32(_x) 191285242Sachim* \brief LEBIT32_TO_BIT32 macro 192285242Sachim* 193285242Sachim* use to convert little endian bit32 to host bit32 194285242Sachim*/ 195285242Sachim#ifndef LEBIT32_TO_BIT32 196285242Sachim#define LEBIT32_TO_BIT32(_x) (_x) 197285242Sachim#endif 198285242Sachim 199285242Sachim/*! \def BIT32_TO_LEBIT32(_x) 200285242Sachim* \brief BIT32_TO_LEBIT32 macro 201285242Sachim* 202285242Sachim* use to convert host bit32 to little endian bit32 203285242Sachim*/ 204285242Sachim#ifndef BIT32_TO_LEBIT32 205285242Sachim#define BIT32_TO_LEBIT32(_x) (_x) 206285242Sachim#endif 207285242Sachim 208285242Sachim/*! \def BEBIT32_TO_BIT32(_x) 209285242Sachim* \brief BEBIT32_TO_BIT32 macro 210285242Sachim* 211285242Sachim* use to convert big endian bit32 to host bit32 212285242Sachim*/ 213285242Sachim#ifndef BEBIT32_TO_BIT32 214285242Sachim#define BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) 215285242Sachim#endif 216285242Sachim 217285242Sachim/*! \def BIT32_TO_BEBIT32(_x) 218285242Sachim* \brief BIT32_TO_BEBIT32 macro 219285242Sachim* 220285242Sachim* use to convert host bit32 to big endian bit32 221285242Sachim*/ 222285242Sachim#ifndef BIT32_TO_BEBIT32 223285242Sachim#define BIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 224285242Sachim#endif 225285242Sachim 226285242Sachim 227285242Sachim/* 228285242Sachim * bit8 to Byte[x] of bit32 229285242Sachim */ 230285242Sachim#ifndef BIT8_TO_BIT32_B0 231285242Sachim#define BIT8_TO_BIT32_B0(_x) ((bit32)(_x)) 232285242Sachim#endif 233285242Sachim 234285242Sachim#ifndef BIT8_TO_BIT32_B1 235285242Sachim#define BIT8_TO_BIT32_B1(_x) (((bit32)(_x)) << 8) 236285242Sachim#endif 237285242Sachim 238285242Sachim#ifndef BIT8_TO_BIT32_B2 239285242Sachim#define BIT8_TO_BIT32_B2(_x) (((bit32)(_x)) << 16) 240285242Sachim#endif 241285242Sachim 242285242Sachim#ifndef BIT8_TO_BIT32_B3 243285242Sachim#define BIT8_TO_BIT32_B3(_x) (((bit32)(_x)) << 24) 244285242Sachim#endif 245285242Sachim 246285242Sachim/* 247285242Sachim * Byte[x] of bit32 to bit8 248285242Sachim */ 249285242Sachim#ifndef BIT32_B0_TO_BIT8 250285242Sachim#define BIT32_B0_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF)) 251285242Sachim#endif 252285242Sachim 253285242Sachim#ifndef BIT32_B1_TO_BIT8 254285242Sachim#define BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8)) 255285242Sachim#endif 256285242Sachim 257285242Sachim#ifndef BIT32_B2_TO_BIT8 258285242Sachim#define BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16)) 259285242Sachim#endif 260285242Sachim 261285242Sachim#ifndef BIT32_B3_TO_BIT8 262285242Sachim#define BIT32_B3_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24)) 263285242Sachim#endif 264285242Sachim 265285242Sachim#elif defined(SA_CPU_BIG_ENDIAN) 266285242Sachim 267285242Sachim/*! \def LEBIT16_TO_BIT16(_x) 268285242Sachim* \brief LEBIT16_TO_BIT16 macro 269285242Sachim* 270285242Sachim* use to convert little endian bit16 to host bit16 271285242Sachim*/ 272285242Sachim#ifndef LEBIT16_TO_BIT16 273285242Sachim#define LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) 274285242Sachim#endif 275285242Sachim 276285242Sachim/*! \def BIT16_TO_LEBIT16(_x) 277285242Sachim* \brief BIT16_TO_LEBIT16 macro 278285242Sachim* 279285242Sachim* use to convert host bit16 to little endian bit16 280285242Sachim*/ 281285242Sachim#ifndef BIT16_TO_LEBIT16 282285242Sachim#define BIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 283285242Sachim#endif 284285242Sachim 285285242Sachim/*! \def BEBIT16_TO_BIT16(_x) 286285242Sachim* \brief BEBIT16_TO_BIT16 macro 287285242Sachim* 288285242Sachim* use to convert big endian bit16 to host bit16 289285242Sachim*/ 290285242Sachim#ifndef BEBIT16_TO_BIT16 291285242Sachim#define BEBIT16_TO_BIT16(_x) (_x) 292285242Sachim#endif 293285242Sachim 294285242Sachim/*! \def BIT16_TO_BEBIT16(_x) 295285242Sachim* \brief BIT16_TO_BEBIT16 macro 296285242Sachim* 297285242Sachim* use to convert host bit16 to big endian bit16 298285242Sachim*/ 299285242Sachim#ifndef BIT16_TO_BEBIT16 300285242Sachim#define BIT16_TO_BEBIT16(_x) (_x) 301285242Sachim#endif 302285242Sachim 303285242Sachim/*! \def LEBIT32_TO_BIT32(_x) 304285242Sachim* \brief LEBIT32_TO_BIT32 macro 305285242Sachim* 306285242Sachim* use to convert little endian bit32 to host bit32 307285242Sachim*/ 308285242Sachim#ifndef LEBIT32_TO_BIT32 309285242Sachim#define LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) 310285242Sachim#endif 311285242Sachim 312285242Sachim/*! \def BIT32_TO_LEBIT32(_x) 313285242Sachim* \brief BIT32_TO_LEBIT32 macro 314285242Sachim* 315285242Sachim* use to convert host bit32 to little endian bit32 316285242Sachim*/ 317285242Sachim#ifndef BIT32_TO_LEBIT32 318285242Sachim#define BIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 319285242Sachim#endif 320285242Sachim 321285242Sachim/*! \def BEBIT32_TO_BIT32(_x) 322285242Sachim* \brief BEBIT32_TO_BIT32 macro 323285242Sachim* 324285242Sachim* use to convert big endian bit32 to host bit32 325285242Sachim*/ 326285242Sachim#ifndef BEBIT32_TO_BIT32 327285242Sachim#define BEBIT32_TO_BIT32(_x) (_x) 328285242Sachim#endif 329285242Sachim 330285242Sachim/*! \def BIT32_TO_BEBIT32(_x) 331285242Sachim* \brief BIT32_TO_BEBIT32 macro 332285242Sachim* 333285242Sachim* use to convert host bit32 to big endian bit32 334285242Sachim*/ 335285242Sachim#ifndef BIT32_TO_BEBIT32 336285242Sachim#define BIT32_TO_BEBIT32(_x) (_x) 337285242Sachim#endif 338285242Sachim 339285242Sachim 340285242Sachim/* 341285242Sachim * bit8 to Byte[x] of bit32 342285242Sachim */ 343285242Sachim#ifndef BIT8_TO_BIT32_B0 344285242Sachim#define BIT8_TO_BIT32_B0(_x) (((bit32)(_x)) << 24) 345285242Sachim#endif 346285242Sachim 347285242Sachim#ifndef BIT8_TO_BIT32_B1 348285242Sachim#define BIT8_TO_BIT32_B1(_x) (((bit32)(_x)) << 16) 349285242Sachim#endif 350285242Sachim 351285242Sachim#ifndef BIT8_TO_BIT32_B2 352285242Sachim#define BIT8_TO_BIT32_B2(_x) (((bit32)(_x)) << 8) 353285242Sachim#endif 354285242Sachim 355285242Sachim#ifndef BIT8_TO_BIT32_B3 356285242Sachim#define BIT8_TO_BIT32_B3(_x) ((bit32)(_x)) 357285242Sachim#endif 358285242Sachim 359285242Sachim/* 360285242Sachim * Byte[x] of bit32 to bit8 361285242Sachim */ 362285242Sachim#ifndef BIT32_B0_TO_BIT8 363285242Sachim#define BIT32_B0_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24)) 364285242Sachim#endif 365285242Sachim 366285242Sachim#ifndef BIT32_B1_TO_BIT8 367285242Sachim#define BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16)) 368285242Sachim#endif 369285242Sachim 370285242Sachim#ifndef BIT32_B2_TO_BIT8 371285242Sachim#define BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8)) 372285242Sachim#endif 373285242Sachim 374285242Sachim#ifndef BIT32_B3_TO_BIT8 375285242Sachim#define BIT32_B3_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF)) 376285242Sachim#endif 377285242Sachim 378285242Sachim#else 379285242Sachim 380285242Sachim#error No definition of SA_CPU_BIG_ENDIAN or SA_CPU_LITTLE_ENDIAN 381285242Sachim 382285242Sachim#endif 383285242Sachim 384285242Sachim 385285242Sachim#if defined(SA_DMA_LITTLE_ENDIAN) 386285242Sachim 387285242Sachim/* 388285242Sachim * ** bit32 to bit32 389285242Sachim * */ 390285242Sachim#ifndef DMA_BIT32_TO_BIT32 391285242Sachim#define DMA_BIT32_TO_BIT32(_x) (_x) 392285242Sachim#endif 393285242Sachim 394285242Sachim#ifndef DMA_LEBIT32_TO_BIT32 395285242Sachim#define DMA_LEBIT32_TO_BIT32(_x) (_x) 396285242Sachim#endif 397285242Sachim 398285242Sachim#ifndef DMA_BEBIT32_TO_BIT32 399285242Sachim#define DMA_BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) 400285242Sachim#endif 401285242Sachim 402285242Sachim#ifndef BIT32_TO_DMA_BIT32 403285242Sachim#define BIT32_TO_DMA_BIT32(_x) (_x) 404285242Sachim#endif 405285242Sachim 406285242Sachim#ifndef BIT32_TO_DMA_LEBIT32 407285242Sachim#define BIT32_TO_DMA_LEBIT32(_x) (_x) 408285242Sachim#endif 409285242Sachim 410285242Sachim#ifndef BIT32_TO_DMA_BEBIT32 411285242Sachim#define BIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 412285242Sachim#endif 413285242Sachim 414285242Sachim 415285242Sachim/* 416285242Sachim * ** bit16 to bit16 417285242Sachim * */ 418285242Sachim#ifndef DMA_BIT16_TO_BIT16 419285242Sachim#define DMA_BIT16_TO_BIT16(_x) (_x) 420285242Sachim#endif 421285242Sachim 422285242Sachim#ifndef DMA_LEBIT16_TO_BIT16 423285242Sachim#define DMA_LEBIT16_TO_BIT16(_x) (_x) 424285242Sachim#endif 425285242Sachim 426285242Sachim#ifndef DMA_BEBIT16_TO_BIT16 427285242Sachim#define DMA_BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) 428285242Sachim#endif 429285242Sachim 430285242Sachim#ifndef BIT16_TO_DMA_BIT16 431285242Sachim#define BIT16_TO_DMA_BIT16(_x) (_x) 432285242Sachim#endif 433285242Sachim 434285242Sachim#ifndef BIT16_TO_DMA_LEBIT16 435285242Sachim#define BIT16_TO_DMA_LEBIT16(_x) (_x) 436285242Sachim#endif 437285242Sachim 438285242Sachim#ifndef BIT16_TO_DMA_BEBIT16 439285242Sachim#define BIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 440285242Sachim#endif 441285242Sachim 442285242Sachim#if defined(SA_CPU_LITTLE_ENDIAN) 443285242Sachim 444285242Sachim#ifndef BEBIT32_TO_DMA_BEBIT32 445285242Sachim#define BEBIT32_TO_DMA_BEBIT32(_x) (_x) 446285242Sachim#endif 447285242Sachim 448285242Sachim#ifndef LEBIT32_TO_DMA_LEBIT32 449285242Sachim#define LEBIT32_TO_DMA_LEBIT32(_x) (_x) 450285242Sachim#endif 451285242Sachim 452285242Sachim#ifndef DMA_LEBIT32_TO_LEBIT32 453285242Sachim#define DMA_LEBIT32_TO_LEBIT32(_x) (_x) 454285242Sachim#endif 455285242Sachim 456285242Sachim#ifndef DMA_BEBIT32_TO_BEBIT32 457285242Sachim#define DMA_BEBIT32_TO_BEBIT32(_x) (_x) 458285242Sachim#endif 459285242Sachim 460285242Sachim/* 461285242Sachim * ** bit16 to bit16 462285242Sachim * */ 463285242Sachim#ifndef BEBIT16_TO_DMA_BEBIT16 464285242Sachim#define BEBIT16_TO_DMA_BEBIT16(_x) (_x) 465285242Sachim#endif 466285242Sachim 467285242Sachim#ifndef LEBIT16_TO_DMA_LEBIT16 468285242Sachim#define LEBIT16_TO_DMA_LEBIT16(_x) (_x) 469285242Sachim#endif 470285242Sachim 471285242Sachim#ifndef DMA_LEBIT16_TO_LEBIT16 472285242Sachim#define DMA_LEBIT16_TO_LEBIT16(_x) (_x) 473285242Sachim#endif 474285242Sachim 475285242Sachim#ifndef DMA_BEBIT16_TO_BEBIT16 476285242Sachim#define DMA_BEBIT16_TO_BEBIT16(_x) (_x) 477285242Sachim#endif 478285242Sachim 479285242Sachim#else /* defined(SA_CPU_BIG_ENDIAN) */ 480285242Sachim 481285242Sachim 482285242Sachim/* 483285242Sachim * ** bit32 to bit32 484285242Sachim * */ 485285242Sachim#ifndef BEBIT32_TO_DMA_BEBIT32 486285242Sachim#define BEBIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 487285242Sachim#endif 488285242Sachim 489285242Sachim#ifndef LEBIT32_TO_DMA_LEBIT32 490285242Sachim#define LEBIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 491285242Sachim#endif 492285242Sachim 493285242Sachim#ifndef DMA_LEBIT32_TO_LEBIT32 494285242Sachim#define DMA_LEBIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 495285242Sachim#endif 496285242Sachim 497285242Sachim#ifndef DMA_BEBIT32_TO_BEBIT32 498285242Sachim#define DMA_BEBIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 499285242Sachim#endif 500285242Sachim 501285242Sachim/* 502285242Sachim * ** bit16 to bit16 503285242Sachim * */ 504285242Sachim#ifndef BEBIT16_TO_DMA_BEBIT16 505285242Sachim#define BEBIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 506285242Sachim#endif 507285242Sachim 508285242Sachim#ifndef LEBIT16_TO_DMA_LEBIT16 509285242Sachim#define LEBIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 510285242Sachim#endif 511285242Sachim 512285242Sachim#ifndef DMA_LEBIT16_TO_LEBIT16 513285242Sachim#define DMA_LEBIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 514285242Sachim#endif 515285242Sachim 516285242Sachim#ifndef DMA_BEBIT16_TO_BEBIT16 517285242Sachim#define DMA_BEBIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 518285242Sachim#endif 519285242Sachim 520285242Sachim#endif 521285242Sachim 522285242Sachim/* 523285242Sachim * bit8 to Byte[x] of bit32 524285242Sachim */ 525285242Sachim#ifndef BIT8_TO_DMA_BIT32_B0 526285242Sachim#define BIT8_TO_DMA_BIT32_B0(_x) ((bit32)(_x)) 527285242Sachim#endif 528285242Sachim 529285242Sachim#ifndef BIT8_TO_DMA_BIT32_B1 530285242Sachim#define BIT8_TO_DMA_BIT32_B1(_x) (((bit32)(_x)) << 8) 531285242Sachim#endif 532285242Sachim 533285242Sachim#ifndef BIT8_TO_DMA_BIT32_B2 534285242Sachim#define BIT8_TO_DMA_BIT32_B2(_x) (((bit32)(_x)) << 16) 535285242Sachim#endif 536285242Sachim 537285242Sachim#ifndef BIT8_TO_DMA_BIT32_B3 538285242Sachim#define BIT8_TO_DMA_BIT32_B3(_x) (((bit32)(_x)) << 24) 539285242Sachim#endif 540285242Sachim 541285242Sachim/* 542285242Sachim * Byte[x] of bit32 to bit8 543285242Sachim */ 544285242Sachim#ifndef DMA_BIT32_B0_TO_BIT8 545285242Sachim#define DMA_BIT32_B0_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF)) 546285242Sachim#endif 547285242Sachim 548285242Sachim#ifndef DMA_BIT32_B1_TO_BIT8 549285242Sachim#define DMA_BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8)) 550285242Sachim#endif 551285242Sachim 552285242Sachim#ifndef DMA_BIT32_B2_TO_BIT8 553285242Sachim#define DMA_BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16)) 554285242Sachim#endif 555285242Sachim 556285242Sachim#ifndef DMA_BIT32_B3_TO_BIT8 557285242Sachim#define DMA_BIT32_B3_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24)) 558285242Sachim#endif 559285242Sachim 560285242Sachim/*| | 561285242Sachim | end of DMA access macros for LITTLE ENDIAN | 562285242Sachim --------------------------------------------------------------------- 563285242Sachim */ 564285242Sachim 565285242Sachim#elif defined(SA_DMA_BIG_ENDIAN) /* DMA big endian */ 566285242Sachim 567285242Sachim/*-------------------------------------------------------------------- 568285242Sachim | DMA buffer access macros for BIG ENDIAN | 569285242Sachim | | 570285242Sachim */ 571285242Sachim 572285242Sachim/* bit32 to bit32 */ 573285242Sachim#ifndef DMA_BEBIT32_TO_BIT32 574285242Sachim#define DMA_BEBIT32_TO_BIT32(_x) (_x) 575285242Sachim#endif 576285242Sachim 577285242Sachim#ifndef DMA_LEBIT32_TO_BIT32 578285242Sachim#define DMA_LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) 579285242Sachim#endif 580285242Sachim 581285242Sachim#ifndef BIT32_TO_DMA_BIT32 582285242Sachim#define BIT32_TO_DMA_BIT32(_x) (_x) 583285242Sachim#endif 584285242Sachim 585285242Sachim#ifndef BIT32_TO_DMA_LEBIT32 586285242Sachim#define BIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 587285242Sachim#endif 588285242Sachim 589285242Sachim#ifndef BIT32_TO_DMA_BEBIT32 590285242Sachim#define BIT32_TO_DMA_BEBIT32(_x) (_x) 591285242Sachim#endif 592285242Sachim 593285242Sachim/* bit16 to bit16 */ 594285242Sachim#ifndef DMA_BEBIT16_TO_BIT16 595285242Sachim#define DMA_BEBIT16_TO_BIT16(_x) (_x) 596285242Sachim#endif 597285242Sachim 598285242Sachim#ifndef DMA_LEBIT16_TO_BIT16 599285242Sachim#define DMA_LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) 600285242Sachim#endif 601285242Sachim 602285242Sachim#ifndef BIT16_TO_DMA_BIT16 603285242Sachim#define BIT16_TO_DMA_BIT16(_x) (_x) 604285242Sachim#endif 605285242Sachim 606285242Sachim#ifndef BIT16_TO_DMA_LEBIT16 607285242Sachim#define BIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 608285242Sachim#endif 609285242Sachim 610285242Sachim#ifndef BIT16_TO_DMA_BEBIT16 611285242Sachim#define BIT16_TO_DMA_BEBIT16(_x) (_x) 612285242Sachim#endif 613285242Sachim 614285242Sachim 615285242Sachim#if defined(SA_CPU_LITTLE_ENDIAN) /* CPU little endain */ 616285242Sachim 617285242Sachim/* bit32 to bit32 */ 618285242Sachim#ifndef BEBIT32_TO_DMA_BEBIT32 619285242Sachim#define BEBIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 620285242Sachim#endif 621285242Sachim 622285242Sachim#ifndef LEBIT32_TO_DMA_LEBIT32 623285242Sachim#define LEBIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 624285242Sachim#endif 625285242Sachim 626285242Sachim#ifndef DMA_LEBIT32_TO_LEBIT32 627285242Sachim#define DMA_LEBIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 628285242Sachim#endif 629285242Sachim 630285242Sachim#ifndef DMA_BEBIT32_TO_BEBIT32 631285242Sachim#define DMA_BEBIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 632285242Sachim#endif 633285242Sachim 634285242Sachim/* bit16 to bit16 */ 635285242Sachim#ifndef BEBIT16_TO_DMA_BEBIT16 636285242Sachim#define BEBIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 637285242Sachim#endif 638285242Sachim 639285242Sachim#ifndef LEBIT16_TO_DMA_LEBIT16 640285242Sachim#define LEBIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 641285242Sachim#endif 642285242Sachim 643285242Sachim#ifndef DMA_LEBIT16_TO_LEBIT16 644285242Sachim#define DMA_LEBIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 645285242Sachim#endif 646285242Sachim 647285242Sachim#ifndef DMA_BEBIT16_TO_BEBIT16 648285242Sachim#define DMA_BEBIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 649285242Sachim#endif 650285242Sachim 651285242Sachim 652285242Sachim#else /* defined(SA_CPU_BIG_ENDIAN) */ 653285242Sachim 654285242Sachim/* bit32 to bit32 */ 655285242Sachim#ifndef BEBIT32_TO_DMA_BEBIT32 656285242Sachim#define BEBIT32_TO_DMA_BEBIT32(_x) (_x) 657285242Sachim#endif 658285242Sachim 659285242Sachim#ifndef LEBIT32_TO_DMA_LEBIT32 660285242Sachim#define LEBIT32_TO_DMA_LEBIT32(_x) (_x) 661285242Sachim#endif 662285242Sachim 663285242Sachim#ifndef DMA_LEBIT32_TO_LEBIT32 664285242Sachim#define DMA_LEBIT32_TO_LEBIT32(_x) (_x) 665285242Sachim#endif 666285242Sachim 667285242Sachim#ifndef DMA_BEBIT32_TO_BEBIT32 668285242Sachim#define DMA_BEBIT32_TO_BEBIT32(_x) (_x) 669285242Sachim#endif 670285242Sachim 671285242Sachim/* bit16 to bit16 */ 672285242Sachim#ifndef BEBIT16_TO_DMA_BEBIT16 673285242Sachim#define BEBIT16_TO_DMA_BEBIT16(_x) (_x) 674285242Sachim#endif 675285242Sachim 676285242Sachim#ifndef LEBIT16_TO_DMA_LEBIT16 677285242Sachim#define LEBIT16_TO_DMA_LEBIT16(_x) (_x) 678285242Sachim#endif 679285242Sachim 680285242Sachim#ifndef DMA_LEBIT16_TO_LEBIT16 681285242Sachim#define DMA_LEBIT16_TO_LEBIT16(_x) (_x) 682285242Sachim#endif 683285242Sachim 684285242Sachim#ifndef DMA_BEBIT16_TO_BEBIT16 685285242Sachim#define DMA_BEBIT16_TO_BEBIT16(_x) (_x) 686285242Sachim#endif 687285242Sachim 688285242Sachim#endif 689285242Sachim 690285242Sachim/* 691285242Sachim * bit8 to Byte[x] of bit32 692285242Sachim */ 693285242Sachim#ifndef BIT8_TO_DMA_BIT32_B0 694285242Sachim#define BIT8_TO_DMA_BIT32_B0(_x) (((bit32)(_x)) << 24) 695285242Sachim#endif 696285242Sachim 697285242Sachim#ifndef BIT8_TO_DMA_BIT32_B1 698285242Sachim#define BIT8_TO_DMA_BIT32_B1(_x) (((bit32)(_x)) << 16) 699285242Sachim#endif 700285242Sachim 701285242Sachim#ifndef BIT8_TO_DMA_BIT32_B2 702285242Sachim#define BIT8_TO_DMA_BIT32_B2(_x) (((bit32)(_x)) << 8) 703285242Sachim#endif 704285242Sachim 705285242Sachim#ifndef BIT8_TO_DMA_BIT32_B3 706285242Sachim#define BIT8_TO_DMA_BIT32_B3(_x) ((bit32)(_x)) 707285242Sachim#endif 708285242Sachim 709285242Sachim/* 710285242Sachim * ** Byte[x] of bit32 to bit8 711285242Sachim * */ 712285242Sachim#ifndef DMA_BIT32_B0_TO_BIT8 713285242Sachim#define DMA_BIT32_B0_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24)) 714285242Sachim#endif 715285242Sachim 716285242Sachim#ifndef DMA_BIT32_B1_TO_BIT8 717285242Sachim#define DMA_BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16)) 718285242Sachim#endif 719285242Sachim 720285242Sachim#ifndef DMA_BIT32_B2_TO_BIT8 721285242Sachim#define DMA_BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8)) 722285242Sachim#endif 723285242Sachim 724285242Sachim#ifndef DMA_BIT32_B3_TO_BIT8 725285242Sachim#define DMA_BIT32_B3_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF)) 726285242Sachim#endif 727285242Sachim 728285242Sachim/*| | 729285242Sachim | end of DMA access macros for BIG ENDIAN | 730285242Sachim --------------------------------------------------------------------- 731285242Sachim*/ 732285242Sachim#else 733285242Sachim 734285242Sachim#error No definition of SA_DMA_BIG_ENDIAN or SA_DMA_LITTLE_ENDIAN 735285242Sachim 736285242Sachim#endif /* DMA endian */ 737285242Sachim/* 738285242Sachim * End of DMA buffer access macros * 739285242Sachim * * 740285242Sachim ********************************************************************** 741285242Sachim */ 742285242Sachim 743285242Sachim/************************************************************************************ 744285242Sachim * * 745285242Sachim * Constants defined for LL Layer starts * 746285242Sachim * * 747285242Sachim ************************************************************************************/ 748285242Sachim 749285242Sachim/********************************************************* 750285242Sachim * sTSDK LL revision and Interface revision, FW version 751285242Sachim *********************************************************/ 752285242Sachim 753285242Sachim#define FW_THIS_VERSION_SPC12G 0x03060005 754285242Sachim 755285242Sachim#define FW_THIS_VERSION_SPC6G 0x02092400 756285242Sachim#define FW_THIS_VERSION_SPC 0x01110000 757285242Sachim 758285242Sachim 759285242Sachim#define STSDK_LL_INTERFACE_VERSION 0x20A 760285242Sachim#define STSDK_LL_OLD_INTERFACE_VERSION 0x1 /* SPC and SPCv before 02030401 */ 761285242Sachim#define STSDK_LL_VERSION FW_THIS_VERSION_SPC6G /**< current sTSDK version */ 762285242Sachim#define MAX_FW_VERSION_SUPPORTED FW_THIS_VERSION_SPC6G /**< FW */ 763285242Sachim#define MATCHING_V_FW_VERSION FW_THIS_VERSION_SPC6G /**< current V matching FW version */ 764285242Sachim#define MIN_FW_SPCVE_VERSION_SUPPORTED 0x02000000 /**< 2.00 FW */ 765285242Sachim 766285242Sachim#define STSDK_LL_12G_INTERFACE_VERSION 0x302 767285242Sachim#define STSDK_LL_12G_VERSION FW_THIS_VERSION_SPC12G /**< current sTSDK version */ 768285242Sachim#define MAX_FW_12G_VERSION_SUPPORTED FW_THIS_VERSION_SPC12G /**< FW */ 769285242Sachim#define MATCHING_12G_V_FW_VERSION FW_THIS_VERSION_SPC12G /**< current V matching FW version */ 770285242Sachim#define MIN_FW_12G_SPCVE_VERSION_SUPPORTED 0x03000000 /**< 3.00 FW */ 771285242Sachim 772285242Sachim#define STSDK_LL_SPC_VERSION 0x01100000 /**< current SPC FW version supported */ 773285242Sachim#define MATCHING_SPC_FW_VERSION FW_THIS_VERSION_SPC /**< current SPC matching FW version */ 774285242Sachim#define MIN_FW_SPC_VERSION_SUPPORTED 0x01062502 /**< 1.06d FW */ 775285242Sachim 776285242Sachim#define STSDK_LL_INTERFACE_VERSION_IGNORE_MASK 0xF00 777285242Sachim/************************************************* 778285242Sachim * constants for API return values 779285242Sachim *************************************************/ 780285242Sachim#define AGSA_RC_SUCCESS 0x00 /**< Successful function return value */ 781285242Sachim#define AGSA_RC_FAILURE 0x01 /**< Failed function return value */ 782285242Sachim#define AGSA_RC_BUSY 0x02 /**< Busy function return value */ 783285242Sachim/* current only return from saGetControllerInfo() and saGetControllerStatus() */ 784285242Sachim#define AGSA_RC_HDA_NO_FW_RUNNING 0x03 /**< HDA mode and no FW running */ 785285242Sachim#define AGSA_RC_FW_NOT_IN_READY_STATE 0x04 /**< FW not in ready state */ 786285242Sachim/* current only return from saInitialize() for version checking */ 787285242Sachim#define AGSA_RC_VERSION_INCOMPATIBLE 0x05 /**< Version mismatch */ 788285242Sachim#define AGSA_RC_VERSION_UNTESTED 0x06 /**< Version not tested */ 789285242Sachim#define AGSA_RC_NOT_SUPPORTED 0x07 /**< Operation not supported on the current hardware */ 790285242Sachim#define AGSA_RC_COMPLETE 0x08 791285242Sachim 792285242Sachim/************************************************* 793285242Sachim * constants for type field in agsaMem_t 794285242Sachim *************************************************/ 795285242Sachim#define AGSA_CACHED_MEM 0x00 /**< CACHED memory type */ 796285242Sachim#define AGSA_DMA_MEM 0x01 /**< DMA memory type */ 797285242Sachim#define AGSA_CACHED_DMA_MEM 0x02 /**< CACHED DMA memory type */ 798285242Sachim 799285242Sachim#ifdef SA_ENABLE_TRACE_FUNCTIONS 800285242Sachim#ifdef FAST_IO_TEST 801285242Sachim#define AGSA_NUM_MEM_CHUNKS (12 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q) /**< max # of memory chunks supported */ 802285242Sachim#else 803285242Sachim#define AGSA_NUM_MEM_CHUNKS (11 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q) /**< max # of memory chunks supported */ 804285242Sachim#endif 805285242Sachim#else 806285242Sachim#ifdef FAST_IO_TEST 807285242Sachim#define AGSA_NUM_MEM_CHUNKS (11 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q) /**< max # of memory chunks supported */ 808285242Sachim#else 809285242Sachim#define AGSA_NUM_MEM_CHUNKS (10 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q) /**< max # of memory chunks supported */ 810285242Sachim#endif 811285242Sachim#endif /* END SA_ENABLE_TRACE_FUNCTIONS */ 812285242Sachim 813285242Sachim 814285242Sachim/********************************** 815285242Sachim * default constant for phy count 816285242Sachim **********************************/ 817285242Sachim#define AGSA_MAX_VALID_PHYS 16 /* was 8 for SPC */ /**< max # of phys supported by the hardware */ 818285242Sachim 819285242Sachim/************************************ 820285242Sachim * default constant for Esgl entries 821285242Sachim ************************************/ 822285242Sachim#define MAX_ESGL_ENTRIES 10 /**< max # of extended SG list entry */ 823285242Sachim 824285242Sachim/******************************************* 825285242Sachim * constant for max inbound/outbound queues 826285242Sachim *******************************************/ 827285242Sachim#define AGSA_MAX_INBOUND_Q 64 /**< max # of inbound queue */ 828285242Sachim#define AGSA_MAX_OUTBOUND_Q 64 /**< max # of outbound queue */ 829285242Sachim#define AGSA_MAX_BEST_INBOUND_Q 16 /* Max inbound Q number with good IO performance */ 830285242Sachim 831285242Sachim/**************************** 832285242Sachim * Phy Control constants 833285242Sachim ****************************/ 834285242Sachim#define AGSA_PHY_LINK_RESET 0x01 835285242Sachim#define AGSA_PHY_HARD_RESET 0x02 836285242Sachim#define AGSA_PHY_GET_ERROR_COUNTS 0x03 /* SPC only used in original saLocalPhyControl */ 837285242Sachim#define AGSA_PHY_CLEAR_ERROR_COUNTS 0x04 /* SPC only */ 838285242Sachim#define AGSA_PHY_GET_BW_COUNTS 0x05 /* SPC only */ 839285242Sachim#define AGSA_PHY_NOTIFY_ENABLE_SPINUP 0x10 840285242Sachim#define AGSA_PHY_BROADCAST_ASYNCH_EVENT 0x12 841285242Sachim#define AGSA_PHY_COMINIT_OOB 0x20 842285242Sachim 843285242Sachim#define AGSA_SAS_PHY_ERR_COUNTERS_PAGE 0x01 /* retrieve the SAS PHY error counters */ 844285242Sachim#define AGSA_SAS_PHY_ERR_COUNTERS_CLR_PAGE 0x02 /* retrieve the SAS PHY error counters After capturing the errors, the hardware error counters are cleared and restarted. */ 845285242Sachim#define AGSA_SAS_PHY_BW_COUNTERS_PAGE 0x03 /* retrieve the SAS PHY transmit and receive bandwidth counters. */ 846285242Sachim#define AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE 0x04 /* retrieve the SAS PHY analog settings */ 847285242Sachim#define AGSA_SAS_PHY_GENERAL_STATUS_PAGE 0x05 /* retrieve the SAS PHY general status for the PHY specified in the phyID parameter */ 848285242Sachim#define AGSA_PHY_SNW3_PAGE 0x06 849285242Sachim#define AGSA_PHY_RATE_CONTROL_PAGE 0x07 /* Used to set several rate control parameters. */ 850285242Sachim#define AGSA_SAS_PHY_MISC_PAGE 0x08 851285242Sachim#define AGSA_SAS_PHY_OPEN_REJECT_RETRY_BACKOFF_THRESHOLD_PAGE 0x08 /* Used to set retry and backoff threshold parameters. */ 852285242Sachim 853285242Sachim/***************** 854285242Sachim * HW Reset 855285242Sachim *****************/ 856285242Sachim#define AGSA_CHIP_RESET 0x00 /**< flag to reset hard reset */ 857285242Sachim#define AGSA_SOFT_RESET 0x01 /**< flag to reset the controller chip */ 858285242Sachim 859285242Sachim/*************************************** 860285242Sachim * Discovery Types 861285242Sachim ***************************************/ 862285242Sachim#define AG_SA_DISCOVERY_TYPE_SAS 0x00 /**< flag to discover SAS devices */ 863285242Sachim#define AG_SA_DISCOVERY_TYPE_SATA 0x01 /**< flag to discover SATA devices */ 864285242Sachim 865285242Sachim/*************************************** 866285242Sachim * Discovery Options 867285242Sachim ***************************************/ 868285242Sachim#define AG_SA_DISCOVERY_OPTION_FULL_START 0x00 /**< flag to start full discovery */ 869285242Sachim#define AG_SA_DISCOVERY_OPTION_INCREMENTAL_START 0x01 /**< flag to start incremental discovery */ 870285242Sachim#define AG_SA_DISCOVERY_OPTION_ABORT 0x02 /**< flag to abort a discovery */ 871285242Sachim 872285242Sachim/**************************************************************** 873285242Sachim * SSP/SMP/SATA Request type 874285242Sachim ****************************************************************/ 875285242Sachim/* bit31-28 - request type 876285242Sachim bit27-16 - reserved 877285242Sachim bit15-10 - SATA ATAP 878285242Sachim bit9-8 - direction 879285242Sachim bit7 - AUTO 880285242Sachim bit6 - reserved 881285242Sachim bit5 - EXT 882285242Sachim bit4 - MSG 883285242Sachim bit3-0 - Initiator, target or task mode (1 to 8) 884285242Sachim */ 885285242Sachim#define AGSA_REQTYPE_MASK 0xF0000000 /**< request type mask */ 886285242Sachim#define AGSA_REQ_TYPE_UNKNOWN 0x00000000 /**< unknown request type */ 887285242Sachim#define AGSA_SSP_REQTYPE 0x80000000 888285242Sachim#define AGSA_SMP_REQTYPE 0x40000000 889285242Sachim#define AGSA_SATA_REQTYPE 0x20000000 890285242Sachim 891285242Sachim#define AGSA_DIR_MASK 0x00000300 892285242Sachim#define AGSA_AUTO_MASK 0x00000080 893285242Sachim#define AGSA_SATA_ATAP_MASK 0x0000FC00 894285242Sachim 895285242Sachim#define AGSA_DIR_NONE 0x00000000 896285242Sachim#define AGSA_DIR_CONTROLLER_TO_HOST 0x00000100 /**< used to be called AGSA_DIR_READ */ 897285242Sachim#define AGSA_DIR_HOST_TO_CONTROLLER 0x00000200 /**< used to be called AGSA_DIR_WRITE */ 898285242Sachim 899285242Sachim/* bit definition - AUTO mode */ 900285242Sachim#define AGSA_AUTO_GOOD_RESPONSE 0x00000080 901285242Sachim 902285242Sachim/* request type - not bit difination */ 903285242Sachim#define AGSA_SSP_INIT 0x00000001 904285242Sachim#define AGSA_SSP_TGT_MODE 0x00000003 905285242Sachim#define AGSA_SSP_TASK_MGNT 0x00000005 906285242Sachim#define AGSA_SSP_TGT_RSP 0x00000006 907285242Sachim#define AGSA_SMP_INIT 0x00000007 908285242Sachim#define AGSA_SMP_TGT 0x00000008 909285242Sachim 910285242Sachim/* request type for SSP Initiator and extend */ 911285242Sachim#define AGSA_SSP_INIT_EXT (AGSA_SSP_INIT | AGSA_SSP_EXT_BIT) 912285242Sachim 913285242Sachim/* request type for SSP Initiator and indirect */ 914285242Sachim#define AGSA_SSP_INIT_INDIRECT (AGSA_SSP_INIT | AGSA_SSP_INDIRECT_BIT) 915285242Sachim 916285242Sachim/* bit definition */ 917285242Sachim#define AGSA_MSG 0x00000010 918285242Sachim#define AGSA_SSP_EXT_BIT 0x00000020 919285242Sachim#define AGSA_SSP_INDIRECT_BIT 0x00000040 920285242Sachim#define AGSA_MSG_BIT AGSA_MSG >> 2 921285242Sachim 922285242Sachim/* agsaSSPIniEncryptIOStartCmd_t dirMTlr bits*/ 923285242Sachim#define AGSA_INDIRECT_CDB_BIT 0x00000008 924285242Sachim#define AGSA_SKIP_MASK_BIT 0x00000010 925285242Sachim#define AGSA_ENCRYPT_BIT 0x00000020 926285242Sachim#define AGSA_DIF_BIT 0x00000040 927285242Sachim#define AGSA_DIF_LA_BIT 0x00000080 928285242Sachim#define AGSA_DIRECTION_BITS 0x00000300 929285242Sachim#define AGSA_SKIP_MASK_OFFSET_BITS 0x0F000000 930285242Sachim#define AGSA_SSP_INFO_LENGTH_BITS 0xF0000000 931285242Sachim 932285242Sachim/* agsaSSPTgtIOStartCmd_t INITagAgrDir bits */ 933285242Sachim#define AGSA_SSP_TGT_BITS_INI_TAG 0xFFFF0000 /* 16 31 */ 934285242Sachim#define AGSA_SSP_TGT_BITS_ODS 0x00008000 /* 15 */ 935285242Sachim#define AGSA_SSP_TGT_BITS_DEE_DIF 0x00004000 /* 14 */ 936285242Sachim#define AGSA_SSP_TGT_BITS_DEE 0x00002000 /* 13 14 */ 937285242Sachim#define AGSA_SSP_TGT_BITS_R 0x00001000 /* 12 */ 938285242Sachim#define AGSA_SSP_TGT_BITS_DAD 0x00000600 /* 11 10 */ 939285242Sachim#define AGSA_SSP_TGT_BITS_DIR 0x00000300 /* 8 9 */ 940285242Sachim#define AGSA_SSP_TGT_BITS_DIR_IN 0x00000100 /* 8 9 */ 941285242Sachim#define AGSA_SSP_TGT_BITS_DIR_OUT 0x00000200 /* 8 9 */ 942285242Sachim#define AGSA_SSP_TGT_BITS_AGR 0x00000080 /* 7 */ 943285242Sachim#define AGSA_SSP_TGT_BITS_RDF 0x00000040 /* 6 */ 944285242Sachim#define AGSA_SSP_TGT_BITS_RTE 0x00000030 /* 4 5 */ 945285242Sachim#define AGSA_SSP_TGT_BITS_AN 0x00000006 /* 2 3 */ 946285242Sachim 947285242Sachim 948285242Sachim/* agsaSSPIniEncryptIOStartCmd_t DIF_flags bit definitions */ 949285242Sachim#define AGSA_DIF_UPDATE_BITS 0xFC000000 950285242Sachim#define AGSA_DIF_VERIFY_BITS 0x03F00000 951285242Sachim#define AGSA_DIF_BLOCK_SIZE_BITS 0x000F0000 952285242Sachim#define AGSA_DIF_ENABLE_BLOCK_COUNT_BIT 0x00000040 953285242Sachim#define AGSA_DIF_CRC_SEED_BIT 0x00000020 954285242Sachim#define AGSA_DIF_CRC_INVERT_BIT 0x00000010 955285242Sachim#define AGSA_DIF_CRC_VERIFY_BIT 0x00000008 956285242Sachim#define AGSA_DIF_OP_BITS 0x00000007 957285242Sachim 958285242Sachim#define AGSA_DIF_OP_INSERT 0x00000000 959285242Sachim#define AGSA_DIF_OP_VERIFY_AND_FORWARD 0x00000001 960285242Sachim#define AGSA_DIF_OP_VERIFY_AND_DELETE 0x00000002 961285242Sachim#define AGSA_DIF_OP_VERIFY_AND_REPLACE 0x00000003 962285242Sachim#define AGSA_DIF_OP_RESERVED2 0x00000004 963285242Sachim#define AGSA_DIF_OP_VERIFY_UDT_REPLACE_CRC 0x00000005 964285242Sachim#define AGSA_DIF_OP_RESERVED3 0x00000006 965285242Sachim#define AGSA_DIF_OP_REPLACE_UDT_REPLACE_CRC 0x00000007 966285242Sachim 967285242Sachim 968285242Sachim/* agsaSSPIniEncryptIOStartCmd_t EncryptFlagsLo bit definitions */ 969285242Sachim#define AGSA_ENCRYPT_DEK_BITS 0xFFFFFF000 970285242Sachim#define AGSA_ENCRYPT_SKIP_DIF_BIT 0x000000010 971285242Sachim#define AGSA_ENCRYPT_KEY_TABLE_BITS 0x00000000C 972285242Sachim#define AGSA_ENCRYPT_KEY_TAG_BIT 0x000000002 973285242Sachim 974285242Sachim/* Cipher mode to be used for this I/O. */ 975285242Sachim#define AGSA_ENCRYPT_ECB_Mode 0 976285242Sachim#define AGSA_ENCRYPT_XTS_Mode 0x6 977285242Sachim 978285242Sachim/* agsaSSPIniEncryptIOStartCmd_t EncryptFlagsHi bit definitions */ 979285242Sachim#define AGSA_ENCRYPT_KEK_SELECT_BITS 0x0000000E0 980285242Sachim#define AGSA_ENCRYPT_SECTOR_SIZE_BITS 0x00000001F 981285242Sachim 982285242Sachim/* defined in the sTSDK spec. */ 983285242Sachim#define AGSA_SSP_INIT_NONDATA (AGSA_SSP_REQTYPE | AGSA_DIR_NONE | AGSA_SSP_INIT) /**< SSP initiator non data request type */ 984285242Sachim#define AGSA_SSP_INIT_READ (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT) /**< SSP initiator read request type */ 985285242Sachim#define AGSA_SSP_INIT_WRITE (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT) /**< SSP initiator write request type */ 986285242Sachim#define AGSA_SSP_TGT_READ_DATA (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE) /**< SSP target read data request type */ 987285242Sachim#define AGSA_SSP_TGT_READ (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE) /**< SSP target read data request type */ 988285242Sachim#define AGSA_SSP_TGT_READ_GOOD_RESP (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE | AGSA_AUTO_GOOD_RESPONSE) /**< SSP target read data with automatic good response request type */ 989285242Sachim#define AGSA_SSP_TGT_WRITE_DATA (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE) /**< SSP target write data request type */ 990285242Sachim#define AGSA_SSP_TGT_WRITE (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE) /**< SSP target write data request type */ 991285242Sachim#define AGSA_SSP_TGT_WRITE_GOOD_RESP (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE | AGSA_AUTO_GOOD_RESPONSE) /**< SSP target write data request type with automatic good response request type*/ 992285242Sachim#define AGSA_SSP_TASK_MGNT_REQ (AGSA_SSP_REQTYPE | AGSA_SSP_TASK_MGNT) /**< SSP task management request type */ 993285242Sachim#define AGSA_SSP_TGT_CMD_OR_TASK_RSP (AGSA_SSP_REQTYPE | AGSA_SSP_TGT_RSP) /**< SSP command or task management response request type */ 994285242Sachim#define AGSA_SMP_INIT_REQ (AGSA_SMP_REQTYPE | AGSA_SMP_INIT) /**< SMP initiator request type */ 995285242Sachim#define AGSA_SMP_TGT_RESPONSE (AGSA_SMP_REQTYPE | AGSA_SMP_TGT) /**< SMP target response request type */ 996285242Sachim#define AGSA_SSP_INIT_READ_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT | AGSA_MSG) 997285242Sachim#define AGSA_SSP_INIT_WRITE_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT | AGSA_MSG) 998285242Sachim#define AGSA_SSP_TASK_MGNT_REQ_M (AGSA_SSP_REQTYPE | AGSA_SSP_TASK_MGNT | AGSA_MSG) 999285242Sachim#define AGSA_SSP_INIT_READ_EXT (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_EXT) /**< SSP initiator read request Ext type */ 1000285242Sachim#define AGSA_SSP_INIT_WRITE_EXT (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_EXT) /**< SSP initiator write request Ext type */ 1001285242Sachim 1002285242Sachim#define AGSA_SSP_INIT_READ_INDIRECT (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_INDIRECT) /**< SSP initiator read request indirect type */ 1003285242Sachim#define AGSA_SSP_INIT_WRITE_INDIRECT (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_INDIRECT) /**< SSP initiator write request indirect type */ 1004285242Sachim 1005285242Sachim#define AGSA_SSP_INIT_READ_INDIRECT_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_INDIRECT | AGSA_MSG) /**< SSP initiator read request indirect type */ 1006285242Sachim#define AGSA_SSP_INIT_WRITE_INDIRECT_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_INDIRECT | AGSA_MSG) /**< SSP initiator write request indirect type */ 1007285242Sachim#define AGSA_SSP_INIT_READ_EXT_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_EXT | AGSA_MSG) 1008285242Sachim#define AGSA_SSP_INIT_WRITE_EXT_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_EXT | AGSA_MSG) 1009285242Sachim 1010285242Sachim#define AGSA_SMP_IOCTL_REQUEST 0xFFFFFFFF 1011285242Sachim 1012285242Sachim#define AGSA_SATA_ATAP_SRST_ASSERT 0x00000400 1013285242Sachim#define AGSA_SATA_ATAP_SRST_DEASSERT 0x00000800 1014285242Sachim#define AGSA_SATA_ATAP_EXECDEVDIAG 0x00000C00 1015285242Sachim#define AGSA_SATA_ATAP_NON_DATA 0x00001000 1016285242Sachim#define AGSA_SATA_ATAP_PIO 0x00001400 1017285242Sachim#define AGSA_SATA_ATAP_DMA 0x00001800 1018285242Sachim#define AGSA_SATA_ATAP_NCQ 0x00001C00 1019285242Sachim#define AGSA_SATA_ATAP_PKT_DEVRESET 0x00002000 1020285242Sachim#define AGSA_SATA_ATAP_PKT 0x00002400 1021285242Sachim 1022285242Sachim#define AGSA_SATA_PROTOCOL_NON_DATA (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_NON_DATA) 1023285242Sachim#define AGSA_SATA_PROTOCOL_PIO_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PIO) /**< SATA PIO read request type */ 1024285242Sachim#define AGSA_SATA_PROTOCOL_DMA_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_DMA) /**< SATA DMA read request type */ 1025285242Sachim#define AGSA_SATA_PROTOCOL_FPDMA_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_NCQ) /**< SATA FDMA read request type */ 1026285242Sachim#define AGSA_SATA_PROTOCOL_PIO_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PIO) /**< SATA PIO read request type */ 1027285242Sachim#define AGSA_SATA_PROTOCOL_DMA_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_DMA) /**< SATA DMA read request type */ 1028285242Sachim#define AGSA_SATA_PROTOCOL_FPDMA_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_NCQ) /**< SATA FDMA read request type */ 1029285242Sachim#define AGSA_SATA_PROTOCOL_DEV_RESET (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT_DEVRESET) /**< SATA device reset request type */ 1030285242Sachim#define AGSA_SATA_PROTOCOL_SRST_ASSERT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_SRST_ASSERT) /**< SATA device reset assert */ 1031285242Sachim#define AGSA_SATA_PROTOCOL_SRST_DEASSERT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_SRST_DEASSERT) /**< SATA device reset deassert */ 1032285242Sachim#define AGSA_SATA_PROTOCOL_D2H_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PKT) 1033285242Sachim#define AGSA_SATA_PROTOCOL_H2D_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PKT) 1034285242Sachim#define AGSA_SATA_PROTOCOL_NON_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT) 1035285242Sachim 1036285242Sachim 1037285242Sachim#define AGSA_SATA_PROTOCOL_NON_DATA_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_NON_DATA | AGSA_MSG) 1038285242Sachim#define AGSA_SATA_PROTOCOL_PIO_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PIO | AGSA_MSG) /**< SATA PIO read request type */ 1039285242Sachim#define AGSA_SATA_PROTOCOL_DMA_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_DMA | AGSA_MSG) /**< SATA DMA read request type */ 1040285242Sachim#define AGSA_SATA_PROTOCOL_FPDMA_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_NCQ | AGSA_MSG) /**< SATA FDMA read request type */ 1041285242Sachim#define AGSA_SATA_PROTOCOL_PIO_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PIO | AGSA_MSG) /**< SATA PIO read request type */ 1042285242Sachim#define AGSA_SATA_PROTOCOL_DMA_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_DMA | AGSA_MSG) /**< SATA DMA read request type */ 1043285242Sachim#define AGSA_SATA_PROTOCOL_FPDMA_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_NCQ | AGSA_MSG) /**< SATA FDMA read request type */ 1044285242Sachim#define AGSA_SATA_PROTOCOL_D2H_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PKT | AGSA_MSG) 1045285242Sachim#define AGSA_SATA_PROTOCOL_H2D_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PKT | AGSA_MSG) 1046285242Sachim#define AGSA_SATA_PROTOCOL_NON_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT | AGSA_MSG) 1047285242Sachim/* TestBase */ 1048285242Sachim#define AGSA_SATA_PROTOCOL_DEV_RESET_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT_DEVRESET | AGSA_MSG) /**< SATA device reset request type */ 1049285242Sachim 1050285242Sachim 1051285242Sachim 1052285242Sachim#define AGSA_INTERRUPT_HANDLE_ALL_CHANNELS 0xFFFFFFFF /**< flag indicates handles interrupts for all channles */ 1053285242Sachim 1054285242Sachim/**************************************************************************** 1055285242Sachim** INBOUND Queue related macros 1056285242Sachim****************************************************************************/ 1057285242Sachim#define AGSA_IBQ_PRIORITY_NORMAL 0x0 1058285242Sachim#define AGSA_IBQ_PRIORITY_HIGH 0x1 1059285242Sachim 1060285242Sachim/**************************************************************************** 1061285242Sachim** Phy properties related macros 1062285242Sachim****************************************************************************/ 1063285242Sachim/* link rate */ 1064285242Sachim#define AGSA_PHY_MAX_LINK_RATE_MASK 0x0000000F /* bits 0-3 */ 1065285242Sachim#define AGSA_PHY_MAX_LINK_RATE_1_5G 0x00000001 /* 0001b */ 1066285242Sachim#define AGSA_PHY_MAX_LINK_RATE_3_0G 0x00000002 /* 0010b */ 1067285242Sachim#define AGSA_PHY_MAX_LINK_RATE_6_0G 0x00000004 /* 0100b */ 1068285242Sachim#define AGSA_PHY_MAX_LINK_RATE_12_0G 0x00000008 /* 1000b */ 1069285242Sachim 1070285242Sachim/* SAS/SATA mode */ 1071285242Sachim#define AGSA_PHY_MODE_MASK 0x00000030 /* bits 4-5 */ 1072285242Sachim#define AGSA_PHY_MODE_SAS 0x00000010 /* 01b */ 1073285242Sachim#define AGSA_PHY_MODE_SATA 0x00000020 /* 10b */ 1074285242Sachim 1075285242Sachim/* control spin-up hold */ 1076285242Sachim#define AGSA_PHY_SPIN_UP_HOLD_MASK 0x00000040 /* bit6 */ 1077285242Sachim#define AGSA_PHY_SPIN_UP_HOLD_ON 0x00000040 /* 1b */ 1078285242Sachim#define AGSA_PHY_SPIN_UP_HOLD_OFF 0x00000000 /* 0b */ 1079285242Sachim 1080285242Sachim/**************************************************************************** 1081285242Sachim** Device Info related macros 1082285242Sachim****************************************************************************/ 1083285242Sachim/* S (SAS/SATA) */ 1084285242Sachim#define AGSA_DEV_INFO_SASSATA_MASK 0x00000010 /* bit 4 */ 1085285242Sachim#define AGSA_DEV_INFO_SASSATA_SAS 0x00000010 /* 1b */ 1086285242Sachim#define AGSA_DEV_INFO_SASSATA_SATA 0x00000000 /* 0b */ 1087285242Sachim 1088285242Sachim/* Rate (link-rate) */ 1089285242Sachim#define AGSA_DEV_INFO_RATE_MASK 0x0000000F /* bits 0-3 */ 1090285242Sachim#define AGSA_DEV_INFO_RATE_1_5G 0x00000008 /* 8h */ 1091285242Sachim#define AGSA_DEV_INFO_RATE_3_0G 0x00000009 /* 9h */ 1092285242Sachim#define AGSA_DEV_INFO_RATE_6_0G 0x0000000A /* Ah */ 1093285242Sachim#define AGSA_DEV_INFO_RATE_12_0G 0x0000000B /* Bh */ 1094285242Sachim 1095285242Sachim/* devType */ 1096285242Sachim#define AGSA_DEV_INFO_DEV_TYPE_MASK 0x000000E0 /* bits 5-7 */ 1097285242Sachim#define AGSA_DEV_INFO_DEV_TYPE_END_DEVICE 0x00000020 /* 001b */ 1098285242Sachim#define AGSA_DEV_INFO_DEV_TYPE_EDGE_EXP_DEVICE 0x00000040 /* 010b */ 1099285242Sachim#define AGSA_DEV_INFO_DEV_TYPE_FANOUT_EXP_DEVICE 0x00000060 /* 011b */ 1100285242Sachim 1101285242Sachim/***************************************************************************** 1102285242Sachim** SAS TM Function definitions see SAS spec p308 Table 105 (Revision 7) 1103285242Sachim*****************************************************************************/ 1104285242Sachim#define AGSA_ABORT_TASK 0x01 1105285242Sachim#define AGSA_ABORT_TASK_SET 0x02 1106285242Sachim#define AGSA_CLEAR_TASK_SET 0x04 1107285242Sachim#define AGSA_LOGICAL_UNIT_RESET 0x08 1108285242Sachim#define AGSA_IT_NEXUS_RESET 0x10 1109285242Sachim#define AGSA_CLEAR_ACA 0x40 1110285242Sachim#define AGSA_QUERY_TASK 0x80 1111285242Sachim#define AGSA_QUERY_TASK_SET 0x81 1112285242Sachim#define AGSA_QUERY_UNIT_ATTENTION 0x82 1113285242Sachim 1114285242Sachim/***************************************************************************** 1115285242Sachim** SAS TM Function Response Code see SAS spec p312 Table 111 (Revision 7) 1116285242Sachim*****************************************************************************/ 1117285242Sachim#define AGSA_TASK_MANAGEMENT_FUNCTION_COMPLETE 0x0 1118285242Sachim#define AGSA_INVALID_FRAME 0x2 1119285242Sachim#define AGSA_TASK_MANAGEMENT_FUNCTION_NOT_SUPPORTED 0x4 1120285242Sachim#define AGSA_TASK_MANAGEMENT_FUNCTION_FAILED 0x5 1121285242Sachim#define AGSA_TASK_MANAGEMENT_FUNCTION_SUCCEEDED 0x8 1122285242Sachim#define AGSA_INCORRECT_LOGICAL_UNIT_NUMBER 0x9 1123285242Sachim/* SAS spec 9.2.2.5.3 p356 Table 128 (Revision 9e) */ 1124285242Sachim#define AGSA_OVERLAPPED_TAG_ATTEMPTED 0xA 1125285242Sachim 1126285242Sachim#define AGSA_SATA_BSY_OVERRIDE 0x00080000 1127285242Sachim#define AGSA_SATA_CLOSE_CLEAR_AFFILIATION 0x00400000 1128285242Sachim 1129285242Sachim#define AGSA_MAX_SMPPAYLOAD_VIA_SFO 40 1130285242Sachim#define AGSA_MAX_SSPPAYLOAD_VIA_SFO 36 1131285242Sachim 1132285242Sachim/* SATA Initiator Request option field defintion */ 1133285242Sachim#define AGSA_RETURN_D2H_FIS_GOOD_COMPLETION 0x000001 1134285242Sachim#define AGSA_SATA_ENABLE_ENCRYPTION 0x000004 1135285242Sachim#define AGSA_SATA_ENABLE_DIF 0x000008 1136285242Sachim#define AGSA_SATA_SKIP_QWORD 0xFFFF00 1137285242Sachim 1138285242Sachim/* SAS Initiator Request flag definitions */ 1139285242Sachim/* Bits 0,1 use TLR_MASK */ 1140285242Sachim 1141285242Sachim#define AGSA_SAS_ENABLE_ENCRYPTION 0x0004 1142285242Sachim#define AGSA_SAS_ENABLE_DIF 0x0008 1143285242Sachim 1144285242Sachim#ifdef SAFLAG_USE_DIF_ENC_IOMB 1145285242Sachim#define AGSA_SAS_USE_DIF_ENC_OPSTART 0x0010 1146285242Sachim#endif /* SAFLAG_USE_DIF_ENC_IOMB */ 1147285242Sachim 1148285242Sachim#define AGSA_SAS_ENABLE_SKIP_MASK 0x0010 1149285242Sachim#define AGSA_SAS_SKIP_MASK_OFFSET 0xFFE0 1150285242Sachim 1151285242Sachim/**************************************************************************** 1152285242Sachim** SMP Phy control Phy Operation field 1153285242Sachim****************************************************************************/ 1154285242Sachim#define AGSA_PHY_CONTROL_LINK_RESET_OP 0x1 1155285242Sachim#define AGSA_PHY_CONTROL_HARD_RESET_OP 0x2 1156285242Sachim#define AGSA_PHY_CONTROL_DISABLE 0x3 1157285242Sachim#define AGSA_PHY_CONTROL_CLEAR_ERROR_LOG_OP 0x5 1158285242Sachim#define AGSA_PHY_CONTROL_CLEAR_AFFILIATION 0x6 1159285242Sachim#define AGSA_PHY_CONTROL_XMIT_SATA_PS_SIGNAL 0x7 1160285242Sachim 1161285242Sachim/**************************************************************************** 1162285242Sachim** SAS Diagnostic Operation code 1163285242Sachim****************************************************************************/ 1164285242Sachim#define AGSA_SAS_DIAG_START 0x1 1165285242Sachim#define AGSA_SAS_DIAG_END 0x0 1166285242Sachim 1167285242Sachim/**************************************************************************** 1168285242Sachim** Port Control constants 1169285242Sachim****************************************************************************/ 1170285242Sachim#define AGSA_PORT_SET_SMP_PHY_WIDTH 0x1 1171285242Sachim#define AGSA_PORT_SET_PORT_RECOVERY_TIME 0x2 1172285242Sachim#define AGSA_PORT_IO_ABORT 0x3 1173285242Sachim#define AGSA_PORT_SET_PORT_RESET_TIME 0x4 1174285242Sachim#define AGSA_PORT_HARD_RESET 0x5 1175285242Sachim#define AGSA_PORT_CLEAN_UP 0x6 1176285242Sachim#define AGSA_STOP_PORT_RECOVERY_TIMER 0x7 1177285242Sachim 1178285242Sachim/* Device State */ 1179285242Sachim#define SA_DS_OPERATIONAL 0x1 1180285242Sachim#define SA_DS_PORT_IN_RESET 0x2 1181285242Sachim#define SA_DS_IN_RECOVERY 0x3 1182285242Sachim#define SA_DS_IN_ERROR 0x4 1183285242Sachim#define SA_DS_NON_OPERATIONAL 0x7 1184285242Sachim 1185285242Sachim/************************************************************************************ 1186285242Sachim * * 1187285242Sachim * Constants defined for LL Layer ends * 1188285242Sachim * * 1189285242Sachim ************************************************************************************/ 1190285242Sachim 1191285242Sachim/************************************************************************************ 1192285242Sachim * * 1193285242Sachim * Constants defined for OS Layer starts * 1194285242Sachim * * 1195285242Sachim ************************************************************************************/ 1196285242Sachim/***************************************** 1197285242Sachim * ossaXXX return values 1198285242Sachim ******************************************/ 1199285242Sachim/* common for all ossaXXX CB */ 1200285242Sachim#define OSSA_SUCCESS 0x00 /**< flag indicates successful callback status */ 1201285242Sachim#define OSSA_FAILURE 0x01 /**< flag indicates failed callback status */ 1202285242Sachim 1203285242Sachim/* ossaHwCB() */ 1204285242Sachim#define OSSA_RESET_PENDING 0x03 /**< flag indicates reset pending callback status */ 1205285242Sachim#define OSSA_CHIP_FAILED 0x04 /**< flag indicates chip failed callback status */ 1206285242Sachim#define OSSA_FREEZE_FAILED 0x05 /**< flag indicates freeze failed callback status */ 1207285242Sachim 1208285242Sachim/* ossaLocalPhyControl() */ 1209285242Sachim#define OSSA_PHY_CONTROL_FAILURE 0x03 /**< flag indicates phy Control operation failure */ 1210285242Sachim 1211285242Sachim/* ossaDeviceRegisterCB() */ 1212285242Sachim#define OSSA_FAILURE_OUT_OF_RESOURCE 0x01 /**< flag indicates failed callback status */ 1213285242Sachim#define OSSA_FAILURE_DEVICE_ALREADY_REGISTERED 0x02 /**< flag indicates failed callback status */ 1214285242Sachim#define OSSA_FAILURE_INVALID_PHY_ID 0x03 /**< flag indicates failed callback status */ 1215285242Sachim#define OSSA_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04 /**< flag indicates failed callback status */ 1216285242Sachim#define OSSA_FAILURE_PORT_ID_OUT_OF_RANGE 0x05 /**< flag indicates failed callback status */ 1217285242Sachim#define OSSA_FAILURE_PORT_NOT_VALID_STATE 0x06 /**< flag indicates failed callback status */ 1218285242Sachim#define OSSA_FAILURE_DEVICE_TYPE_NOT_VALID 0x07 /**< flag indicates failed callback status */ 1219285242Sachim#define OSSA_ERR_DEVICE_HANDLE_UNAVAILABLE 0x1020 1220285242Sachim#define OSSA_ERR_DEVICE_ALREADY_REGISTERED 0x1021 1221285242Sachim#define OSSA_ERR_DEVICE_TYPE_NOT_VALID 0x1022 1222285242Sachim 1223285242Sachim#define OSSA_MPI_ERR_DEVICE_ACCEPT_PENDING 0x1027 /**/ 1224285242Sachim 1225285242Sachim#define OSSA_ERR_PORT_INVALID 0x1041 1226285242Sachim#define OSSA_ERR_PORT_STATE_NOT_VALID 0x1042 1227285242Sachim 1228285242Sachim#define OSSA_ERR_PORT_SMP_PHY_WIDTH_EXCEED 0x1045 1229285242Sachim 1230285242Sachim#define OSSA_ERR_PHY_ID_INVALID 0x1061 1231285242Sachim#define OSSA_ERR_PHY_ID_ALREADY_REGISTERED 0x1062 1232285242Sachim 1233285242Sachim 1234285242Sachim 1235285242Sachim/* ossaDeregisterDeviceCB() */ 1236285242Sachim#define OSSA_INVALID_HANDLE 0x02 /**< flag indicates failed callback status */ 1237285242Sachim#define OSSA_ERR_DEVICE_HANDLE_INVALID 0x1023 /* MPI_ERR_DEVICE_HANDLE_INVALID The device handle associated with DEVICE_ID does not exist. */ 1238285242Sachim#define OSSA_ERR_DEVICE_BUSY 0x1024 /* MPI_ERR_DEVICE_BUSY Device has outstanding I/Os. */ 1239285242Sachim 1240285242Sachim 1241285242Sachim#define OSSA_RC_ACCEPT 0x00 /**< flag indicates the result of the callback function */ 1242285242Sachim#define OSSA_RC_REJECT 0x01 /**< flag indicates the result of the callback function */ 1243285242Sachim 1244285242Sachim/* ossaSetDeviceStateCB() */ 1245285242Sachim#define OSSA_INVALID_STATE 0x0001 1246285242Sachim#define OSSA_ERR_DEVICE_NEW_STATE_INVALID 0x1025 1247285242Sachim#define OSSA_ERR_DEVICE_STATE_CHANGE_NOT_ALLOWED 0x1026 1248285242Sachim#define OSSA_ERR_DEVICE_STATE_INVALID 0x0049 1249285242Sachim 1250285242Sachim/* status of ossaSASDiagExecuteCB() */ 1251285242Sachim#define OSSA_DIAG_SUCCESS 0x00 /* Successful SAS diagnostic command. */ 1252285242Sachim#define OSSA_DIAG_INVALID_COMMAND 0x01 /* Invalid SAS diagnostic command. */ 1253285242Sachim#define OSSA_REGISTER_ACCESS_TIMEOUT 0x02 /* Register access has been timed-out. This is applicable only to the SPCv controller. */ 1254285242Sachim#define OSSA_DIAG_FAIL 0x02 /* SAS diagnostic command failed. This is applicable only to the SPC controller. */ 1255285242Sachim#define OSSA_DIAG_NOT_IN_DIAGNOSTIC_MODE 0x03 /* Attempted to execute SAS diagnostic command but PHY is not in diagnostic mode */ 1256285242Sachim#define OSSA_DIAG_INVALID_PHY 0x04 /* Attempted to execute SAS diagnostic command on an invalid/out-of-range PHY. */ 1257285242Sachim#define OSSA_MEMORY_ALLOC_FAILURE 0x05 /* Memory allocation failed in diagnostic. This is applicable only to the SPCv controller. */ 1258285242Sachim 1259285242Sachim 1260285242Sachim/* status of ossaSASDiagStartEndCB() */ 1261285242Sachim#define OSSA_DIAG_SE_SUCCESS 0x00 1262285242Sachim#define OSSA_DIAG_SE_INVALID_PHY_ID 0x01 1263285242Sachim#define OSSA_DIAG_PHY_NOT_DISABLED 0x02 1264285242Sachim#define OSSA_DIAG_OTHER_FAILURE 0x03 /* SPC */ 1265285242Sachim#define OSSA_DIAG_OPCODE_INVALID 0x03 1266285242Sachim 1267285242Sachim/* status of ossaPortControlCB() */ 1268285242Sachim#define OSSA_PORT_CONTROL_FAILURE 0x03 1269285242Sachim 1270285242Sachim#define OSSA_MPI_ERR_PORT_IO_RESOURCE_UNAVAILABLE 0x1004 1271285242Sachim#define OSSA_MPI_ERR_PORT_INVALID 0x1041 /**/ 1272285242Sachim#define OSSA_MPI_ERR_PORT_OP_NOT_IN_USE 0x1043 /**/ 1273285242Sachim#define OSSA_MPI_ERR_PORT_OP_NOT_SUPPORTED 0x1044 /**/ 1274285242Sachim#define OSSA_MPI_ERR_PORT_SMP_WIDTH_EXCEEDED 0x1045 /**/ 1275285242Sachim#define OSSA_MPI_ERR_PORT_NOT_IN_CORRECT_STATE 0x1047 /**/ 1276285242Sachim 1277285242Sachim/*regDumpNum of agsaRegDumpInfo_t */ 1278285242Sachim#define GET_GSM_SM_INFO 0x02 1279285242Sachim#define GET_IOST_RB_INFO 0x03 1280285242Sachim 1281285242Sachim/************************************************************************************ 1282285242Sachim * HW Events 1283285242Sachim ************************************************************************************/ 1284285242Sachim#define OSSA_HW_EVENT_RESET_START 0x01 /**< flag indicates reset started event */ 1285285242Sachim#define OSSA_HW_EVENT_RESET_COMPLETE 0x02 /**< flag indicates chip reset completed event */ 1286285242Sachim#define OSSA_HW_EVENT_PHY_STOP_STATUS 0x03 /**< flag indicates phy stop event status */ 1287285242Sachim#define OSSA_HW_EVENT_SAS_PHY_UP 0x04 /**< flag indicates SAS link up event */ 1288285242Sachim#define OSSA_HW_EVENT_SATA_PHY_UP 0x05 /**< flag indicates SATA link up event */ 1289285242Sachim#define OSSA_HW_EVENT_SATA_SPINUP_HOLD 0x06 /**< flag indicates SATA spinup hold event */ 1290285242Sachim#define OSSA_HW_EVENT_PHY_DOWN 0x07 /**< flag indicates link down event */ 1291285242Sachim 1292285242Sachim#define OSSA_HW_EVENT_BROADCAST_CHANGE 0x09 /**< flag indicates broadcast change event */ 1293285242Sachim/* not used spcv 0x0A*/ 1294285242Sachim#define OSSA_HW_EVENT_PHY_ERROR 0x0A /**< flag indicates link error event */ 1295285242Sachim#define OSSA_HW_EVENT_BROADCAST_SES 0x0B /**< flag indicates broadcast change (SES) event */ 1296285242Sachim#define OSSA_HW_EVENT_PHY_ERR_INBOUND_CRC 0x0C 1297285242Sachim#define OSSA_HW_EVENT_HARD_RESET_RECEIVED 0x0D /**< flag indicates hardware reset received event */ 1298285242Sachim/* not used spcv 0x0E*/ 1299285242Sachim#define OSSA_HW_EVENT_MALFUNCTION 0x0E /**< flag indicates unrecoverable Error */ 1300285242Sachim#define OSSA_HW_EVENT_ID_FRAME_TIMEOUT 0x0F /**< flag indicates ID Frame Timeout event */ 1301285242Sachim#define OSSA_HW_EVENT_BROADCAST_EXP 0x10 /**< flag indicates broadcast (EXPANDER) event */ 1302285242Sachim/* not used spcv 0x11*/ 1303285242Sachim#define OSSA_HW_EVENT_PHY_START_STATUS 0x11 /**< flag indicates phy start event status */ 1304285242Sachim#define OSSA_HW_EVENT_PHY_ERR_INVALID_DWORD 0x12 /**< flag indicates Link error invalid DWORD */ 1305285242Sachim#define OSSA_HW_EVENT_PHY_ERR_DISPARITY_ERROR 0x13 /**< flag indicates Phy error disparity */ 1306285242Sachim#define OSSA_HW_EVENT_PHY_ERR_CODE_VIOLATION 0x14 /**< flag indicates Phy error code violation */ 1307285242Sachim#define OSSA_HW_EVENT_PHY_ERR_LOSS_OF_DWORD_SYNCH 0x15 /**< flag indicates Link error loss of DWORD synch */ 1308285242Sachim#define OSSA_HW_EVENT_PHY_ERR_PHY_RESET_FAILED 0x16 /**< flag indicates Link error phy reset failed */ 1309285242Sachim#define OSSA_HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17 /**< flag indicates Port Recovery timeout */ 1310285242Sachim#define OSSA_HW_EVENT_PORT_RECOVER 0x18 /**< flag indicates Port Recovery */ 1311285242Sachim#define OSSA_HW_EVENT_PORT_RESET_TIMER_TMO 0x19 /**< flag indicates Port Reset Timer out */ 1312285242Sachim#define OSSA_HW_EVENT_PORT_RESET_COMPLETE 0x20 /**< flag indicates Port Reset Complete */ 1313285242Sachim#define OSSA_HW_EVENT_BROADCAST_ASYNCH_EVENT 0x21 /**< flag indicates Broadcast Asynch Event */ 1314285242Sachim#define OSSA_HW_EVENT_IT_NEXUS_LOSS 0x22 /**< Custom: H/W event for IT Nexus Loss */ 1315285242Sachim 1316285242Sachim#define OSSA_HW_EVENT_OPEN_RETRY_BACKOFF_THR_ADJUSTED 0x25 1317285242Sachim 1318285242Sachim#define OSSA_HW_EVENT_ENCRYPTION 0x83 /**< TSDK internal flag indicating that an encryption event occurred */ 1319285242Sachim#define OSSA_HW_EVENT_MODE 0x84 /**< TSDK internal flag indicating that a controller mode page operation completed */ 1320285242Sachim#define OSSA_HW_EVENT_SECURITY_MODE 0x85 /**< TSDK internal flag indicating that saEncryptSetMode() completed */ 1321285242Sachim 1322285242Sachim 1323285242Sachim/* port state */ 1324285242Sachim#define OSSA_PORT_NOT_ESTABLISHED 0x00 /**< flag indicates port is not established */ 1325285242Sachim#define OSSA_PORT_VALID 0x01 /**< flag indicates port valid */ 1326285242Sachim#define OSSA_PORT_LOSTCOMM 0x02 /**< flag indicates port lost communication */ 1327285242Sachim#define OSSA_PORT_IN_RESET 0x04 /**< flag indicates port in reset state */ 1328285242Sachim#define OSSA_PORT_3RDPARTY_RESET 0x07 /**< flag indicates port in 3rd party reset state */ 1329285242Sachim#define OSSA_PORT_INVALID 0x08 /**< flag indicates port invalid */ 1330285242Sachim 1331285242Sachim/* status for agsaHWEventMode_t */ 1332285242Sachim#define OSSA_CTL_SUCCESS 0x0000 1333285242Sachim#define OSSA_CTL_INVALID_CONFIG_PAGE 0x1001 1334285242Sachim#define OSSA_CTL_INVALID_PARAM_IN_CONFIG_PAGE 0x1002 1335285242Sachim#define OSSA_CTL_INVALID_ENCRYPTION_SECURITY_MODE 0x1003 1336285242Sachim#define OSSA_CTL_RESOURCE_NOT_AVAILABLE 0x1004 1337285242Sachim#define OSSA_CTL_CONTROLLER_NOT_IDLE 0x1005 1338285242Sachim// #define OSSA_CTL_NVM_MEMORY_ACCESS_ERR 0x100B 1339285242Sachim#define OSSA_CTL_OPERATOR_AUTHENTICATION_FAILURE 0x100XX 1340285242Sachim 1341285242Sachim 1342285242Sachim 1343285242Sachim/************************************************************************************ 1344285242Sachim * General Events value 1345285242Sachim ************************************************************************************/ 1346285242Sachim#define OSSA_INBOUND_V_BIT_NOT_SET 0x01 1347285242Sachim#define OSSA_INBOUND_OPC_NOT_SUPPORTED 0x02 1348285242Sachim#define OSSA_INBOUND_IOMB_INVALID_OBID 0x03 1349285242Sachim 1350285242Sachim/************************************************************************************ 1351285242Sachim * FW Flash Update status values 1352285242Sachim ************************************************************************************/ 1353285242Sachim#define OSSA_FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x00 /**< flag indicates fw flash update completed */ 1354285242Sachim#define OSSA_FLASH_UPDATE_IN_PROGRESS 0x01 /**< flag indicates fw flash update in progress */ 1355285242Sachim#define OSSA_FLASH_UPDATE_HDR_ERR 0x02 /**< flag indicates fw flash header error */ 1356285242Sachim#define OSSA_FLASH_UPDATE_OFFSET_ERR 0x03 /**< flag indicates fw flash offset error */ 1357285242Sachim#define OSSA_FLASH_UPDATE_CRC_ERR 0x04 /**< flag indicates fw flash CRC error */ 1358285242Sachim#define OSSA_FLASH_UPDATE_LENGTH_ERR 0x05 /**< flag indicates fw flash length error */ 1359285242Sachim#define OSSA_FLASH_UPDATE_HW_ERR 0x06 /**< flag indicates fw flash HW error */ 1360285242Sachim#define OSSA_FLASH_UPDATE_HMAC_ERR 0x0E /**< flag indicates fw flash Firmware image HMAC authentication failure.*/ 1361285242Sachim 1362285242Sachim#define OSSA_FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10 /**< flag indicates fw flash down load not supported */ 1363285242Sachim#define OSSA_FLASH_UPDATE_DISABLED 0x11 /**< flag indicates fw flash Update disabled */ 1364285242Sachim#define OSSA_FLASH_FWDNLD_DEVICE_UNSUPPORT 0x12 /**< flag indicates fw flash Update disabled */ 1365285242Sachim 1366285242Sachim/************************************************************************************ 1367285242Sachim* Discovery status values 1368285242Sachim************************************************************************************/ 1369285242Sachim#define OSSA_DISCOVER_STARTED 0x00 /**< flag indicates discover started */ 1370285242Sachim#define OSSA_DISCOVER_FOUND_DEVICE 0x01 /**< flag indicates discovery found a new device */ 1371285242Sachim#define OSSA_DISCOVER_REMOVED_DEVICE 0x02 /**< flag indicates discovery found a device removed */ 1372285242Sachim#define OSSA_DISCOVER_COMPLETE 0x03 /**< flag indicates discover completed */ 1373285242Sachim#define OSSA_DISCOVER_ABORT 0x04 /**< flag indicates discover error12 */ 1374285242Sachim#define OSSA_DISCOVER_ABORT_ERROR_1 0x05 /**< flag indicates discover error1 */ 1375285242Sachim#define OSSA_DISCOVER_ABORT_ERROR_2 0x06 /**< flag indicates discover error2 */ 1376285242Sachim#define OSSA_DISCOVER_ABORT_ERROR_3 0x07 /**< flag indicates discover error3 */ 1377285242Sachim#define OSSA_DISCOVER_ABORT_ERROR_4 0x08 /**< flag indicates discover error4 */ 1378285242Sachim#define OSSA_DISCOVER_ABORT_ERROR_5 0x09 /**< flag indicates discover error5 */ 1379285242Sachim#define OSSA_DISCOVER_ABORT_ERROR_6 0x0A /**< flag indicates discover error6 */ 1380285242Sachim#define OSSA_DISCOVER_ABORT_ERROR_7 0x0B /**< flag indicates discover error7 */ 1381285242Sachim#define OSSA_DISCOVER_ABORT_ERROR_8 0x0C /**< flag indicates discover error8 */ 1382285242Sachim#define OSSA_DISCOVER_ABORT_ERROR_9 0x0D /**< flag indicates discover error9 */ 1383285242Sachim 1384285242Sachim/*********************************************************************************** 1385285242Sachim * Log Debug Levels 1386285242Sachim ***********************************************************************************/ 1387285242Sachim#define OSSA_DEBUG_LEVEL_0 0x00 /**< debug level 0 */ 1388285242Sachim#define OSSA_DEBUG_LEVEL_1 0x01 /**< debug level 1 */ 1389285242Sachim#define OSSA_DEBUG_LEVEL_2 0x02 /**< debug level 2 */ 1390285242Sachim#define OSSA_DEBUG_LEVEL_3 0x03 /**< debug level 3 */ 1391285242Sachim#define OSSA_DEBUG_LEVEL_4 0x04 /**< debug level 4 */ 1392285242Sachim 1393285242Sachim#define OSSA_DEBUG_PRINT_INVALID_NUMBER 0xFFFFFFFF /**< the number won't be printed by OS layer */ 1394285242Sachim 1395285242Sachim#define OSSA_FRAME_TYPE_SSP_CMD 0x06 /**< flag indicates received frame is SSP command */ 1396285242Sachim#define OSSA_FRAME_TYPE_SSP_TASK 0x16 /**< flag indicates received frame is SSP task management */ 1397285242Sachim 1398285242Sachim/* Event Source Type of saRegisterEventCallback() */ 1399285242Sachim#define OSSA_EVENT_SOURCE_DEVICE_HANDLE_ADDED 0x00 1400285242Sachim#define OSSA_EVENT_SOURCE_DEVICE_HANDLE_REMOVED 0x01 1401285242Sachim 1402285242Sachim/* Status of Get Device Info CB */ 1403285242Sachim#define OSSA_DEV_INFO_INVALID_HANDLE 0x01 1404285242Sachim#define OSSA_DEV_INFO_NO_EXTENDED_INFO 0x02 1405285242Sachim#define OSSA_DEV_INFO_SAS_EXTENDED_INFO 0x03 1406285242Sachim#define OSSA_DEV_INFO_SATA_EXTENDED_INFO 0x04 1407285242Sachim 1408285242Sachim/* Diagnostic Command Type */ 1409285242Sachim#define AGSA_CMD_TYPE_DIAG_OPRN_PERFORM 0x00 1410285242Sachim#define AGSA_CMD_TYPE_DIAG_OPRN_STOP 0x01 1411285242Sachim#define AGSA_CMD_TYPE_DIAG_THRESHOLD_SPECIFY 0x02 1412285242Sachim#define AGSA_CMD_TYPE_DIAG_RECEIVE_ENABLE 0x03 1413285242Sachim#define AGSA_CMD_TYPE_DIAG_REPORT_GET 0x04 1414285242Sachim#define AGSA_CMD_TYPE_DIAG_ERR_CNT_RESET 0x05 1415285242Sachim 1416285242Sachim/* Command Description for CMD_TYPE DIAG_OPRN_PERFORM, DIAG_OPRN_STOP, THRESHOLD_SPECIFY */ 1417285242Sachim#define AGSA_CMD_DESC_PRBS 0x00 1418285242Sachim#define AGSA_CMD_DESC_CJTPAT 0x01 1419285242Sachim#define AGSA_CMD_DESC_USR_PATTERNS 0x02 1420285242Sachim#define AGSA_CMD_DESC_PRBS_ERR_INSERT 0x08 1421285242Sachim#define AGSA_CMD_DESC_PRBS_INVERT 0x09 1422285242Sachim#define AGSA_CMD_DESC_CJTPAT_INVERT 0x0A 1423285242Sachim#define AGSA_CMD_DESC_CODE_VIOL_INSERT 0x0B 1424285242Sachim#define AGSA_CMD_DESC_DISP_ERR_INSERT 0x0C 1425285242Sachim#define AGSA_CMD_DESC_SSPA_PERF_EVENT_1 0x0E 1426285242Sachim#define AGSA_CMD_DESC_LINE_SIDE_ANA_LPBK 0x10 1427285242Sachim#define AGSA_CMD_DESC_LINE_SIDE_DIG_LPBK 0x11 1428285242Sachim#define AGSA_CMD_DESC_SYS_SIDE_ANA_LPBK 0x12 1429285242Sachim 1430285242Sachim/* Command Description for CMD_TYPE DIAG_REPORT_GET and ERR_CNT_RESET */ 1431285242Sachim#define AGSA_CMD_DESC_PRBS_ERR_CNT 0x00 1432285242Sachim#define AGSA_CMD_DESC_CODE_VIOL_ERR_CNT 0x01 1433285242Sachim#define AGSA_CMD_DESC_DISP_ERR_CNT 0x02 1434285242Sachim#define AGSA_CMD_DESC_LOST_DWD_SYNC_CNT 0x05 1435285242Sachim#define AGSA_CMD_DESC_INVALID_DWD_CNT 0x06 1436285242Sachim#define AGSA_CMD_DESC_CODE_VIOL_ERR_CNT_THHD 0x09 1437285242Sachim#define AGSA_CMD_DESC_DISP_ERR_CNT_THHD 0x0A 1438285242Sachim#define AGSA_CMD_DESC_SSPA_PERF_CNT 0x0B 1439285242Sachim#define AGSA_CMD_DESC_PHY_RST_CNT 0x0C 1440285242Sachim#define AGSA_CMD_DESC_SSPA_PERF_1_THRESHOLD 0x0E 1441285242Sachim 1442285242Sachim#define AGSA_CMD_DESC_CODE_VIOL_ERR_THHD 0x19 1443285242Sachim#define AGSA_CMD_DESC_DISP_ERR_THHD 0x1A 1444285242Sachim#define AGSA_CMD_DESC_RX_LINK_BANDWIDTH 0x1B 1445285242Sachim#define AGSA_CMD_DESC_TX_LINK_BANDWIDTH 0x1C 1446285242Sachim#define AGSA_CMD_DESC_ALL 0x1F 1447285242Sachim 1448285242Sachim/* NVMDevice type */ 1449285242Sachim#define AGSA_NVMD_TWI_DEVICES 0x00 1450285242Sachim#define AGSA_NVMD_CONFIG_SEEPROM 0x01 1451285242Sachim#define AGSA_NVMD_VPD_FLASH 0x04 1452285242Sachim#define AGSA_NVMD_AAP1_REG_FLASH 0x05 1453285242Sachim#define AGSA_NVMD_IOP_REG_FLASH 0x06 1454285242Sachim#define AGSA_NVMD_EXPANSION_ROM 0x07 1455285242Sachim#define AGSA_NVMD_REG_FLASH 0x05 1456285242Sachim 1457285242Sachim 1458285242Sachim/* GET/SET NVMD Data Response errors */ 1459285242Sachim#define OSSA_NVMD_SUCCESS 0x0000 1460285242Sachim#define OSSA_NVMD_MODE_ERROR 0x0001 1461285242Sachim#define OSSA_NVMD_LENGTH_ERROR 0x0002 1462285242Sachim#define OSSA_NVMD_TWI_ADDRESS_SIZE_ERROR 0x0005 1463285242Sachim#define OSSA_NVMD_TWI_NACK_ERROR 0x2001 1464285242Sachim#define OSSA_NVMD_TWI_LOST_ARB_ERROR 0x2002 1465285242Sachim#define OSSA_NVMD_TWI_TIMEOUT_ERROR 0x2021 1466285242Sachim#define OSSA_NVMD_TWI_BUS_NACK_ERROR 0x2081 1467285242Sachim#define OSSA_NVMD_TWI_ARB_FAILED_ERROR 0x2082 1468285242Sachim#define OSSA_NVMD_TWI_BUS_TIMEOUT_ERROR 0x20FF 1469285242Sachim#define OSSA_NVMD_FLASH_PARTITION_NUM_ERROR 0x9001 1470285242Sachim#define OSSA_NVMD_FLASH_LENGTH_TOOBIG_ERROR 0x9002 1471285242Sachim#define OSSA_NVMD_FLASH_PROGRAM_ERROR 0x9003 1472285242Sachim#define OSSA_NVMD_FLASH_DEVICEID_ERROR 0x9004 1473285242Sachim#define OSSA_NVMD_FLASH_VENDORID_ERROR 0x9005 1474285242Sachim#define OSSA_NVMD_FLASH_ERASE_TIMEOUT_ERROR 0x9006 1475285242Sachim#define OSSA_NVMD_FLASH_ERASE_ERROR 0x9007 1476285242Sachim#define OSSA_NVMD_FLASH_BUSY_ERROR 0x9008 1477285242Sachim#define OSSA_NVMD_FLASH_NOT_SUPPORT_DEVICE_ERROR 0x9009 1478285242Sachim#define OSSA_NVMD_FLASH_CFI_INF_ERROR 0x900A 1479285242Sachim#define OSSA_NVMD_FLASH_MORE_ERASE_BLOCK_ERROR 0x900B 1480285242Sachim#define OSSA_NVMD_FLASH_READ_ONLY_ERROR 0x900C 1481285242Sachim#define OSSA_NVMD_FLASH_MAP_TYPE_ERROR 0x900D 1482285242Sachim#define OSSA_NVMD_FLASH_MAP_DISABLE_ERROR 0x900E 1483285242Sachim 1484285242Sachim/************************************************************ 1485285242Sachim* ossaHwCB Encryption encryptOperation of agsaHWEventEncrypt_t 1486285242Sachim************************************************************/ 1487285242Sachim#define OSSA_HW_ENCRYPT_KEK_UPDATE 0x0000 1488285242Sachim#define OSSA_HW_ENCRYPT_KEK_UPDATE_AND_STORE 0x0001 1489285242Sachim#define OSSA_HW_ENCRYPT_KEK_INVALIDTE 0x0002 1490285242Sachim#define OSSA_HW_ENCRYPT_DEK_UPDATE 0x0003 1491285242Sachim#define OSSA_HW_ENCRYPT_DEK_INVALIDTE 0x0004 1492285242Sachim#define OSSA_HW_ENCRYPT_OPERATOR_MANAGEMENT 0x0005 1493285242Sachim#define OSSA_HW_ENCRYPT_TEST_EXECUTE 0x0006 1494285242Sachim#define OSSA_HW_ENCRYPT_SET_OPERATOR 0x0007 1495285242Sachim#define OSSA_HW_ENCRYPT_GET_OPERATOR 0x0008 1496285242Sachim 1497285242Sachim 1498285242Sachim/************************************************************ 1499285242Sachim* ossaHwCB Encryption status of agsaHWEventEncrypt_t 1500285242Sachim************************************************************/ 1501285242Sachim/* KEK and DEK managment status from PM */ 1502285242Sachim#define OSSA_INVALID_ENCRYPTION_SECURITY_MODE 0x1003 1503285242Sachim#define OSSA_KEK_MGMT_SUBOP_NOT_SUPPORTED_ 0x2000 /*not in PM 101222*/ 1504285242Sachim#define OSSA_DEK_MGMT_SUBOP_NOT_SUPPORTED 0x2000 1505285242Sachim#define OSSA_MPI_ENC_ERR_ILLEGAL_DEK_PARAM 0x2001 1506285242Sachim#define OSSA_MPI_ERR_DEK_MANAGEMENT_DEK_UNWRAP_FAIL 0x2002 1507285242Sachim#define OSSA_MPI_ENC_ERR_ILLEGAL_KEK_PARAM 0x2021 1508285242Sachim#define OSSA_MPI_ERR_KEK_MANAGEMENT_KEK_UNWRAP_FAIL 0x2022 1509285242Sachim#define OSSA_MPI_ERR_KEK_MANAGEMENT_NVRAM_OPERATION_FAIL 0x2023 1510285242Sachim 1511285242Sachim/*encrypt operator management response status */ 1512285242Sachim#define OSSA_OPR_MGMT_OP_NOT_SUPPORTED 0x2060 1513285242Sachim#define OSSA_MPI_ENC_ERR_OPR_PARAM_ILLEGAL 0x2061 1514285242Sachim#define OSSA_MPI_ENC_ERR_OPR_ID_NOT_FOUND 0x2062 1515285242Sachim#define OSSA_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH 0x2063 1516285242Sachim#define OSSA_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED 0x2064 1517285242Sachim 1518285242Sachim/*encrypt saSetOperator() response status */ 1519285242Sachim#define OSSA_MPI_ENC_ERR_CONTROLLER_NOT_IDLE 0x1005 1520285242Sachim#define OSSA_MPI_ENC_NVM_MEM_ACCESS_ERR 0x100B 1521285242Sachim 1522285242Sachim/* agsaEncryptSMX | agsaEncryptCipherMode == cipherMode for saEncryptSetMode()*/ 1523285242Sachim/* Make sure all definitions are unique bits */ 1524285242Sachim#define agsaEncryptSMF 0x00000000 1525285242Sachim#define agsaEncryptSMA 0x00000100 1526285242Sachim#define agsaEncryptSMB 0x00000200 1527285242Sachim#define agsaEncryptReturnSMF (1 << 12) 1528285242Sachim#define agsaEncryptAuthorize (1 << 13) 1529285242Sachim 1530285242Sachim/* 1531285242SachimBits 16-23: Allowable Cipher Mode(ACM) 1532285242SachimBit 16: Enable AES ECB. If set to 1, AES ECB is enable. If set to 0, AES ECB is disabled. 1533285242SachimBit 22: Enable AES XTS. If set to 1, AES XTS is enable. If set to 0, AES XTS is disabled. 1534285242Sachim*/ 1535285242Sachim#define agsaEncryptAcmMask 0x00ff0000 1536285242Sachim#define agsaEncryptEnableAES_ECB (1 << 16) 1537285242Sachim#define agsaEncryptEnableAES_XTS (1 << 22) 1538285242Sachim 1539285242Sachim 1540285242Sachim 1541285242Sachim#define agsaEncryptCipherModeECB 0x00000001 1542285242Sachim#define agsaEncryptCipherModeXTS 0x00000002 1543285242Sachim 1544285242Sachim 1545285242Sachim 1546285242Sachim#define agsaEncryptStatusNoNVRAM 0x00000001 1547285242Sachim#define agsaEncryptStatusNVRAMErr 0x00000002 1548285242Sachim 1549285242Sachim/* 1550285242Sachim 1551285242SachimBin Hex Sector Total 1552285242Sachim00000 :0x0 512B 512 1553285242Sachim11000 :0x1 520B 520 1554285242Sachim00010 :0x2 4K 4096 1555285242Sachim00011 :0x3 4K+64B 4160 1556285242Sachim00100 :0x4 4K+128B 4224 1557285242Sachim 1558285242Sachim11000 :0x18 512+8B 520 1559285242Sachim11001 :0x19 520+8B 528 1560285242Sachim11010 :0x1A 4K+8B 4104 1561285242Sachim11011 :0x1B 4K+64B+8B 4168 1562285242Sachim11100 :0x1C 4K+128B+8B 4232 1563285242Sachim 1564285242Sachim*/ 1565285242Sachim 1566285242Sachim#define agsaEncryptSectorSize512 0 1567285242Sachim/* define agsaEncryptSectorSize520 1 Not supported */ 1568285242Sachim#define agsaEncryptSectorSize4096 2 1569285242Sachim#define agsaEncryptSectorSize4160 3 1570285242Sachim#define agsaEncryptSectorSize4224 4 1571285242Sachim 1572285242Sachim#define agsaEncryptDIFSectorSize520 (agsaEncryptSectorSize512 | 0x18) 1573285242Sachim#define agsaEncryptDIFSectorSize528 ( 0x19) 1574285242Sachim#define agsaEncryptDIFSectorSize4104 (agsaEncryptSectorSize4096 | 0x18) 1575285242Sachim#define agsaEncryptDIFSectorSize4168 (agsaEncryptSectorSize4160 | 0x18) 1576285242Sachim#define agsaEncryptDIFSectorSize4232 (agsaEncryptSectorSize4224 | 0x18) 1577285242Sachim 1578285242Sachim 1579285242Sachim#define AGSA_ENCRYPT_STORE_NVRAM 1 1580285242Sachim 1581285242Sachim/************************************************************ 1582285242Sachim* ossaHwCB Mode page event definitions 1583285242Sachim************************************************************/ 1584285242Sachim#define agsaModePageGet 1 1585285242Sachim#define agsaModePageSet 2 1586285242Sachim 1587285242Sachim/************************************************************ 1588285242Sachim* saSgpio() SGPIO Function and Register type 1589285242Sachim************************************************************/ 1590285242Sachim#define AGSA_READ_SGPIO_REGISTER 0x02 1591285242Sachim#define AGSA_WRITE_SGPIO_REGISTER 0x82 1592285242Sachim 1593285242Sachim#define AGSA_SGPIO_CONFIG_REG 0x0 1594285242Sachim#define AGSA_SGPIO_DRIVE_BY_DRIVE_RECEIVE_REG 0x1 1595285242Sachim#define AGSA_SGPIO_GENERAL_PURPOSE_RECEIVE_REG 0x2 1596285242Sachim#define AGSA_SGPIO_DRIVE_BY_DRIVE_TRANSMIT_REG 0x3 1597285242Sachim#define AGSA_SGPIO_GENERAL_PURPOSE_TRANSMIT_REG 0x4 1598285242Sachim 1599285242Sachim/************************************************************ 1600285242Sachim* ossaSGpioCB() Function result 1601285242Sachim************************************************************/ 1602285242Sachim#define OSSA_SGPIO_COMMAND_SUCCESS 0x00 1603285242Sachim#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE 0x01 1604285242Sachim#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE 0x02 1605285242Sachim#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_INDEX 0x03 1606285242Sachim#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_COUNT 0x04 1607285242Sachim#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_REG_TYPE 0x05 1608285242Sachim#define OSSA_SGPIO_CMD_ERROR_WRONG_FUNCTION 0x06 1609285242Sachim#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE_REG_INDEX 0x19 1610285242Sachim#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE_REG_CNT 0x81 1611285242Sachim#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE_REG_INDEX 0x1A 1612285242Sachim#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE_REG_COUNT 0x82 1613285242Sachim#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_INDEX_REG_COUNT 0x83 1614285242Sachim#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_REG_TYPE_REG_INDEX 0x1D 1615285242Sachim#define OSSA_SGPIO_CMD_ERROR_WRONG_ALL_HEADER_PARAMS 0x9D 1616285242Sachim 1617285242Sachim#define OSSA_SGPIO_MAX_READ_DATA_COUNT 0x0D 1618285242Sachim#define OSSA_SGPIO_MAX_WRITE_DATA_COUNT 0x0C 1619285242Sachim 1620285242Sachim/************************************************************ 1621285242Sachim* ossaGetDFEDataCB() status 1622285242Sachim************************************************************/ 1623285242Sachim#define OSSA_DFE_MPI_IO_SUCCESS 0x0000 1624285242Sachim#define OSSA_DFE_DATA_OVERFLOW 0x0002 1625285242Sachim#define OSSA_DFE_MPI_ERR_RESOURCE_UNAVAILABLE 0x1004 1626285242Sachim#define OSSA_DFE_CHANNEL_DOWN 0x100E 1627285242Sachim#define OSSA_DFE_MEASUREMENT_IN_PROGRESS 0x100F 1628285242Sachim#define OSSA_DFE_CHANNEL_INVALID 0x1010 1629285242Sachim#define OSSA_DFE_DMA_FAILURE 0x1011 1630285242Sachim 1631285242Sachim/************************************************************************************ 1632285242Sachim * * 1633285242Sachim * Constants defined for OS Layer ends * 1634285242Sachim * * 1635285242Sachim ************************************************************************************/ 1636285242Sachim 1637285242Sachim/************************************************************************************ 1638285242Sachim * * 1639285242Sachim * Data Structures Defined for LL API start * 1640285242Sachim * * 1641285242Sachim ************************************************************************************/ 1642285242Sachim/** \brief data structure stores OS specific and LL specific context 1643285242Sachim * 1644285242Sachim * The agsaContext_t data structure contains two generic pointers, 1645285242Sachim * also known as handles, which are used to store OS Layer-specific and 1646285242Sachim * LL Layer-specific contexts. Only the handle specific to a layer can 1647285242Sachim * be modified by the layer. The other layer's handle must be returned 1648285242Sachim * unmodified when communicating between the layers. 1649285242Sachim 1650285242Sachim * A layer's handle is typically typecast to an instance of a layer-specific 1651285242Sachim * data structure. The layer can use its handle to point to any data type 1652285242Sachim * that is to be associated with a function call. A handle provides a way 1653285242Sachim * to uniquely identify responses when multiple calls to the same function 1654285242Sachim * are necessary. 1655285242Sachim * 1656285242Sachim */ 1657285242Sachimtypedef struct agsaContext_s 1658285242Sachim{ 1659285242Sachim void *osData; /**< Pointer-sized value used internally by the OS Layer */ 1660285242Sachim void *sdkData; /**< Pointer-sized value used internally by the LL Layer */ 1661285242Sachim} agsaContext_t; 1662285242Sachim 1663285242Sachim/** \brief hold points to global data strutures used by the LL and OS Layers 1664285242Sachim * 1665285242Sachim * The agsaRoot_t data structure is used to hold pointer-sized values for 1666285242Sachim * internal use by the LL and OS Layers. It is intended that the 1667285242Sachim * sdkData element of the agsaRoot_t data structure be used to 1668285242Sachim * identify an instance of the hardware context. The sdkData 1669285242Sachim * element is set by the LL Layer in the saHwInitialize() 1670285242Sachim * function and returned to the OS Layer in the agsaRoot_t data 1671285242Sachim * structure 1672285242Sachim */ 1673285242Sachimtypedef agsaContext_t agsaRoot_t; 1674285242Sachim 1675285242Sachim/** \brief holds the pointers to the device data structure used by the LL and OS Layers 1676285242Sachim * 1677285242Sachim * The agsaDevHandle_t data structure is the device instance handle. 1678285242Sachim * It holds pointer-sized values used internally by each of the LL and 1679285242Sachim * OS Layers. It is intended that the agsaDevHandle_t data 1680285242Sachim * structure be used to identify a specific device instance. A 1681285242Sachim * device instance is uniquely identified by its device handle. 1682285242Sachim */ 1683285242Sachimtypedef agsaContext_t agsaDevHandle_t; 1684285242Sachim 1685285242Sachim/** \brief holds the pointers to the port data structure used by the LL and 1686285242Sachim * OS Layers 1687285242Sachim * 1688285242Sachim * The agsaPortContext_t data structure is used to describe an instance of 1689285242Sachim * SAS port or SATA port. It holds pointer-sized values used 1690285242Sachim * internally by each of the LL and OS Layers. 1691285242Sachim * 1692285242Sachim * When connected to other SAS end-devices or expanders, each instance of 1693285242Sachim * agsaPortContext_t represents a SAS local narrow-port or 1694285242Sachim * wide-port. 1695285242Sachim * 1696285242Sachim * When connected to SATA device, each instance of agsaPortContext_t 1697285242Sachim * represents a local SATA port. 1698285242Sachim * 1699285242Sachim */ 1700285242Sachimtypedef agsaContext_t agsaPortContext_t; 1701285242Sachim 1702285242Sachim/** \brief data structure pointer to IO request structure 1703285242Sachim * 1704285242Sachim * It is intended that the agsaIORequest_t structure be used to 1705285242Sachim * uniquely identify each I/O Request for either target or 1706285242Sachim * initiator. The OS Layer is responsible for allocating and 1707285242Sachim * managing agsaIORequest_t structures. The LL Layer uses each 1708285242Sachim * structure only between calls to: saSSPStart() and 1709285242Sachim * ossaSSPCompleted(), saSATAStart() and ossaSATACompleted(), 1710285242Sachim * saSMPStart() and ossaSMPCompleted() 1711285242Sachim * 1712285242Sachim */ 1713285242Sachimtypedef agsaContext_t agsaIORequest_t; 1714285242Sachim 1715285242Sachim/** \brief handle to access frame 1716285242Sachim * 1717285242Sachim * This data structure is the handle to access frame 1718285242Sachim */ 1719285242Sachimtypedef void *agsaFrameHandle_t; 1720285242Sachim 1721285242Sachim/** \brief describe a SAS ReCofiguration structure in the SAS/SATA hardware 1722285242Sachim * 1723285242Sachim * Describe a SAS ReConfiguration in the SAS/SATA hardware 1724285242Sachim * 1725285242Sachim */ 1726285242Sachimtypedef struct agsaSASReconfig_s { 1727285242Sachim bit32 flags; /* flag to indicate a change to the default parameter 1728285242Sachim bit31-30:reserved 1729285242Sachim bit29: a change to the default SAS/SATA ports is requested 1730285242Sachim bit28: the OPEN REJECT (RETRY) in command phase is requested 1731285242Sachim bit27: the OPEN REJECT (RETRY) in data phase is requested 1732285242Sachim bit26: REJECT will be mapped into OPEN REJECT 1733285242Sachim bit25: delay for SATA Head-of-Line blocking detection timeout 1734285242Sachim bit24-00:reserved */ 1735285242Sachim bit16 reserved0; /* reserved */ 1736285242Sachim bit8 reserved1; /* reserved */ 1737285242Sachim bit8 maxPorts; /* This field is valid if bit 29 of the flags field is set to 1 */ 1738285242Sachim bit16 openRejectRetriesCmd; /* This field is valid if bit 28 of the flags field is set to 1 */ 1739285242Sachim bit16 openRejectRetriesData; /* This field is valid if bit 27 of the flags field is set to 1.*/ 1740285242Sachim bit16 reserved2; /* reserved */ 1741285242Sachim bit16 sataHolTmo; /* This field is valid if bit 25 of the flags field is set to 1 */ 1742285242Sachim} agsaSASReconfig_t; 1743285242Sachim 1744285242Sachim/** \brief describe a Phy Analog Setup registers for a Controller in the SAS/SATA hardware 1745285242Sachim * 1746285242Sachim * Describe a Phy Analog Setup registers for a controller in the SAS/SATA hardware 1747285242Sachim * 1748285242Sachim */ 1749285242Sachimtypedef struct agsaPhyAnalogSetupRegisters_s 1750285242Sachim{ 1751285242Sachim bit32 spaRegister0; 1752285242Sachim bit32 spaRegister1; 1753285242Sachim bit32 spaRegister2; 1754285242Sachim bit32 spaRegister3; 1755285242Sachim bit32 spaRegister4; 1756285242Sachim bit32 spaRegister5; 1757285242Sachim bit32 spaRegister6; 1758285242Sachim bit32 spaRegister7; 1759285242Sachim bit32 spaRegister8; 1760285242Sachim bit32 spaRegister9; 1761285242Sachim} agsaPhyAnalogSetupRegisters_t; 1762285242Sachim 1763285242Sachim#define MAX_INDEX 10 1764285242Sachim 1765285242Sachim/** \brief 1766285242Sachim * 1767285242Sachim */ 1768285242Sachimtypedef struct agsaPhyAnalogSetupTable_s 1769285242Sachim{ 1770285242Sachim agsaPhyAnalogSetupRegisters_t phyAnalogSetupRegisters[MAX_INDEX]; 1771285242Sachim} agsaPhyAnalogSetupTable_t; 1772285242Sachim 1773285242Sachim/** \brief describe a Phy Analog Setting 1774285242Sachim * 1775285242Sachim * Describe a Phy Analog Setup registers for a controller in the SAS/SATA hardware 1776285242Sachim * 1777285242Sachim */ 1778285242Sachimtypedef struct agsaPhyAnalogSettingsPage_s 1779285242Sachim{ 1780285242Sachim bit32 Dword0; 1781285242Sachim bit32 Dword1; 1782285242Sachim bit32 Dword2; 1783285242Sachim bit32 Dword3; 1784285242Sachim bit32 Dword4; 1785285242Sachim bit32 Dword5; 1786285242Sachim bit32 Dword6; 1787285242Sachim bit32 Dword7; 1788285242Sachim bit32 Dword8; 1789285242Sachim bit32 Dword9; 1790285242Sachim} agsaPhyAnalogSettingsPage_t; 1791285242Sachim 1792285242Sachim 1793285242Sachim/** \brief describe a Open reject retry backoff threshold page 1794285242Sachim * 1795285242Sachim * Describe a Open reject retry backoff threshold registers in the SAS/SATA hardware 1796285242Sachim * 1797285242Sachim */ 1798285242Sachimtypedef struct agsaSASPhyOpenRejectRetryBackOffThresholdPage_s 1799285242Sachim{ 1800285242Sachim bit32 Dword0; 1801285242Sachim bit32 Dword1; 1802285242Sachim bit32 Dword2; 1803285242Sachim bit32 Dword3; 1804285242Sachim} agsaSASPhyOpenRejectRetryBackOffThresholdPage_t; 1805285242Sachim 1806285242Sachim/** \brief describe a Phy Rate Control 1807285242Sachim * 4.56 agsaPhyRateControlPage_t 1808285242Sachim * Description 1809285242Sachim * This profile page is used to read or set several rate control 1810285242Sachim * parameters. The page code for this profile page is 0x07. This page can 1811285242Sachim * be READ by issuing saGetPhyProfile(). It can be read anytime and there 1812285242Sachim * is no need to quiesce the I/O to the controller. 1813285242Sachim * Related parameters can be modified by issuing saSetPhyProfile() before 1814285242Sachim * calling saPhyStart() to the PHY. 1815285242Sachim * Note: This page is applicable only to the SPCv controller. 1816285242Sachim * Usage 1817285242Sachim * Initiator and target. 1818285242Sachim */ 1819285242Sachimtypedef struct agsaPhyRateControlPage_s 1820285242Sachim{ 1821285242Sachim bit32 Dword0; 1822285242Sachim bit32 Dword1; 1823285242Sachim bit32 Dword2; 1824285242Sachim} agsaPhyRateControlPage_t; 1825285242Sachim 1826285242Sachim/** 1827285242Sachim * Dword0 Bits 0-11: ALIGN_RATE(ALNR). Align Insertion rate is 2 in every 1828285242Sachim * ALIGN_RATE+1 DWord. The default value results in the standard compliant 1829285242Sachim * value of 2/256. This rate applies to out of connection, SMP and SSP 1830285242Sachim * connections. The default value is 0x0ff. Other bits are reserved. 1831285242Sachim * Dword1 Bits 0 -11: STP_ALIGN_RATE(STPALNR) Align Insertion rate is 2 in 1832285242Sachim * every ALIGN_RATE+1 DWords. Default value results in standard compliant 1833285242Sachim * value of 2/256. This rate applies to out of STP connections. The default 1834285242Sachim * value is 0x0ff. Other bits are reserved. 1835285242Sachim * Dword2 Bits 0-7: SSP_FRAME_RATE(SSPFRMR) The number of idle DWords 1836285242Sachim * between each SSP frame. 0 means no idle cycles. The default value is 1837285242Sachim * 0x0. Other bits are reserved. 1838285242Sachim**/ 1839285242Sachim 1840285242Sachim/** \brief describe a Register Dump information for a Controller in the SAS/SATA hardware 1841285242Sachim * 1842285242Sachim * Describe a register dump information for a controller in the SAS/SATA hardware 1843285242Sachim * 1844285242Sachim */ 1845285242Sachimtypedef struct agsaRegDumpInfo_s 1846285242Sachim{ 1847285242Sachim bit8 regDumpSrc; 1848285242Sachim bit8 regDumpNum; 1849285242Sachim bit8 reserved[2]; 1850285242Sachim bit32 regDumpOffset; 1851285242Sachim bit32 directLen; 1852285242Sachim void *directData; 1853285242Sachim bit32 indirectAddrUpper32; 1854285242Sachim bit32 indirectAddrLower32; 1855285242Sachim bit32 indirectLen; 1856285242Sachim} agsaRegDumpInfo_t; 1857285242Sachim 1858285242Sachim/* 1859285242Sachim7 : SPC GSM register at [MEMBASE-III SHIFT = 0x00_0000] 1860285242Sachim8 : SPC GSM register at [MEMBASE-III SHIFT = 0x05_0000] 1861285242Sachim9 : BDMA GSM register at [MEMBASE-III SHIFT = 0x01_0000] 1862285242Sachim10: PCIe APP GSM register at [MEMBASE-III SHIFT = 0x01_0000] 1863285242Sachim11: PCIe PHY GSM register at [MEMBASE-III SHIFT = 0x01_0000] 1864285242Sachim12: PCIe CORE GSM register at [MEMBASE-III SHIFT = 0x01_0000] 1865285242Sachim13: OSSP GSM register at [MEMBASE-III SHIFT = 0x02_0000] 1866285242Sachim14: SSPA GSM register at [MEMBASE-III SHIFT = 0x03_0000] 1867285242Sachim15: SSPA GSM register at [MEMBASE-III SHIFT = 0x04_0000] 1868285242Sachim16: HSST GSM register at [MEMBASE-III SHIFT = 0x02_0000] 1869285242Sachim17: LMS_DSS(A) GSM register at [MEMBASE-III SHIFT = 0x03_0000] 1870285242Sachim18: SSPL_6G GSM register at [MEMBASE-III SHIFT = 0x03_0000] 1871285242Sachim19: HSST(A) GSM register at [MEMBASE-III SHIFT = 0x03_0000] 1872285242Sachim20: LMS_DSS(A) GSM register at [MEMBASE-III SHIFT = 0x04_0000] 1873285242Sachim21: SSPL_6G GSM register at [MEMBASE-III SHIFT = 0x04_0000] 1874285242Sachim22: HSST(A) GSM register at [MEMBASE-III SHIFT = 0x04_0000] 1875285242Sachim23: MBIC IOP GSM register at [MEMBASE-III SHIFT = 0x06_0000] 1876285242Sachim24: MBIC AAP1 GSM register at [MEMBASE-III SHIFT = 0x07_0000] 1877285242Sachim25: SPBC GSM register at [MEMBASE-III SHIFT = 0x09_0000] 1878285242Sachim26: GSM GSM register at [MEMBASE-III SHIFT = 0x70_0000] 1879285242Sachim*/ 1880285242Sachim 1881285242Sachim#define TYPE_GSM_SPACE 1 1882285242Sachim#define TYPE_QUEUE 2 1883285242Sachim#define TYPE_FATAL 3 1884285242Sachim#define TYPE_NON_FATAL 4 1885285242Sachim#define TYPE_INBOUND_QUEUE 5 1886285242Sachim#define TYPE_OUTBOUND_QUEUE 6 1887285242Sachim 1888285242Sachim 1889285242Sachim#define BAR_SHIFT_GSM_OFFSET 0x400000 1890285242Sachim 1891285242Sachim#define ONE_MEGABYTE 0x100000 1892285242Sachim#define SIXTYFOURKBYTE (1024 * 64) 1893285242Sachim 1894285242Sachim 1895285242Sachim 1896285242Sachim#define TYPE_INBOUND 1 1897285242Sachim#define TYPE_OUTBOUND 2 1898285242Sachim 1899285242Sachimtypedef struct 1900285242Sachim{ 1901285242Sachim bit32 DataType; 1902285242Sachim union 1903285242Sachim { 1904285242Sachim struct 1905285242Sachim { 1906285242Sachim bit32 directLen; 1907285242Sachim bit32 directOffset; 1908285242Sachim bit32 readLen; 1909285242Sachim void *directData; 1910285242Sachim }gsmBuf; 1911285242Sachim 1912285242Sachim struct 1913285242Sachim { 1914285242Sachim bit16 queueType; 1915285242Sachim bit16 queueIndex; 1916285242Sachim bit32 directLen; 1917285242Sachim void *directData; 1918285242Sachim }queueBuf; 1919285242Sachim 1920285242Sachim struct 1921285242Sachim { 1922285242Sachim bit32 directLen; 1923285242Sachim bit32 directOffset; 1924285242Sachim bit32 readLen; 1925285242Sachim void *directData; 1926285242Sachim }dataBuf; 1927285242Sachim } BufferType; 1928285242Sachim} agsaForensicData_t; 1929285242Sachim 1930285242Sachim/** \brief describe a NVMData for a Controller in the SAS/SATA hardware 1931285242Sachim * 1932285242Sachim * Describe a NVMData for a controller in the SAS/SATA hardware 1933285242Sachim * 1934285242Sachim */ 1935285242Sachimtypedef struct agsaNVMDData_s 1936285242Sachim{ 1937285242Sachim bit32 indirectPayload :1; 1938285242Sachim bit32 reserved :7; 1939285242Sachim bit32 TWIDeviceAddress :8; 1940285242Sachim bit32 TWIBusNumber :4; 1941285242Sachim bit32 TWIDevicePageSize :4; 1942285242Sachim bit32 TWIDeviceAddressSize :4; 1943285242Sachim bit32 NVMDevice :4; 1944285242Sachim bit32 directLen :8; 1945285242Sachim bit32 dataOffsetAddress :24; 1946285242Sachim void *directData; 1947285242Sachim bit32 indirectAddrUpper32; 1948285242Sachim bit32 indirectAddrLower32; 1949285242Sachim bit32 indirectLen; 1950285242Sachim bit32 signature; 1951285242Sachim} agsaNVMDData_t; 1952285242Sachim 1953285242Sachim 1954285242Sachim/* status of ossaPCIeDiagExecuteCB() is shared with ossaSASDiagExecuteCB() */ 1955285242Sachim#define OSSA_PCIE_DIAG_SUCCESS 0x0000 1956285242Sachim#define OSSA_PCIE_DIAG_INVALID_COMMAND 0x0001 1957285242Sachim#define OSSA_PCIE_DIAG_INTERNAL_FAILURE 0x0002 1958285242Sachim#define OSSA_PCIE_DIAG_INVALID_CMD_TYPE 0x1006 1959285242Sachim#define OSSA_PCIE_DIAG_INVALID_CMD_DESC 0x1007 1960285242Sachim#define OSSA_PCIE_DIAG_INVALID_PCIE_ADDR 0x1008 1961285242Sachim#define OSSA_PCIE_DIAG_INVALID_BLOCK_SIZE 0x1009 1962285242Sachim#define OSSA_PCIE_DIAG_LENGTH_NOT_BLOCK_SIZE_ALIGNED 0x100A 1963285242Sachim#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_MISMATCH 0x3000 1964285242Sachim#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH 0x3001 1965285242Sachim#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH 0x3002 1966285242Sachim#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_CRC_MISMATCH 0x3003 1967285242Sachim#define OSSA_PCIE_DIAG_MPI_ERR_INVALID_LENGTH 0x0042 1968285242Sachim#define OSSA_PCIE_DIAG_MPI_ERR_IO_RESOURCE_UNAVAILABLE 0x1004 1969285242Sachim#define OSSA_PCIE_DIAG_MPI_ERR_CONTROLLER_NOT_IDLE 0x1005 1970285242Sachim 1971285242Sachim 1972285242Sachimtypedef struct agsaPCIeDiagExecute_s 1973285242Sachim{ 1974285242Sachim bit32 command; 1975285242Sachim bit32 flags; 1976285242Sachim bit16 initialIOSeed; 1977285242Sachim bit16 reserved; 1978285242Sachim bit32 rdAddrLower; 1979285242Sachim bit32 rdAddrUpper; 1980285242Sachim bit32 wrAddrLower; 1981285242Sachim bit32 wrAddrUpper; 1982285242Sachim bit32 len; 1983285242Sachim bit32 pattern; 1984285242Sachim bit8 udtArray[6]; 1985285242Sachim bit8 udrtArray[6]; 1986285242Sachim} agsaPCIeDiagExecute_t; 1987285242Sachim 1988285242Sachim 1989285242Sachim/** \brief agsaPCIeDiagResponse_t 1990285242Sachim * 1991285242Sachim * status of ossaPCIeDiagExecuteCB() 1992285242Sachim * The agsaPCIeDiagResponse_t structure is a parameter passed to 1993285242Sachim * ossaPCIeDiagExecuteCB() 1994285242Sachim * to contain a PCIe Diagnostic command response. 1995285242Sachim */ 1996285242Sachim 1997285242Sachimtypedef struct agsaPCIeDiagResponse_s { 1998285242Sachim bit32 ERR_BLKH; 1999285242Sachim bit32 ERR_BLKL; 2000285242Sachim bit32 DWord8; 2001285242Sachim bit32 DWord9; 2002285242Sachim bit32 DWord10; 2003285242Sachim bit32 DWord11; 2004285242Sachim bit32 DIF_ERR; 2005285242Sachim} agsaPCIeDiagResponse_t; 2006285242Sachim 2007285242Sachim 2008285242Sachim/** \brief describe a fatal error information for a Controller in the SAS/SATA hardware 2009285242Sachim * 2010285242Sachim * Describe a fatal error information for a controller in the SAS/SATA hardware 2011285242Sachim * 2012285242Sachim */ 2013285242Sachimtypedef struct agsaFatalErrorInfo_s 2014285242Sachim{ 2015285242Sachim bit32 errorInfo0; 2016285242Sachim bit32 errorInfo1; 2017285242Sachim bit32 errorInfo2; 2018285242Sachim bit32 errorInfo3; 2019285242Sachim bit32 regDumpBusBaseNum0; 2020285242Sachim bit32 regDumpOffset0; 2021285242Sachim bit32 regDumpLen0; 2022285242Sachim bit32 regDumpBusBaseNum1; 2023285242Sachim bit32 regDumpOffset1; 2024285242Sachim bit32 regDumpLen1; 2025285242Sachim} agsaFatalErrorInfo_t; 2026285242Sachim 2027285242Sachim/** \brief describe a information for a Event in the SAS/SATA hardware 2028285242Sachim * 2029285242Sachim * Describe a general information for a Event in the SAS/SATA hardware 2030285242Sachim * 2031285242Sachim */ 2032285242Sachimtypedef struct agsaEventSource_s 2033285242Sachim{ 2034285242Sachim agsaPortContext_t *agPortContext; 2035285242Sachim bit32 event; 2036285242Sachim bit32 param; 2037285242Sachim} agsaEventSource_t; 2038285242Sachim 2039285242Sachim/** \brief describe a information for a Controller in the SAS/SATA hardware 2040285242Sachim * 2041285242Sachim * Describe a general information for a controller in the SAS/SATA hardware 2042285242Sachim * 2043285242Sachim */ 2044285242Sachimtypedef struct agsaControllerInfo_s 2045285242Sachim{ 2046285242Sachim bit32 signature; /* coherent controller information */ 2047285242Sachim bit32 fwInterfaceRev; /* host and controller interface version */ 2048285242Sachim bit32 hwRevision; /* controller HW Revision number */ 2049285242Sachim bit32 fwRevision; /* controller FW Revision number */ 2050285242Sachim bit32 ilaRevision; /* controller ILA Revision number */ 2051285242Sachim bit32 maxPendingIO; /* maximum number of outstanding I/Os supported */ 2052285242Sachim bit32 maxDevices; /* Maximum Device Supported by controller */ 2053285242Sachim bit32 maxSgElements; /* maximum number of SG elements supported */ 2054285242Sachim bit32 queueSupport; /* maximum number of IQ and OQ supported 2055285242Sachim bit31-19 reserved 2056285242Sachim bit18 interrupt coalescing 2057285242Sachim bit17 reserved 2058285242Sachim bit16 high priority IQ supported 2059285242Sachim bit15-08 maximum number of OQ 2060285242Sachim bit07-00 maximum number of IQ */ 2061285242Sachim bit8 phyCount; /* number of phy available in the controller */ 2062285242Sachim bit8 controllerSetting;/* Controller setting 2063285242Sachim bit07-04 reserved 2064285242Sachim bit03-00 HDA setting */ 2065285242Sachim bit8 PCILinkRate; /* PCI generation 1/2/3 2.5g/5g/8g */ 2066285242Sachim bit8 PCIWidth; /* PCI number of lanes */ 2067285242Sachim bit32 sasSpecsSupport; /* the supported SAS spec. */ 2068285242Sachim bit32 sdkInterfaceRev; /* sdk interface reversion */ 2069285242Sachim bit32 sdkRevision; /* sdk reversion */ 2070285242Sachim} agsaControllerInfo_t; 2071285242Sachim 2072285242Sachim/** \brief describe a status for a Controller in the SAS/SATA hardware 2073285242Sachim * 2074285242Sachim * Describe a general status for a controller in the SAS/SATA hardware 2075285242Sachim * 2076285242Sachim */ 2077285242Sachimtypedef struct agsaControllerStatus_s 2078285242Sachim{ 2079285242Sachim agsaFatalErrorInfo_t fatalErrorInfo; /* fatal error information */ 2080285242Sachim bit32 interfaceState; /* host and controller interface state 2081285242Sachim bit02-00 state of host and controller 2082285242Sachim bit16-03 reserved 2083285242Sachim bit31-16 detail of error based on error state */ 2084285242Sachim bit32 iqFreezeState0; /* freeze state of 1st set of IQ */ 2085285242Sachim bit32 iqFreezeState1; /* freeze state of 2nd set of IQ */ 2086285242Sachim bit32 tickCount0; /* tick count in second for internal CPU-0 */ 2087285242Sachim bit32 tickCount1; /* tick count in second for internal CPU-1 */ 2088285242Sachim bit32 tickCount2; /* tick count in second for internal CPU-2 */ 2089285242Sachim bit32 phyStatus[8]; /* status of phy 0 to phy 15 */ 2090285242Sachim bit32 recoverableErrorInfo[8]; /* controller specific recoverable error information */ 2091285242Sachim bit32 bootStatus; 2092285242Sachim bit16 bootComponentState[8]; 2093285242Sachim 2094285242Sachim} agsaControllerStatus_t; 2095285242Sachim 2096285242Sachim/** \brief describe a GPIO Event Setup Infomation in the SAS/SATA hardware 2097285242Sachim * 2098285242Sachim * Describe a configuration for a GPIO Event Setup Infomation in the SAS/SATA hardware 2099285242Sachim * 2100285242Sachim */ 2101285242Sachimtypedef struct agsaGpioEventSetupInfo_s 2102285242Sachim{ 2103285242Sachim bit32 gpioPinMask; 2104285242Sachim bit32 gpioEventLevel; 2105285242Sachim bit32 gpioEventRisingEdge; 2106285242Sachim bit32 gpioEventFallingEdge; 2107285242Sachim} agsaGpioEventSetupInfo_t; 2108285242Sachim 2109285242Sachim/** \brief describe a GPIO Pin Setup Infomation in the SAS/SATA hardware 2110285242Sachim * 2111285242Sachim * Describe a configuration for a GPIO Pin Setup Infomation in the SAS/SATA hardware 2112285242Sachim * 2113285242Sachim */ 2114285242Sachimtypedef struct agsaGpioPinSetupInfo_t 2115285242Sachim{ 2116285242Sachim bit32 gpioPinMask; 2117285242Sachim bit32 gpioInputEnabled; 2118285242Sachim bit32 gpioTypePart1; 2119285242Sachim bit32 gpioTypePart2; 2120285242Sachim} agsaGpioPinSetupInfo_t; 2121285242Sachim 2122285242Sachim/** \brief describe a serial GPIO operation in the SAS/SATA hardware 2123285242Sachim * 2124285242Sachim * Describe a configuration for a GPIO write Setup Infomation in the SAS/SATA hardware 2125285242Sachim * 2126285242Sachim */ 2127285242Sachimtypedef struct agsaGpioWriteSetupInfo_s 2128285242Sachim{ 2129285242Sachim bit32 gpioWritemask; 2130285242Sachim bit32 gpioWriteVal; 2131285242Sachim}agsaGpioWriteSetupInfo_t; 2132285242Sachim 2133285242Sachim/** \brief describe a GPIO Read Infomation in the SAS/SATA hardware 2134285242Sachim * 2135285242Sachim * Describe a configuration for a GPIO read Infomation in the SAS/SATA hardware 2136285242Sachim * 2137285242Sachim */ 2138285242Sachimtypedef struct agsaGpioReadInfo_s 2139285242Sachim{ 2140285242Sachim bit32 gpioReadValue; 2141285242Sachim bit32 gpioInputEnabled; /* GPIOIE */ 2142285242Sachim bit32 gpioEventLevelChangePart1; /* GPIEVCHANGE (pins 11-0) */ 2143285242Sachim bit32 gpioEventLevelChangePart2; /* GPIEVCHANGE (pins 23-20) */ 2144285242Sachim bit32 gpioEventRisingEdgePart1; /* GPIEVRISE (pins 11-0) */ 2145285242Sachim bit32 gpioEventRisingEdgePart2; /* GPIEVRISE (pins 23-20) */ 2146285242Sachim bit32 gpioEventFallingEdgePart1; /* GPIEVALL (pins 11-0) */ 2147285242Sachim bit32 gpioEventFallingEdgePart2; /* GPIEVALL (pins 23-20) */ 2148285242Sachim}agsaGpioReadInfo_t; 2149285242Sachim 2150285242Sachim/** \brief describe a serial GPIO request and response in the SAS/SATA hardware 2151285242Sachim * 2152285242Sachim * Describe the fields required for serial GPIO request and response in the SAS/SATA hardware 2153285242Sachim * 2154285242Sachim */ 2155285242Sachimtypedef struct agsaSGpioReqResponse_s 2156285242Sachim{ 2157285242Sachim bit8 smpFrameType; /* 0x40 for request, 0x41 for response*/ 2158285242Sachim bit8 function; /* 0x02 for read, 0x82 for write */ 2159285242Sachim bit8 registerType; /* used only in request */ 2160285242Sachim bit8 registerIndex; /* used only in request */ 2161285242Sachim bit8 registerCount; /* used only in request */ 2162285242Sachim bit8 functionResult; /* used only in response */ 2163285242Sachim bit32 readWriteData[OSSA_SGPIO_MAX_READ_DATA_COUNT]; /* write data for request; read data for response */ 2164285242Sachim} agsaSGpioReqResponse_t; 2165285242Sachim 2166285242Sachim 2167285242Sachim/** \brief describe a serial GPIO operation response in the SAS/SATA hardware 2168285242Sachim * 2169285242Sachim * Describe the fields required for serial GPIO operations response in the SAS/SATA hardware 2170285242Sachim * 2171285242Sachim */ 2172285242Sachimtypedef struct agsaSGpioCfg0 2173285242Sachim{ 2174285242Sachim bit8 reserved1; 2175285242Sachim bit8 version:4; 2176285242Sachim bit8 reserved2:4; 2177285242Sachim bit8 gpRegisterCount:4; 2178285242Sachim bit8 cfgRegisterCount:3; 2179285242Sachim bit8 gpioEnable:1; 2180285242Sachim bit8 supportedDriveCount; 2181285242Sachim} agsaSGpioCfg0_t; 2182285242Sachim 2183285242Sachim/** \brief SGPIO configuration register 1 2184285242Sachim * 2185285242Sachim * These fields constitute SGPIO configuration register 1, as defined by SFF-8485 spec 2186285242Sachim * 2187285242Sachim */ 2188285242Sachimtypedef struct agsaSGpioCfg1{ 2189285242Sachim bit8 reserved; 2190285242Sachim bit8 blinkGenA:4; 2191285242Sachim bit8 blinkGenB:4; 2192285242Sachim bit8 maxActOn:4; 2193285242Sachim bit8 forceActOff:4; 2194285242Sachim bit8 stretchActOn:4; 2195285242Sachim bit8 stretchActOff:4; 2196285242Sachim} agsaSGpioCfg1_t; 2197285242Sachim 2198285242Sachim/** \brief describe a configuration for a PHY in the SAS/SATA hardware 2199285242Sachim * 2200285242Sachim * Describe a configuration for a PHY in the SAS/SATA hardware 2201285242Sachim * 2202285242Sachim */ 2203285242Sachimtypedef struct agsaPhyConfig_s 2204285242Sachim{ 2205285242Sachim bit32 phyProperties; 2206285242Sachim /**< b31-b8 reserved */ 2207285242Sachim /**< b16-b19 SSC Disable */ 2208285242Sachim /**< b15-b8 phy analog setup index */ 2209285242Sachim /**< b7 phy analog setup enable */ 2210285242Sachim /**< b6 Control spin up hold */ 2211285242Sachim /**< b5-b4 SAS/SATA mode, bit4 - SAS, bit5 - SATA, 11b - Auto mode */ 2212285242Sachim /**< b3-b0 Max. Link Rate, bit0 - 1.5Gb/s, bit1 - 3.0Gb/s, 2213285242Sachim bit2 - 6.0Gb/s, bit3 - reserved */ 2214285242Sachim} agsaPhyConfig_t; 2215285242Sachim 2216285242Sachim 2217285242Sachim/** \brief Structure is used as a parameter passed in saLocalPhyControlCB() to describe the error counter 2218285242Sachim * 2219285242Sachim * Description 2220285242Sachim * This profile page is used to read or set the SNW-3 PHY capabilities of a 2221285242Sachim * SAS PHY. This page can be read by calling saGetPhyProfile(). It can be 2222285242Sachim * read anytime and there is no need to quiesce he I/O to the controller. 2223285242Sachim * The format of the 32-bit SNW3 is the same as defined in the SAS 2 2224285242Sachim * specification. 2225285242Sachim * Local SNW3 can be modified by calling saSetPhyProfile() before 2226285242Sachim * saPhyStart() to the PHY. REQUESTED LOGICAL LINK RATE is reserved. 2227285242Sachim * The SPCv will calculate the PARITY field. 2228285242Sachim 2229285242Sachim * Note: This page is applicable only to the SPCv controller. 2230285242Sachim * Usage 2231285242Sachim * Initiator and target. 2232285242Sachim */ 2233285242Sachim 2234285242Sachimtypedef struct agsaPhySNW3Page_s 2235285242Sachim{ 2236285242Sachim bit32 LSNW3; 2237285242Sachim bit32 RSNW3; 2238285242Sachim} agsaPhySNW3Page_t; 2239285242Sachim 2240285242Sachim/** \brief structure describe error counters of a PHY in the SAS/SATA 2241285242Sachim * 2242285242Sachim * Structure is used as a parameter passed in saLocalPhyControlCB() 2243285242Sachim * to describe the error counter 2244285242Sachim * 2245285242Sachim */ 2246285242Sachimtypedef struct agsaPhyErrCounters_s 2247285242Sachim{ 2248285242Sachim bit32 invalidDword; /* Number of invalid dwords that have been 2249285242Sachim received outside of phy reset sequences.*/ 2250285242Sachim bit32 runningDisparityError; /* Number of dwords containing running disparity 2251285242Sachim errors that have been received outside of phy 2252285242Sachim reset sequences.*/ 2253285242Sachim bit32 lossOfDwordSynch; /* Number of times the phy has restarted the link 2254285242Sachim reset sequence because it lost dword synchronization.*/ 2255285242Sachim bit32 phyResetProblem; /* Number of times the phy did not obtain dword 2256285242Sachim synchronization during the final SAS speed 2257285242Sachim negotiation window.*/ 2258285242Sachim bit32 elasticityBufferOverflow; /* Number of times the phys receive elasticity 2259285242Sachim buffer has overflowed.*/ 2260285242Sachim bit32 receivedErrorPrimitive; /* Number of times the phy received an ERROR primitive */ 2261285242Sachim bit32 inboundCRCError; /* Number of inbound CRC Error */ 2262285242Sachim bit32 codeViolation; /* Number of code violation */ 2263285242Sachim} agsaPhyErrCounters_t; 2264285242Sachim 2265285242Sachim 2266285242Sachim/** \brief 2267285242Sachim * used in saGetPhyProfile 2268285242Sachim */ 2269285242Sachimtypedef struct agsaPhyErrCountersPage_s 2270285242Sachim{ 2271285242Sachim bit32 invalidDword; 2272285242Sachim bit32 runningDisparityError; 2273285242Sachim bit32 codeViolation; 2274285242Sachim bit32 lossOfDwordSynch; 2275285242Sachim bit32 phyResetProblem; 2276285242Sachim bit32 inboundCRCError; 2277285242Sachim} agsaPhyErrCountersPage_t; 2278285242Sachim 2279285242Sachim/** \brief structure describes bandwidth counters of a PHY in the SAS/SATA 2280285242Sachim * 2281285242Sachim * Structure is used as a parameter passed in saGetPhyProfile() 2282285242Sachim * to describe the error counter 2283285242Sachim * 2284285242Sachim */ 2285285242Sachim 2286285242Sachimtypedef struct agsaPhyBWCountersPage_s 2287285242Sachim{ 2288285242Sachim bit32 TXBWCounter; 2289285242Sachim bit32 RXBWCounter; 2290285242Sachim} agsaPhyBWCountersPage_t; 2291285242Sachim 2292285242Sachim 2293285242Sachim 2294285242Sachim/** \brief structure describe hardware configuration 2295285242Sachim * 2296285242Sachim * Structure is used as a parameter passed in saInitialize() to describe the 2297285242Sachim * configuration used during hardware initialization 2298285242Sachim * 2299285242Sachim */ 2300285242Sachimtypedef struct agsaHwConfig_s 2301285242Sachim{ 2302285242Sachim bit32 phyCount; /**< Number of PHYs that are to be configured 2303285242Sachim and initialized. */ 2304285242Sachim bit32 hwInterruptCoalescingTimer; /**< Host Interrupt CoalescingTimer */ 2305285242Sachim bit32 hwInterruptCoalescingControl; /**< Host Interrupt CoalescingControl */ 2306285242Sachim bit32 intReassertionOption; /**< Interrupt Ressertion Option */ 2307285242Sachim bit32 hwOption; /** PCAD64 on 64 bit addressing */ 2308285242Sachim 2309285242Sachim agsaPhyAnalogSetupTable_t phyAnalogConfig; /**< Phy Analog Setting Table */ 2310285242Sachim} agsaHwConfig_t; 2311285242Sachim 2312285242Sachim/** \brief structure describe software configuration 2313285242Sachim * 2314285242Sachim * Structure is used as a parameter passed in saInitialize() to describe the 2315285242Sachim * configuration used during software initialization 2316285242Sachim * 2317285242Sachim */ 2318285242Sachimtypedef struct agsaSwConfig_s 2319285242Sachim{ 2320285242Sachim bit32 maxActiveIOs; /**< Maximum active I/O requests supported */ 2321285242Sachim bit32 numDevHandles; /**< Number of SAS/SATA device handles allocated 2322285242Sachim in the pool */ 2323285242Sachim bit32 smpReqTimeout; /**< SMP request time out in millisecond */ 2324285242Sachim bit32 numberOfEventRegClients; /**< Maximum number of OS Layer clients for the event 2325285242Sachim registration defined by saRegisterEventCallback() */ 2326285242Sachim bit32 sizefEventLog1; /**< Size of Event Log 1 */ 2327285242Sachim bit32 sizefEventLog2; /**< Size of Event Log 2 */ 2328285242Sachim bit32 eventLog1Option; /**< Option of Event Log 1 */ 2329285242Sachim bit32 eventLog2Option; /**< Option of Event Log 2 */ 2330285242Sachim 2331285242Sachim bit32 fatalErrorInterruptEnable:1; /**< 0 Fatal Error Iterrupt Enable */ 2332285242Sachim bit32 sgpioSupportEnable:1; /**< 1 SGPIO Support Enable */ 2333285242Sachim bit32 fatalErrorInterruptVector:8; /**< 2-9 Fatal Error Interrupt Vector */ 2334285242Sachim bit32 max_MSI_InterruptVectors:8; /**< 10-18 Maximum MSI Interrupt Vectors */ 2335285242Sachim bit32 max_MSIX_InterruptVectors:8; /**< 18-25 Maximum MSIX Interrupt Vectors */ 2336285242Sachim bit32 legacyInt_X:1; /**< 26 Support Legacy Interrupt */ 2337285242Sachim bit32 hostDirectAccessSupport:1; /**< 27 Support HDA mode */ 2338285242Sachim bit32 hostDirectAccessMode:2; /**< 28-29 HDA mode: 00b - HDA SoftReset, 01b - HDA Normal */ 2339285242Sachim bit32 enableDIF:1; /**< 30 */ 2340285242Sachim bit32 enableEncryption:1; /**< 31 */ 2341285242Sachim#ifdef SA_CONFIG_MDFD_REGISTRY 2342285242Sachim bit32 disableMDF; /*disable MDF*/ 2343285242Sachim#endif 2344285242Sachim bit32 param1; /**< parameter1 */ 2345285242Sachim bit32 param2; /**< parameter2 */ 2346285242Sachim void *param3; /**< parameter3 */ 2347285242Sachim void *param4; /**< paramater4 */ 2348285242Sachim bit32 stallUsec; 2349285242Sachim bit32 FWConfig; 2350285242Sachim bit32 PortRecoveryResetTimer; 2351285242Sachim void *mpiContextTable; /** Pointer to a table that contains agsaMPIContext_t 2352285242Sachim entries. This table is used to fill in MPI table 2353285242Sachim fields. Values in this table are written to MPI table last. 2354285242Sachim Any previous values in MPI table are overwritten by values 2355285242Sachim in this table. */ 2356285242Sachim 2357285242Sachim bit32 mpiContextTablelen; /** Number of agsaMPIContext_t entries in mpiContextTable */ 2358285242Sachim 2359285242Sachim#if defined(SALLSDK_DEBUG) 2360285242Sachim bit32 sallDebugLevel; /**< Low Layer debug level */ 2361285242Sachim#endif 2362285242Sachim 2363285242Sachim#ifdef SA_ENABLE_PCI_TRIGGER 2364285242Sachim bit32 PCI_trigger; 2365285242Sachim#endif /* SA_ENABLE_PCI_TRIGGER */ 2366285242Sachim 2367285242Sachim#ifdef SA_ENABLE_TRACE_FUNCTIONS 2368285242Sachim bit32 TraceDestination; 2369285242Sachim bit32 TraceBufferSize; 2370285242Sachim bit32 TraceMask; 2371285242Sachim#endif /* SA_ENABLE_TRACE_FUNCTIONS */ 2372285242Sachim} agsaSwConfig_t; 2373285242Sachim 2374285242Sachim 2375285242Sachimtypedef struct agsaQueueInbound_s 2376285242Sachim{ 2377285242Sachim bit32 elementCount:16; /* Maximum number of elements in the queue (queue depth). 2378285242Sachim A value of zero indicates that the host disabled this queue.*/ 2379285242Sachim bit32 elementSize:16; /* Size of each element in the queue in bytes.*/ 2380285242Sachim bit32 priority:2; /* Queue priority: 2381285242Sachim 00: normal priority 2382285242Sachim 01: high priority 2383285242Sachim 10: reserved 2384285242Sachim 11: reserved */ 2385285242Sachim bit32 reserved:30; 2386285242Sachim} agsaQueueInbound_t; 2387285242Sachim 2388285242Sachimtypedef struct agsaQueueOutbound_s 2389285242Sachim{ 2390285242Sachim bit32 elementCount:16; /* Maximum number of elements in the queue (queue depth). 2391285242Sachim A value of zero indicates that the host disabled 2392285242Sachim this queue.*/ 2393285242Sachim bit32 elementSize:16; /* Size of each element in the queue in bytes.*/ 2394285242Sachim bit32 interruptDelay:16; /* Time, in usec, to delay interrupts to the host. 2395285242Sachim Zero means not to delay based on time. An 2396285242Sachim interrupt is passed to the host when either of 2397285242Sachim the interruptDelay or interruptCount parameters 2398285242Sachim is satisfied. Default value is 0.*/ 2399285242Sachim bit32 interruptCount:16; /* Number of interrupts required before passing to 2400285242Sachim the host. Zero means not to coalesce based on count. */ 2401285242Sachim bit32 interruptVectorIndex:8; /* MSI/MSI-X interrupt vector index. For MSI, when 2402285242Sachim Multiple Messages is enabled, this field is the 2403285242Sachim index to the MSI vectors derived from a single 2404285242Sachim Message Address and multiple Message Data. 2405285242Sachim For MSI-X, this field is the index to the 2406285242Sachim MSI-X Table Structure. */ 2407285242Sachim bit32 interruptEnable:1; /* 0b: No interrupt to host (host polling) 2408285242Sachim 1b: Interrupt enabled */ 2409285242Sachim bit32 reserved:23; 2410285242Sachim 2411285242Sachim} agsaQueueOutbound_t; 2412285242Sachim 2413285242Sachimtypedef struct agsaPhyCalibrationTbl_s 2414285242Sachim{ 2415285242Sachim bit32 txPortConfig1; /* transmitter per port configuration 1 SAS_SATA G1 */ 2416285242Sachim bit32 txPortConfig2; /* transmitter per port configuration 2 SAS_SATA G1*/ 2417285242Sachim bit32 txPortConfig3; /* transmitter per port configuration 3 SAS_SATA G1*/ 2418285242Sachim bit32 txConfig1; /* transmitter configuration 1 */ 2419285242Sachim bit32 rvPortConfig1; /* reveiver per port configuration 1 SAS_SATA G1G2 */ 2420285242Sachim bit32 rvPortConfig2; /* reveiver per port configuration 2 SAS_SATA G3 */ 2421285242Sachim bit32 rvConfig1; /* reveiver per configuration 1 */ 2422285242Sachim bit32 rvConfig2; /* reveiver per configuration 2 */ 2423285242Sachim bit32 reserved[2]; /* reserved */ 2424285242Sachim} agsaPhyCalibrationTbl_t; 2425285242Sachim 2426285242Sachimtypedef struct agsaQueueConfig_s 2427285242Sachim{ 2428285242Sachim bit16 numInboundQueues; 2429285242Sachim bit16 numOutboundQueues; 2430285242Sachim bit8 sasHwEventQueue[AGSA_MAX_VALID_PHYS]; 2431285242Sachim bit8 sataNCQErrorEventQueue[AGSA_MAX_VALID_PHYS]; 2432285242Sachim bit8 tgtITNexusEventQueue[AGSA_MAX_VALID_PHYS]; 2433285242Sachim bit8 tgtSSPEventQueue[AGSA_MAX_VALID_PHYS]; 2434285242Sachim bit8 tgtSMPEventQueue[AGSA_MAX_VALID_PHYS]; 2435285242Sachim bit8 iqNormalPriorityProcessingDepth; 2436285242Sachim bit8 iqHighPriorityProcessingDepth; 2437285242Sachim bit8 generalEventQueue; 2438285242Sachim bit8 tgtDeviceRemovedEventQueue; 2439285242Sachim bit32 queueOption; 2440285242Sachim agsaQueueInbound_t inboundQueues[AGSA_MAX_INBOUND_Q]; 2441285242Sachim agsaQueueOutbound_t outboundQueues[AGSA_MAX_OUTBOUND_Q]; 2442285242Sachim} agsaQueueConfig_t; 2443285242Sachim 2444285242Sachim#define OQ_SHARE_PATH_BIT 0x00000001 2445285242Sachim 2446285242Sachimtypedef struct agsaFwImg_s 2447285242Sachim{ 2448285242Sachim bit8 *aap1Img; /**< AAP1 Image */ 2449285242Sachim bit32 aap1Len; /**< AAP1 Image Length */ 2450285242Sachim bit8 *ilaImg; /**< ILA Image */ 2451285242Sachim bit32 ilaLen; /**< ILA Image Length */ 2452285242Sachim bit8 *iopImg; /**< IOP Image */ 2453285242Sachim bit32 iopLen; /**< IOP Image Length */ 2454285242Sachim bit8 *istrImg; /**< Init String */ 2455285242Sachim bit32 istrLen; /**< Init String Length */ 2456285242Sachim} agsaFwImg_t; 2457285242Sachim 2458285242Sachim/** \brief generic memory descriptor 2459285242Sachim * 2460285242Sachim * a generic memory descriptor used for describing a memory requirement in a structure 2461285242Sachim * 2462285242Sachim */ 2463285242Sachimtypedef struct agsaMem_s 2464285242Sachim{ 2465285242Sachim void *virtPtr; /**< Virtual pointer to the memory chunk */ 2466285242Sachim void *osHandle; /**< Handle used for OS to free memory */ 2467285242Sachim bit32 phyAddrUpper; /**< Upper 32 bits of physical address */ 2468285242Sachim bit32 phyAddrLower; /**< Lower 32 bits of physical address */ 2469285242Sachim bit32 totalLength; /**< Total length in bytes allocated */ 2470285242Sachim bit32 numElements; /**< Number of elements */ 2471285242Sachim bit32 singleElementLength; /**< Size in bytes of an element */ 2472285242Sachim bit32 alignment; /**< Alignment in bytes needed. A value of one indicates 2473285242Sachim no specific alignment requirement */ 2474285242Sachim bit32 type; /**< DMA or Cache */ 2475285242Sachim bit32 reserved; /**< reserved */ 2476285242Sachim} agsaMem_t; 2477285242Sachim 2478285242Sachim/** \brief specify the controller Event Log for the SAS/SATA LL Layer 2479285242Sachim * 2480285242Sachim * data structure used in the saGetControllerEventLogInfo() function calls 2481285242Sachim * 2482285242Sachim */ 2483285242Sachimtypedef struct agsaControllerEventLog_s 2484285242Sachim{ 2485285242Sachim agsaMem_t eventLog1; 2486285242Sachim agsaMem_t eventLog2; 2487285242Sachim bit32 eventLog1Option; 2488285242Sachim bit32 eventLog2Option; 2489285242Sachim} agsaControllerEventLog_t; 2490285242Sachim 2491285242Sachim/* Log Option - bit3-0 */ 2492285242Sachim#define DISABLE_LOGGING 0x0 2493285242Sachim#define CRITICAL_ERROR 0x1 2494285242Sachim#define WARNING 0x2 2495285242Sachim#define NOTICE 0x3 2496285242Sachim#define INFORMATION 0x4 2497285242Sachim#define DEBUGGING 0x5 2498285242Sachim 2499285242Sachim/** \brief specify the SAS Diagnostic Parameters for the SAS/SATA LL Layer 2500285242Sachim * 2501285242Sachim * data structure used in the saGetRequirements() and the saInitialize() function calls 2502285242Sachim * 2503285242Sachim */ 2504285242Sachimtypedef struct agsaSASDiagExecute_s 2505285242Sachim{ 2506285242Sachim bit32 command; 2507285242Sachim bit32 param0; 2508285242Sachim bit32 param1; 2509285242Sachim bit32 param2; 2510285242Sachim bit32 param3; 2511285242Sachim bit32 param4; 2512285242Sachim bit32 param5; 2513285242Sachim} agsaSASDiagExecute_t; 2514285242Sachim 2515285242Sachim 2516285242Sachim/** \brief for the SAS/SATA LL Layer 2517285242Sachim * 2518285242Sachim * This data structure contains the general status of a SAS Phy. 2519285242Sachim * Section 4.60 2520285242Sachim */ 2521285242Sachimtypedef struct agsaSASPhyGeneralStatusPage_s 2522285242Sachim{ 2523285242Sachim bit32 Dword0; 2524285242Sachim bit32 Dword1; 2525285242Sachim} agsaSASPhyGeneralStatusPage_t; 2526285242Sachim 2527285242Sachim 2528285242Sachim/** \brief specify the memory allocation requirement for the SAS/SATA LL Layer 2529285242Sachim * 2530285242Sachim * data structure used in the saGetRequirements() and the saInitialize() function calls 2531285242Sachim * 2532285242Sachim */ 2533285242Sachimtypedef struct agsaMemoryRequirement_s 2534285242Sachim{ 2535285242Sachim bit32 count; /**< The number of memory chunks used 2536285242Sachim in the agMemory table */ 2537285242Sachim agsaMem_t agMemory[AGSA_NUM_MEM_CHUNKS]; /**< The structure that defines the memory 2538285242Sachim requirement structure */ 2539285242Sachim} agsaMemoryRequirement_t; 2540285242Sachim 2541285242Sachim 2542285242Sachim/** \brief describe a SAS address and PHY Identifier 2543285242Sachim * 2544285242Sachim * This structure is used 2545285242Sachim * 2546285242Sachim */ 2547285242Sachimtypedef struct agsaSASAddressID_s 2548285242Sachim{ 2549285242Sachim bit8 sasAddressLo[4]; /**< HOST SAS address lower part */ 2550285242Sachim bit8 sasAddressHi[4]; /**< HOST SAS address higher part */ 2551285242Sachim bit8 phyIdentifier; /**< PHY IDENTIFIER of the PHY */ 2552285242Sachim} agsaSASAddressID_t; 2553285242Sachim 2554285242Sachim/** \brief data structure provides some information about a SATA device 2555285242Sachim * 2556285242Sachim * data structure provides some information about a SATA device discovered 2557285242Sachim * following the SATA discovery. 2558285242Sachim * 2559285242Sachim */ 2560285242Sachimtypedef struct agsaDeviceInfo_s 2561285242Sachim{ 2562285242Sachim bit16 smpTimeout; 2563285242Sachim bit16 it_NexusTimeout; 2564285242Sachim bit16 firstBurstSize; 2565285242Sachim bit8 reserved; 2566285242Sachim /* Not Used */ 2567285242Sachim bit8 devType_S_Rate; 2568285242Sachim /* Bit 6-7: reserved 2569285242Sachim Bit 4-5: Two-bit flag to specify a SSP/SMP, or directly attached SATA or STP device 2570285242Sachim 00: STP device 2571285242Sachim 01: SSP or SMP device 2572285242Sachim 10: Direct SATA device 2573285242Sachim Bit 0-3: Connection Rate field when opening the device. 2574285242Sachim Code Description: 2575285242Sachim 08h: 1.5 Gbps 2576285242Sachim 09h: 3.0 Gbps 2577285242Sachim 0ah: 6.0 Gbps 2578285242Sachim All others Reserved 2579285242Sachim */ 2580285242Sachim bit8 sasAddressHi[4]; 2581285242Sachim bit8 sasAddressLo[4]; 2582285242Sachim bit32 flag; 2583285242Sachim/* 2584285242Sachimflag 2585285242SachimBit 0: Retry flag. 2586285242Sachim 1b: enable SAS TLR (Transport Layer Retry). 2587285242Sachim 0b: disable SAS TLR (Transport Layer Retry). 2588285242Sachim When used during device registration, it is recommended that TLR is 2589285242Sachim enabled, i.e. set the bit to 1. 2590285242SachimBit 1: Priority setting for AWT (Arbitration Wait Time) for this device. 2591285242Sachim 0b: Default setting (recommended). Actual AWT value TBD. 2592285242Sachim 1b: Increase priority. Actual AWT value TBD. 2593285242SachimBit 2-3: Reserved 2594285242SachimBit 4-11: Zero-based PHY identifier. This field is used only if bits 4-5 in devType_S_Rate are set to 10b 2595285242Sachim which indicates a directly-attached SATA drive. 2596285242SachimBit 12-15: Reserved 2597285242SachimBit 16-19 : Maximum Connection Number. This field specifies the maximum number of connections that 2598285242Sachim can be established with the device concurrently. This field is set to the lowest port width along the pathway 2599285242Sachim from the controller to the device. This is applicable only to the SPCv controller. 2600285242Sachim However, for backward compatibility reasons, if this field is set to zero, it is treated as 1 so that the controller 2601285242Sachim can establish at least one connection. 2602285242SachimBit 20: Initiator Role 2603285242Sachim This bit indicates whether the device has SSP initiator role capability. This is applicable only to the SPCv controller. 2604285242Sachim 0b : The device has no SSP initiator capability. 2605285242Sachim 1b : The device has SSP initiator capability. 2606285242SachimBit 21: ATAPI Device Flag. (Only applies to the SPCv) Flag to indicate ATAPI protocol support 2607285242Sachim 0b : Device does not support ATAPI protocol. 2608285242Sachim 1b : Device supports ATAPI protocol. 2609285242SachimBit 22-31: Reserved 2610285242Sachim*/ 2611285242Sachim} agsaDeviceInfo_t; 2612285242Sachim 2613285242Sachim 2614285242Sachim#define DEV_INFO_MASK 0xFF 2615285242Sachim#define DEV_INFO_MCN_SHIFT 16 2616285242Sachim#define DEV_INFO_IR_SHIFT 20 2617285242Sachim 2618285242Sachim#define RETRY_DEVICE_FLAG (1 << SHIFT0) 2619285242Sachim#define AWT_DEVICE_FLAG (1 << SHIFT1) 2620285242Sachim#define SSP_DEVICE_FLAG (1 << SHIFT20) 2621285242Sachim#define ATAPI_DEVICE_FLAG 0x200000 /* bit21 */ 2622285242Sachim#define XFER_RDY_PRIORTY_DEVICE_FLAG (1 << SHIFT22) 2623285242Sachim 2624285242Sachim 2625285242Sachim#define DEV_LINK_RATE 0x3F 2626285242Sachim 2627285242Sachim#define SA_DEVINFO_GET_SAS_ADDRESSLO(devInfo) \ 2628285242Sachim DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressLo) 2629285242Sachim 2630285242Sachim#define SA_DEVINFO_GET_SAS_ADDRESSHI(devInfo) \ 2631285242Sachim DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressHi) 2632285242Sachim 2633285242Sachim#define SA_DEVINFO_GET_DEVICETTYPE(devInfo) \ 2634285242Sachim (((devInfo)->devType_S_Rate & 0xC0) >> 5) 2635285242Sachim 2636285242Sachim#define SA_DEVINFO_PUT_SAS_ADDRESSLO(devInfo, src32) \ 2637285242Sachim *(bit32 *)((devInfo)->sasAddressLo) = BIT32_TO_DMA_BEBIT32(src32) 2638285242Sachim 2639285242Sachim#define SA_DEVINFO_PUT_SAS_ADDRESSHI(devInfo, src32) \ 2640285242Sachim *(bit32 *)((devInfo)->sasAddressHi) = BIT32_TO_DMA_BEBIT32(src32) 2641285242Sachim 2642285242Sachim/** \brief data structure provides some information about a SATA device 2643285242Sachim * 2644285242Sachim * data structure provides some information about a SATA device discovered 2645285242Sachim * following the SATA discovery. 2646285242Sachim * 2647285242Sachim */ 2648285242Sachimtypedef struct agsaSATADeviceInfo_s 2649285242Sachim{ 2650285242Sachim agsaDeviceInfo_t commonDevInfo; /**< The general/common part of the 2651285242Sachim SAS/SATA device information */ 2652285242Sachim bit8 connection; /**< How device is connected: 2653285242Sachim 0: Direct attached. 2654285242Sachim 1: Behind Port Multiplier, 2655285242Sachim portMultiplierField is valid. 2656285242Sachim 2: STP, stpPhyIdentifier is valid */ 2657285242Sachim 2658285242Sachim bit8 portMultiplierField; /**< The first 4 bits indicate that 2659285242Sachim the Port Multiplier field is defined 2660285242Sachim by SATA-II. This field is valid only 2661285242Sachim if the connection field above is 2662285242Sachim set to 1 */ 2663285242Sachim 2664285242Sachim bit8 stpPhyIdentifier; /**< PHY ID of the STP PHY. Valid only if 2665285242Sachim connection field is set to 2 (STP). */ 2666285242Sachim 2667285242Sachim bit8 reserved; 2668285242Sachim bit8 signature[8]; /**< The signature of SATA in Task 2669285242Sachim File registers following power up. 2670285242Sachim Only five bytes are defined by ATA. 2671285242Sachim The added three bytes are for 2672285242Sachim alignment purposes */ 2673285242Sachim} agsaSATADeviceInfo_t; 2674285242Sachim 2675285242Sachim/** \brief data structure provides some information about a SAS device 2676285242Sachim * 2677285242Sachim * data structure provides some information about a SAS device discovered 2678285242Sachim * following the SAS discovery 2679285242Sachim * 2680285242Sachim */ 2681285242Sachimtypedef struct agsaSASDeviceInfo_s 2682285242Sachim{ 2683285242Sachim agsaDeviceInfo_t commonDevInfo; /**< The general/common part of the SAS/SATA 2684285242Sachim device information */ 2685285242Sachim bit8 initiator_ssp_stp_smp; /**< SAS initiator capabilities */ 2686285242Sachim /* b4-7: reserved */ 2687285242Sachim /* b3: SSP initiator port */ 2688285242Sachim /* b2: STP initiator port */ 2689285242Sachim /* b1: SMP initiator port */ 2690285242Sachim /* b0: reserved */ 2691285242Sachim bit8 target_ssp_stp_smp; /**< SAS target capabilities */ 2692285242Sachim /* b4-7: reserved */ 2693285242Sachim /* b3: SSP target port */ 2694285242Sachim /* b2: STP target port */ 2695285242Sachim /* b1: SMP target port */ 2696285242Sachim /* b0: reserved */ 2697285242Sachim bit32 numOfPhys; /**< Number of PHYs in the device */ 2698285242Sachim bit8 phyIdentifier; /**< PHY IDENTIFIER in IDENTIFY address 2699285242Sachim frame as defined by the SAS 2700285242Sachim specification. */ 2701285242Sachim} agsaSASDeviceInfo_t; 2702285242Sachim 2703285242Sachim#define SA_SASDEV_SSP_BIT SA_IDFRM_SSP_BIT /* SSP Initiator port */ 2704285242Sachim#define SA_SASDEV_STP_BIT SA_IDFRM_STP_BIT /* STP Initiator port */ 2705285242Sachim#define SA_SASDEV_SMP_BIT SA_IDFRM_SMP_BIT /* SMP Initiator port */ 2706285242Sachim#define SA_SASDEV_SATA_BIT SA_IDFRM_SATA_BIT /* SATA device, valid in the discovery response only */ 2707285242Sachim 2708285242Sachim#define SA_SASDEV_IS_SSP_INITIATOR(sasDev) \ 2709285242Sachim (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_SSP_BIT) == SA_SASDEV_SSP_BIT) 2710285242Sachim 2711285242Sachim#define SA_SASDEV_IS_STP_INITIATOR(sasDev) \ 2712285242Sachim (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_STP_BIT) == SA_SASDEV_STP_BIT) 2713285242Sachim 2714285242Sachim#define SA_SASDEV_IS_SMP_INITIATOR(sasDev) \ 2715285242Sachim (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_SMP_BIT) == SA_SASDEV_SMP_BIT) 2716285242Sachim 2717285242Sachim#define SA_SASDEV_IS_SSP_TARGET(sasDev) \ 2718285242Sachim (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SSP_BIT) == SA_SASDEV_SSP_BIT) 2719285242Sachim 2720285242Sachim#define SA_SASDEV_IS_STP_TARGET(sasDev) \ 2721285242Sachim (((sasDev)->target_ssp_stp_smp & SA_SASDEV_STP_BIT) == SA_SASDEV_STP_BIT) 2722285242Sachim 2723285242Sachim#define SA_SASDEV_IS_SMP_TARGET(sasDev) \ 2724285242Sachim (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SMP_BIT) == SA_SASDEV_SMP_BIT) 2725285242Sachim 2726285242Sachim#define SA_SASDEV_IS_SATA_DEVICE(sasDev) \ 2727285242Sachim (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SATA_BIT) == SA_SASDEV_SATA_BIT) 2728285242Sachim 2729285242Sachim 2730285242Sachim 2731285242Sachim 2732285242Sachim/** \brief the data structure describe SG list 2733285242Sachim * 2734285242Sachim * the data structure describe SG list 2735285242Sachim * 2736285242Sachim */ 2737285242Sachimtypedef struct _SASG_DESCRIPTOR 2738285242Sachim{ 2739285242Sachim bit32 sgLower; /**< Lower 32 bits of data area physical address */ 2740285242Sachim bit32 sgUpper; /**< Upper 32 bits of data area physical address */ 2741285242Sachim bit32 len; /**< Total data length in bytes */ 2742285242Sachim} SASG_DESCRIPTOR, * PSASG_DESCRIPTOR; 2743285242Sachim 2744285242Sachim/** \brief data structure used to pass information about the scatter-gather list to the LL Layer 2745285242Sachim * 2746285242Sachim * The ESGL pages are uncached, have a configurable number of SGL 2747285242Sachim * of (min, max) = (1, 10), and are 16-byte aligned. Although 2748285242Sachim * the application can configure the page size, the size must be 2749285242Sachim * incremented in TBD-byte increments. Refer the hardware 2750285242Sachim * documentation for more detail on the format of ESGL 2751285242Sachim * structure. 2752285242Sachim * 2753285242Sachim */ 2754285242Sachimtypedef struct agsaSgl_s 2755285242Sachim{ 2756285242Sachim bit32 sgLower; /**< Lower 32 bits of data area physical address */ 2757285242Sachim bit32 sgUpper; /**< Upper 32 bits of data area physical address */ 2758285242Sachim bit32 len; /**< Total data length in bytes */ 2759285242Sachim bit32 extReserved; /**< bit31 is for extended sgl list */ 2760285242Sachim} agsaSgl_t; 2761285242Sachim 2762285242Sachim/** \brief data structure is used to pass information about the extended 2763285242Sachim * scatter-gather list (ESGL) to the LL Layer 2764285242Sachim * 2765285242Sachim * The agsaEsgl_t data structure is used to pass information about the 2766285242Sachim * extended scatter-gather list (ESGL) to the LL Layer. 2767285242Sachim * 2768285242Sachim * When ESGL is used, its starting address is specified the first descriptor 2769285242Sachim * entry (i.e. descriptor[0]) in agsaSgl_t structure. 2770285242Sachim * 2771285242Sachim * The ESGL pages are uncached, have a fixed number of SGL of 10, and are 2772285242Sachim * 16-byte aligned. Refer the hardware documentation for more 2773285242Sachim * detail on ESGL. 2774285242Sachim * 2775285242Sachim */ 2776285242Sachimtypedef struct agsaEsgl_s 2777285242Sachim{ 2778285242Sachim agsaSgl_t descriptor[MAX_ESGL_ENTRIES]; 2779285242Sachim} agsaEsgl_t; 2780285242Sachim 2781285242Sachim/** \brief data structure describes an SSP Command INFORMATION UNIT 2782285242Sachim * 2783285242Sachim * data structure describes an SSP Command INFORMATION UNIT used for SSP command and is part of 2784285242Sachim * the SSP frame. 2785285242Sachim * 2786285242Sachim * Currently, Additional CDB length is supported to 16 bytes 2787285242Sachim * 2788285242Sachim */ 2789285242Sachim#define MAX_CDB_LEN 32 2790285242Sachimtypedef struct agsaSSPCmdInfoUnitExt_s 2791285242Sachim{ 2792285242Sachim bit8 lun[8]; 2793285242Sachim bit8 reserved1; 2794285242Sachim bit8 efb_tp_taskAttribute; 2795285242Sachim bit8 reserved2; 2796285242Sachim bit8 additionalCdbLen; 2797285242Sachim bit8 cdb[MAX_CDB_LEN]; 2798285242Sachim} agsaSSPCmdInfoUnitExt_t ; 2799285242Sachim 2800285242Sachim#define DIF_UDT_SIZE 6 2801285242Sachim 2802285242Sachim/* difAction in agsaDif_t */ 2803285242Sachim#define AGSA_DIF_INSERT 0 2804285242Sachim#define AGSA_DIF_VERIFY_FORWARD 1 2805285242Sachim#define AGSA_DIF_VERIFY_DELETE 2 2806285242Sachim#define AGSA_DIF_VERIFY_REPLACE 3 2807285242Sachim#define AGSA_DIF_VERIFY_UDT_REPLACE_CRC 5 2808285242Sachim#define AGSA_DIF_REPLACE_UDT_REPLACE_CRC 7 2809285242Sachim 2810285242Sachim#define agsaDIFSectorSize512 0 2811285242Sachim#define agsaDIFSectorSize520 1 2812285242Sachim#define agsaDIFSectorSize4096 2 2813285242Sachim#define agsaDIFSectorSize4160 3 2814285242Sachim 2815285242Sachim 2816285242Sachim 2817285242Sachimtypedef struct agsaDif_s 2818285242Sachim{ 2819285242Sachim agBOOLEAN enableDIFPerLA; 2820285242Sachim bit32 flags; 2821285242Sachim bit16 initialIOSeed; 2822285242Sachim bit16 reserved; 2823285242Sachim bit32 DIFPerLAAddrLo; 2824285242Sachim bit32 DIFPerLAAddrHi; 2825285242Sachim bit16 DIFPerLARegion0SecCount; 2826285242Sachim bit16 Reserved2; 2827285242Sachim bit8 udtArray[DIF_UDT_SIZE]; 2828285242Sachim bit8 udrtArray[DIF_UDT_SIZE]; 2829285242Sachim} agsaDif_t; 2830285242Sachim 2831285242Sachim 2832285242Sachim/* From LL SDK2 */ 2833285242Sachim#define DIF_FLAG_BITS_ACTION 0x00000007 /* 0-2*/ 2834285242Sachim#define DIF_FLAG_BITS_CRC_VER 0x00000008 /* 3 */ 2835285242Sachim#define DIF_FLAG_BITS_CRC_INV 0x00000010 /* 4 */ 2836285242Sachim#define DIF_FLAG_BITS_CRC_SEED 0x00000020 /* 5 */ 2837285242Sachim#define DIF_FLAG_BITS_UDT_REF_TAG 0x00000040 /* 6 */ 2838285242Sachim#define DIF_FLAG_BITS_UDT_APP_TAG 0x00000080 /* 7 */ 2839285242Sachim#define DIF_FLAG_BITS_UDTR_REF_BLKCOUNT 0x00000100 /* 8 */ 2840285242Sachim#define DIF_FLAG_BITS_UDTR_APP_BLKCOUNT 0x00000200 /* 9 */ 2841285242Sachim#define DIF_FLAG_BITS_CUST_APP_TAG 0x00000C00 /* 10 11*/ 2842285242Sachim#define DIF_FLAG_BITS_EPRC 0x00001000 /* 12 */ 2843285242Sachim#define DIF_FLAG_BITS_Reserved 0x0000E000 /* 13 14 15*/ 2844285242Sachim#define DIF_FLAG_BITS_BLOCKSIZE_MASK 0x00070000 /* 16 17 18 */ 2845285242Sachim#define DIF_FLAG_BITS_BLOCKSIZE_SHIFT 16 2846285242Sachim#define DIF_FLAG_BITS_BLOCKSIZE_512 0x00000000 /* */ 2847285242Sachim#define DIF_FLAG_BITS_BLOCKSIZE_520 0x00010000 /* 16 */ 2848285242Sachim#define DIF_FLAG_BITS_BLOCKSIZE_4096 0x00020000 /* 17 */ 2849285242Sachim#define DIF_FLAG_BITS_BLOCKSIZE_4160 0x00030000 /* 16 17 */ 2850285242Sachim#define DIF_FLAG_BITS_UDTVMASK 0x03F00000 /* 20 21 22 23 24 25 */ 2851285242Sachim#define DIF_FLAG_BITS_UDTV_SHIFT 20 2852285242Sachim#define DIF_FLAG_BITS_UDTUPMASK 0xF6000000 /* 26 27 28 29 30 31 */ 2853285242Sachim#define DIF_FLAG_BITS_UDTUPSHIFT 26 2854285242Sachim 2855285242Sachimtypedef struct agsaEncryptDek_s 2856285242Sachim{ 2857285242Sachim bit32 dekTable; 2858285242Sachim bit32 dekIndex; 2859285242Sachim} agsaEncryptDek_t; 2860285242Sachim 2861285242Sachimtypedef struct agsaEncrypt_s 2862285242Sachim{ 2863285242Sachim agsaEncryptDek_t dekInfo; 2864285242Sachim bit32 kekIndex; 2865285242Sachim agBOOLEAN keyTagCheck; 2866285242Sachim agBOOLEAN enableEncryptionPerLA; /* new */ 2867285242Sachim bit32 sectorSizeIndex; 2868285242Sachim bit32 cipherMode; 2869285242Sachim bit32 keyTag_W0; 2870285242Sachim bit32 keyTag_W1; 2871285242Sachim bit32 tweakVal_W0; 2872285242Sachim bit32 tweakVal_W1; 2873285242Sachim bit32 tweakVal_W2; 2874285242Sachim bit32 tweakVal_W3; 2875285242Sachim bit32 EncryptionPerLAAddrLo; /* new */ 2876285242Sachim bit32 EncryptionPerLAAddrHi; /* new */ 2877285242Sachim bit16 EncryptionPerLRegion0SecCount; /* new */ 2878285242Sachim bit16 reserved; 2879285242Sachim} agsaEncrypt_t; 2880285242Sachim 2881285242Sachim/** \brief data structure describes a SAS SSP command request to be sent to the target device 2882285242Sachim * 2883285242Sachim * data structure describes a SAS SSP command request to be sent to the 2884285242Sachim * target device. This structure limits the CDB length in SSP 2885285242Sachim * command up to 16 bytes long. 2886285242Sachim * 2887285242Sachim * This data structure is one instance of the generic request issued to 2888285242Sachim * saSSPStart() and is passed as an agsaSASRequestBody_t . 2889285242Sachim * 2890285242Sachim */ 2891285242Sachimtypedef struct agsaSSPInitiatorRequest_s 2892285242Sachim{ 2893285242Sachim agsaSgl_t agSgl; /**< This structure is used to define either 2894285242Sachim an ESGL list or a single SGL for the SSP 2895285242Sachim command operation */ 2896285242Sachim bit32 dataLength; /**< Total data length in bytes */ 2897285242Sachim bit16 firstBurstSize; /**< First Burst Size field as defined by 2898285242Sachim SAS specification */ 2899285242Sachim bit16 flag; /**< bit1-0 TLR as SAS specification 2900285242Sachim bit31-2 reserved */ 2901285242Sachim agsaSSPCmdInfoUnit_t sspCmdIU; /**< Structure containing SSP Command 2902285242Sachim INFORMATION UNIT */ 2903285242Sachim agsaDif_t dif; 2904285242Sachim agsaEncrypt_t encrypt; 2905285242Sachim#ifdef SA_TESTBASE_EXTRA 2906285242Sachim /* Added by TestBase */ 2907285242Sachim bit16 bstIndex; 2908285242Sachim#endif /* SA_TESTBASE_EXTRA */ 2909285242Sachim} agsaSSPInitiatorRequest_t; 2910285242Sachim 2911285242Sachim/** \brief data structure describes a SAS SSP command request Ext to be sent to the target device 2912285242Sachim * 2913285242Sachim * data structure describes a SAS SSP command request to be sent to the 2914285242Sachim * target device. This structure support the CDB length in SSP 2915285242Sachim * command more than 16 bytes long. 2916285242Sachim * 2917285242Sachim * This data structure is one instance of the generic request issued to 2918285242Sachim * saSSPStart() and is passed as an agsaSASRequestBody_t . 2919285242Sachim * 2920285242Sachim */ 2921285242Sachimtypedef struct agsaSSPInitiatorRequestExt_s 2922285242Sachim{ 2923285242Sachim agsaSgl_t agSgl; /**< This structure is used to define either 2924285242Sachim an ESGL list or a single SGL for the SSP 2925285242Sachim command operation */ 2926285242Sachim bit32 dataLength; 2927285242Sachim bit16 firstBurstSize; 2928285242Sachim bit16 flag; 2929285242Sachim agsaSSPCmdInfoUnitExt_t sspCmdIUExt; 2930285242Sachim agsaDif_t dif; 2931285242Sachim agsaEncrypt_t encrypt; 2932285242Sachim} agsaSSPInitiatorRequestExt_t; 2933285242Sachim 2934285242Sachim 2935285242Sachimtypedef struct agsaSSPInitiatorRequestIndirect_s 2936285242Sachim{ 2937285242Sachim agsaSgl_t agSgl; /**< This structure is used to define either 2938285242Sachim an ESGL list or a single SGL for the SSP 2939285242Sachim command operation */ 2940285242Sachim bit32 dataLength; 2941285242Sachim bit16 firstBurstSize; 2942285242Sachim bit16 flag; 2943285242Sachim bit32 sspInitiatorReqAddrUpper32; /**< The upper 32 bits of the 64-bit physical DMA address of the SSP initiator request buffer */ 2944285242Sachim bit32 sspInitiatorReqAddrLower32; /**< The lower 32 bits of the 64-bit physical DMA address of the SSP initiator request buffer */ 2945285242Sachim bit32 sspInitiatorReqLen; /**< Specifies the length of the SSP initiator request in bytes */ 2946285242Sachim agsaDif_t dif; 2947285242Sachim agsaEncrypt_t encrypt; 2948285242Sachim 2949285242Sachim}agsaSSPInitiatorRequestIndirect_t; 2950285242Sachim 2951285242Sachim 2952285242Sachim 2953285242Sachim 2954285242Sachim/** \brief data structure describes a SAS SSP target read and write request 2955285242Sachim * 2956285242Sachim * The agsaSSPTargetRequest_t data structure describes a SAS SSP target read 2957285242Sachim * and write request to be issued on the port. It includes the 2958285242Sachim * length of the data to be received or sent, an offset into the 2959285242Sachim * data block where the transfer is to start, and a list of 2960285242Sachim * scatter-gather buffers. 2961285242Sachim * 2962285242Sachim * This data structure is one instance of the generic request issued 2963285242Sachim * to saSSPStart() and is passed as an agsaSASRequestBody_t . 2964285242Sachim * 2965285242Sachim */ 2966285242Sachim/** bit definitions for sspOption 2967285242Sachim Bit 0-1: Transport Layer Retry setting for other phase: 2968285242Sachim 00b: No retry 2969285242Sachim 01b: Retry on ACK/NAK timeout 2970285242Sachim 10b: Retry on NAK received 2971285242Sachim 11b: Retry on both ACK/NAK timeout and NAK received 2972285242Sachim Bit 2-3: Transport Layer Retry setting for data phase: 2973285242Sachim 00b: No retry 2974285242Sachim 01b: Retry on ACK/NAK timeout 2975285242Sachim 10b: Retry on NAK received 2976285242Sachim 11b: Retry on both ACK/NAK timeout and NAK received 2977285242Sachim Bit 4: Retry Data Frame. Valid only on write command. Indicates whether Target supports RTL for this particular IO. 2978285242Sachim 1b: enabled 2979285242Sachim 0b: disabled 2980285242Sachim Bit 5: Auto good response on successful read (data transfer from target to initiator) request. 2981285242Sachim 1b: Enabled 2982285242Sachim 0b: Disabled 2983285242Sachim Bits 6-15 : Reserved. 2984285242Sachim */ 2985285242Sachimtypedef struct agsaSSPTargetRequest_s 2986285242Sachim{ 2987285242Sachim agsaSgl_t agSgl; /**< This structure is used to define either an ESGL list or 2988285242Sachim a single SGL for the target read or write operation */ 2989285242Sachim bit32 dataLength; /**< Specifies the amount of data to be sent in this data phase */ 2990285242Sachim bit32 offset; /**< Specifies the offset into the overall data block 2991285242Sachim where this data phase is to begin */ 2992285242Sachim bit16 agTag; /**< Tag from ossaSSPReqReceived(). */ 2993285242Sachim bit16 sspOption; /**< SSP option for retry */ 2994285242Sachim agsaDif_t dif; 2995285242Sachim} agsaSSPTargetRequest_t; 2996285242Sachim 2997285242Sachim#define SSP_OPTION_BITS 0x3F /**< bit5-AGR, bit4-RDF bit3,2-RTE, bit1,0-AN */ 2998285242Sachim#define SSP_OPTION_ODS 0x8000 /**< bit15-ODS */ 2999285242Sachim 3000285242Sachim#define SSP_OPTION_OTHR_NO_RETRY 0 3001285242Sachim#define SSP_OPTION_OTHR_RETRY_ON_ACK_NAK_TIMEOUT 1 3002285242Sachim#define SSP_OPTION_OTHR_RETRY_ON_NAK_RECEIVED 2 3003285242Sachim#define SSP_OPTION_OTHR_RETRY_ON_BOTH_ACK_NAK_TIMEOUT_AND_NAK_RECEIVED 3 3004285242Sachim 3005285242Sachim#define SSP_OPTION_DATA_NO_RETRY 0 3006285242Sachim#define SSP_OPTION_DATA_RETRY_ON_ACK_NAK_TIMEOUT 1 3007285242Sachim#define SSP_OPTION_DATA_RETRY_ON_NAK_RECEIVED 2 3008285242Sachim#define SSP_OPTION_DATA_RETRY_ON_BOTH_ACK_NAK_TIMEOUT_AND_NAK_RECEIVED 3 3009285242Sachim 3010285242Sachim#define SSP_OPTION_RETRY_DATA_FRAME_ENABLED (1 << SHIFT4) 3011285242Sachim#define SSP_OPTION_AUTO_GOOD_RESPONSE (1 << SHIFT5) 3012285242Sachim#define SSP_OPTION_ENCRYPT (1 << SHIFT6) 3013285242Sachim#define SSP_OPTION_DIF (1 << SHIFT7) 3014285242Sachim#define SSP_OPTION_OVERRIDE_DEVICE_STATE (1 << SHIFT15) 3015285242Sachim 3016285242Sachim 3017285242Sachim/** \brief data structure describes a SAS SSP target response to be issued 3018285242Sachim * on the port 3019285242Sachim * 3020285242Sachim * This data structure is one instance of the generic request issued to 3021285242Sachim * saSSPStart() and is passed as an agsaSASRequestBody_t 3022285242Sachim * 3023285242Sachim */ 3024285242Sachimtypedef struct agsaSSPTargetResponse_s 3025285242Sachim{ 3026285242Sachim bit32 agTag; /**< Tag from ossaSSPReqReceived(). */ 3027285242Sachim void *frameBuf; 3028285242Sachim bit32 respBufLength; /**< Specifies the length of the Response buffer */ 3029285242Sachim bit32 respBufUpper; /**< Upper 32 bit of physical address of OS Layer 3030285242Sachim allocated the Response buffer 3031285242Sachim (agsaSSPResponseInfoUnit_t). 3032285242Sachim Valid only when respBufLength is not zero */ 3033285242Sachim bit32 respBufLower; /**< Lower 32 bit of physical address of OS Layer 3034285242Sachim allocated the Response buffer 3035285242Sachim (agsaSSPResponseInfoUnit_t). 3036285242Sachim Valid only when respBufLength is not zero */ 3037285242Sachim bit32 respOption; /**< Bit 0-1: ACK and NAK retry option: 3038285242Sachim 00b: No retry 3039285242Sachim 01b: Retry on ACK/NAK timeout 3040285242Sachim 10b: Retry on NAK received 3041285242Sachim 11b: Retry on both ACK/NAK timeout and NAK received */ 3042285242Sachim} agsaSSPTargetResponse_t; 3043285242Sachim 3044285242Sachim#define RESP_OPTION_BITS 0x3 /** bit0-1 */ 3045285242Sachim#define RESP_OPTION_ODS 0x8000 /** bit15 */ 3046285242Sachim 3047285242Sachim/** \brief data structure describes a SMP request or response frame to be sent on the SAS port 3048285242Sachim * 3049285242Sachim * The agsaSMPFrame_t data structure describes a SMP request or response 3050285242Sachim * frame to be issued or sent on the SAS port. 3051285242Sachim * 3052285242Sachim * This data structure is one instance of the generic request issued to 3053285242Sachim * saSMPStart() and is passed as an agsaSASRequestBody_t . 3054285242Sachim * 3055285242Sachim */ 3056285242Sachimtypedef struct agsaSMPFrame_s 3057285242Sachim{ 3058285242Sachim void *outFrameBuf; /**< if payload is less than 32 bytes,A virtual 3059285242Sachim frameBuf can be used. instead of physical 3060285242Sachim address. Set to NULL and use physical 3061285242Sachim address if payload is > 32 bytes */ 3062285242Sachim bit32 outFrameAddrUpper32; /**< The upper 32 bits of the 64-bit physical 3063285242Sachim DMA address of the SMP frame buffer */ 3064285242Sachim bit32 outFrameAddrLower32; /**< The lower 32 bits of the 64-bit physical 3065285242Sachim DMA address of the SMP frame buffer */ 3066285242Sachim bit32 outFrameLen; /**< Specifies the length of the SMP request 3067285242Sachim frame excluding the CRC field in bytes */ 3068285242Sachim bit32 inFrameAddrUpper32; /**< The upper 32 bits of the 64-bit phsical address 3069285242Sachim of DMA address of response SMP Frame buffer */ 3070285242Sachim bit32 inFrameAddrLower32; /**< The lower 32 bits of the 64-bit phsical address 3071285242Sachim of DMA address of response SMP Frame buffer */ 3072285242Sachim bit32 inFrameLen; /**< Specifies the length of the SMP response 3073285242Sachim frame excluding the CRC field in bytes */ 3074285242Sachim bit32 expectedRespLen; /**< Specifies the length of SMP Response */ 3075285242Sachim bit32 flag; /** For the SPCv controller: 3076285242Sachim Bit 0: Indirect Response (IR). This indicates 3077285242Sachim direct or indirect mode for SMP response frame 3078285242Sachim to be received. 3079285242Sachim 0b: Direct mode 3080285242Sachim 1b: Indirect mode 3081285242Sachim 3082285242Sachim Bit 1: Indirect Payload (IP). This indicates 3083285242Sachim direct or indirect mode for SMP request frame 3084285242Sachim to be sent. 3085285242Sachim 0b: Direct mode 3086285242Sachim 1b: Indirect mode 3087285242Sachim 3088285242Sachim Bits 2-31: Reserved 3089285242Sachim For the SPC controller: This is not applicable. 3090285242Sachim */ 3091285242Sachim 3092285242Sachim} agsaSMPFrame_t; 3093285242Sachim 3094285242Sachim#define smpFrameFlagDirectResponse 0 3095285242Sachim#define smpFrameFlagIndirectResponse 1 3096285242Sachim#define smpFrameFlagDirectPayload 0 3097285242Sachim#define smpFrameFlagIndirectPayload 2 3098285242Sachim 3099285242Sachim/** \brief union data structure specifies a request 3100285242Sachim * 3101285242Sachim * union data structure specifies a request 3102285242Sachim */ 3103285242Sachimtypedef union agsaSASRequestBody_u 3104285242Sachim{ 3105285242Sachim agsaSSPInitiatorRequest_t sspInitiatorReq; /**< Structure containing the SSP initiator request, Support up to 16 bytes CDB */ 3106285242Sachim agsaSSPInitiatorRequestExt_t sspInitiatorReqExt; /**< Structure containing the SSP initiator request for CDB > 16 bytes */ 3107285242Sachim agsaSSPInitiatorRequestIndirect_t sspInitiatorReqIndirect; /**< Structure containing the SSP indirect initiator request */ 3108285242Sachim agsaSSPTargetRequest_t sspTargetReq; /**< Structure containing the SSP Target request */ 3109285242Sachim agsaSSPScsiTaskMgntReq_t sspTaskMgntReq; /**< Structure containing the SSP SCSI Task Management request */ 3110285242Sachim agsaSSPTargetResponse_t sspTargetResponse; /**< Structure containing the SSP Target response. */ 3111285242Sachim agsaSMPFrame_t smpFrame; /**< Structure containing SMP request or response frame */ 3112285242Sachim}agsaSASRequestBody_t; 3113285242Sachim 3114285242Sachim 3115285242Sachim 3116285242Sachim 3117285242Sachim/** \brief data structure describes an STP or direct connect SATA command 3118285242Sachim * 3119285242Sachim * The agsaSATAInitiatorRequest_t data structure describes an STP or direct 3120285242Sachim * connect SATA command request to be sent to the device and 3121285242Sachim * passed as a parameter to saSATAStart() function. 3122285242Sachim * 3123285242Sachim * This structure is an encapsulation of SATA FIS (Frame Information 3124285242Sachim * Structures), which enables the execution of ATA command 3125285242Sachim * descriptor using SATA transport 3126285242Sachim * 3127285242Sachim */ 3128285242Sachimtypedef struct agsaSATAInitiatorRequest_s 3129285242Sachim{ 3130285242Sachim agsaSgl_t agSgl; /**< This structure is used to define either an ESGL 3131285242Sachim list or a single SGL for operation that involves 3132285242Sachim DMA transfer */ 3133285242Sachim 3134285242Sachim bit32 dataLength; /**< Total data length in bytes */ 3135285242Sachim 3136285242Sachim bit32 option; /**< Operational option, defined using the bit field. 3137285242Sachim b7-1: reserved 3138285242Sachim b0: AGSA-STP-CLOSE-CLEAR-AFFILIATION */ 3139285242Sachim 3140285242Sachim agsaSATAHostFis_t fis; /**< The FIS request */ 3141285242Sachim agsaDif_t dif; 3142285242Sachim agsaEncrypt_t encrypt; 3143285242Sachim bit8 scsiCDB[16]; 3144285242Sachim#ifdef SA_TESTBASE_EXTRA 3145285242Sachim /* Added by TestBase */ 3146285242Sachim bit16 bstIndex; 3147285242Sachim#endif /* SA_TESTBASE_EXTRA */ 3148285242Sachim} agsaSATAInitiatorRequest_t; 3149285242Sachim 3150285242Sachim 3151285242Sachim/* controller Configuration page */ 3152285242Sachim#define AGSA_SAS_PROTOCOL_TIMER_CONFIG_PAGE 0x04 3153285242Sachim#define AGSA_INTERRUPT_CONFIGURATION_PAGE 0x05 3154285242Sachim#define AGSA_IO_GENERAL_CONFIG_PAGE 0x06 3155285242Sachim#define AGSA_ENCRYPTION_GENERAL_CONFIG_PAGE 0x20 3156285242Sachim#define AGSA_ENCRYPTION_DEK_CONFIG_PAGE 0x21 3157285242Sachim#define AGSA_ENCRYPTION_CONTROL_PARM_PAGE 0x22 3158285242Sachim#define AGSA_ENCRYPTION_HMAC_CONFIG_PAGE 0x23 3159285242Sachim 3160285242Sachim#ifdef HIALEAH_ENCRYPTION 3161285242Sachimtypedef struct agsaEncryptGeneralPage_s { 3162285242Sachim bit32 numberOfKeksPageCode; /* 0x20 */ 3163285242Sachim bit32 KeyCardIdKekIndex; 3164285242Sachim bit32 KeyCardId3_0; 3165285242Sachim bit32 KeyCardId7_4; 3166285242Sachim bit32 KeyCardId11_8; 3167285242Sachim} agsaEncryptGeneralPage_t; 3168285242Sachim#else 3169285242Sachimtypedef struct agsaEncryptGeneralPage_s { 3170285242Sachim bit32 pageCode; /* 0x20 */ 3171285242Sachim bit32 numberOfDeks; 3172285242Sachim} agsaEncryptGeneralPage_t; 3173285242Sachim#endif /* HIALEAH_ENCRYPTION */ 3174285242Sachim 3175285242Sachim#define AGSA_ENC_CONFIG_PAGE_KEK_NUMBER 0x0000FF00 3176285242Sachim#define AGSA_ENC_CONFIG_PAGE_KEK_SHIFT 8 3177285242Sachim 3178285242Sachim/* sTSDK 4.14 */ 3179285242Sachimtypedef struct agsaEncryptDekConfigPage_s { 3180285242Sachim bit32 pageCode; 3181285242Sachim bit32 table0AddrLo; 3182285242Sachim bit32 table0AddrHi; 3183285242Sachim bit32 table0Entries; 3184285242Sachim bit32 table0BFES; 3185285242Sachim bit32 table1AddrLo; 3186285242Sachim bit32 table1AddrHi; 3187285242Sachim bit32 table1Entries; 3188285242Sachim bit32 table1BFES; 3189285242Sachim} agsaEncryptDekConfigPage_t; 3190285242Sachim 3191285242Sachim#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_TABLE_NUMBER 0xF0000000 3192285242Sachim#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_TABLE_SHIFT SHIFT28 3193285242Sachim#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_CACHE_WAY 0x0F000000 3194285242Sachim#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_CACHE_SHIFT SHIFT24 3195285242Sachim 3196285242Sachim/*sTSDK 4.18 */ 3197285242Sachim/* CCS (Current Crypto Services) and NOPR (Number of Operators) are valid only in GET_CONTROLLER_CONFIG */ 3198285242Sachim/* NAR, CORCAP and USRCAP are valid only when AUT==1 */ 3199285242Sachimtypedef struct agsaEncryptControlParamPage_s { 3200285242Sachim bit32 pageCode; /* 0x22 */ 3201285242Sachim bit32 CORCAP; /* Crypto Officer Role Capabilities */ 3202285242Sachim bit32 USRCAP; /* User Role Capabilities */ 3203285242Sachim bit32 CCS; /* Current Crypto Services */ 3204285242Sachim bit32 NOPR; /* Number of Operators */ 3205285242Sachim} agsaEncryptControlParamPage_t; 3206285242Sachim 3207285242Sachimtypedef struct agsaEncryptInfo_s { 3208285242Sachim bit32 encryptionCipherMode; 3209285242Sachim bit32 encryptionSecurityMode; 3210285242Sachim bit32 status; 3211285242Sachim bit32 flag; 3212285242Sachim} agsaEncryptInfo_t; 3213285242Sachim 3214285242Sachim 3215285242Sachim#define OperatorAuthenticationEnable_AUT 1 3216285242Sachim#define ReturnToFactoryMode_ARF 2 3217285242Sachim 3218285242Sachim/*sTSDK 4.19 */ 3219285242Sachimtypedef struct agsaEncryptSelfTestBitMap_s { 3220285242Sachim bit32 AES_Test; 3221285242Sachim bit32 KEY_WRAP_Test; 3222285242Sachim bit32 HMAC_Test; 3223285242Sachim} agsaEncryptSelfTestBitMap_t; 3224285242Sachim 3225285242Sachimtypedef struct agsaEncryptSelfTestStatusBitMap_s{ 3226285242Sachim bit32 AES_Status; 3227285242Sachim bit32 KEY_WRAP_Status; 3228285242Sachim bit32 HMAC_Status; 3229285242Sachim} agsaEncryptSelfTestStatusBitMap_t; 3230285242Sachim 3231285242Sachimtypedef struct agsaEncryptHMACTestDescriptor_s 3232285242Sachim{ 3233285242Sachim bit32 Dword0; 3234285242Sachim bit32 MsgAddrLo; 3235285242Sachim bit32 MsgAddrHi; 3236285242Sachim bit32 MsgLen; 3237285242Sachim bit32 DigestAddrLo; 3238285242Sachim bit32 DigestAddrHi; 3239285242Sachim bit32 KeyAddrLo; 3240285242Sachim bit32 KeyAddrHi; 3241285242Sachim bit32 KeyLen; 3242285242Sachim} agsaEncryptHMACTestDescriptor_t; 3243285242Sachim 3244285242Sachimtypedef struct agsaEncryptHMACTestResult_s 3245285242Sachim{ 3246285242Sachim bit32 Dword0; 3247285242Sachim bit32 Dword[12]; 3248285242Sachim} agsaEncryptHMACTestResult_t; 3249285242Sachim 3250285242Sachimtypedef struct agsaEncryptSHATestDescriptor_s 3251285242Sachim{ 3252285242Sachim bit32 Dword0; 3253285242Sachim bit32 MsgAddrLo; 3254285242Sachim bit32 MsgAddrHi; 3255285242Sachim bit32 MsgLen; 3256285242Sachim bit32 DigestAddrLo; 3257285242Sachim bit32 DigestAddrHi; 3258285242Sachim} agsaEncryptSHATestDescriptor_t; 3259285242Sachim 3260285242Sachimtypedef struct agsaEncryptSHATestResult_s 3261285242Sachim{ 3262285242Sachim bit32 Dword0; 3263285242Sachim bit32 Dword[12]; 3264285242Sachim} agsaEncryptSHATestResult_t; 3265285242Sachim 3266285242Sachim/* types of self test */ 3267285242Sachim#define AGSA_BIST_TEST 0x1 3268285242Sachim#define AGSA_HMAC_TEST 0x2 3269285242Sachim#define AGSA_SHA_TEST 0x3 3270285242Sachim 3271285242Sachim 3272285242Sachim/*sTSDK 4.13 */ 3273285242Sachimtypedef struct agsaEncryptDekBlob_s { 3274285242Sachim bit8 dekBlob[80]; 3275285242Sachim} agsaEncryptDekBlob_t; 3276285242Sachim 3277285242Sachimtypedef struct agsaEncryptKekBlob_s { 3278285242Sachim bit8 kekBlob[48]; 3279285242Sachim} agsaEncryptKekBlob_t; 3280285242Sachim 3281285242Sachim/*sTSDK 4.45 */ 3282285242Sachimtypedef struct agsaEncryptHMACConfigPage_s 3283285242Sachim{ 3284285242Sachim bit32 PageCode; 3285285242Sachim bit32 CustomerTag; 3286285242Sachim bit32 KeyAddrLo; 3287285242Sachim bit32 KeyAddrHi; 3288285242Sachim} agsaEncryptHMACConfigPage_t; 3289285242Sachim 3290285242Sachim/*sTSDK 4.38 */ 3291285242Sachim#define AGSA_ID_SIZE 31 3292285242Sachimtypedef struct agsaID_s { 3293285242Sachim bit8 ID[AGSA_ID_SIZE]; 3294285242Sachim}agsaID_t; 3295285242Sachim 3296285242Sachim 3297285242Sachim#define SA_OPR_MGMNT_FLAG_MASK 0x00003000 3298285242Sachim#define SA_OPR_MGMNT_FLAG_SHIFT 12 3299285242Sachim 3300285242Sachim/* */ 3301285242Sachimtypedef struct agsaSASPhyMiscPage_s { 3302285242Sachim bit32 Dword0; 3303285242Sachim bit32 Dword1; 3304285242Sachim} agsaSASPhyMiscPage_t ; 3305285242Sachim 3306285242Sachim 3307285242Sachimtypedef struct agsaHWEventEncrypt_s { 3308285242Sachim bit32 encryptOperation; 3309285242Sachim bit32 status; 3310285242Sachim bit32 eq; /* error qualifier */ 3311285242Sachim bit32 info; 3312285242Sachim void *handle; 3313285242Sachim void *param; 3314285242Sachim} agsaHWEventEncrypt_t; 3315285242Sachim 3316285242Sachim/*sTSDK 4.32 */ 3317285242Sachimtypedef struct agsaHWEventMode_s { 3318285242Sachim bit32 modePageOperation; 3319285242Sachim bit32 status; 3320285242Sachim bit32 modePageLen; 3321285242Sachim void *modePage; 3322285242Sachim void *context; 3323285242Sachim} agsaHWEventMode_t; 3324285242Sachim 3325285242Sachim/*sTSDK 4.33 */ 3326285242Sachimtypedef struct agsaInterruptConfigPage_s { 3327285242Sachim bit32 pageCode; 3328285242Sachim bit32 vectorMask0; 3329285242Sachim bit32 vectorMask1; 3330285242Sachim bit32 ICTC0; 3331285242Sachim bit32 ICTC1; 3332285242Sachim bit32 ICTC2; 3333285242Sachim bit32 ICTC3; 3334285242Sachim bit32 ICTC4; 3335285242Sachim bit32 ICTC5; 3336285242Sachim bit32 ICTC6; 3337285242Sachim bit32 ICTC7; 3338285242Sachim} agsaInterruptConfigPage_t; 3339285242Sachimtypedef struct agsaIoGeneralPage_s { 3340285242Sachim bit32 pageCode; /* 0x06 */ 3341285242Sachim bit32 ActiveMask; 3342285242Sachim bit32 QrntTime; 3343285242Sachim} agsaIoGeneralPage_t; 3344285242Sachim 3345285242Sachim/* \brief data structure defines detail information about Agilent Error 3346285242Sachim* Detection Code (DIF) errors. 3347285242Sachim* 3348285242Sachim* The agsaDifDetails_t data structure defines detail information about 3349285242Sachim* PMC Error Detection Code (DIF) error. Please refer to the latest T10 SBC 3350285242Sachim* and SPC draft/specification for the definition of the Protection 3351285242Sachim* Information. 3352285242Sachim* 3353285242Sachim* This structure is filled by the function saGetDifErrorDetails(). 3354285242Sachim*/ 3355285242Sachim 3356285242Sachimtypedef struct agsaDifDetails_s { 3357285242Sachim bit32 UpperLBA; 3358285242Sachim bit32 LowerLBA; 3359285242Sachim bit8 sasAddressHi[4]; 3360285242Sachim bit8 sasAddressLo[4]; 3361285242Sachim bit32 ExpectedCRCUDT01; 3362285242Sachim bit32 ExpectedUDT2345; 3363285242Sachim bit32 ActualCRCUDT01; 3364285242Sachim bit32 ActualUDT2345; 3365285242Sachim bit32 DIFErrDevID; 3366285242Sachim bit32 ErrBoffsetEDataLen; 3367285242Sachim void * frame; 3368285242Sachim} agsaDifDetails_t; 3369285242Sachim 3370285242Sachim/** \brief data structure for SAS protocol timer configuration page. 3371285242Sachim * 3372285242Sachim */ 3373285242Sachimtypedef struct agsaSASProtocolTimerConfigurationPage_s{ 3374285242Sachim bit32 pageCode; /* 0 */ 3375285242Sachim bit32 MST_MSI; /* 1 */ 3376285242Sachim bit32 STP_SSP_MCT_TMO; /* 2 */ 3377285242Sachim bit32 STP_FRM_TMO; /* 3 */ 3378285242Sachim bit32 STP_IDLE_TMO; /* 4 */ 3379285242Sachim bit32 OPNRJT_RTRY_INTVL; /* 5 */ 3380285242Sachim bit32 Data_Cmd_OPNRJT_RTRY_TMO; /* 6 */ 3381285242Sachim bit32 Data_Cmd_OPNRJT_RTRY_THR; /* 7 */ 3382285242Sachim bit32 MAX_AIP; /* 8 */ 3383285242Sachim} agsaSASProtocolTimerConfigurationPage_t; 3384285242Sachim 3385285242Sachim 3386285242Sachim/** \brief data structure for firmware flash update saFwFlashUpdate(). 3387285242Sachim * 3388285242Sachim * The agsaUpdateFwFlash data structure specifies a request to saFwFlashUpdate() 3389285242Sachim */ 3390285242Sachimtypedef struct agsaUpdateFwFlash_s 3391285242Sachim{ 3392285242Sachim bit32 currentImageOffset; 3393285242Sachim bit32 currentImageLen; 3394285242Sachim bit32 totalImageLen; 3395285242Sachim agsaSgl_t agSgl; 3396285242Sachim} agsaUpdateFwFlash_t; 3397285242Sachim 3398285242Sachim 3399285242Sachim 3400285242Sachim/** \brief data structure for extended firmware flash update saFwFlashExtUpdate(). 3401285242Sachim * 3402285242Sachim * The agsaFlashExtExecute_s data structure specifies a request to saFwFlashExtUpdate() 3403285242Sachim */ 3404285242Sachimtypedef struct agsaFlashExtExecute_s 3405285242Sachim{ 3406285242Sachim bit32 command; 3407285242Sachim bit32 partOffset; 3408285242Sachim bit32 dataLen; 3409285242Sachim agsaSgl_t *agSgl; 3410285242Sachim} agsaFlashExtExecute_t; 3411285242Sachim 3412285242Sachim 3413285242Sachim/** \brief data structure for firmware flash update saFwFlashUpdate(). 3414285242Sachim * 3415285242Sachim * The agsaFlashExtResponse_t data structure specifies a request to ossaFlashExtExecuteCB().() 3416285242Sachim */ 3417285242Sachimtypedef struct agsaFlashExtResponse_s 3418285242Sachim{ 3419285242Sachim bit32 epart_size; 3420285242Sachim bit32 epart_sect_size; 3421285242Sachim} agsaFlashExtResponse_t; 3422285242Sachim 3423285242Sachim 3424285242Sachim/** \brief data structure for set fields in MPI table. 3425285242Sachim * The agsaMPIContext_t data structure is used to set fields in MPI table. 3426285242Sachim * For details of MPI table, refer to PM8001 Tachyon SPC 8x6G Programmers' 3427285242Sachim * Manual PMC-2080222 or PM8008/PM8009/PM8018 Tachyon SPCv/SPCve/SPCv+ Programmers Manual 3428285242Sachim * PMC-2091148/PMC-2102373. 3429285242Sachim sTSDK section 4.39 3430285242Sachim */ 3431285242Sachim 3432285242Sachimtypedef struct agsaMPIContext_s 3433285242Sachim{ 3434285242Sachim bit32 MPITableType; 3435285242Sachim bit32 offset; 3436285242Sachim bit32 value; 3437285242Sachim} agsaMPIContext_t; 3438285242Sachim 3439285242Sachim#define AGSA_MPI_MAIN_CONFIGURATION_TABLE 1 3440285242Sachim#define AGSA_MPI_GENERAL_STATUS_TABLE 2 3441285242Sachim#define AGSA_MPI_INBOUND_QUEUE_CONFIGURATION_TABLE 3 3442285242Sachim#define AGSA_MPI_OUTBOUND_QUEUE_CONFIGURATION_TABLE 4 3443285242Sachim#define AGSA_MPI_SAS_PHY_ANALOG_SETUP_TABLE 5 3444285242Sachim#define AGSA_MPI_INTERRUPT_VECTOR_TABLE 6 3445285242Sachim#define AGSA_MPI_PER_SAS_PHY_ATTRIBUTE_TABLE 7 3446285242Sachim#define AGSA_MPI_OUTBOUND_QUEUE_FAILOVER_TABLE 8 3447285242Sachim 3448285242Sachim 3449285242Sachim/************************************************************/ 3450285242Sachim/*This flag and datastructure are specific for fw profiling, Now defined as compiler flag*/ 3451285242Sachim//#define SPC_ENABLE_PROFILE 3452285242Sachim 3453285242Sachim#ifdef SPC_ENABLE_PROFILE 3454285242Sachimtypedef struct agsaFwProfile_s 3455285242Sachim{ 3456285242Sachim bit32 tcid; 3457285242Sachim bit32 processor; 3458285242Sachim bit32 cmd; 3459285242Sachim bit32 len; 3460285242Sachim bit32 codeStartAdd; 3461285242Sachim bit32 codeEndAdd; 3462285242Sachim agsaSgl_t agSgl; 3463285242Sachim} agsaFwProfile_t; 3464285242Sachim#endif 3465285242Sachim/************************************************************/ 3466285242Sachim/** \brief Callback definition for .ossaDeviceRegistration 3467285242Sachim * 3468285242Sachim */ 3469285242Sachimtypedef void (*ossaDeviceRegistrationCB_t)( 3470285242Sachim agsaRoot_t *agRoot, 3471285242Sachim agsaContext_t *agContext, 3472285242Sachim bit32 status, 3473285242Sachim agsaDevHandle_t *agDevHandle, 3474285242Sachim bit32 deviceID 3475285242Sachim ); 3476285242Sachim 3477285242Sachim/** \brief Callback definition for 3478285242Sachim * 3479285242Sachim */ 3480285242Sachimtypedef void (*ossaDeregisterDeviceHandleCB_t)( 3481285242Sachim agsaRoot_t *agRoot, 3482285242Sachim agsaContext_t *agContext, 3483285242Sachim agsaDevHandle_t *agDevHandle, 3484285242Sachim bit32 status 3485285242Sachim ); 3486285242Sachim 3487285242Sachim/** \brief Callback definition for 3488285242Sachim * 3489285242Sachim */ 3490285242Sachimtypedef void (*ossaGenericCB_t)(void); 3491285242Sachim 3492285242Sachim 3493285242Sachim/** \brief Callback definition for abort SMP SSP SATA callback 3494285242Sachim * 3495285242Sachim */ 3496285242Sachimtypedef void (*ossaGenericAbortCB_t)( 3497285242Sachim agsaRoot_t *agRoot, 3498285242Sachim agsaIORequest_t *agIORequest, 3499285242Sachim bit32 flag, 3500285242Sachim bit32 status 3501285242Sachim ); 3502285242Sachim 3503285242Sachim 3504285242Sachimtypedef void (*ossaLocalPhyControlCB_t)( 3505285242Sachim agsaRoot_t *agRoot, 3506285242Sachim agsaContext_t *agContext, 3507285242Sachim bit32 phyId, 3508285242Sachim bit32 phyOperation, 3509285242Sachim bit32 status, 3510285242Sachim void *parm 3511285242Sachim ); 3512285242Sachim 3513285242Sachim 3514285242Sachim/** \brief Callback definition for 3515285242Sachim * 3516285242Sachim */ 3517285242Sachimtypedef void (*ossaSATACompletedCB_t)( 3518285242Sachim agsaRoot_t *agRoot, 3519285242Sachim agsaIORequest_t *agIORequest, 3520285242Sachim bit32 agIOStatus, 3521285242Sachim void *agFirstDword, 3522285242Sachim bit32 agIOInfoLen, 3523285242Sachim void *agParam 3524285242Sachim ); 3525285242Sachim 3526285242Sachim 3527285242Sachim/** \brief Callback definition for 3528285242Sachim * 3529285242Sachim */ 3530285242Sachimtypedef void (*ossaSMPCompletedCB_t)( 3531285242Sachim agsaRoot_t *agRoot, 3532285242Sachim agsaIORequest_t *agIORequest, 3533285242Sachim bit32 agIOStatus, 3534285242Sachim bit32 agIOInfoLen, 3535285242Sachim agsaFrameHandle_t agFrameHandle 3536285242Sachim ); 3537285242Sachim 3538285242Sachim 3539285242Sachim/** \brief Callback definition for 3540285242Sachim * 3541285242Sachim */ 3542285242Sachimtypedef void (*ossaSSPCompletedCB_t)( 3543285242Sachim agsaRoot_t *agRoot, 3544285242Sachim agsaIORequest_t *agIORequest, 3545285242Sachim bit32 agIOStatus, 3546285242Sachim bit32 agIOInfoLen, 3547285242Sachim void *agParam, 3548285242Sachim bit16 sspTag, 3549285242Sachim bit32 agOtherInfo 3550285242Sachim ); 3551285242Sachim 3552285242Sachim/** \brief Callback definition for 3553285242Sachim * 3554285242Sachim */ 3555285242Sachimtypedef void (*ossaSetDeviceInfoCB_t) ( 3556285242Sachim agsaRoot_t *agRoot, 3557285242Sachim agsaContext_t *agContext, 3558285242Sachim agsaDevHandle_t *agDevHandle, 3559285242Sachim bit32 status, 3560285242Sachim bit32 option, 3561285242Sachim bit32 param 3562285242Sachim ); 3563285242Sachim 3564285242Sachimtypedef struct agsaOffloadDifDetails_s 3565285242Sachim{ 3566285242Sachim bit32 ExpectedCRCUDT01; 3567285242Sachim bit32 ExpectedUDT2345; 3568285242Sachim bit32 ActualCRCUDT01; 3569285242Sachim bit32 ActualUDT2345; 3570285242Sachim bit32 DIFErr; 3571285242Sachim bit32 ErrBoffset; 3572285242Sachim} agsaOffloadDifDetails_t; 3573285242Sachim 3574285242Sachimtypedef struct agsaDifEncPayload_s 3575285242Sachim{ 3576285242Sachim agsaSgl_t SrcSgl; 3577285242Sachim bit32 SrcDL; 3578285242Sachim agsaSgl_t DstSgl; 3579285242Sachim bit32 DstDL; 3580285242Sachim agsaDif_t dif; 3581285242Sachim agsaEncrypt_t encrypt; 3582285242Sachim} agsaDifEncPayload_t; 3583285242Sachim 3584285242Sachimtypedef void (*ossaVhistCaptureCB_t) ( 3585285242Sachim agsaRoot_t *agRoot, 3586285242Sachim agsaContext_t *agContext, 3587285242Sachim bit32 status, 3588285242Sachim bit32 len); 3589285242Sachim 3590285242Sachimtypedef void (*ossaDIFEncryptionOffloadStartCB_t) ( 3591285242Sachim agsaRoot_t *agRoot, 3592285242Sachim agsaContext_t *agContext, 3593285242Sachim bit32 status, 3594285242Sachim agsaOffloadDifDetails_t *agsaOffloadDifDetails 3595285242Sachim ); 3596285242Sachim 3597285242Sachim#define SA_RESERVED_REQUEST_COUNT 16 3598285242Sachim 3599285242Sachim#ifdef SA_FW_TIMER_READS_STATUS 3600285242Sachim#define SA_FW_TIMER_READS_STATUS_INTERVAL 20 3601285242Sachim#endif /* SA_FW_TIMER_READS_STATUS */ 3602285242Sachim 3603285242Sachim#define SIZE_DW 4 /**< Size in bytes */ 3604285242Sachim#define SIZE_QW 8 /**< Size in bytes */ 3605285242Sachim 3606285242Sachim#define PCIBAR0 0 /**< PCI Base Address 0 */ 3607285242Sachim#define PCIBAR1 1 /**< PCI Base Address 1 */ 3608285242Sachim#define PCIBAR2 2 /**< PCI Base Address 2 */ 3609285242Sachim#define PCIBAR3 3 /**< PCI Base Address 3 */ 3610285242Sachim#define PCIBAR4 4 /**< PCI Base Address 4 */ 3611285242Sachim#define PCIBAR5 5 /**< PCI Base Address 5 */ 3612285242Sachim 3613285242Sachim/** \brief describe an element of SPC-SPCV converter 3614285242Sachim * 3615285242Sachim * This structure is used 3616285242Sachim * 3617285242Sachim */ 3618285242Sachimtypedef struct agsaBarOffset_s 3619285242Sachim{ 3620285242Sachim bit32 Generic; /* */ 3621285242Sachim bit32 Bar; /* */ 3622285242Sachim bit32 Offset; /* */ 3623285242Sachim bit32 Length; /* */ 3624285242Sachim} agsaBarOffset_t; 3625285242Sachim 3626285242Sachimtypedef union agsabit32bit64_U 3627285242Sachim{ 3628285242Sachim bit32 S32[2]; 3629285242Sachim bit64 B64; 3630285242Sachim} agsabit32bit64; 3631285242Sachim 3632285242Sachim/* 3633285242SachimThe agsaIOErrorEventStats_t data structure is used as parameter in ossaGetIOErrorStatsCB(),ossaGetIOEventStatsCB(). 3634285242SachimThis data structure contains the number of IO error and event. 3635285242Sachim*/ 3636285242Sachimtypedef struct agsaIOErrorEventStats_s 3637285242Sachim{ 3638285242Sachim bit32 agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS; 3639285242Sachim bit32 agOSSA_IO_ABORTED; 3640285242Sachim bit32 agOSSA_IO_OVERFLOW; 3641285242Sachim bit32 agOSSA_IO_UNDERFLOW; 3642285242Sachim bit32 agOSSA_IO_FAILED; 3643285242Sachim bit32 agOSSA_IO_ABORT_RESET; 3644285242Sachim bit32 agOSSA_IO_NOT_VALID; 3645285242Sachim bit32 agOSSA_IO_NO_DEVICE; 3646285242Sachim bit32 agOSSA_IO_ILLEGAL_PARAMETER; 3647285242Sachim bit32 agOSSA_IO_LINK_FAILURE; 3648285242Sachim bit32 agOSSA_IO_PROG_ERROR; 3649285242Sachim bit32 agOSSA_IO_DIF_IN_ERROR; 3650285242Sachim bit32 agOSSA_IO_DIF_OUT_ERROR; 3651285242Sachim bit32 agOSSA_IO_ERROR_HW_TIMEOUT; 3652285242Sachim bit32 agOSSA_IO_XFER_ERROR_BREAK; 3653285242Sachim bit32 agOSSA_IO_XFER_ERROR_PHY_NOT_READY; 3654285242Sachim bit32 agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED; 3655285242Sachim bit32 agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION; 3656285242Sachim bit32 agOSSA_IO_OPEN_CNX_ERROR_BREAK; 3657285242Sachim bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS; 3658285242Sachim bit32 agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION; 3659285242Sachim bit32 agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED; 3660285242Sachim bit32 agOSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY; 3661285242Sachim bit32 agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION; 3662285242Sachim bit32 agOSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR; 3663285242Sachim bit32 agOSSA_IO_XFER_ERROR_NAK_RECEIVED; 3664285242Sachim bit32 agOSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT; 3665285242Sachim bit32 agOSSA_IO_XFER_ERROR_PEER_ABORTED; 3666285242Sachim bit32 agOSSA_IO_XFER_ERROR_RX_FRAME; 3667285242Sachim bit32 agOSSA_IO_XFER_ERROR_DMA; 3668285242Sachim bit32 agOSSA_IO_XFER_ERROR_CREDIT_TIMEOUT; 3669285242Sachim bit32 agOSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT; 3670285242Sachim bit32 agOSSA_IO_XFER_ERROR_SATA; 3671285242Sachim bit32 agOSSA_IO_XFER_ERROR_ABORTED_DUE_TO_SRST; 3672285242Sachim bit32 agOSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE; 3673285242Sachim bit32 agOSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE; 3674285242Sachim bit32 agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT; 3675285242Sachim bit32 agOSSA_IO_XFER_SMP_RESP_CONNECTION_ERROR; 3676285242Sachim bit32 agOSSA_IO_XFER_ERROR_UNEXPECTED_PHASE; 3677285242Sachim bit32 agOSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN; 3678285242Sachim bit32 agOSSA_IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED; 3679285242Sachim bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT; 3680285242Sachim bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK; 3681285242Sachim bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK; 3682285242Sachim bit32 agOSSA_IO_XFER_ERROR_OFFSET_MISMATCH; 3683285242Sachim bit32 agOSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN; 3684285242Sachim bit32 agOSSA_IO_XFER_CMD_FRAME_ISSUED; 3685285242Sachim bit32 agOSSA_IO_ERROR_INTERNAL_SMP_RESOURCE; 3686285242Sachim bit32 agOSSA_IO_PORT_IN_RESET; 3687285242Sachim bit32 agOSSA_IO_DS_NON_OPERATIONAL; 3688285242Sachim bit32 agOSSA_IO_DS_IN_RECOVERY; 3689285242Sachim bit32 agOSSA_IO_TM_TAG_NOT_FOUND; 3690285242Sachim bit32 agOSSA_IO_XFER_PIO_SETUP_ERROR; 3691285242Sachim bit32 agOSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR; 3692285242Sachim bit32 agOSSA_IO_DS_IN_ERROR; 3693285242Sachim bit32 agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY; 3694285242Sachim bit32 agOSSA_IO_ABORT_IN_PROGRESS; 3695285242Sachim bit32 agOSSA_IO_ABORT_DELAYED; 3696285242Sachim bit32 agOSSA_IO_INVALID_LENGTH; 3697285242Sachim bit32 agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT; 3698285242Sachim bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED; 3699285242Sachim bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO; 3700285242Sachim bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST; 3701285242Sachim bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE; 3702285242Sachim bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED; 3703285242Sachim bit32 agOSSA_IO_DS_INVALID; 3704285242Sachim bit32 agOSSA_IO_XFER_READ_COMPL_ERR; 3705285242Sachim bit32 agOSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR; 3706285242Sachim bit32 agOSSA_IO_XFR_ERROR_INTERNAL_CRC_ERROR; 3707285242Sachim bit32 agOSSA_MPI_IO_RQE_BUSY_FULL; 3708285242Sachim bit32 agOSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE; 3709285242Sachim bit32 agOSSA_MPI_ERR_ATAPI_DEVICE_BUSY; 3710285242Sachim bit32 agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS; 3711285242Sachim bit32 agOSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH; 3712285242Sachim bit32 agOSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID; 3713285242Sachim bit32 agOSSA_IO_XFR_ERROR_DEK_IV_MISMATCH; 3714285242Sachim bit32 agOSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR; 3715285242Sachim bit32 agOSSA_IO_XFR_ERROR_INTERNAL_RAM; 3716285242Sachim bit32 agOSSA_IO_XFR_ERROR_DIF_MISMATCH; 3717285242Sachim bit32 agOSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH; 3718285242Sachim bit32 agOSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH; 3719285242Sachim bit32 agOSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH; 3720285242Sachim bit32 agOSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME; 3721285242Sachim bit32 agOSSA_IO_XFER_ERR_EOB_DATA_OVERRUN; 3722285242Sachim bit32 agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS; 3723285242Sachim bit32 agOSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED; 3724285242Sachim bit32 agOSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE; 3725285242Sachim bit32 agOSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR; 3726285242Sachim bit32 agOSSA_MPI_ERR_OFFLOAD_DIF_OR_ENC_NOT_ENABLED; 3727285242Sachim bit32 agOSSA_IO_XFER_ERROR_DMA_ACTIVATE_TIMEOUT; 3728285242Sachim bit32 agOSSA_IO_UNKNOWN_ERROR; 3729285242Sachim} agsaIOErrorEventStats_t; 3730285242Sachim 3731285242Sachim 3732285242Sachim/************************************************************************************ 3733285242Sachim * * 3734285242Sachim * Data Structures Defined for LL API ends * 3735285242Sachim * * 3736285242Sachim ************************************************************************************/ 3737285242Sachim#ifdef SALL_API_TEST 3738285242Sachimtypedef struct agsaIOCountInfo_s 3739285242Sachim{ 3740285242Sachim bit32 numSSPStarted; // saSSPStart() 3741285242Sachim bit32 numSSPAborted; // saSSPAbort() 3742285242Sachim bit32 numSSPAbortedCB; // ossaSSPAbortCB() 3743285242Sachim bit32 numSSPCompleted; // includes success and aborted IOs 3744285242Sachim bit32 numSMPStarted; // saSMPStart() 3745285242Sachim bit32 numSMPAborted; // saSMPAbort() 3746285242Sachim bit32 numSMPAbortedCB; // ossaSMPAbortCB() 3747285242Sachim bit32 numSMPCompleted; // includes success and aborted IOs 3748285242Sachim bit32 numSataStarted; // saSATAStart() 3749285242Sachim bit32 numSataAborted; // saSATAAbort() 3750285242Sachim bit32 numSataAbortedCB; // ossaSATAAbortCB() 3751285242Sachim bit32 numSataCompleted; // includes success and aborted IOs 3752285242Sachim bit32 numEchoSent; // saEchoCommand() 3753285242Sachim bit32 numEchoCB; // ossaEchoCB() 3754285242Sachim bit32 numUNKNWRespIOMB; // unknow Response IOMB received 3755285242Sachim bit32 numOurIntCount; //InterruptHandler() counter 3756285242Sachim bit32 numSpuriousInt; //spurious interrupts 3757285242Sachim// bit32 numSpInts[64]; //spuriours interrupts count for each OBQ (PI=CI) 3758285242Sachim// bit32 numSpInts1[64]; //spuriours interrupts count for each OBQ (PI!=CI) 3759285242Sachim} agsaIOCountInfo_t; 3760285242Sachim 3761285242Sachim/* Total IO Counter */ 3762285242Sachim#define LL_COUNTERS 17 3763285242Sachim/* Counter Bit Map */ 3764285242Sachim#define COUNTER_SSP_START 0x000001 3765285242Sachim#define COUNTER_SSP_ABORT 0x000002 3766285242Sachim#define COUNTER_SSPABORT_CB 0x000004 3767285242Sachim#define COUNTER_SSP_COMPLETEED 0x000008 3768285242Sachim#define COUNTER_SMP_START 0x000010 3769285242Sachim#define COUNTER_SMP_ABORT 0x000020 3770285242Sachim#define COUNTER_SMPABORT_CB 0x000040 3771285242Sachim#define COUNTER_SMP_COMPLETEED 0x000080 3772285242Sachim#define COUNTER_SATA_START 0x000100 3773285242Sachim#define COUNTER_SATA_ABORT 0x000200 3774285242Sachim#define COUNTER_SATAABORT_CB 0x000400 3775285242Sachim#define COUNTER_SATA_COMPLETEED 0x000800 3776285242Sachim#define COUNTER_ECHO_SENT 0x001000 3777285242Sachim#define COUNTER_ECHO_CB 0x002000 3778285242Sachim#define COUNTER_UNKWN_IOMB 0x004000 3779285242Sachim#define COUNTER_OUR_INT 0x008000 3780285242Sachim#define COUNTER_SPUR_INT 0x010000 3781285242Sachim#define ALL_COUNTERS 0xFFFFFF 3782285242Sachim 3783285242Sachimtypedef union agsaLLCountInfo_s 3784285242Sachim{ 3785285242Sachim agsaIOCountInfo_t IOCounter; 3786285242Sachim bit32 arrayIOCounter[LL_COUNTERS]; 3787285242Sachim} agsaLLCountInfo_t; 3788285242Sachim 3789285242Sachim#endif /* SALL_API_TEST */ 3790285242Sachim 3791285242Sachim#define MAX_IO_DEVICE_ENTRIES 4096 /**< Maximum Device Entries */ 3792285242Sachim 3793285242Sachim 3794285242Sachim#ifdef SA_ENABLE_POISION_TLP 3795285242Sachim#define SA_PTNFE_POISION_TLP 1 /* Enable if one */ 3796285242Sachim#else /* SA_ENABLE_POISION_TLP */ 3797285242Sachim#define SA_PTNFE_POISION_TLP 0 /* Disable if zero default setting */ 3798285242Sachim#endif /* SA_ENABLE_POISION_TLP */ 3799285242Sachim 3800285242Sachim#ifdef SA_DISABLE_MDFD 3801285242Sachim#define SA_MDFD_MULTI_DATA_FETCH 1 /* Disable if one */ 3802285242Sachim#else /* SA_DISABLE_MDFD */ 3803285242Sachim#define SA_MDFD_MULTI_DATA_FETCH 0 /* Enable if zero default setting */ 3804285242Sachim#endif /* SA_DISABLE_MDFD */ 3805285242Sachim 3806285242Sachim#ifdef SA_ENABLE_ARBTE 3807285242Sachim#define SA_ARBTE 1 /* Enable if one */ 3808285242Sachim#else /* SA_ENABLE_ARBTE */ 3809285242Sachim#define SA_ARBTE 0 /* Disable if zero default setting */ 3810285242Sachim#endif /* SA_ENABLE_ARBTE */ 3811285242Sachim 3812285242Sachim#ifdef SA_DISABLE_OB_COAL 3813285242Sachim#define SA_OUTBOUND_COALESCE 0 /* Disable if zero */ 3814285242Sachim#else /* SA_DISABLE_OB_COAL */ 3815285242Sachim#define SA_OUTBOUND_COALESCE 1 /* Enable if one default setting */ 3816285242Sachim#endif /* SA_DISABLE_OB_COAL */ 3817285242Sachim 3818285242Sachim 3819285242Sachim/*********************************************************************************** 3820285242Sachim * * 3821285242Sachim * The OS Layer Functions Declarations start * 3822285242Sachim * * 3823285242Sachim ***********************************************************************************/ 3824285242Sachim#include "saosapi.h" 3825285242Sachim/*********************************************************************************** 3826285242Sachim * * 3827285242Sachim * The OS Layer Functions Declarations end * 3828285242Sachim * * 3829285242Sachim ***********************************************************************************/ 3830285242Sachim 3831285242Sachim/*********************************************************************************** 3832285242Sachim * * 3833285242Sachim * The LL Layer Functions Declarations start * 3834285242Sachim * * 3835285242Sachim ***********************************************************************************/ 3836285242Sachim 3837285242Sachim#ifdef FAST_IO_TEST 3838285242Sachim/* needs to be allocated by the xPrepare() caller, one struct per IO */ 3839285242Sachimtypedef struct agsaFastCBBuf_s 3840285242Sachim{ 3841285242Sachim void *cb; 3842285242Sachim void *cbArg; 3843285242Sachim void *pSenseData; 3844285242Sachim bit8 *senseLen; 3845285242Sachim /* internal */ 3846285242Sachim void *oneDeviceData; /* tdsaDeviceData_t */ 3847285242Sachim} agsaFastCBBuf_t; 3848285242Sachim 3849285242Sachimtypedef struct agsaFastCommand_s 3850285242Sachim{ 3851285242Sachim /* in */ 3852285242Sachim void *agRoot; 3853285242Sachim /* modified by TD tiFastPrepare() */ 3854285242Sachim void *devHandle; /* agsaDevHandle_t* */ 3855285242Sachim void *agSgl; /* agsaSgl_t* */ 3856285242Sachim bit32 dataLength; 3857285242Sachim bit32 extDataLength; 3858285242Sachim bit8 additionalCdbLen; 3859285242Sachim bit8 *cdb; 3860285242Sachim bit8 *lun; 3861285242Sachim /* modified by TD tiFastPrepare() */ 3862285242Sachim bit8 taskAttribute; /* TD_xxx */ 3863285242Sachim bit16 flag; /* TLR_MASK */ 3864285242Sachim bit32 agRequestType; 3865285242Sachim bit32 queueNum; 3866285242Sachim agsaFastCBBuf_t *safb; 3867285242Sachim} agsaFastCommand_t; 3868285242Sachim#endif 3869285242Sachim 3870285242Sachim 3871285242Sachim 3872285242Sachim/* Enable test by setting bits in gFPGA_TEST */ 3873285242Sachim 3874285242Sachim#define EnableFPGA_TEST_ICCcontrol 0x01 3875285242Sachim#define EnableFPGA_TEST_ReadDEV 0x02 3876285242Sachim#define EnableFPGA_TEST_WriteCALAll 0x04 3877285242Sachim#define EnableFPGA_TEST_ReconfigSASParams 0x08 3878285242Sachim#define EnableFPGA_TEST_LocalPhyControl 0x10 3879285242Sachim#define EnableFPGA_TEST_PortControl 0x20 3880285242Sachim 3881285242Sachim 3882285242Sachim/* 3883285242SachimPM8001/PM8008/PM8009/PM8018 sTSDK Low-Level Architecture Specification 3884285242SachimSDK2 3885285242Sachim3.3 Encryption Status Definitions 3886285242SachimEncryption engine generated errors. 3887285242SachimTable 7 Encryption Engine Generated Errors 3888285242SachimError Definition 3889285242Sachim*/ 3890285242Sachim 3891285242Sachim/* 3892285242SachimPM 1.01 3893285242Sachimsection 4.26.12.6 Encryption Errors 3894285242SachimTable 51 lists initialization errors related to encryption functionality. For information on errors reported 3895285242Sachimfor inbound IOMB commands, refer to the corresponding outbound response sections. The error codes 3896285242Sachimlisted in Table 51 are reported in the Scratchpad 3 Register. 3897285242Sachim*/ 3898285242Sachim#define OSSA_ENCRYPT_ENGINE_FAILURE_MASK 0x00FF0000 /* Encrypt Engine failed the BIST Test */ 3899285242Sachim#define OSSA_ENCRYPT_SEEPROM_NOT_FOUND 0x01 /* SEEPROM is not installed. This condition is reported based on the bootstrap pin setting. */ 3900285242Sachim#define OSSA_ENCRYPT_SEEPROM_IPW_RD_ACCESS_TMO 0x02 /* SEEPROM access timeout detected while reading initialization password or Allowable Cipher Modes. */ 3901285242Sachim#define OSSA_ENCRYPT_SEEPROM_IPW_RD_CRC_ERR 0x03 /* CRC Error detected when reading initialization password or Allowable Cipher Modes. */ 3902285242Sachim#define OSSA_ENCRYPT_SEEPROM_IPW_INVALID 0x04 /* Initialization password read from SEEPROM doesn't match any valid password value. This could also mean SEEPROM is blank. */ 3903285242Sachim#define OSSA_ENCRYPT_SEEPROM_WR_ACCESS_TMO 0x05 /* access timeout detected while writing initialization password or Allowable Cipher Modes. */ 3904285242Sachim#define OSSA_ENCRYPT_FLASH_ACCESS_TMO 0x20 /* Timeout while reading flash memory. */ 3905285242Sachim#define OSSA_ENCRYPT_FLASH_SECTOR_ERASE_TMO 0x21 /* Flash sector erase timeout while writing to flash memory. */ 3906285242Sachim#define OSSA_ENCRYPT_FLASH_SECTOR_ERASE_ERR 0x22 /* Flash sector erase failure while writing to flash memory. */ 3907285242Sachim#define OSSA_ENCRYPT_FLASH_ECC_CHECK_ERR 0x23 /* Flash ECC check failure. */ 3908285242Sachim#define OSSA_ENCRYPT_FLASH_NOT_INSTALLED 0x24 /* Flash memory not installed, this error is only detected in Security Mode B. */ 3909285242Sachim#define OSSA_ENCRYPT_INITIAL_KEK_NOT_FOUND 0x40 /* Initial KEK is not found in the flash memory. This error is only detected in Security Mode B. */ 3910285242Sachim#define OSSA_ENCRYPT_AES_BIST_ERR 0x41 /* Built-In Test Failure */ 3911285242Sachim#define OSSA_ENCRYPT_KWP_BIST_FAILURE 0x42 /* Built-In Test Failed on Key Wrap Engine */ 3912285242Sachim 3913285242Sachim/* 0x01:ENC_ERR_SEEPROM_NOT_INSTALLED */ 3914285242Sachim/* 0x02:ENC_ERR_SEEPROM_IPW_RD_ACCESS_TMO */ 3915285242Sachim/* 0x03:ENC_ERR_SEEPROM_IPW_RD_CRC_ERR */ 3916285242Sachim/* 0x04:ENC_ERR_SEEPROM_IPW_INVALID */ 3917285242Sachim/* 0x05:ENC_ERR_SEEPROM_WR_ACCESS_TMO */ 3918285242Sachim/* 0x20:ENC_ERR_FLASH_ACCESS_TMO */ 3919285242Sachim/* 0x21:ENC_ERR_FLASH_SECTOR_ERASE_TMO */ 3920285242Sachim/* 0x22:ENC_ERR_FLASH_SECTOR_ERASE_FAILURE */ 3921285242Sachim/* 0x23:ENC_ERR_FLASH_ECC_CHECK_FAILURE */ 3922285242Sachim/* 0x24:ENC_ERR_FLASH_NOT_INSTALLED */ 3923285242Sachim/* 0x40:ENC_ERR_INITIAL_KEK_NOT_FOUND */ 3924285242Sachim/* 0x41:ENC_ERR_AES_BIST_FAILURE */ 3925285242Sachim/* 0x42:ENC_ERR_KWP_BIST_FAILURE */ 3926285242Sachim 3927285242Sachim/* 3928285242SachimThis field indicates self test failure in DIF engine bits [27:24]. 3929285242Sachim*/ 3930285242Sachim 3931285242Sachim#define OSSA_DIF_ENGINE_FAILURE_MASK 0x0F000000 /* DIF Engine failed the BIST Test */ 3932285242Sachim 3933285242Sachim#define OSSA_DIF_ENGINE_0_BIST_FAILURE 0x1 /* DIF Engine 0 failed the BIST Test */ 3934285242Sachim#define OSSA_DIF_ENGINE_1_BIST_FAILURE 0x2 /* DIF Engine 1 failed the BIST Test */ 3935285242Sachim#define OSSA_DIF_ENGINE_2_BIST_FAILURE 0x4 /* DIF Engine 2 failed the BIST Test */ 3936285242Sachim#define OSSA_DIF_ENGINE_3_BIST_FAILURE 0x8 /* DIF Engine 3 failed the BIST Test */ 3937285242Sachim 3938285242Sachim#define SA_ROLE_CAPABILITIES_CSP 0x001 3939285242Sachim#define SA_ROLE_CAPABILITIES_OPR 0x002 3940285242Sachim#define SA_ROLE_CAPABILITIES_SCO 0x004 3941285242Sachim#define SA_ROLE_CAPABILITIES_STS 0x008 3942285242Sachim#define SA_ROLE_CAPABILITIES_TST 0x010 3943285242Sachim#define SA_ROLE_CAPABILITIES_KEK 0x020 3944285242Sachim#define SA_ROLE_CAPABILITIES_DEK 0x040 3945285242Sachim#define SA_ROLE_CAPABILITIES_IOS 0x080 3946285242Sachim#define SA_ROLE_CAPABILITIES_FWU 0x100 3947285242Sachim#define SA_ROLE_CAPABILITIES_PRM 0x200 3948285242Sachim 3949285242Sachim 3950285242Sachim#include "saapi.h" 3951285242Sachim/*********************************************************************************** 3952285242Sachim * * 3953285242Sachim * The LL Layer Functions Declarations end * 3954285242Sachim * * 3955285242Sachim ***********************************************************************************/ 3956285242Sachim 3957285242Sachim#endif /*__SA_H__ */ 3958