if_pcn.c revision 99165
1/* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/pci/if_pcn.c 99165 2002-06-30 22:16:22Z luigi $ 34 */ 35 36/* 37 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 38 * from http://www.amd.com. 39 * 40 * Written by Bill Paul <wpaul@osd.bsdi.com> 41 */ 42 43/* 44 * The AMD PCnet/PCI controllers are more advanced and functional 45 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 46 * backwards compatibility with the LANCE and thus can be made 47 * to work with older LANCE drivers. This is in fact how the 48 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 49 * is that the PCnet/PCI devices offer several performance enhancements 50 * which can't be exploited in LANCE compatibility mode. Chief among 51 * these enhancements is the ability to perform PCI DMA operations 52 * using 32-bit addressing (which eliminates the need for ISA 53 * bounce-buffering), and special receive buffer alignment (which 54 * allows the receive handler to pass packets to the upper protocol 55 * layers without copying on both the x86 and alpha platforms). 56 */ 57 58#include <sys/param.h> 59#include <sys/systm.h> 60#include <sys/sockio.h> 61#include <sys/mbuf.h> 62#include <sys/malloc.h> 63#include <sys/kernel.h> 64#include <sys/socket.h> 65 66#include <net/if.h> 67#include <net/if_arp.h> 68#include <net/ethernet.h> 69#include <net/if_dl.h> 70#include <net/if_media.h> 71 72#include <net/bpf.h> 73 74#include <vm/vm.h> /* for vtophys */ 75#include <vm/pmap.h> /* for vtophys */ 76#include <machine/bus_pio.h> 77#include <machine/bus_memio.h> 78#include <machine/bus.h> 79#include <machine/resource.h> 80#include <sys/bus.h> 81#include <sys/rman.h> 82 83#include <dev/mii/mii.h> 84#include <dev/mii/miivar.h> 85 86#include <pci/pcireg.h> 87#include <pci/pcivar.h> 88 89#define PCN_USEIOSPACE 90 91#include <pci/if_pcnreg.h> 92 93MODULE_DEPEND(pcn, miibus, 1, 1, 1); 94 95/* "controller miibus0" required. See GENERIC if you get errors here. */ 96#include "miibus_if.h" 97 98#ifndef lint 99static const char rcsid[] = 100 "$FreeBSD: head/sys/pci/if_pcn.c 99165 2002-06-30 22:16:22Z luigi $"; 101#endif 102 103/* 104 * Various supported device vendors/types and their names. 105 */ 106static struct pcn_type pcn_devs[] = { 107 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 108 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 109 { 0, 0, NULL } 110}; 111 112static u_int32_t pcn_csr_read (struct pcn_softc *, int); 113static u_int16_t pcn_csr_read16 (struct pcn_softc *, int); 114static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int); 115static void pcn_csr_write (struct pcn_softc *, int, int); 116static u_int32_t pcn_bcr_read (struct pcn_softc *, int); 117static void pcn_bcr_write (struct pcn_softc *, int, int); 118 119static int pcn_probe (device_t); 120static int pcn_attach (device_t); 121static int pcn_detach (device_t); 122 123static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *); 124static int pcn_encap (struct pcn_softc *, 125 struct mbuf *, u_int32_t *); 126static void pcn_rxeof (struct pcn_softc *); 127static void pcn_txeof (struct pcn_softc *); 128static void pcn_intr (void *); 129static void pcn_tick (void *); 130static void pcn_start (struct ifnet *); 131static int pcn_ioctl (struct ifnet *, u_long, caddr_t); 132static void pcn_init (void *); 133static void pcn_stop (struct pcn_softc *); 134static void pcn_watchdog (struct ifnet *); 135static void pcn_shutdown (device_t); 136static int pcn_ifmedia_upd (struct ifnet *); 137static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *); 138 139static int pcn_miibus_readreg (device_t, int, int); 140static int pcn_miibus_writereg (device_t, int, int, int); 141static void pcn_miibus_statchg (device_t); 142 143static void pcn_setfilt (struct ifnet *); 144static void pcn_setmulti (struct pcn_softc *); 145static u_int32_t pcn_crc (caddr_t); 146static void pcn_reset (struct pcn_softc *); 147static int pcn_list_rx_init (struct pcn_softc *); 148static int pcn_list_tx_init (struct pcn_softc *); 149 150#ifdef PCN_USEIOSPACE 151#define PCN_RES SYS_RES_IOPORT 152#define PCN_RID PCN_PCI_LOIO 153#else 154#define PCN_RES SYS_RES_MEMORY 155#define PCN_RID PCN_PCI_LOMEM 156#endif 157 158static device_method_t pcn_methods[] = { 159 /* Device interface */ 160 DEVMETHOD(device_probe, pcn_probe), 161 DEVMETHOD(device_attach, pcn_attach), 162 DEVMETHOD(device_detach, pcn_detach), 163 DEVMETHOD(device_shutdown, pcn_shutdown), 164 165 /* bus interface */ 166 DEVMETHOD(bus_print_child, bus_generic_print_child), 167 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 168 169 /* MII interface */ 170 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 171 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 172 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 173 174 { 0, 0 } 175}; 176 177static driver_t pcn_driver = { 178 "pcn", 179 pcn_methods, 180 sizeof(struct pcn_softc) 181}; 182 183static devclass_t pcn_devclass; 184 185DRIVER_MODULE(if_pcn, pci, pcn_driver, pcn_devclass, 0, 0); 186DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 187 188#define PCN_CSR_SETBIT(sc, reg, x) \ 189 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 190 191#define PCN_CSR_CLRBIT(sc, reg, x) \ 192 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 193 194#define PCN_BCR_SETBIT(sc, reg, x) \ 195 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 196 197#define PCN_BCR_CLRBIT(sc, reg, x) \ 198 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 199 200static u_int32_t pcn_csr_read(sc, reg) 201 struct pcn_softc *sc; 202 int reg; 203{ 204 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 205 return(CSR_READ_4(sc, PCN_IO32_RDP)); 206} 207 208static u_int16_t pcn_csr_read16(sc, reg) 209 struct pcn_softc *sc; 210 int reg; 211{ 212 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 213 return(CSR_READ_2(sc, PCN_IO16_RDP)); 214} 215 216static void pcn_csr_write(sc, reg, val) 217 struct pcn_softc *sc; 218 int reg; 219{ 220 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 221 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 222 return; 223} 224 225static u_int32_t pcn_bcr_read(sc, reg) 226 struct pcn_softc *sc; 227 int reg; 228{ 229 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 230 return(CSR_READ_4(sc, PCN_IO32_BDP)); 231} 232 233static u_int16_t pcn_bcr_read16(sc, reg) 234 struct pcn_softc *sc; 235 int reg; 236{ 237 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 238 return(CSR_READ_2(sc, PCN_IO16_BDP)); 239} 240 241static void pcn_bcr_write(sc, reg, val) 242 struct pcn_softc *sc; 243 int reg; 244{ 245 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 246 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 247 return; 248} 249 250static int pcn_miibus_readreg(dev, phy, reg) 251 device_t dev; 252 int phy, reg; 253{ 254 struct pcn_softc *sc; 255 int val; 256 257 sc = device_get_softc(dev); 258 259 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 260 return(0); 261 262 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 263 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 264 if (val == 0xFFFF) 265 return(0); 266 267 sc->pcn_phyaddr = phy; 268 269 return(val); 270} 271 272static int pcn_miibus_writereg(dev, phy, reg, data) 273 device_t dev; 274 int phy, reg, data; 275{ 276 struct pcn_softc *sc; 277 278 sc = device_get_softc(dev); 279 280 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 281 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 282 283 return(0); 284} 285 286static void pcn_miibus_statchg(dev) 287 device_t dev; 288{ 289 struct pcn_softc *sc; 290 struct mii_data *mii; 291 292 sc = device_get_softc(dev); 293 mii = device_get_softc(sc->pcn_miibus); 294 295 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 296 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 297 } else { 298 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 299 } 300 301 return; 302} 303 304#define DC_POLY 0xEDB88320 305 306static u_int32_t pcn_crc(addr) 307 caddr_t addr; 308{ 309 u_int32_t idx, bit, data, crc; 310 311 /* Compute CRC for the address value. */ 312 crc = 0xFFFFFFFF; /* initial value */ 313 314 for (idx = 0; idx < 6; idx++) { 315 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 316 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 317 } 318 319 return ((crc >> 26) & 0x3F); 320} 321 322static void pcn_setmulti(sc) 323 struct pcn_softc *sc; 324{ 325 struct ifnet *ifp; 326 struct ifmultiaddr *ifma; 327 u_int32_t h, i; 328 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 329 330 ifp = &sc->arpcom.ac_if; 331 332 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 333 334 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 335 for (i = 0; i < 4; i++) 336 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 337 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 338 return; 339 } 340 341 /* first, zot all the existing hash bits */ 342 for (i = 0; i < 4; i++) 343 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 344 345 /* now program new ones */ 346 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 347 if (ifma->ifma_addr->sa_family != AF_LINK) 348 continue; 349 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 350 hashes[h >> 4] |= 1 << (h & 0xF); 351 } 352 353 for (i = 0; i < 4; i++) 354 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 355 356 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 357 358 return; 359} 360 361static void pcn_reset(sc) 362 struct pcn_softc *sc; 363{ 364 /* 365 * Issue a reset by reading from the RESET register. 366 * Note that we don't know if the chip is operating in 367 * 16-bit or 32-bit mode at this point, so we attempt 368 * to reset the chip both ways. If one fails, the other 369 * will succeed. 370 */ 371 CSR_READ_2(sc, PCN_IO16_RESET); 372 CSR_READ_4(sc, PCN_IO32_RESET); 373 374 /* Wait a little while for the chip to get its brains in order. */ 375 DELAY(1000); 376 377 /* Select 32-bit (DWIO) mode */ 378 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 379 380 /* Select software style 3. */ 381 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 382 383 return; 384} 385 386/* 387 * Probe for an AMD chip. Check the PCI vendor and device 388 * IDs against our list and return a device name if we find a match. 389 */ 390static int pcn_probe(dev) 391 device_t dev; 392{ 393 struct pcn_type *t; 394 struct pcn_softc *sc; 395 int rid; 396 u_int32_t chip_id; 397 398 t = pcn_devs; 399 sc = device_get_softc(dev); 400 401 while(t->pcn_name != NULL) { 402 if ((pci_get_vendor(dev) == t->pcn_vid) && 403 (pci_get_device(dev) == t->pcn_did)) { 404 /* 405 * Temporarily map the I/O space 406 * so we can read the chip ID register. 407 */ 408 rid = PCN_RID; 409 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 410 0, ~0, 1, RF_ACTIVE); 411 if (sc->pcn_res == NULL) { 412 device_printf(dev, 413 "couldn't map ports/memory\n"); 414 return(ENXIO); 415 } 416 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 417 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 418 mtx_init(&sc->pcn_mtx, 419 device_get_nameunit(dev), MTX_NETWORK_LOCK, 420 MTX_DEF); 421 PCN_LOCK(sc); 422 /* 423 * Note: we can *NOT* put the chip into 424 * 32-bit mode yet. The lnc driver will only 425 * work in 16-bit mode, and once the chip 426 * goes into 32-bit mode, the only way to 427 * get it out again is with a hardware reset. 428 * So if pcn_probe() is called before the 429 * lnc driver's probe routine, the chip will 430 * be locked into 32-bit operation and the lnc 431 * driver will be unable to attach to it. 432 * Note II: if the chip happens to already 433 * be in 32-bit mode, we still need to check 434 * the chip ID, but first we have to detect 435 * 32-bit mode using only 16-bit operations. 436 * The safest way to do this is to read the 437 * PCI subsystem ID from BCR23/24 and compare 438 * that with the value read from PCI config 439 * space. 440 */ 441 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 442 chip_id <<= 16; 443 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 444 /* 445 * Note III: the test for 0x10001000 is a hack to 446 * pacify VMware, who's pseudo-PCnet interface is 447 * broken. Reading the subsystem register from PCI 448 * config space yeilds 0x00000000 while reading the 449 * same value from I/O space yeilds 0x10001000. It's 450 * not supposed to be that way. 451 */ 452 if (chip_id == pci_read_config(dev, 453 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 454 /* We're in 16-bit mode. */ 455 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 456 chip_id <<= 16; 457 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 458 } else { 459 /* We're in 32-bit mode. */ 460 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 461 chip_id <<= 16; 462 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 463 } 464 bus_release_resource(dev, PCN_RES, 465 PCN_RID, sc->pcn_res); 466 PCN_UNLOCK(sc); 467 mtx_destroy(&sc->pcn_mtx); 468 chip_id >>= 12; 469 sc->pcn_type = chip_id & PART_MASK; 470 switch(sc->pcn_type) { 471 case Am79C971: 472 case Am79C972: 473 case Am79C973: 474 case Am79C975: 475 case Am79C976: 476 case Am79C978: 477 break; 478 default: 479 return(ENXIO); 480 break; 481 } 482 device_set_desc(dev, t->pcn_name); 483 return(0); 484 } 485 t++; 486 } 487 488 return(ENXIO); 489} 490 491/* 492 * Attach the interface. Allocate softc structures, do ifmedia 493 * setup and ethernet/BPF attach. 494 */ 495static int pcn_attach(dev) 496 device_t dev; 497{ 498 u_int32_t eaddr[2]; 499 u_int32_t command; 500 struct pcn_softc *sc; 501 struct ifnet *ifp; 502 int unit, error = 0, rid; 503 504 sc = device_get_softc(dev); 505 unit = device_get_unit(dev); 506 507 /* Initialize our mutex. */ 508 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 509 MTX_DEF | MTX_RECURSE); 510 PCN_LOCK(sc); 511 512 /* 513 * Handle power management nonsense. 514 */ 515 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 516 u_int32_t iobase, membase, irq; 517 518 /* Save important PCI config data. */ 519 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 520 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 521 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 522 523 /* Reset the power state. */ 524 printf("pcn%d: chip is in D%d power mode " 525 "-- setting to D0\n", unit, 526 pci_get_powerstate(dev)); 527 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 528 529 /* Restore PCI config data. */ 530 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 531 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 532 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 533 } 534 535 /* 536 * Map control/status registers. 537 */ 538 pci_enable_busmaster(dev); 539 pci_enable_io(dev, SYS_RES_IOPORT); 540 pci_enable_io(dev, SYS_RES_MEMORY); 541 command = pci_read_config(dev, PCIR_COMMAND, 4); 542 543#ifdef PCN_USEIOSPACE 544 if (!(command & PCIM_CMD_PORTEN)) { 545 printf("pcn%d: failed to enable I/O ports!\n", unit); 546 error = ENXIO;; 547 goto fail; 548 } 549#else 550 if (!(command & PCIM_CMD_MEMEN)) { 551 printf("pcn%d: failed to enable memory mapping!\n", unit); 552 error = ENXIO;; 553 goto fail; 554 } 555#endif 556 557 rid = PCN_RID; 558 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 559 0, ~0, 1, RF_ACTIVE); 560 561 if (sc->pcn_res == NULL) { 562 printf("pcn%d: couldn't map ports/memory\n", unit); 563 error = ENXIO; 564 goto fail; 565 } 566 567 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 568 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 569 570 /* Allocate interrupt */ 571 rid = 0; 572 sc->pcn_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 573 RF_SHAREABLE | RF_ACTIVE); 574 575 if (sc->pcn_irq == NULL) { 576 printf("pcn%d: couldn't map interrupt\n", unit); 577 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 578 error = ENXIO; 579 goto fail; 580 } 581 582 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 583 pcn_intr, sc, &sc->pcn_intrhand); 584 585 if (error) { 586 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_res); 587 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 588 printf("pcn%d: couldn't set up irq\n", unit); 589 goto fail; 590 } 591 592 /* Reset the adapter. */ 593 pcn_reset(sc); 594 595 /* 596 * Get station address from the EEPROM. 597 */ 598 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 599 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 600 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 601 602 /* 603 * An AMD chip was detected. Inform the world. 604 */ 605 printf("pcn%d: Ethernet address: %6D\n", unit, 606 sc->arpcom.ac_enaddr, ":"); 607 608 sc->pcn_unit = unit; 609 callout_handle_init(&sc->pcn_stat_ch); 610 611 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 612 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 613 614 if (sc->pcn_ldata == NULL) { 615 printf("pcn%d: no memory for list buffers!\n", unit); 616 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 617 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 618 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 619 error = ENXIO; 620 goto fail; 621 } 622 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 623 624 ifp = &sc->arpcom.ac_if; 625 ifp->if_softc = sc; 626 ifp->if_unit = unit; 627 ifp->if_name = "pcn"; 628 ifp->if_mtu = ETHERMTU; 629 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 630 ifp->if_ioctl = pcn_ioctl; 631 ifp->if_output = ether_output; 632 ifp->if_start = pcn_start; 633 ifp->if_watchdog = pcn_watchdog; 634 ifp->if_init = pcn_init; 635 ifp->if_baudrate = 10000000; 636 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 637 638 /* 639 * Do MII setup. 640 */ 641 if (mii_phy_probe(dev, &sc->pcn_miibus, 642 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 643 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 644 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 645 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 646 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 647 error = ENXIO; 648 goto fail; 649 } 650 651 /* 652 * Call MI attach routine. 653 */ 654 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 655 callout_handle_init(&sc->pcn_stat_ch); 656 PCN_UNLOCK(sc); 657 return(0); 658 659fail: 660 PCN_UNLOCK(sc); 661 mtx_destroy(&sc->pcn_mtx); 662 663 return(error); 664} 665 666static int pcn_detach(dev) 667 device_t dev; 668{ 669 struct pcn_softc *sc; 670 struct ifnet *ifp; 671 672 sc = device_get_softc(dev); 673 ifp = &sc->arpcom.ac_if; 674 675 PCN_LOCK(sc); 676 677 pcn_reset(sc); 678 pcn_stop(sc); 679 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 680 681 if (sc->pcn_miibus != NULL) { 682 bus_generic_detach(dev); 683 device_delete_child(dev, sc->pcn_miibus); 684 } 685 686 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 687 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 688 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 689 690 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), M_DEVBUF); 691 PCN_UNLOCK(sc); 692 693 mtx_destroy(&sc->pcn_mtx); 694 695 return(0); 696} 697 698/* 699 * Initialize the transmit descriptors. 700 */ 701static int pcn_list_tx_init(sc) 702 struct pcn_softc *sc; 703{ 704 struct pcn_list_data *ld; 705 struct pcn_ring_data *cd; 706 int i; 707 708 cd = &sc->pcn_cdata; 709 ld = sc->pcn_ldata; 710 711 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 712 cd->pcn_tx_chain[i] = NULL; 713 ld->pcn_tx_list[i].pcn_tbaddr = 0; 714 ld->pcn_tx_list[i].pcn_txctl = 0; 715 ld->pcn_tx_list[i].pcn_txstat = 0; 716 } 717 718 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 719 720 return(0); 721} 722 723 724/* 725 * Initialize the RX descriptors and allocate mbufs for them. 726 */ 727static int pcn_list_rx_init(sc) 728 struct pcn_softc *sc; 729{ 730 struct pcn_list_data *ld; 731 struct pcn_ring_data *cd; 732 int i; 733 734 ld = sc->pcn_ldata; 735 cd = &sc->pcn_cdata; 736 737 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 738 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 739 return(ENOBUFS); 740 } 741 742 cd->pcn_rx_prod = 0; 743 744 return(0); 745} 746 747/* 748 * Initialize an RX descriptor and attach an MBUF cluster. 749 */ 750static int pcn_newbuf(sc, idx, m) 751 struct pcn_softc *sc; 752 int idx; 753 struct mbuf *m; 754{ 755 struct mbuf *m_new = NULL; 756 struct pcn_rx_desc *c; 757 758 c = &sc->pcn_ldata->pcn_rx_list[idx]; 759 760 if (m == NULL) { 761 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 762 if (m_new == NULL) 763 return(ENOBUFS); 764 765 MCLGET(m_new, M_DONTWAIT); 766 if (!(m_new->m_flags & M_EXT)) { 767 m_freem(m_new); 768 return(ENOBUFS); 769 } 770 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 771 } else { 772 m_new = m; 773 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 774 m_new->m_data = m_new->m_ext.ext_buf; 775 } 776 777 m_adj(m_new, ETHER_ALIGN); 778 779 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 780 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 781 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 782 c->pcn_bufsz |= PCN_RXLEN_MBO; 783 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 784 785 return(0); 786} 787 788/* 789 * A frame has been uploaded: pass the resulting mbuf chain up to 790 * the higher level protocols. 791 */ 792static void pcn_rxeof(sc) 793 struct pcn_softc *sc; 794{ 795 struct ether_header *eh; 796 struct mbuf *m; 797 struct ifnet *ifp; 798 struct pcn_rx_desc *cur_rx; 799 int i; 800 801 ifp = &sc->arpcom.ac_if; 802 i = sc->pcn_cdata.pcn_rx_prod; 803 804 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 805 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 806 m = sc->pcn_cdata.pcn_rx_chain[i]; 807 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 808 809 /* 810 * If an error occurs, update stats, clear the 811 * status word and leave the mbuf cluster in place: 812 * it should simply get re-used next time this descriptor 813 * comes up in the ring. 814 */ 815 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 816 ifp->if_ierrors++; 817 pcn_newbuf(sc, i, m); 818 PCN_INC(i, PCN_RX_LIST_CNT); 819 continue; 820 } 821 822 if (pcn_newbuf(sc, i, NULL)) { 823 /* Ran out of mbufs; recycle this one. */ 824 pcn_newbuf(sc, i, m); 825 ifp->if_ierrors++; 826 PCN_INC(i, PCN_RX_LIST_CNT); 827 continue; 828 } 829 830 PCN_INC(i, PCN_RX_LIST_CNT); 831 832 /* No errors; receive the packet. */ 833 ifp->if_ipackets++; 834 eh = mtod(m, struct ether_header *); 835 m->m_len = m->m_pkthdr.len = 836 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 837 m->m_pkthdr.rcvif = ifp; 838 839 /* Remove header from mbuf and pass it on. */ 840 m_adj(m, sizeof(struct ether_header)); 841 ether_input(ifp, eh, m); 842 } 843 844 sc->pcn_cdata.pcn_rx_prod = i; 845 846 return; 847} 848 849/* 850 * A frame was downloaded to the chip. It's safe for us to clean up 851 * the list buffers. 852 */ 853 854static void pcn_txeof(sc) 855 struct pcn_softc *sc; 856{ 857 struct pcn_tx_desc *cur_tx = NULL; 858 struct ifnet *ifp; 859 u_int32_t idx; 860 861 ifp = &sc->arpcom.ac_if; 862 863 /* 864 * Go through our tx list and free mbufs for those 865 * frames that have been transmitted. 866 */ 867 idx = sc->pcn_cdata.pcn_tx_cons; 868 while (idx != sc->pcn_cdata.pcn_tx_prod) { 869 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 870 871 if (!PCN_OWN_TXDESC(cur_tx)) 872 break; 873 874 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 875 sc->pcn_cdata.pcn_tx_cnt--; 876 PCN_INC(idx, PCN_TX_LIST_CNT); 877 continue; 878 } 879 880 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 881 ifp->if_oerrors++; 882 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 883 ifp->if_collisions++; 884 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 885 ifp->if_collisions++; 886 } 887 888 ifp->if_collisions += 889 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 890 891 ifp->if_opackets++; 892 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 893 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 894 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 895 } 896 897 sc->pcn_cdata.pcn_tx_cnt--; 898 PCN_INC(idx, PCN_TX_LIST_CNT); 899 } 900 901 if (idx != sc->pcn_cdata.pcn_tx_cons) { 902 /* Some buffers have been freed. */ 903 sc->pcn_cdata.pcn_tx_cons = idx; 904 ifp->if_flags &= ~IFF_OACTIVE; 905 } 906 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 907 908 return; 909} 910 911static void pcn_tick(xsc) 912 void *xsc; 913{ 914 struct pcn_softc *sc; 915 struct mii_data *mii; 916 struct ifnet *ifp; 917 918 sc = xsc; 919 ifp = &sc->arpcom.ac_if; 920 PCN_LOCK(sc); 921 922 mii = device_get_softc(sc->pcn_miibus); 923 mii_tick(mii); 924 925 /* link just died */ 926 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 927 sc->pcn_link = 0; 928 929 /* link just came up, restart */ 930 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE && 931 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 932 sc->pcn_link++; 933 if (ifp->if_snd.ifq_head != NULL) 934 pcn_start(ifp); 935 } 936 937 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 938 939 PCN_UNLOCK(sc); 940 941 return; 942} 943 944static void pcn_intr(arg) 945 void *arg; 946{ 947 struct pcn_softc *sc; 948 struct ifnet *ifp; 949 u_int32_t status; 950 951 sc = arg; 952 ifp = &sc->arpcom.ac_if; 953 954 /* Supress unwanted interrupts */ 955 if (!(ifp->if_flags & IFF_UP)) { 956 pcn_stop(sc); 957 return; 958 } 959 960 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 961 962 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 963 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 964 965 if (status & PCN_CSR_RINT) 966 pcn_rxeof(sc); 967 968 if (status & PCN_CSR_TINT) 969 pcn_txeof(sc); 970 971 if (status & PCN_CSR_ERR) { 972 pcn_init(sc); 973 break; 974 } 975 } 976 977 if (ifp->if_snd.ifq_head != NULL) 978 pcn_start(ifp); 979 980 return; 981} 982 983/* 984 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 985 * pointers to the fragment pointers. 986 */ 987static int pcn_encap(sc, m_head, txidx) 988 struct pcn_softc *sc; 989 struct mbuf *m_head; 990 u_int32_t *txidx; 991{ 992 struct pcn_tx_desc *f = NULL; 993 struct mbuf *m; 994 int frag, cur, cnt = 0; 995 996 /* 997 * Start packing the mbufs in this chain into 998 * the fragment pointers. Stop when we run out 999 * of fragments or hit the end of the mbuf chain. 1000 */ 1001 m = m_head; 1002 cur = frag = *txidx; 1003 1004 for (m = m_head; m != NULL; m = m->m_next) { 1005 if (m->m_len != 0) { 1006 if ((PCN_TX_LIST_CNT - 1007 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 1008 return(ENOBUFS); 1009 f = &sc->pcn_ldata->pcn_tx_list[frag]; 1010 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 1011 f->pcn_txctl |= PCN_TXCTL_MBO; 1012 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 1013 if (cnt == 0) 1014 f->pcn_txctl |= PCN_TXCTL_STP; 1015 else 1016 f->pcn_txctl |= PCN_TXCTL_OWN; 1017 cur = frag; 1018 PCN_INC(frag, PCN_TX_LIST_CNT); 1019 cnt++; 1020 } 1021 } 1022 1023 if (m != NULL) 1024 return(ENOBUFS); 1025 1026 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1027 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1028 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1029 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1030 sc->pcn_cdata.pcn_tx_cnt += cnt; 1031 *txidx = frag; 1032 1033 return(0); 1034} 1035 1036/* 1037 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1038 * to the mbuf data regions directly in the transmit lists. We also save a 1039 * copy of the pointers since the transmit list fragment pointers are 1040 * physical addresses. 1041 */ 1042static void pcn_start(ifp) 1043 struct ifnet *ifp; 1044{ 1045 struct pcn_softc *sc; 1046 struct mbuf *m_head = NULL; 1047 u_int32_t idx; 1048 1049 sc = ifp->if_softc; 1050 1051 PCN_LOCK(sc); 1052 1053 if (!sc->pcn_link) { 1054 PCN_UNLOCK(sc); 1055 return; 1056 } 1057 1058 idx = sc->pcn_cdata.pcn_tx_prod; 1059 1060 if (ifp->if_flags & IFF_OACTIVE) { 1061 PCN_UNLOCK(sc); 1062 return; 1063 } 1064 1065 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1066 IF_DEQUEUE(&ifp->if_snd, m_head); 1067 if (m_head == NULL) 1068 break; 1069 1070 if (pcn_encap(sc, m_head, &idx)) { 1071 IF_PREPEND(&ifp->if_snd, m_head); 1072 ifp->if_flags |= IFF_OACTIVE; 1073 break; 1074 } 1075 1076 /* 1077 * If there's a BPF listener, bounce a copy of this frame 1078 * to him. 1079 */ 1080 if (ifp->if_bpf) 1081 bpf_mtap(ifp, m_head); 1082 1083 } 1084 1085 /* Transmit */ 1086 sc->pcn_cdata.pcn_tx_prod = idx; 1087 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1088 1089 /* 1090 * Set a timeout in case the chip goes out to lunch. 1091 */ 1092 ifp->if_timer = 5; 1093 1094 PCN_UNLOCK(sc); 1095 1096 return; 1097} 1098 1099static void pcn_setfilt(ifp) 1100 struct ifnet *ifp; 1101{ 1102 struct pcn_softc *sc; 1103 1104 sc = ifp->if_softc; 1105 1106 /* If we want promiscuous mode, set the allframes bit. */ 1107 if (ifp->if_flags & IFF_PROMISC) { 1108 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1109 } else { 1110 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1111 } 1112 1113 /* Set the capture broadcast bit to capture broadcast frames. */ 1114 if (ifp->if_flags & IFF_BROADCAST) { 1115 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1116 } else { 1117 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1118 } 1119 1120 return; 1121} 1122 1123static void pcn_init(xsc) 1124 void *xsc; 1125{ 1126 struct pcn_softc *sc = xsc; 1127 struct ifnet *ifp = &sc->arpcom.ac_if; 1128 struct mii_data *mii = NULL; 1129 1130 PCN_LOCK(sc); 1131 1132 /* 1133 * Cancel pending I/O and free all RX/TX buffers. 1134 */ 1135 pcn_stop(sc); 1136 pcn_reset(sc); 1137 1138 mii = device_get_softc(sc->pcn_miibus); 1139 1140 /* Set MAC address */ 1141 pcn_csr_write(sc, PCN_CSR_PAR0, 1142 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1143 pcn_csr_write(sc, PCN_CSR_PAR1, 1144 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1145 pcn_csr_write(sc, PCN_CSR_PAR2, 1146 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1147 1148 /* Init circular RX list. */ 1149 if (pcn_list_rx_init(sc) == ENOBUFS) { 1150 printf("pcn%d: initialization failed: no " 1151 "memory for rx buffers\n", sc->pcn_unit); 1152 pcn_stop(sc); 1153 PCN_UNLOCK(sc); 1154 return; 1155 } 1156 1157 /* 1158 * Init tx descriptors. 1159 */ 1160 pcn_list_tx_init(sc); 1161 1162 /* Set up the mode register. */ 1163 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1164 1165 /* Set up RX filter. */ 1166 pcn_setfilt(ifp); 1167 1168 /* 1169 * Load the multicast filter. 1170 */ 1171 pcn_setmulti(sc); 1172 1173 /* 1174 * Load the addresses of the RX and TX lists. 1175 */ 1176 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1177 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1178 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1179 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1180 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1181 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1182 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1183 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1184 1185 /* Set the RX and TX ring sizes. */ 1186 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1187 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1188 1189 /* We're not using the initialization block. */ 1190 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1191 1192 /* Enable fast suspend mode. */ 1193 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1194 1195 /* 1196 * Enable burst read and write. Also set the no underflow 1197 * bit. This will avoid transmit underruns in certain 1198 * conditions while still providing decent performance. 1199 */ 1200 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1201 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1202 1203 /* Enable graceful recovery from underflow. */ 1204 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1205 1206 /* Enable auto-padding of short TX frames. */ 1207 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1208 1209 /* Disable MII autoneg (we handle this ourselves). */ 1210 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1211 1212 if (sc->pcn_type == Am79C978) 1213 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1214 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1215 1216 /* Enable interrupts and start the controller running. */ 1217 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1218 1219 mii_mediachg(mii); 1220 1221 ifp->if_flags |= IFF_RUNNING; 1222 ifp->if_flags &= ~IFF_OACTIVE; 1223 1224 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 1225 PCN_UNLOCK(sc); 1226 1227 return; 1228} 1229 1230/* 1231 * Set media options. 1232 */ 1233static int pcn_ifmedia_upd(ifp) 1234 struct ifnet *ifp; 1235{ 1236 struct pcn_softc *sc; 1237 struct mii_data *mii; 1238 1239 sc = ifp->if_softc; 1240 mii = device_get_softc(sc->pcn_miibus); 1241 1242 sc->pcn_link = 0; 1243 if (mii->mii_instance) { 1244 struct mii_softc *miisc; 1245 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1246 mii_phy_reset(miisc); 1247 } 1248 mii_mediachg(mii); 1249 1250 return(0); 1251} 1252 1253/* 1254 * Report current media status. 1255 */ 1256static void pcn_ifmedia_sts(ifp, ifmr) 1257 struct ifnet *ifp; 1258 struct ifmediareq *ifmr; 1259{ 1260 struct pcn_softc *sc; 1261 struct mii_data *mii; 1262 1263 sc = ifp->if_softc; 1264 1265 mii = device_get_softc(sc->pcn_miibus); 1266 mii_pollstat(mii); 1267 ifmr->ifm_active = mii->mii_media_active; 1268 ifmr->ifm_status = mii->mii_media_status; 1269 1270 return; 1271} 1272 1273static int pcn_ioctl(ifp, command, data) 1274 struct ifnet *ifp; 1275 u_long command; 1276 caddr_t data; 1277{ 1278 struct pcn_softc *sc = ifp->if_softc; 1279 struct ifreq *ifr = (struct ifreq *) data; 1280 struct mii_data *mii = NULL; 1281 int error = 0; 1282 1283 PCN_LOCK(sc); 1284 1285 switch(command) { 1286 case SIOCSIFADDR: 1287 case SIOCGIFADDR: 1288 case SIOCSIFMTU: 1289 error = ether_ioctl(ifp, command, data); 1290 break; 1291 case SIOCSIFFLAGS: 1292 if (ifp->if_flags & IFF_UP) { 1293 if (ifp->if_flags & IFF_RUNNING && 1294 ifp->if_flags & IFF_PROMISC && 1295 !(sc->pcn_if_flags & IFF_PROMISC)) { 1296 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1297 PCN_EXTCTL1_SPND); 1298 pcn_setfilt(ifp); 1299 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1300 PCN_EXTCTL1_SPND); 1301 pcn_csr_write(sc, PCN_CSR_CSR, 1302 PCN_CSR_INTEN|PCN_CSR_START); 1303 } else if (ifp->if_flags & IFF_RUNNING && 1304 !(ifp->if_flags & IFF_PROMISC) && 1305 sc->pcn_if_flags & IFF_PROMISC) { 1306 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1307 PCN_EXTCTL1_SPND); 1308 pcn_setfilt(ifp); 1309 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1310 PCN_EXTCTL1_SPND); 1311 pcn_csr_write(sc, PCN_CSR_CSR, 1312 PCN_CSR_INTEN|PCN_CSR_START); 1313 } else if (!(ifp->if_flags & IFF_RUNNING)) 1314 pcn_init(sc); 1315 } else { 1316 if (ifp->if_flags & IFF_RUNNING) 1317 pcn_stop(sc); 1318 } 1319 sc->pcn_if_flags = ifp->if_flags; 1320 error = 0; 1321 break; 1322 case SIOCADDMULTI: 1323 case SIOCDELMULTI: 1324 pcn_setmulti(sc); 1325 error = 0; 1326 break; 1327 case SIOCGIFMEDIA: 1328 case SIOCSIFMEDIA: 1329 mii = device_get_softc(sc->pcn_miibus); 1330 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1331 break; 1332 default: 1333 error = EINVAL; 1334 break; 1335 } 1336 1337 PCN_UNLOCK(sc); 1338 1339 return(error); 1340} 1341 1342static void pcn_watchdog(ifp) 1343 struct ifnet *ifp; 1344{ 1345 struct pcn_softc *sc; 1346 1347 sc = ifp->if_softc; 1348 1349 PCN_LOCK(sc); 1350 1351 ifp->if_oerrors++; 1352 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1353 1354 pcn_stop(sc); 1355 pcn_reset(sc); 1356 pcn_init(sc); 1357 1358 if (ifp->if_snd.ifq_head != NULL) 1359 pcn_start(ifp); 1360 1361 PCN_UNLOCK(sc); 1362 1363 return; 1364} 1365 1366/* 1367 * Stop the adapter and free any mbufs allocated to the 1368 * RX and TX lists. 1369 */ 1370static void pcn_stop(sc) 1371 struct pcn_softc *sc; 1372{ 1373 register int i; 1374 struct ifnet *ifp; 1375 1376 ifp = &sc->arpcom.ac_if; 1377 PCN_LOCK(sc); 1378 ifp->if_timer = 0; 1379 1380 untimeout(pcn_tick, sc, sc->pcn_stat_ch); 1381 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1382 sc->pcn_link = 0; 1383 1384 /* 1385 * Free data in the RX lists. 1386 */ 1387 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1388 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1389 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1390 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1391 } 1392 } 1393 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1394 sizeof(sc->pcn_ldata->pcn_rx_list)); 1395 1396 /* 1397 * Free the TX list buffers. 1398 */ 1399 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1400 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1401 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1402 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1403 } 1404 } 1405 1406 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1407 sizeof(sc->pcn_ldata->pcn_tx_list)); 1408 1409 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1410 PCN_UNLOCK(sc); 1411 1412 return; 1413} 1414 1415/* 1416 * Stop all chip I/O so that the kernel's probe routines don't 1417 * get confused by errant DMAs when rebooting. 1418 */ 1419static void pcn_shutdown(dev) 1420 device_t dev; 1421{ 1422 struct pcn_softc *sc; 1423 1424 sc = device_get_softc(dev); 1425 1426 PCN_LOCK(sc); 1427 pcn_reset(sc); 1428 pcn_stop(sc); 1429 PCN_UNLOCK(sc); 1430 1431 return; 1432} 1433