if_pcn.c revision 72084
1/* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/pci/if_pcn.c 72084 2001-02-06 10:12:15Z phk $ 34 */ 35 36/* 37 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 38 * from http://www.amd.com. 39 * 40 * Written by Bill Paul <wpaul@osd.bsdi.com> 41 */ 42 43/* 44 * The AMD PCnet/PCI controllers are more advanced and functional 45 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 46 * backwards compatibility with the LANCE and thus can be made 47 * to work with older LANCE drivers. This is in fact how the 48 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 49 * is that the PCnet/PCI devices offer several performance enhancements 50 * which can't be exploited in LANCE compatibility mode. Chief among 51 * these enhancements is the ability to perform PCI DMA operations 52 * using 32-bit addressing (which eliminates the need for ISA 53 * bounce-buffering), and special receive buffer alignment (which 54 * allows the receive handler to pass packets to the upper protocol 55 * layers without copying on both the x86 and alpha platforms). 56 */ 57 58#include <sys/param.h> 59#include <sys/systm.h> 60#include <sys/sockio.h> 61#include <sys/mbuf.h> 62#include <sys/malloc.h> 63#include <sys/kernel.h> 64#include <sys/socket.h> 65 66#include <net/if.h> 67#include <net/if_arp.h> 68#include <net/ethernet.h> 69#include <net/if_dl.h> 70#include <net/if_media.h> 71 72#include <net/bpf.h> 73 74#include <vm/vm.h> /* for vtophys */ 75#include <vm/pmap.h> /* for vtophys */ 76#include <machine/bus_pio.h> 77#include <machine/bus_memio.h> 78#include <machine/bus.h> 79#include <machine/resource.h> 80#include <sys/bus.h> 81#include <sys/rman.h> 82 83#include <dev/mii/mii.h> 84#include <dev/mii/miivar.h> 85 86#include <pci/pcireg.h> 87#include <pci/pcivar.h> 88 89#define PCN_USEIOSPACE 90 91#include <pci/if_pcnreg.h> 92 93MODULE_DEPEND(pcn, miibus, 1, 1, 1); 94 95/* "controller miibus0" required. See GENERIC if you get errors here. */ 96#include "miibus_if.h" 97 98#ifndef lint 99static const char rcsid[] = 100 "$FreeBSD: head/sys/pci/if_pcn.c 72084 2001-02-06 10:12:15Z phk $"; 101#endif 102 103/* 104 * Various supported device vendors/types and their names. 105 */ 106static struct pcn_type pcn_devs[] = { 107 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 108 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 109 { 0, 0, NULL } 110}; 111 112static u_int32_t pcn_csr_read __P((struct pcn_softc *, int)); 113static u_int16_t pcn_csr_read16 __P((struct pcn_softc *, int)); 114static u_int16_t pcn_bcr_read16 __P((struct pcn_softc *, int)); 115static void pcn_csr_write __P((struct pcn_softc *, int, int)); 116static u_int32_t pcn_bcr_read __P((struct pcn_softc *, int)); 117static void pcn_bcr_write __P((struct pcn_softc *, int, int)); 118 119static int pcn_probe __P((device_t)); 120static int pcn_attach __P((device_t)); 121static int pcn_detach __P((device_t)); 122 123static int pcn_newbuf __P((struct pcn_softc *, int, struct mbuf *)); 124static int pcn_encap __P((struct pcn_softc *, 125 struct mbuf *, u_int32_t *)); 126static void pcn_rxeof __P((struct pcn_softc *)); 127static void pcn_txeof __P((struct pcn_softc *)); 128static void pcn_intr __P((void *)); 129static void pcn_tick __P((void *)); 130static void pcn_start __P((struct ifnet *)); 131static int pcn_ioctl __P((struct ifnet *, u_long, caddr_t)); 132static void pcn_init __P((void *)); 133static void pcn_stop __P((struct pcn_softc *)); 134static void pcn_watchdog __P((struct ifnet *)); 135static void pcn_shutdown __P((device_t)); 136static int pcn_ifmedia_upd __P((struct ifnet *)); 137static void pcn_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 138 139static int pcn_miibus_readreg __P((device_t, int, int)); 140static int pcn_miibus_writereg __P((device_t, int, int, int)); 141static void pcn_miibus_statchg __P((device_t)); 142 143static void pcn_setfilt __P((struct ifnet *)); 144static void pcn_setmulti __P((struct pcn_softc *)); 145static u_int32_t pcn_crc __P((caddr_t)); 146static void pcn_reset __P((struct pcn_softc *)); 147static int pcn_list_rx_init __P((struct pcn_softc *)); 148static int pcn_list_tx_init __P((struct pcn_softc *)); 149 150#ifdef PCN_USEIOSPACE 151#define PCN_RES SYS_RES_IOPORT 152#define PCN_RID PCN_PCI_LOIO 153#else 154#define PCN_RES SYS_RES_MEMORY 155#define PCN_RID PCN_PCI_LOMEM 156#endif 157 158static device_method_t pcn_methods[] = { 159 /* Device interface */ 160 DEVMETHOD(device_probe, pcn_probe), 161 DEVMETHOD(device_attach, pcn_attach), 162 DEVMETHOD(device_detach, pcn_detach), 163 DEVMETHOD(device_shutdown, pcn_shutdown), 164 165 /* bus interface */ 166 DEVMETHOD(bus_print_child, bus_generic_print_child), 167 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 168 169 /* MII interface */ 170 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 171 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 172 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 173 174 { 0, 0 } 175}; 176 177static driver_t pcn_driver = { 178 "pcn", 179 pcn_methods, 180 sizeof(struct pcn_softc) 181}; 182 183static devclass_t pcn_devclass; 184 185DRIVER_MODULE(if_pcn, pci, pcn_driver, pcn_devclass, 0, 0); 186DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 187 188#define PCN_CSR_SETBIT(sc, reg, x) \ 189 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 190 191#define PCN_CSR_CLRBIT(sc, reg, x) \ 192 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 193 194#define PCN_BCR_SETBIT(sc, reg, x) \ 195 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 196 197#define PCN_BCR_CLRBIT(sc, reg, x) \ 198 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 199 200static u_int32_t pcn_csr_read(sc, reg) 201 struct pcn_softc *sc; 202 int reg; 203{ 204 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 205 return(CSR_READ_4(sc, PCN_IO32_RDP)); 206} 207 208static u_int16_t pcn_csr_read16(sc, reg) 209 struct pcn_softc *sc; 210 int reg; 211{ 212 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 213 return(CSR_READ_2(sc, PCN_IO16_RDP)); 214} 215 216static void pcn_csr_write(sc, reg, val) 217 struct pcn_softc *sc; 218 int reg; 219{ 220 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 221 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 222 return; 223} 224 225static u_int32_t pcn_bcr_read(sc, reg) 226 struct pcn_softc *sc; 227 int reg; 228{ 229 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 230 return(CSR_READ_4(sc, PCN_IO32_BDP)); 231} 232 233static u_int16_t pcn_bcr_read16(sc, reg) 234 struct pcn_softc *sc; 235 int reg; 236{ 237 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 238 return(CSR_READ_2(sc, PCN_IO16_BDP)); 239} 240 241static void pcn_bcr_write(sc, reg, val) 242 struct pcn_softc *sc; 243 int reg; 244{ 245 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 246 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 247 return; 248} 249 250static int pcn_miibus_readreg(dev, phy, reg) 251 device_t dev; 252 int phy, reg; 253{ 254 struct pcn_softc *sc; 255 int val; 256 257 sc = device_get_softc(dev); 258 259 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 260 return(0); 261 262 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 263 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 264 if (val == 0xFFFF) 265 return(0); 266 267 sc->pcn_phyaddr = phy; 268 269 return(val); 270} 271 272static int pcn_miibus_writereg(dev, phy, reg, data) 273 device_t dev; 274 int phy, reg, data; 275{ 276 struct pcn_softc *sc; 277 278 sc = device_get_softc(dev); 279 280 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 281 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 282 283 return(0); 284} 285 286static void pcn_miibus_statchg(dev) 287 device_t dev; 288{ 289 struct pcn_softc *sc; 290 struct mii_data *mii; 291 292 sc = device_get_softc(dev); 293 mii = device_get_softc(sc->pcn_miibus); 294 295 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 296 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 297 } else { 298 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 299 } 300 301 return; 302} 303 304#define DC_POLY 0xEDB88320 305 306static u_int32_t pcn_crc(addr) 307 caddr_t addr; 308{ 309 u_int32_t idx, bit, data, crc; 310 311 /* Compute CRC for the address value. */ 312 crc = 0xFFFFFFFF; /* initial value */ 313 314 for (idx = 0; idx < 6; idx++) { 315 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 316 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 317 } 318 319 return ((crc >> 26) & 0x3F); 320} 321 322static void pcn_setmulti(sc) 323 struct pcn_softc *sc; 324{ 325 struct ifnet *ifp; 326 struct ifmultiaddr *ifma; 327 u_int32_t h, i; 328 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 329 330 ifp = &sc->arpcom.ac_if; 331 332 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 333 334 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 335 for (i = 0; i < 4; i++) 336 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 337 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 338 return; 339 } 340 341 /* first, zot all the existing hash bits */ 342 for (i = 0; i < 4; i++) 343 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 344 345 /* now program new ones */ 346 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 347 if (ifma->ifma_addr->sa_family != AF_LINK) 348 continue; 349 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 350 hashes[h >> 4] |= 1 << (h & 0xF); 351 } 352 353 for (i = 0; i < 4; i++) 354 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 355 356 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 357 358 return; 359} 360 361static void pcn_reset(sc) 362 struct pcn_softc *sc; 363{ 364 /* 365 * Issue a reset by reading from the RESET register. 366 * Note that we don't know if the chip is operating in 367 * 16-bit or 32-bit mode at this point, so we attempt 368 * to reset the chip both ways. If one fails, the other 369 * will succeed. 370 */ 371 CSR_READ_2(sc, PCN_IO16_RESET); 372 CSR_READ_4(sc, PCN_IO32_RESET); 373 374 /* Wait a little while for the chip to get its brains in order. */ 375 DELAY(1000); 376 377 /* Select 32-bit (DWIO) mode */ 378 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 379 380 /* Select software style 3. */ 381 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 382 383 return; 384} 385 386/* 387 * Probe for an AMD chip. Check the PCI vendor and device 388 * IDs against our list and return a device name if we find a match. 389 */ 390static int pcn_probe(dev) 391 device_t dev; 392{ 393 struct pcn_type *t; 394 struct pcn_softc *sc; 395 int rid; 396 u_int32_t chip_id; 397 398 t = pcn_devs; 399 sc = device_get_softc(dev); 400 401 while(t->pcn_name != NULL) { 402 if ((pci_get_vendor(dev) == t->pcn_vid) && 403 (pci_get_device(dev) == t->pcn_did)) { 404 /* 405 * Temporarily map the I/O space 406 * so we can read the chip ID register. 407 */ 408 rid = PCN_RID; 409 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 410 0, ~0, 1, RF_ACTIVE); 411 if (sc->pcn_res == NULL) { 412 device_printf(dev, 413 "couldn't map ports/memory\n"); 414 return(ENXIO); 415 } 416 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 417 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 418 mtx_init(&sc->pcn_mtx, 419 device_get_nameunit(dev), MTX_DEF); 420 PCN_LOCK(sc); 421 /* 422 * Note: we can *NOT* put the chip into 423 * 32-bit mode yet. The lnc driver will only 424 * work in 16-bit mode, and once the chip 425 * goes into 32-bit mode, the only way to 426 * get it out again is with a hardware reset. 427 * So if pcn_probe() is called before the 428 * lnc driver's probe routine, the chip will 429 * be locked into 32-bit operation and the lnc 430 * driver will be unable to attach to it. 431 * Note II: if the chip happens to already 432 * be in 32-bit mode, we still need to check 433 * the chip ID, but first we have to detect 434 * 32-bit mode using only 16-bit operations. 435 * The safest way to do this is to read the 436 * PCI subsystem ID from BCR23/24 and compare 437 * that with the value read from PCI config 438 * space. 439 */ 440 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 441 chip_id <<= 16; 442 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 443 if (chip_id == pci_read_config(dev, 444 PCIR_SUBVEND_0, 4)) { 445 /* We're in 16-bit mode. */ 446 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 447 chip_id <<= 16; 448 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 449 } else { 450 /* We're in 32-bit mode. */ 451 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 452 chip_id <<= 16; 453 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 454 } 455 bus_release_resource(dev, PCN_RES, 456 PCN_RID, sc->pcn_res); 457 PCN_UNLOCK(sc); 458 mtx_destroy(&sc->pcn_mtx); 459 chip_id >>= 12; 460 sc->pcn_type = chip_id & PART_MASK; 461 switch(sc->pcn_type) { 462 case Am79C971: 463 case Am79C972: 464 case Am79C973: 465 case Am79C975: 466 case Am79C976: 467 case Am79C978: 468 break; 469 default: 470 return(ENXIO); 471 break; 472 } 473 device_set_desc(dev, t->pcn_name); 474 return(0); 475 } 476 t++; 477 } 478 479 return(ENXIO); 480} 481 482/* 483 * Attach the interface. Allocate softc structures, do ifmedia 484 * setup and ethernet/BPF attach. 485 */ 486static int pcn_attach(dev) 487 device_t dev; 488{ 489 u_int32_t eaddr[2]; 490 u_int32_t command; 491 struct pcn_softc *sc; 492 struct ifnet *ifp; 493 int unit, error = 0, rid; 494 495 sc = device_get_softc(dev); 496 unit = device_get_unit(dev); 497 498 /* Initialize our mutex. */ 499 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 500 PCN_LOCK(sc); 501 502 /* 503 * Handle power management nonsense. 504 */ 505 506 command = pci_read_config(dev, PCN_PCI_CAPID, 4) & 0x000000FF; 507 if (command == 0x01) { 508 509 command = pci_read_config(dev, PCN_PCI_PWRMGMTCTRL, 4); 510 if (command & PCN_PSTATE_MASK) { 511 u_int32_t iobase, membase, irq; 512 513 /* Save important PCI config data. */ 514 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 515 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 516 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 517 518 /* Reset the power state. */ 519 printf("pcn%d: chip is in D%d power mode " 520 "-- setting to D0\n", unit, command & PCN_PSTATE_MASK); 521 command &= 0xFFFFFFFC; 522 pci_write_config(dev, PCN_PCI_PWRMGMTCTRL, command, 4); 523 524 /* Restore PCI config data. */ 525 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 526 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 527 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 528 } 529 } 530 531 /* 532 * Map control/status registers. 533 */ 534 command = pci_read_config(dev, PCIR_COMMAND, 4); 535 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 536 pci_write_config(dev, PCIR_COMMAND, command, 4); 537 command = pci_read_config(dev, PCIR_COMMAND, 4); 538 539#ifdef PCN_USEIOSPACE 540 if (!(command & PCIM_CMD_PORTEN)) { 541 printf("pcn%d: failed to enable I/O ports!\n", unit); 542 error = ENXIO;; 543 goto fail; 544 } 545#else 546 if (!(command & PCIM_CMD_MEMEN)) { 547 printf("pcn%d: failed to enable memory mapping!\n", unit); 548 error = ENXIO;; 549 goto fail; 550 } 551#endif 552 553 rid = PCN_RID; 554 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 555 0, ~0, 1, RF_ACTIVE); 556 557 if (sc->pcn_res == NULL) { 558 printf("pcn%d: couldn't map ports/memory\n", unit); 559 error = ENXIO; 560 goto fail; 561 } 562 563 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 564 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 565 566 /* Allocate interrupt */ 567 rid = 0; 568 sc->pcn_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 569 RF_SHAREABLE | RF_ACTIVE); 570 571 if (sc->pcn_irq == NULL) { 572 printf("pcn%d: couldn't map interrupt\n", unit); 573 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 574 error = ENXIO; 575 goto fail; 576 } 577 578 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 579 pcn_intr, sc, &sc->pcn_intrhand); 580 581 if (error) { 582 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_res); 583 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 584 printf("pcn%d: couldn't set up irq\n", unit); 585 goto fail; 586 } 587 588 /* Reset the adapter. */ 589 pcn_reset(sc); 590 591 /* 592 * Get station address from the EEPROM. 593 */ 594 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 595 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 596 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 597 598 /* 599 * An AMD chip was detected. Inform the world. 600 */ 601 printf("pcn%d: Ethernet address: %6D\n", unit, 602 sc->arpcom.ac_enaddr, ":"); 603 604 sc->pcn_unit = unit; 605 callout_handle_init(&sc->pcn_stat_ch); 606 607 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 608 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 609 610 if (sc->pcn_ldata == NULL) { 611 printf("pcn%d: no memory for list buffers!\n", unit); 612 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 613 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 614 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 615 error = ENXIO; 616 goto fail; 617 } 618 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 619 620 ifp = &sc->arpcom.ac_if; 621 ifp->if_softc = sc; 622 ifp->if_unit = unit; 623 ifp->if_name = "pcn"; 624 ifp->if_mtu = ETHERMTU; 625 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 626 ifp->if_ioctl = pcn_ioctl; 627 ifp->if_output = ether_output; 628 ifp->if_start = pcn_start; 629 ifp->if_watchdog = pcn_watchdog; 630 ifp->if_init = pcn_init; 631 ifp->if_baudrate = 10000000; 632 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 633 634 /* 635 * Do MII setup. 636 */ 637 if (mii_phy_probe(dev, &sc->pcn_miibus, 638 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 639 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 640 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 641 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 642 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 643 error = ENXIO; 644 goto fail; 645 } 646 647 /* 648 * Call MI attach routine. 649 */ 650 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 651 callout_handle_init(&sc->pcn_stat_ch); 652 PCN_UNLOCK(sc); 653 return(0); 654 655fail: 656 PCN_UNLOCK(sc); 657 mtx_destroy(&sc->pcn_mtx); 658 659 return(error); 660} 661 662static int pcn_detach(dev) 663 device_t dev; 664{ 665 struct pcn_softc *sc; 666 struct ifnet *ifp; 667 668 sc = device_get_softc(dev); 669 ifp = &sc->arpcom.ac_if; 670 671 PCN_LOCK(sc); 672 673 pcn_reset(sc); 674 pcn_stop(sc); 675 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 676 677 if (sc->pcn_miibus != NULL) { 678 bus_generic_detach(dev); 679 device_delete_child(dev, sc->pcn_miibus); 680 } 681 682 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 683 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 684 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 685 686 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), M_DEVBUF); 687 PCN_UNLOCK(sc); 688 689 mtx_destroy(&sc->pcn_mtx); 690 691 return(0); 692} 693 694/* 695 * Initialize the transmit descriptors. 696 */ 697static int pcn_list_tx_init(sc) 698 struct pcn_softc *sc; 699{ 700 struct pcn_list_data *ld; 701 struct pcn_ring_data *cd; 702 int i; 703 704 cd = &sc->pcn_cdata; 705 ld = sc->pcn_ldata; 706 707 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 708 cd->pcn_tx_chain[i] = NULL; 709 ld->pcn_tx_list[i].pcn_tbaddr = 0; 710 ld->pcn_tx_list[i].pcn_txctl = 0; 711 ld->pcn_tx_list[i].pcn_txstat = 0; 712 } 713 714 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 715 716 return(0); 717} 718 719 720/* 721 * Initialize the RX descriptors and allocate mbufs for them. 722 */ 723static int pcn_list_rx_init(sc) 724 struct pcn_softc *sc; 725{ 726 struct pcn_list_data *ld; 727 struct pcn_ring_data *cd; 728 int i; 729 730 ld = sc->pcn_ldata; 731 cd = &sc->pcn_cdata; 732 733 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 734 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 735 return(ENOBUFS); 736 } 737 738 cd->pcn_rx_prod = 0; 739 740 return(0); 741} 742 743/* 744 * Initialize an RX descriptor and attach an MBUF cluster. 745 */ 746static int pcn_newbuf(sc, idx, m) 747 struct pcn_softc *sc; 748 int idx; 749 struct mbuf *m; 750{ 751 struct mbuf *m_new = NULL; 752 struct pcn_rx_desc *c; 753 754 c = &sc->pcn_ldata->pcn_rx_list[idx]; 755 756 if (m == NULL) { 757 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 758 if (m_new == NULL) { 759 printf("pcn%d: no memory for rx list " 760 "-- packet dropped!\n", sc->pcn_unit); 761 return(ENOBUFS); 762 } 763 764 MCLGET(m_new, M_DONTWAIT); 765 if (!(m_new->m_flags & M_EXT)) { 766 printf("pcn%d: no memory for rx list " 767 "-- packet dropped!\n", sc->pcn_unit); 768 m_freem(m_new); 769 return(ENOBUFS); 770 } 771 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 772 } else { 773 m_new = m; 774 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 775 m_new->m_data = m_new->m_ext.ext_buf; 776 } 777 778 m_adj(m_new, ETHER_ALIGN); 779 780 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 781 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 782 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 783 c->pcn_bufsz |= PCN_RXLEN_MBO; 784 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 785 786 return(0); 787} 788 789/* 790 * A frame has been uploaded: pass the resulting mbuf chain up to 791 * the higher level protocols. 792 */ 793static void pcn_rxeof(sc) 794 struct pcn_softc *sc; 795{ 796 struct ether_header *eh; 797 struct mbuf *m; 798 struct ifnet *ifp; 799 struct pcn_rx_desc *cur_rx; 800 int i; 801 802 ifp = &sc->arpcom.ac_if; 803 i = sc->pcn_cdata.pcn_rx_prod; 804 805 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 806 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 807 m = sc->pcn_cdata.pcn_rx_chain[i]; 808 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 809 810 /* 811 * If an error occurs, update stats, clear the 812 * status word and leave the mbuf cluster in place: 813 * it should simply get re-used next time this descriptor 814 * comes up in the ring. 815 */ 816 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 817 ifp->if_ierrors++; 818 pcn_newbuf(sc, i, m); 819 PCN_INC(i, PCN_RX_LIST_CNT); 820 continue; 821 } 822 823 if (pcn_newbuf(sc, i, NULL)) { 824 /* Ran out of mbufs; recycle this one. */ 825 pcn_newbuf(sc, i, m); 826 ifp->if_ierrors++; 827 PCN_INC(i, PCN_RX_LIST_CNT); 828 continue; 829 } 830 831 PCN_INC(i, PCN_RX_LIST_CNT); 832 833 /* No errors; receive the packet. */ 834 ifp->if_ipackets++; 835 eh = mtod(m, struct ether_header *); 836 m->m_len = m->m_pkthdr.len = 837 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 838 m->m_pkthdr.rcvif = ifp; 839 840 /* Remove header from mbuf and pass it on. */ 841 m_adj(m, sizeof(struct ether_header)); 842 ether_input(ifp, eh, m); 843 } 844 845 sc->pcn_cdata.pcn_rx_prod = i; 846 847 return; 848} 849 850/* 851 * A frame was downloaded to the chip. It's safe for us to clean up 852 * the list buffers. 853 */ 854 855static void pcn_txeof(sc) 856 struct pcn_softc *sc; 857{ 858 struct pcn_tx_desc *cur_tx = NULL; 859 struct ifnet *ifp; 860 u_int32_t idx; 861 862 ifp = &sc->arpcom.ac_if; 863 864 /* Clear the timeout timer. */ 865 ifp->if_timer = 0; 866 867 /* 868 * Go through our tx list and free mbufs for those 869 * frames that have been transmitted. 870 */ 871 idx = sc->pcn_cdata.pcn_tx_cons; 872 while (idx != sc->pcn_cdata.pcn_tx_prod) { 873 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 874 875 if (!PCN_OWN_TXDESC(cur_tx)) 876 break; 877 878 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 879 sc->pcn_cdata.pcn_tx_cnt--; 880 PCN_INC(idx, PCN_TX_LIST_CNT); 881 continue; 882 } 883 884 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 885 ifp->if_oerrors++; 886 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 887 ifp->if_collisions++; 888 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 889 ifp->if_collisions++; 890 } 891 892 ifp->if_collisions += 893 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 894 895 ifp->if_opackets++; 896 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 897 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 898 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 899 } 900 901 sc->pcn_cdata.pcn_tx_cnt--; 902 PCN_INC(idx, PCN_TX_LIST_CNT); 903 ifp->if_timer = 0; 904 } 905 906 sc->pcn_cdata.pcn_tx_cons = idx; 907 908 if (cur_tx != NULL) 909 ifp->if_flags &= ~IFF_OACTIVE; 910 911 return; 912} 913 914static void pcn_tick(xsc) 915 void *xsc; 916{ 917 struct pcn_softc *sc; 918 struct mii_data *mii; 919 struct ifnet *ifp; 920 921 sc = xsc; 922 ifp = &sc->arpcom.ac_if; 923 PCN_LOCK(sc); 924 925 mii = device_get_softc(sc->pcn_miibus); 926 mii_tick(mii); 927 928 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 929 sc->pcn_link = 0; 930 931 if (!sc->pcn_link) { 932 mii_pollstat(mii); 933 if (mii->mii_media_status & IFM_ACTIVE && 934 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 935 sc->pcn_link++; 936 if (ifp->if_snd.ifq_head != NULL) 937 pcn_start(ifp); 938 } 939 940 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 941 942 PCN_UNLOCK(sc); 943 944 return; 945} 946 947static void pcn_intr(arg) 948 void *arg; 949{ 950 struct pcn_softc *sc; 951 struct ifnet *ifp; 952 u_int32_t status; 953 954 sc = arg; 955 ifp = &sc->arpcom.ac_if; 956 957 /* Supress unwanted interrupts */ 958 if (!(ifp->if_flags & IFF_UP)) { 959 pcn_stop(sc); 960 return; 961 } 962 963 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 964 965 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 966 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 967 968 if (status & PCN_CSR_RINT) 969 pcn_rxeof(sc); 970 971 if (status & PCN_CSR_TINT) 972 pcn_txeof(sc); 973 974 if (status & PCN_CSR_ERR) { 975 pcn_init(sc); 976 break; 977 } 978 } 979 980 if (ifp->if_snd.ifq_head != NULL) 981 pcn_start(ifp); 982 983 return; 984} 985 986/* 987 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 988 * pointers to the fragment pointers. 989 */ 990static int pcn_encap(sc, m_head, txidx) 991 struct pcn_softc *sc; 992 struct mbuf *m_head; 993 u_int32_t *txidx; 994{ 995 struct pcn_tx_desc *f = NULL; 996 struct mbuf *m; 997 int frag, cur, cnt = 0; 998 999 /* 1000 * Start packing the mbufs in this chain into 1001 * the fragment pointers. Stop when we run out 1002 * of fragments or hit the end of the mbuf chain. 1003 */ 1004 m = m_head; 1005 cur = frag = *txidx; 1006 1007 for (m = m_head; m != NULL; m = m->m_next) { 1008 if (m->m_len != 0) { 1009 if ((PCN_TX_LIST_CNT - 1010 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 1011 return(ENOBUFS); 1012 f = &sc->pcn_ldata->pcn_tx_list[frag]; 1013 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 1014 f->pcn_txctl |= PCN_TXCTL_MBO; 1015 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 1016 if (cnt == 0) 1017 f->pcn_txctl |= PCN_TXCTL_STP; 1018 else 1019 f->pcn_txctl |= PCN_TXCTL_OWN; 1020 cur = frag; 1021 PCN_INC(frag, PCN_TX_LIST_CNT); 1022 cnt++; 1023 } 1024 } 1025 1026 if (m != NULL) 1027 return(ENOBUFS); 1028 1029 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1030 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1031 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1032 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1033 sc->pcn_cdata.pcn_tx_cnt += cnt; 1034 *txidx = frag; 1035 1036 return(0); 1037} 1038 1039/* 1040 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1041 * to the mbuf data regions directly in the transmit lists. We also save a 1042 * copy of the pointers since the transmit list fragment pointers are 1043 * physical addresses. 1044 */ 1045static void pcn_start(ifp) 1046 struct ifnet *ifp; 1047{ 1048 struct pcn_softc *sc; 1049 struct mbuf *m_head = NULL; 1050 u_int32_t idx; 1051 1052 sc = ifp->if_softc; 1053 1054 PCN_LOCK(sc); 1055 1056 if (!sc->pcn_link) { 1057 PCN_UNLOCK(sc); 1058 return; 1059 } 1060 1061 idx = sc->pcn_cdata.pcn_tx_prod; 1062 1063 if (ifp->if_flags & IFF_OACTIVE) { 1064 PCN_UNLOCK(sc); 1065 return; 1066 } 1067 1068 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1069 IF_DEQUEUE(&ifp->if_snd, m_head); 1070 if (m_head == NULL) 1071 break; 1072 1073 if (pcn_encap(sc, m_head, &idx)) { 1074 IF_PREPEND(&ifp->if_snd, m_head); 1075 ifp->if_flags |= IFF_OACTIVE; 1076 break; 1077 } 1078 1079 /* 1080 * If there's a BPF listener, bounce a copy of this frame 1081 * to him. 1082 */ 1083 if (ifp->if_bpf) 1084 bpf_mtap(ifp, m_head); 1085 1086 } 1087 1088 /* Transmit */ 1089 sc->pcn_cdata.pcn_tx_prod = idx; 1090 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1091 1092 /* 1093 * Set a timeout in case the chip goes out to lunch. 1094 */ 1095 ifp->if_timer = 5; 1096 1097 PCN_UNLOCK(sc); 1098 1099 return; 1100} 1101 1102static void pcn_setfilt(ifp) 1103 struct ifnet *ifp; 1104{ 1105 struct pcn_softc *sc; 1106 1107 sc = ifp->if_softc; 1108 1109 /* If we want promiscuous mode, set the allframes bit. */ 1110 if (ifp->if_flags & IFF_PROMISC) { 1111 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1112 } else { 1113 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1114 } 1115 1116 /* Set the capture broadcast bit to capture broadcast frames. */ 1117 if (ifp->if_flags & IFF_BROADCAST) { 1118 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1119 } else { 1120 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1121 } 1122 1123 return; 1124} 1125 1126static void pcn_init(xsc) 1127 void *xsc; 1128{ 1129 struct pcn_softc *sc = xsc; 1130 struct ifnet *ifp = &sc->arpcom.ac_if; 1131 struct mii_data *mii = NULL; 1132 1133 PCN_LOCK(sc); 1134 1135 /* 1136 * Cancel pending I/O and free all RX/TX buffers. 1137 */ 1138 pcn_stop(sc); 1139 pcn_reset(sc); 1140 1141 mii = device_get_softc(sc->pcn_miibus); 1142 1143 /* Set MAC address */ 1144 pcn_csr_write(sc, PCN_CSR_PAR0, 1145 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1146 pcn_csr_write(sc, PCN_CSR_PAR1, 1147 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1148 pcn_csr_write(sc, PCN_CSR_PAR2, 1149 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1150 1151 /* Init circular RX list. */ 1152 if (pcn_list_rx_init(sc) == ENOBUFS) { 1153 printf("pcn%d: initialization failed: no " 1154 "memory for rx buffers\n", sc->pcn_unit); 1155 pcn_stop(sc); 1156 PCN_UNLOCK(sc); 1157 return; 1158 } 1159 1160 /* 1161 * Init tx descriptors. 1162 */ 1163 pcn_list_tx_init(sc); 1164 1165 /* Set up the mode register. */ 1166 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1167 1168 /* Set up RX filter. */ 1169 pcn_setfilt(ifp); 1170 1171 /* 1172 * Load the multicast filter. 1173 */ 1174 pcn_setmulti(sc); 1175 1176 /* 1177 * Load the addresses of the RX and TX lists. 1178 */ 1179 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1180 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1181 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1182 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1183 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1184 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1185 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1186 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1187 1188 /* Set the RX and TX ring sizes. */ 1189 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1190 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1191 1192 /* We're not using the initialization block. */ 1193 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1194 1195 /* Enable fast suspend mode. */ 1196 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1197 1198 /* 1199 * Enable burst read and write. Also set the no underflow 1200 * bit. This will avoid transmit underruns in certain 1201 * conditions while still providing decent performance. 1202 */ 1203 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1204 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1205 1206 /* Enable graceful recovery from underflow. */ 1207 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1208 1209 /* Enable auto-padding of short TX frames. */ 1210 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1211 1212 /* Disable MII autoneg (we handle this ourselves). */ 1213 PCN_BCR_CLRBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1214 1215 if (sc->pcn_type == Am79C978) 1216 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1217 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1218 1219 /* Enable interrupts and start the controller running. */ 1220 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1221 1222 mii_mediachg(mii); 1223 1224 ifp->if_flags |= IFF_RUNNING; 1225 ifp->if_flags &= ~IFF_OACTIVE; 1226 1227 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 1228 PCN_UNLOCK(sc); 1229 1230 return; 1231} 1232 1233/* 1234 * Set media options. 1235 */ 1236static int pcn_ifmedia_upd(ifp) 1237 struct ifnet *ifp; 1238{ 1239 struct pcn_softc *sc; 1240 struct mii_data *mii; 1241 1242 sc = ifp->if_softc; 1243 mii = device_get_softc(sc->pcn_miibus); 1244 1245 sc->pcn_link = 0; 1246 if (mii->mii_instance) { 1247 struct mii_softc *miisc; 1248 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1249 mii_phy_reset(miisc); 1250 } 1251 mii_mediachg(mii); 1252 1253 return(0); 1254} 1255 1256/* 1257 * Report current media status. 1258 */ 1259static void pcn_ifmedia_sts(ifp, ifmr) 1260 struct ifnet *ifp; 1261 struct ifmediareq *ifmr; 1262{ 1263 struct pcn_softc *sc; 1264 struct mii_data *mii; 1265 1266 sc = ifp->if_softc; 1267 1268 mii = device_get_softc(sc->pcn_miibus); 1269 mii_pollstat(mii); 1270 ifmr->ifm_active = mii->mii_media_active; 1271 ifmr->ifm_status = mii->mii_media_status; 1272 1273 return; 1274} 1275 1276static int pcn_ioctl(ifp, command, data) 1277 struct ifnet *ifp; 1278 u_long command; 1279 caddr_t data; 1280{ 1281 struct pcn_softc *sc = ifp->if_softc; 1282 struct ifreq *ifr = (struct ifreq *) data; 1283 struct mii_data *mii = NULL; 1284 int error = 0; 1285 1286 PCN_LOCK(sc); 1287 1288 switch(command) { 1289 case SIOCSIFADDR: 1290 case SIOCGIFADDR: 1291 case SIOCSIFMTU: 1292 error = ether_ioctl(ifp, command, data); 1293 break; 1294 case SIOCSIFFLAGS: 1295 if (ifp->if_flags & IFF_UP) { 1296 if (ifp->if_flags & IFF_RUNNING && 1297 ifp->if_flags & IFF_PROMISC && 1298 !(sc->pcn_if_flags & IFF_PROMISC)) { 1299 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1300 PCN_EXTCTL1_SPND); 1301 pcn_setfilt(ifp); 1302 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1303 PCN_EXTCTL1_SPND); 1304 pcn_csr_write(sc, PCN_CSR_CSR, 1305 PCN_CSR_INTEN|PCN_CSR_START); 1306 } else if (ifp->if_flags & IFF_RUNNING && 1307 !(ifp->if_flags & IFF_PROMISC) && 1308 sc->pcn_if_flags & IFF_PROMISC) { 1309 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1310 PCN_EXTCTL1_SPND); 1311 pcn_setfilt(ifp); 1312 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1313 PCN_EXTCTL1_SPND); 1314 pcn_csr_write(sc, PCN_CSR_CSR, 1315 PCN_CSR_INTEN|PCN_CSR_START); 1316 } else if (!(ifp->if_flags & IFF_RUNNING)) 1317 pcn_init(sc); 1318 } else { 1319 if (ifp->if_flags & IFF_RUNNING) 1320 pcn_stop(sc); 1321 } 1322 sc->pcn_if_flags = ifp->if_flags; 1323 error = 0; 1324 break; 1325 case SIOCADDMULTI: 1326 case SIOCDELMULTI: 1327 pcn_setmulti(sc); 1328 error = 0; 1329 break; 1330 case SIOCGIFMEDIA: 1331 case SIOCSIFMEDIA: 1332 mii = device_get_softc(sc->pcn_miibus); 1333 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1334 break; 1335 default: 1336 error = EINVAL; 1337 break; 1338 } 1339 1340 PCN_UNLOCK(sc); 1341 1342 return(error); 1343} 1344 1345static void pcn_watchdog(ifp) 1346 struct ifnet *ifp; 1347{ 1348 struct pcn_softc *sc; 1349 1350 sc = ifp->if_softc; 1351 1352 PCN_LOCK(sc); 1353 1354 ifp->if_oerrors++; 1355 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1356 1357 pcn_stop(sc); 1358 pcn_reset(sc); 1359 pcn_init(sc); 1360 1361 if (ifp->if_snd.ifq_head != NULL) 1362 pcn_start(ifp); 1363 1364 PCN_UNLOCK(sc); 1365 1366 return; 1367} 1368 1369/* 1370 * Stop the adapter and free any mbufs allocated to the 1371 * RX and TX lists. 1372 */ 1373static void pcn_stop(sc) 1374 struct pcn_softc *sc; 1375{ 1376 register int i; 1377 struct ifnet *ifp; 1378 1379 ifp = &sc->arpcom.ac_if; 1380 PCN_LOCK(sc); 1381 ifp->if_timer = 0; 1382 1383 untimeout(pcn_tick, sc, sc->pcn_stat_ch); 1384 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1385 sc->pcn_link = 0; 1386 1387 /* 1388 * Free data in the RX lists. 1389 */ 1390 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1391 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1392 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1393 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1394 } 1395 } 1396 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1397 sizeof(sc->pcn_ldata->pcn_rx_list)); 1398 1399 /* 1400 * Free the TX list buffers. 1401 */ 1402 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1403 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1404 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1405 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1406 } 1407 } 1408 1409 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1410 sizeof(sc->pcn_ldata->pcn_tx_list)); 1411 1412 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1413 PCN_UNLOCK(sc); 1414 1415 return; 1416} 1417 1418/* 1419 * Stop all chip I/O so that the kernel's probe routines don't 1420 * get confused by errant DMAs when rebooting. 1421 */ 1422static void pcn_shutdown(dev) 1423 device_t dev; 1424{ 1425 struct pcn_softc *sc; 1426 1427 sc = device_get_softc(dev); 1428 1429 PCN_LOCK(sc); 1430 pcn_reset(sc); 1431 pcn_stop(sc); 1432 PCN_UNLOCK(sc); 1433 1434 return; 1435} 1436