if_pcn.c revision 66690
1/* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/pci/if_pcn.c 66690 2000-10-05 19:40:19Z wpaul $ 34 */ 35 36/* 37 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 38 * from http://www.amd.com. 39 * 40 * Written by Bill Paul <wpaul@osd.bsdi.com> 41 */ 42 43/* 44 * The AMD PCnet/PCI controllers are more advanced and functional 45 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 46 * backwards compatibility with the LANCE and thus can be made 47 * to work with older LANCE drivers. This is in fact how the 48 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 49 * is that the PCnet/PCI devices offer several performance enhancements 50 * which can't be exploited in LANCE compatibility mode. Chief among 51 * these enhancements is the ability to perform PCI DMA operations 52 * using 32-bit addressing (which eliminates the need for ISA 53 * bounce-buffering), and special receive buffer alignment (which 54 * allows the receive handler to pass packets to the upper protocol 55 * layers without copying on both the x86 and alpha platforms). 56 */ 57 58#include <sys/param.h> 59#include <sys/systm.h> 60#include <sys/sockio.h> 61#include <sys/mbuf.h> 62#include <sys/malloc.h> 63#include <sys/kernel.h> 64#include <sys/socket.h> 65 66#include <net/if.h> 67#include <net/if_arp.h> 68#include <net/ethernet.h> 69#include <net/if_dl.h> 70#include <net/if_media.h> 71 72#include <net/bpf.h> 73 74#include <vm/vm.h> /* for vtophys */ 75#include <vm/pmap.h> /* for vtophys */ 76#include <machine/clock.h> /* for DELAY */ 77#include <machine/bus_pio.h> 78#include <machine/bus_memio.h> 79#include <machine/bus.h> 80#include <machine/resource.h> 81#include <sys/bus.h> 82#include <sys/rman.h> 83 84#include <dev/mii/mii.h> 85#include <dev/mii/miivar.h> 86 87#include <pci/pcireg.h> 88#include <pci/pcivar.h> 89 90#define PCN_USEIOSPACE 91 92#include <pci/if_pcnreg.h> 93 94MODULE_DEPEND(pcn, miibus, 1, 1, 1); 95 96/* "controller miibus0" required. See GENERIC if you get errors here. */ 97#include "miibus_if.h" 98 99#ifndef lint 100static const char rcsid[] = 101 "$FreeBSD: head/sys/pci/if_pcn.c 66690 2000-10-05 19:40:19Z wpaul $"; 102#endif 103 104/* 105 * Various supported device vendors/types and their names. 106 */ 107static struct pcn_type pcn_devs[] = { 108 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 109 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 110 { 0, 0, NULL } 111}; 112 113static u_int32_t pcn_csr_read __P((struct pcn_softc *, int)); 114static void pcn_csr_write __P((struct pcn_softc *, int, int)); 115static u_int32_t pcn_bcr_read __P((struct pcn_softc *, int)); 116static void pcn_bcr_write __P((struct pcn_softc *, int, int)); 117 118static int pcn_probe __P((device_t)); 119static int pcn_attach __P((device_t)); 120static int pcn_detach __P((device_t)); 121 122static int pcn_newbuf __P((struct pcn_softc *, int, struct mbuf *)); 123static int pcn_encap __P((struct pcn_softc *, 124 struct mbuf *, u_int32_t *)); 125static void pcn_rxeof __P((struct pcn_softc *)); 126static void pcn_txeof __P((struct pcn_softc *)); 127static void pcn_intr __P((void *)); 128static void pcn_tick __P((void *)); 129static void pcn_start __P((struct ifnet *)); 130static int pcn_ioctl __P((struct ifnet *, u_long, caddr_t)); 131static void pcn_init __P((void *)); 132static void pcn_stop __P((struct pcn_softc *)); 133static void pcn_watchdog __P((struct ifnet *)); 134static void pcn_shutdown __P((device_t)); 135static int pcn_ifmedia_upd __P((struct ifnet *)); 136static void pcn_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 137 138static int pcn_miibus_readreg __P((device_t, int, int)); 139static int pcn_miibus_writereg __P((device_t, int, int, int)); 140static void pcn_miibus_statchg __P((device_t)); 141 142static void pcn_setmulti __P((struct pcn_softc *)); 143static u_int32_t pcn_crc __P((caddr_t)); 144static void pcn_reset __P((struct pcn_softc *)); 145static int pcn_list_rx_init __P((struct pcn_softc *)); 146static int pcn_list_tx_init __P((struct pcn_softc *)); 147 148#ifdef PCN_USEIOSPACE 149#define PCN_RES SYS_RES_IOPORT 150#define PCN_RID PCN_PCI_LOIO 151#else 152#define PCN_RES SYS_RES_MEMORY 153#define PCN_RID PCN_PCI_LOMEM 154#endif 155 156static device_method_t pcn_methods[] = { 157 /* Device interface */ 158 DEVMETHOD(device_probe, pcn_probe), 159 DEVMETHOD(device_attach, pcn_attach), 160 DEVMETHOD(device_detach, pcn_detach), 161 DEVMETHOD(device_shutdown, pcn_shutdown), 162 163 /* bus interface */ 164 DEVMETHOD(bus_print_child, bus_generic_print_child), 165 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 166 167 /* MII interface */ 168 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 169 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 170 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 171 172 { 0, 0 } 173}; 174 175static driver_t pcn_driver = { 176 "pcn", 177 pcn_methods, 178 sizeof(struct pcn_softc) 179}; 180 181static devclass_t pcn_devclass; 182 183DRIVER_MODULE(if_pcn, pci, pcn_driver, pcn_devclass, 0, 0); 184DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 185 186#define PCN_CSR_SETBIT(sc, reg, x) \ 187 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 188 189#define PCN_CSR_CLRBIT(sc, reg, x) \ 190 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 191 192#define PCN_BCR_SETBIT(sc, reg, x) \ 193 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 194 195#define PCN_BCR_CLRBIT(sc, reg, x) \ 196 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 197 198static u_int32_t pcn_csr_read(sc, reg) 199 struct pcn_softc *sc; 200 int reg; 201{ 202 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 203 return(CSR_READ_4(sc, PCN_IO32_RDP)); 204} 205 206static void pcn_csr_write(sc, reg, val) 207 struct pcn_softc *sc; 208 int reg; 209{ 210 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 211 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 212 return; 213} 214 215static u_int32_t pcn_bcr_read(sc, reg) 216 struct pcn_softc *sc; 217 int reg; 218{ 219 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 220 return(CSR_READ_4(sc, PCN_IO32_BDP)); 221} 222 223static void pcn_bcr_write(sc, reg, val) 224 struct pcn_softc *sc; 225 int reg; 226{ 227 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 228 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 229 return; 230} 231 232static int pcn_miibus_readreg(dev, phy, reg) 233 device_t dev; 234 int phy, reg; 235{ 236 struct pcn_softc *sc; 237 int val; 238 239 sc = device_get_softc(dev); 240 241 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 242 return(0); 243 244 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 245 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 246 if (val == 0xFFFF) 247 return(0); 248 249 sc->pcn_phyaddr = phy; 250 251 return(val); 252} 253 254static int pcn_miibus_writereg(dev, phy, reg, data) 255 device_t dev; 256 int phy, reg, data; 257{ 258 struct pcn_softc *sc; 259 260 sc = device_get_softc(dev); 261 262 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 263 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 264 265 return(0); 266} 267 268static void pcn_miibus_statchg(dev) 269 device_t dev; 270{ 271 struct pcn_softc *sc; 272 struct mii_data *mii; 273 274 sc = device_get_softc(dev); 275 mii = device_get_softc(sc->pcn_miibus); 276 277 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 278 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 279 } else { 280 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 281 } 282 283 return; 284} 285 286#define DC_POLY 0xEDB88320 287 288static u_int32_t pcn_crc(addr) 289 caddr_t addr; 290{ 291 u_int32_t idx, bit, data, crc; 292 293 /* Compute CRC for the address value. */ 294 crc = 0xFFFFFFFF; /* initial value */ 295 296 for (idx = 0; idx < 6; idx++) { 297 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 298 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 299 } 300 301 return ((crc >> 26) & 0x3F); 302} 303 304static void pcn_setmulti(sc) 305 struct pcn_softc *sc; 306{ 307 struct ifnet *ifp; 308 struct ifmultiaddr *ifma; 309 u_int32_t h, i; 310 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 311 312 ifp = &sc->arpcom.ac_if; 313 314 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 315 316 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 317 for (i = 0; i < 4; i++) 318 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 319 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 320 return; 321 } 322 323 /* first, zot all the existing hash bits */ 324 for (i = 0; i < 4; i++) 325 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 326 327 /* now program new ones */ 328 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 329 ifma = ifma->ifma_link.le_next) { 330 if (ifma->ifma_addr->sa_family != AF_LINK) 331 continue; 332 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 333 hashes[h >> 4] |= 1 << (h & 0xF); 334 } 335 336 for (i = 0; i < 4; i++) 337 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 338 339 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 340 341 return; 342} 343 344static void pcn_reset(sc) 345 struct pcn_softc *sc; 346{ 347 /* 348 * Issue a reset by reading from the RESET register. 349 * Note that we don't know if the chip is operating in 350 * 16-bit or 32-bit mode at this point, so we attempt 351 * to reset the chip both ways. If one fails, the other 352 * will succeed. 353 */ 354 CSR_READ_2(sc, PCN_IO16_RESET); 355 CSR_READ_4(sc, PCN_IO32_RESET); 356 357 /* Wait a little while for the chip to get its brains in order. */ 358 DELAY(1000); 359 360 /* Select 32-bit (DWIO) mode */ 361 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 362 363 /* Select software style 3. */ 364 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 365 366 return; 367} 368 369/* 370 * Probe for an AMD chip. Check the PCI vendor and device 371 * IDs against our list and return a device name if we find a match. 372 */ 373static int pcn_probe(dev) 374 device_t dev; 375{ 376 struct pcn_type *t; 377 struct pcn_softc *sc; 378 int rid; 379 u_int32_t chip_id; 380 381 t = pcn_devs; 382 sc = device_get_softc(dev); 383 384 while(t->pcn_name != NULL) { 385 if ((pci_get_vendor(dev) == t->pcn_vid) && 386 (pci_get_device(dev) == t->pcn_did)) { 387 /* 388 * Temporarily map the I/O space 389 * so we can read the chip ID register. 390 */ 391 rid = PCN_RID; 392 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 393 0, ~0, 1, RF_ACTIVE); 394 if (sc->pcn_res == NULL) { 395 device_printf(dev, 396 "couldn't map ports/memory\n"); 397 return(ENXIO); 398 } 399 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 400 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 401 pcn_reset(sc); 402 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 403 chip_id <<= 16; 404 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 405 bus_release_resource(dev, PCN_RES, 406 PCN_RID, sc->pcn_res); 407 chip_id >>= 12; 408 sc->pcn_type = chip_id & PART_MASK; 409 switch(sc->pcn_type) { 410 case Am79C971: 411 case Am79C972: 412 case Am79C973: 413 case Am79C975: 414 case Am79C976: 415 case Am79C978: 416 break; 417 default: 418 return(ENXIO); 419 break; 420 } 421 device_set_desc(dev, t->pcn_name); 422 return(0); 423 } 424 t++; 425 } 426 427 return(ENXIO); 428} 429 430/* 431 * Attach the interface. Allocate softc structures, do ifmedia 432 * setup and ethernet/BPF attach. 433 */ 434static int pcn_attach(dev) 435 device_t dev; 436{ 437 int s; 438 u_int32_t eaddr[2]; 439 u_int32_t command; 440 struct pcn_softc *sc; 441 struct ifnet *ifp; 442 int unit, error = 0, rid; 443 444 s = splimp(); 445 446 sc = device_get_softc(dev); 447 unit = device_get_unit(dev); 448 449 /* 450 * Handle power management nonsense. 451 */ 452 453 command = pci_read_config(dev, PCN_PCI_CAPID, 4) & 0x000000FF; 454 if (command == 0x01) { 455 456 command = pci_read_config(dev, PCN_PCI_PWRMGMTCTRL, 4); 457 if (command & PCN_PSTATE_MASK) { 458 u_int32_t iobase, membase, irq; 459 460 /* Save important PCI config data. */ 461 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 462 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 463 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 464 465 /* Reset the power state. */ 466 printf("pcn%d: chip is in D%d power mode " 467 "-- setting to D0\n", unit, command & PCN_PSTATE_MASK); 468 command &= 0xFFFFFFFC; 469 pci_write_config(dev, PCN_PCI_PWRMGMTCTRL, command, 4); 470 471 /* Restore PCI config data. */ 472 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 473 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 474 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 475 } 476 } 477 478 /* 479 * Map control/status registers. 480 */ 481 command = pci_read_config(dev, PCIR_COMMAND, 4); 482 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 483 pci_write_config(dev, PCIR_COMMAND, command, 4); 484 command = pci_read_config(dev, PCIR_COMMAND, 4); 485 486#ifdef PCN_USEIOSPACE 487 if (!(command & PCIM_CMD_PORTEN)) { 488 printf("pcn%d: failed to enable I/O ports!\n", unit); 489 error = ENXIO;; 490 goto fail; 491 } 492#else 493 if (!(command & PCIM_CMD_MEMEN)) { 494 printf("pcn%d: failed to enable memory mapping!\n", unit); 495 error = ENXIO;; 496 goto fail; 497 } 498#endif 499 500 rid = PCN_RID; 501 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 502 0, ~0, 1, RF_ACTIVE); 503 504 if (sc->pcn_res == NULL) { 505 printf("pcn%d: couldn't map ports/memory\n", unit); 506 error = ENXIO; 507 goto fail; 508 } 509 510 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 511 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 512 513 /* Allocate interrupt */ 514 rid = 0; 515 sc->pcn_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 516 RF_SHAREABLE | RF_ACTIVE); 517 518 if (sc->pcn_irq == NULL) { 519 printf("pcn%d: couldn't map interrupt\n", unit); 520 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 521 error = ENXIO; 522 goto fail; 523 } 524 525 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 526 pcn_intr, sc, &sc->pcn_intrhand); 527 528 if (error) { 529 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_res); 530 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 531 printf("pcn%d: couldn't set up irq\n", unit); 532 goto fail; 533 } 534 535 /* Reset the adapter. */ 536 pcn_reset(sc); 537 538 /* 539 * Get station address from the EEPROM. 540 */ 541 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 542 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 543 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 544 545 /* 546 * An AMD chip was detected. Inform the world. 547 */ 548 printf("pcn%d: Ethernet address: %6D\n", unit, 549 sc->arpcom.ac_enaddr, ":"); 550 551 sc->pcn_unit = unit; 552 callout_handle_init(&sc->pcn_stat_ch); 553 554 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 555 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 556 557 if (sc->pcn_ldata == NULL) { 558 printf("pcn%d: no memory for list buffers!\n", unit); 559 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 560 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 561 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 562 error = ENXIO; 563 goto fail; 564 } 565 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 566 567 ifp = &sc->arpcom.ac_if; 568 ifp->if_softc = sc; 569 ifp->if_unit = unit; 570 ifp->if_name = "pcn"; 571 ifp->if_mtu = ETHERMTU; 572 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 573 ifp->if_ioctl = pcn_ioctl; 574 ifp->if_output = ether_output; 575 ifp->if_start = pcn_start; 576 ifp->if_watchdog = pcn_watchdog; 577 ifp->if_init = pcn_init; 578 ifp->if_baudrate = 10000000; 579 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 580 581 /* 582 * Do MII setup. 583 */ 584 if (mii_phy_probe(dev, &sc->pcn_miibus, 585 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 586 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 587 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 588 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 589 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 590 error = ENXIO; 591 goto fail; 592 } 593 594 /* 595 * Call MI attach routine. 596 */ 597 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 598 callout_handle_init(&sc->pcn_stat_ch); 599 600fail: 601 splx(s); 602 return(error); 603} 604 605static int pcn_detach(dev) 606 device_t dev; 607{ 608 struct pcn_softc *sc; 609 struct ifnet *ifp; 610 int s; 611 612 s = splimp(); 613 614 sc = device_get_softc(dev); 615 ifp = &sc->arpcom.ac_if; 616 617 pcn_reset(sc); 618 pcn_stop(sc); 619 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 620 621 if (sc->pcn_miibus != NULL) { 622 bus_generic_detach(dev); 623 device_delete_child(dev, sc->pcn_miibus); 624 } 625 626 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 627 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 628 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 629 630 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), M_DEVBUF); 631 632 splx(s); 633 634 return(0); 635} 636 637/* 638 * Initialize the transmit descriptors. 639 */ 640static int pcn_list_tx_init(sc) 641 struct pcn_softc *sc; 642{ 643 struct pcn_list_data *ld; 644 struct pcn_ring_data *cd; 645 int i; 646 647 cd = &sc->pcn_cdata; 648 ld = sc->pcn_ldata; 649 650 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 651 cd->pcn_tx_chain[i] = NULL; 652 ld->pcn_tx_list[i].pcn_tbaddr = 0; 653 ld->pcn_tx_list[i].pcn_txctl = 0; 654 ld->pcn_tx_list[i].pcn_txstat = 0; 655 } 656 657 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 658 659 return(0); 660} 661 662 663/* 664 * Initialize the RX descriptors and allocate mbufs for them. 665 */ 666static int pcn_list_rx_init(sc) 667 struct pcn_softc *sc; 668{ 669 struct pcn_list_data *ld; 670 struct pcn_ring_data *cd; 671 int i; 672 673 ld = sc->pcn_ldata; 674 cd = &sc->pcn_cdata; 675 676 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 677 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 678 return(ENOBUFS); 679 } 680 681 cd->pcn_rx_prod = 0; 682 683 return(0); 684} 685 686/* 687 * Initialize an RX descriptor and attach an MBUF cluster. 688 */ 689static int pcn_newbuf(sc, idx, m) 690 struct pcn_softc *sc; 691 int idx; 692 struct mbuf *m; 693{ 694 struct mbuf *m_new = NULL; 695 struct pcn_rx_desc *c; 696 697 c = &sc->pcn_ldata->pcn_rx_list[idx]; 698 699 if (m == NULL) { 700 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 701 if (m_new == NULL) { 702 printf("pcn%d: no memory for rx list " 703 "-- packet dropped!\n", sc->pcn_unit); 704 return(ENOBUFS); 705 } 706 707 MCLGET(m_new, M_DONTWAIT); 708 if (!(m_new->m_flags & M_EXT)) { 709 printf("pcn%d: no memory for rx list " 710 "-- packet dropped!\n", sc->pcn_unit); 711 m_freem(m_new); 712 return(ENOBUFS); 713 } 714 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 715 } else { 716 m_new = m; 717 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 718 m_new->m_data = m_new->m_ext.ext_buf; 719 } 720 721 m_adj(m_new, ETHER_ALIGN); 722 723 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 724 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 725 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 726 c->pcn_bufsz |= PCN_RXLEN_MBO; 727 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 728 729 return(0); 730} 731 732/* 733 * A frame has been uploaded: pass the resulting mbuf chain up to 734 * the higher level protocols. 735 */ 736static void pcn_rxeof(sc) 737 struct pcn_softc *sc; 738{ 739 struct ether_header *eh; 740 struct mbuf *m; 741 struct ifnet *ifp; 742 struct pcn_rx_desc *cur_rx; 743 int i; 744 745 ifp = &sc->arpcom.ac_if; 746 i = sc->pcn_cdata.pcn_rx_prod; 747 748 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 749 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 750 m = sc->pcn_cdata.pcn_rx_chain[i]; 751 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 752 753 /* 754 * If an error occurs, update stats, clear the 755 * status word and leave the mbuf cluster in place: 756 * it should simply get re-used next time this descriptor 757 * comes up in the ring. 758 */ 759 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 760 ifp->if_ierrors++; 761 pcn_newbuf(sc, i, m); 762 PCN_INC(i, PCN_RX_LIST_CNT); 763 continue; 764 } 765 766 if (pcn_newbuf(sc, i, NULL)) { 767 /* Ran out of mbufs; recycle this one. */ 768 pcn_newbuf(sc, i, m); 769 ifp->if_ierrors++; 770 PCN_INC(i, PCN_RX_LIST_CNT); 771 continue; 772 } 773 774 PCN_INC(i, PCN_RX_LIST_CNT); 775 776 /* No errors; receive the packet. */ 777 ifp->if_ipackets++; 778 eh = mtod(m, struct ether_header *); 779 m->m_len = m->m_pkthdr.len = 780 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 781 m->m_pkthdr.rcvif = ifp; 782 783 /* Remove header from mbuf and pass it on. */ 784 m_adj(m, sizeof(struct ether_header)); 785 ether_input(ifp, eh, m); 786 } 787 788 sc->pcn_cdata.pcn_rx_prod = i; 789 790 return; 791} 792 793/* 794 * A frame was downloaded to the chip. It's safe for us to clean up 795 * the list buffers. 796 */ 797 798static void pcn_txeof(sc) 799 struct pcn_softc *sc; 800{ 801 struct pcn_tx_desc *cur_tx = NULL; 802 struct ifnet *ifp; 803 u_int32_t idx; 804 805 ifp = &sc->arpcom.ac_if; 806 807 /* Clear the timeout timer. */ 808 ifp->if_timer = 0; 809 810 /* 811 * Go through our tx list and free mbufs for those 812 * frames that have been transmitted. 813 */ 814 idx = sc->pcn_cdata.pcn_tx_cons; 815 while (idx != sc->pcn_cdata.pcn_tx_prod) { 816 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 817 818 if (!PCN_OWN_TXDESC(cur_tx)) 819 break; 820 821 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 822 sc->pcn_cdata.pcn_tx_cnt--; 823 PCN_INC(idx, PCN_TX_LIST_CNT); 824 continue; 825 } 826 827 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 828 ifp->if_oerrors++; 829 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 830 ifp->if_collisions++; 831 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 832 ifp->if_collisions++; 833 } 834 835 ifp->if_collisions += 836 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 837 838 ifp->if_opackets++; 839 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 840 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 841 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 842 } 843 844 sc->pcn_cdata.pcn_tx_cnt--; 845 PCN_INC(idx, PCN_TX_LIST_CNT); 846 ifp->if_timer = 0; 847 } 848 849 sc->pcn_cdata.pcn_tx_cons = idx; 850 851 if (cur_tx != NULL) 852 ifp->if_flags &= ~IFF_OACTIVE; 853 854 return; 855} 856 857static void pcn_tick(xsc) 858 void *xsc; 859{ 860 struct pcn_softc *sc; 861 struct mii_data *mii; 862 struct ifnet *ifp; 863 int s; 864 865 s = splimp(); 866 867 sc = xsc; 868 ifp = &sc->arpcom.ac_if; 869 870 mii = device_get_softc(sc->pcn_miibus); 871 mii_tick(mii); 872 873 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 874 sc->pcn_link = 0; 875 876 if (!sc->pcn_link) { 877 mii_pollstat(mii); 878 if (mii->mii_media_status & IFM_ACTIVE && 879 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 880 sc->pcn_link++; 881 if (ifp->if_snd.ifq_head != NULL) 882 pcn_start(ifp); 883 } 884 885 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 886 887 splx(s); 888 889 return; 890} 891 892static void pcn_intr(arg) 893 void *arg; 894{ 895 struct pcn_softc *sc; 896 struct ifnet *ifp; 897 u_int32_t status; 898 899 sc = arg; 900 ifp = &sc->arpcom.ac_if; 901 902 /* Supress unwanted interrupts */ 903 if (!(ifp->if_flags & IFF_UP)) { 904 pcn_stop(sc); 905 return; 906 } 907 908 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 909 910 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 911 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 912 913 if (status & PCN_CSR_RINT) 914 pcn_rxeof(sc); 915 916 if (status & PCN_CSR_TINT) 917 pcn_txeof(sc); 918 919 if (status & PCN_CSR_ERR) { 920 pcn_init(sc); 921 break; 922 } 923 } 924 925 if (ifp->if_snd.ifq_head != NULL) 926 pcn_start(ifp); 927 928 return; 929} 930 931/* 932 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 933 * pointers to the fragment pointers. 934 */ 935static int pcn_encap(sc, m_head, txidx) 936 struct pcn_softc *sc; 937 struct mbuf *m_head; 938 u_int32_t *txidx; 939{ 940 struct pcn_tx_desc *f = NULL; 941 struct mbuf *m; 942 int frag, cur, cnt = 0; 943 944 /* 945 * Start packing the mbufs in this chain into 946 * the fragment pointers. Stop when we run out 947 * of fragments or hit the end of the mbuf chain. 948 */ 949 m = m_head; 950 cur = frag = *txidx; 951 952 for (m = m_head; m != NULL; m = m->m_next) { 953 if (m->m_len != 0) { 954 if ((PCN_TX_LIST_CNT - 955 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 956 return(ENOBUFS); 957 f = &sc->pcn_ldata->pcn_tx_list[frag]; 958 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 959 f->pcn_txctl |= PCN_TXCTL_MBO; 960 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 961 if (cnt == 0) 962 f->pcn_txctl |= PCN_TXCTL_STP; 963 else 964 f->pcn_txctl |= PCN_TXCTL_OWN; 965 cur = frag; 966 PCN_INC(frag, PCN_TX_LIST_CNT); 967 cnt++; 968 } 969 } 970 971 if (m != NULL) 972 return(ENOBUFS); 973 974 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 975 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 976 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 977 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 978 sc->pcn_cdata.pcn_tx_cnt += cnt; 979 *txidx = frag; 980 981 return(0); 982} 983 984/* 985 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 986 * to the mbuf data regions directly in the transmit lists. We also save a 987 * copy of the pointers since the transmit list fragment pointers are 988 * physical addresses. 989 */ 990static void pcn_start(ifp) 991 struct ifnet *ifp; 992{ 993 struct pcn_softc *sc; 994 struct mbuf *m_head = NULL; 995 u_int32_t idx; 996 997 sc = ifp->if_softc; 998 999 if (!sc->pcn_link) 1000 return; 1001 1002 idx = sc->pcn_cdata.pcn_tx_prod; 1003 1004 if (ifp->if_flags & IFF_OACTIVE) 1005 return; 1006 1007 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1008 IF_DEQUEUE(&ifp->if_snd, m_head); 1009 if (m_head == NULL) 1010 break; 1011 1012 if (pcn_encap(sc, m_head, &idx)) { 1013 IF_PREPEND(&ifp->if_snd, m_head); 1014 ifp->if_flags |= IFF_OACTIVE; 1015 break; 1016 } 1017 1018 /* 1019 * If there's a BPF listener, bounce a copy of this frame 1020 * to him. 1021 */ 1022 if (ifp->if_bpf) 1023 bpf_mtap(ifp, m_head); 1024 1025 } 1026 1027 /* Transmit */ 1028 sc->pcn_cdata.pcn_tx_prod = idx; 1029 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1030 1031 /* 1032 * Set a timeout in case the chip goes out to lunch. 1033 */ 1034 ifp->if_timer = 5; 1035 1036 return; 1037} 1038 1039static void pcn_init(xsc) 1040 void *xsc; 1041{ 1042 struct pcn_softc *sc = xsc; 1043 struct ifnet *ifp = &sc->arpcom.ac_if; 1044 struct mii_data *mii = NULL; 1045 int s; 1046 1047 s = splimp(); 1048 1049 /* 1050 * Cancel pending I/O and free all RX/TX buffers. 1051 */ 1052 pcn_stop(sc); 1053 pcn_reset(sc); 1054 1055 mii = device_get_softc(sc->pcn_miibus); 1056 1057 /* Set MAC address */ 1058 pcn_csr_write(sc, PCN_CSR_PAR0, 1059 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1060 pcn_csr_write(sc, PCN_CSR_PAR1, 1061 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1062 pcn_csr_write(sc, PCN_CSR_PAR2, 1063 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1064 1065 /* Init circular RX list. */ 1066 if (pcn_list_rx_init(sc) == ENOBUFS) { 1067 printf("pcn%d: initialization failed: no " 1068 "memory for rx buffers\n", sc->pcn_unit); 1069 pcn_stop(sc); 1070 (void)splx(s); 1071 return; 1072 } 1073 1074 /* 1075 * Init tx descriptors. 1076 */ 1077 pcn_list_tx_init(sc); 1078 1079 /* Set up the mode register. */ 1080 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1081 1082 /* If we want promiscuous mode, set the allframes bit. */ 1083 if (ifp->if_flags & IFF_PROMISC) { 1084 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1085 } else { 1086 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1087 } 1088 1089 /* Set the capture broadcast bit to capture broadcast frames. */ 1090 if (ifp->if_flags & IFF_BROADCAST) { 1091 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1092 } else { 1093 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1094 } 1095 1096 /* 1097 * Load the multicast filter. 1098 */ 1099 pcn_setmulti(sc); 1100 1101 /* 1102 * Load the addresses of the RX and TX lists. 1103 */ 1104 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1105 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1106 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1107 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1108 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1109 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1110 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1111 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1112 1113 /* Set the RX and TX ring sizes. */ 1114 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1115 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1116 1117 /* We're not using the initialization block. */ 1118 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1119 1120 /* Enable fast suspend mode. */ 1121 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1122 1123 /* 1124 * Enable burst read and write. Also set the no underflow 1125 * bit. This will avoid transmit underruns in certain 1126 * conditions while still providing decent performance. 1127 */ 1128 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1129 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1130 1131 /* Enable graceful recovery from underflow. */ 1132 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1133 1134 /* Enable auto-padding of short TX frames. */ 1135 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1136 1137 /* Disable MII autoneg (we handle this ourselves). */ 1138 PCN_BCR_CLRBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1139 1140 if (sc->pcn_type == Am79C978) 1141 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1142 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1143 1144 /* Enable interrupts and start the controller running. */ 1145 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1146 1147 mii_mediachg(mii); 1148 1149 ifp->if_flags |= IFF_RUNNING; 1150 ifp->if_flags &= ~IFF_OACTIVE; 1151 1152 (void)splx(s); 1153 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 1154 1155 return; 1156} 1157 1158/* 1159 * Set media options. 1160 */ 1161static int pcn_ifmedia_upd(ifp) 1162 struct ifnet *ifp; 1163{ 1164 struct pcn_softc *sc; 1165 struct mii_data *mii; 1166 1167 sc = ifp->if_softc; 1168 mii = device_get_softc(sc->pcn_miibus); 1169 1170 sc->pcn_link = 0; 1171 if (mii->mii_instance) { 1172 struct mii_softc *miisc; 1173 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1174 miisc = LIST_NEXT(miisc, mii_list)) 1175 mii_phy_reset(miisc); 1176 } 1177 mii_mediachg(mii); 1178 1179 return(0); 1180} 1181 1182/* 1183 * Report current media status. 1184 */ 1185static void pcn_ifmedia_sts(ifp, ifmr) 1186 struct ifnet *ifp; 1187 struct ifmediareq *ifmr; 1188{ 1189 struct pcn_softc *sc; 1190 struct mii_data *mii; 1191 1192 sc = ifp->if_softc; 1193 1194 mii = device_get_softc(sc->pcn_miibus); 1195 mii_pollstat(mii); 1196 ifmr->ifm_active = mii->mii_media_active; 1197 ifmr->ifm_status = mii->mii_media_status; 1198 1199 return; 1200} 1201 1202static int pcn_ioctl(ifp, command, data) 1203 struct ifnet *ifp; 1204 u_long command; 1205 caddr_t data; 1206{ 1207 struct pcn_softc *sc = ifp->if_softc; 1208 struct ifreq *ifr = (struct ifreq *) data; 1209 struct mii_data *mii = NULL; 1210 int s, error = 0; 1211 1212 s = splimp(); 1213 1214 switch(command) { 1215 case SIOCSIFADDR: 1216 case SIOCGIFADDR: 1217 case SIOCSIFMTU: 1218 error = ether_ioctl(ifp, command, data); 1219 break; 1220 case SIOCSIFFLAGS: 1221 if (ifp->if_flags & IFF_UP) { 1222 if (ifp->if_flags & IFF_RUNNING && 1223 ifp->if_flags & IFF_PROMISC && 1224 !(sc->pcn_if_flags & IFF_PROMISC)) { 1225 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1226 PCN_EXTCTL1_SPND); 1227 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, 1228 PCN_MODE_PROMISC); 1229 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1230 PCN_EXTCTL1_SPND); 1231 } else if (ifp->if_flags & IFF_RUNNING && 1232 !(ifp->if_flags & IFF_PROMISC) && 1233 sc->pcn_if_flags & IFF_PROMISC) { 1234 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1235 PCN_EXTCTL1_SPND); 1236 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, 1237 PCN_MODE_PROMISC); 1238 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1239 PCN_EXTCTL1_SPND); 1240 } else if (!(ifp->if_flags & IFF_RUNNING)) 1241 pcn_init(sc); 1242 } else { 1243 if (ifp->if_flags & IFF_RUNNING) 1244 pcn_stop(sc); 1245 } 1246 sc->pcn_if_flags = ifp->if_flags; 1247 error = 0; 1248 break; 1249 case SIOCADDMULTI: 1250 case SIOCDELMULTI: 1251 pcn_setmulti(sc); 1252 error = 0; 1253 break; 1254 case SIOCGIFMEDIA: 1255 case SIOCSIFMEDIA: 1256 mii = device_get_softc(sc->pcn_miibus); 1257 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1258 break; 1259 default: 1260 error = EINVAL; 1261 break; 1262 } 1263 1264 (void)splx(s); 1265 1266 return(error); 1267} 1268 1269static void pcn_watchdog(ifp) 1270 struct ifnet *ifp; 1271{ 1272 struct pcn_softc *sc; 1273 1274 sc = ifp->if_softc; 1275 1276 ifp->if_oerrors++; 1277 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1278 1279 pcn_stop(sc); 1280 pcn_reset(sc); 1281 pcn_init(sc); 1282 1283 if (ifp->if_snd.ifq_head != NULL) 1284 pcn_start(ifp); 1285 1286 return; 1287} 1288 1289/* 1290 * Stop the adapter and free any mbufs allocated to the 1291 * RX and TX lists. 1292 */ 1293static void pcn_stop(sc) 1294 struct pcn_softc *sc; 1295{ 1296 register int i; 1297 struct ifnet *ifp; 1298 1299 ifp = &sc->arpcom.ac_if; 1300 ifp->if_timer = 0; 1301 1302 untimeout(pcn_tick, sc, sc->pcn_stat_ch); 1303 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1304 sc->pcn_link = 0; 1305 1306 /* 1307 * Free data in the RX lists. 1308 */ 1309 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1310 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1311 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1312 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1313 } 1314 } 1315 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1316 sizeof(sc->pcn_ldata->pcn_rx_list)); 1317 1318 /* 1319 * Free the TX list buffers. 1320 */ 1321 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1322 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1323 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1324 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1325 } 1326 } 1327 1328 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1329 sizeof(sc->pcn_ldata->pcn_tx_list)); 1330 1331 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1332 1333 return; 1334} 1335 1336/* 1337 * Stop all chip I/O so that the kernel's probe routines don't 1338 * get confused by errant DMAs when rebooting. 1339 */ 1340static void pcn_shutdown(dev) 1341 device_t dev; 1342{ 1343 struct pcn_softc *sc; 1344 1345 sc = device_get_softc(dev); 1346 1347 pcn_reset(sc); 1348 pcn_stop(sc); 1349 1350 return; 1351} 1352