if_pcn.c revision 66592
1/* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/pci/if_pcn.c 66592 2000-10-03 18:11:36Z wpaul $ 34 */ 35 36/* 37 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 38 * from http://www.amd.com. 39 * 40 * Written by Bill Paul <wpaul@osd.bsdi.com> 41 */ 42 43/* 44 * The AMD PCnet/PCI controllers are more advanced and functional 45 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 46 * backwards compatibility with the LANCE and thus can be made 47 * to work with older LANCE drivers. This is in fact how the 48 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 49 * is that the PCnet/PCI devices offer several performance enhancements 50 * which can't be exploited in LANCE compatibility mode. Chief among 51 * these enhancements is the ability to perform PCI DMA operations 52 * using 32-bit addressing (which eliminates the need for ISA 53 * bounce-buffering), and special receive buffer alignment (which 54 * allows the receive handler to pass packets to the upper protocol 55 * layers without copying on both the x86 and alpha platforms). 56 */ 57 58#include <sys/param.h> 59#include <sys/systm.h> 60#include <sys/sockio.h> 61#include <sys/mbuf.h> 62#include <sys/malloc.h> 63#include <sys/kernel.h> 64#include <sys/socket.h> 65 66#include <net/if.h> 67#include <net/if_arp.h> 68#include <net/ethernet.h> 69#include <net/if_dl.h> 70#include <net/if_media.h> 71 72#include <net/bpf.h> 73 74#include <vm/vm.h> /* for vtophys */ 75#include <vm/pmap.h> /* for vtophys */ 76#include <machine/clock.h> /* for DELAY */ 77#include <machine/bus_pio.h> 78#include <machine/bus_memio.h> 79#include <machine/bus.h> 80#include <machine/resource.h> 81#include <sys/bus.h> 82#include <sys/rman.h> 83 84#include <dev/mii/mii.h> 85#include <dev/mii/miivar.h> 86 87#include <pci/pcireg.h> 88#include <pci/pcivar.h> 89 90#define PCN_USEIOSPACE 91 92#include <pci/if_pcnreg.h> 93 94MODULE_DEPEND(pcn, miibus, 1, 1, 1); 95 96/* "controller miibus0" required. See GENERIC if you get errors here. */ 97#include "miibus_if.h" 98 99#ifndef lint 100static const char rcsid[] = 101 "$FreeBSD: head/sys/pci/if_pcn.c 66592 2000-10-03 18:11:36Z wpaul $"; 102#endif 103 104/* 105 * Various supported device vendors/types and their names. 106 */ 107static struct pcn_type pcn_devs[] = { 108 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 109 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 110 { 0, 0, NULL } 111}; 112 113static u_int32_t pcn_csr_read __P((struct pcn_softc *, int)); 114static void pcn_csr_write __P((struct pcn_softc *, int, int)); 115static u_int32_t pcn_bcr_read __P((struct pcn_softc *, int)); 116static void pcn_bcr_write __P((struct pcn_softc *, int, int)); 117 118static int pcn_probe __P((device_t)); 119static int pcn_attach __P((device_t)); 120static int pcn_detach __P((device_t)); 121 122static int pcn_newbuf __P((struct pcn_softc *, int, struct mbuf *)); 123static int pcn_encap __P((struct pcn_softc *, 124 struct mbuf *, u_int32_t *)); 125static void pcn_rxeof __P((struct pcn_softc *)); 126static void pcn_txeof __P((struct pcn_softc *)); 127static void pcn_intr __P((void *)); 128static void pcn_tick __P((void *)); 129static void pcn_start __P((struct ifnet *)); 130static int pcn_ioctl __P((struct ifnet *, u_long, caddr_t)); 131static void pcn_init __P((void *)); 132static void pcn_stop __P((struct pcn_softc *)); 133static void pcn_watchdog __P((struct ifnet *)); 134static void pcn_shutdown __P((device_t)); 135static int pcn_ifmedia_upd __P((struct ifnet *)); 136static void pcn_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 137 138static int pcn_miibus_readreg __P((device_t, int, int)); 139static int pcn_miibus_writereg __P((device_t, int, int, int)); 140static void pcn_miibus_statchg __P((device_t)); 141 142static void pcn_setmulti __P((struct pcn_softc *)); 143static u_int32_t pcn_crc __P((caddr_t)); 144static void pcn_reset __P((struct pcn_softc *)); 145static int pcn_list_rx_init __P((struct pcn_softc *)); 146static int pcn_list_tx_init __P((struct pcn_softc *)); 147 148#ifdef PCN_USEIOSPACE 149#define PCN_RES SYS_RES_IOPORT 150#define PCN_RID PCN_PCI_LOIO 151#else 152#define PCN_RES SYS_RES_MEMORY 153#define PCN_RID PCN_PCI_LOMEM 154#endif 155 156static device_method_t pcn_methods[] = { 157 /* Device interface */ 158 DEVMETHOD(device_probe, pcn_probe), 159 DEVMETHOD(device_attach, pcn_attach), 160 DEVMETHOD(device_detach, pcn_detach), 161 DEVMETHOD(device_shutdown, pcn_shutdown), 162 163 /* bus interface */ 164 DEVMETHOD(bus_print_child, bus_generic_print_child), 165 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 166 167 /* MII interface */ 168 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 169 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 170 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 171 172 { 0, 0 } 173}; 174 175static driver_t pcn_driver = { 176 "pcn", 177 pcn_methods, 178 sizeof(struct pcn_softc) 179}; 180 181static devclass_t pcn_devclass; 182 183DRIVER_MODULE(if_pcn, pci, pcn_driver, pcn_devclass, 0, 0); 184DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 185 186#define PCN_CSR_SETBIT(sc, reg, x) \ 187 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 188 189#define PCN_CSR_CLRBIT(sc, reg, x) \ 190 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 191 192#define PCN_BCR_SETBIT(sc, reg, x) \ 193 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 194 195#define PCN_BCR_CLRBIT(sc, reg, x) \ 196 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 197 198static u_int32_t pcn_csr_read(sc, reg) 199 struct pcn_softc *sc; 200 int reg; 201{ 202 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 203 return(CSR_READ_4(sc, PCN_IO32_RDP)); 204} 205 206static void pcn_csr_write(sc, reg, val) 207 struct pcn_softc *sc; 208 int reg; 209{ 210 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 211 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 212 return; 213} 214 215static u_int32_t pcn_bcr_read(sc, reg) 216 struct pcn_softc *sc; 217 int reg; 218{ 219 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 220 return(CSR_READ_4(sc, PCN_IO32_BDP)); 221} 222 223static void pcn_bcr_write(sc, reg, val) 224 struct pcn_softc *sc; 225 int reg; 226{ 227 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 228 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 229 return; 230} 231 232static int pcn_miibus_readreg(dev, phy, reg) 233 device_t dev; 234 int phy, reg; 235{ 236 struct pcn_softc *sc; 237 int val; 238 239 sc = device_get_softc(dev); 240 241 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 242 return(0); 243 244 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 245 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 246 if (val == 0xFFFF) 247 return(0); 248 249 sc->pcn_phyaddr = phy; 250 251 return(val); 252} 253 254static int pcn_miibus_writereg(dev, phy, reg, data) 255 device_t dev; 256 int phy, reg, data; 257{ 258 struct pcn_softc *sc; 259 260 sc = device_get_softc(dev); 261 262 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 263 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 264 265 return(0); 266} 267 268static void pcn_miibus_statchg(dev) 269 device_t dev; 270{ 271 struct pcn_softc *sc; 272 struct mii_data *mii; 273 274 sc = device_get_softc(dev); 275 mii = device_get_softc(sc->pcn_miibus); 276 277 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 278 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 279 } else { 280 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 281 } 282 283 return; 284} 285 286#define DC_POLY 0xEDB88320 287 288static u_int32_t pcn_crc(addr) 289 caddr_t addr; 290{ 291 u_int32_t idx, bit, data, crc; 292 293 /* Compute CRC for the address value. */ 294 crc = 0xFFFFFFFF; /* initial value */ 295 296 for (idx = 0; idx < 6; idx++) { 297 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 298 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 299 } 300 301 return ((crc >> 26) & 0x3F); 302} 303 304static void pcn_setmulti(sc) 305 struct pcn_softc *sc; 306{ 307 struct ifnet *ifp; 308 struct ifmultiaddr *ifma; 309 u_int32_t h, i; 310 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 311 312 ifp = &sc->arpcom.ac_if; 313 314 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 315 316 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 317 for (i = 0; i < 4; i++) 318 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 319 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 320 return; 321 } 322 323 /* first, zot all the existing hash bits */ 324 for (i = 0; i < 4; i++) 325 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 326 327 /* now program new ones */ 328 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 329 ifma = ifma->ifma_link.le_next) { 330 if (ifma->ifma_addr->sa_family != AF_LINK) 331 continue; 332 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 333 hashes[h >> 4] |= 1 << (h & 0xF); 334 } 335 336 for (i = 0; i < 4; i++) 337 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 338 339 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 340 341 return; 342} 343 344static void pcn_reset(sc) 345 struct pcn_softc *sc; 346{ 347 /* 348 * Issue a reset by reading from the RESET register. 349 * Note that we don't know if the chip is operating in 350 * 16-bit or 32-bit mode at this point, so we attempt 351 * to reset the chip both ways. If one fails, the other 352 * will succeed. 353 */ 354 CSR_READ_2(sc, PCN_IO16_RESET); 355 CSR_READ_4(sc, PCN_IO32_RESET); 356 357 /* Wait a little while for the chip to get its brains in order. */ 358 DELAY(1000); 359 360 /* Select 32-bit (DWIO) mode */ 361 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 362 363 /* Select software style 3. */ 364 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 365 366 return; 367} 368 369/* 370 * Probe for an AMD chip. Check the PCI vendor and device 371 * IDs against our list and return a device name if we find a match. 372 */ 373static int pcn_probe(dev) 374 device_t dev; 375{ 376 struct pcn_type *t; 377 struct pcn_softc *sc; 378 int rid; 379 u_int32_t chip_id; 380 381 t = pcn_devs; 382 sc = device_get_softc(dev); 383 384 while(t->pcn_name != NULL) { 385 if ((pci_get_vendor(dev) == t->pcn_vid) && 386 (pci_get_device(dev) == t->pcn_did)) { 387 /* 388 * Temporarily map the I/O space 389 * so we can read the chip ID register. 390 */ 391 rid = PCN_RID; 392 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 393 0, ~0, 1, RF_ACTIVE); 394 if (sc->pcn_res == NULL) { 395 device_printf(dev, 396 "couldn't map ports/memory\n"); 397 return(ENXIO); 398 } 399 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 400 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 401 pcn_reset(sc); 402 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 403 chip_id <<= 16; 404 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 405 bus_release_resource(dev, PCN_RES, 406 PCN_RID, sc->pcn_res); 407 chip_id >>= 12; 408 sc->pcn_type = chip_id & PART_MASK; 409 switch(sc->pcn_type) { 410 case Am79C971: 411 case Am79C972: 412 case Am79C973: 413 case Am79C976: 414 case Am79C978: 415 break; 416 default: 417 return(ENXIO); 418 break; 419 } 420 device_set_desc(dev, t->pcn_name); 421 return(0); 422 } 423 t++; 424 } 425 426 return(ENXIO); 427} 428 429/* 430 * Attach the interface. Allocate softc structures, do ifmedia 431 * setup and ethernet/BPF attach. 432 */ 433static int pcn_attach(dev) 434 device_t dev; 435{ 436 int s; 437 u_int32_t eaddr[2]; 438 u_int32_t command; 439 struct pcn_softc *sc; 440 struct ifnet *ifp; 441 int unit, error = 0, rid; 442 443 s = splimp(); 444 445 sc = device_get_softc(dev); 446 unit = device_get_unit(dev); 447 448 /* 449 * Handle power management nonsense. 450 */ 451 452 command = pci_read_config(dev, PCN_PCI_CAPID, 4) & 0x000000FF; 453 if (command == 0x01) { 454 455 command = pci_read_config(dev, PCN_PCI_PWRMGMTCTRL, 4); 456 if (command & PCN_PSTATE_MASK) { 457 u_int32_t iobase, membase, irq; 458 459 /* Save important PCI config data. */ 460 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 461 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 462 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 463 464 /* Reset the power state. */ 465 printf("pcn%d: chip is in D%d power mode " 466 "-- setting to D0\n", unit, command & PCN_PSTATE_MASK); 467 command &= 0xFFFFFFFC; 468 pci_write_config(dev, PCN_PCI_PWRMGMTCTRL, command, 4); 469 470 /* Restore PCI config data. */ 471 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 472 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 473 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 474 } 475 } 476 477 /* 478 * Map control/status registers. 479 */ 480 command = pci_read_config(dev, PCIR_COMMAND, 4); 481 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 482 pci_write_config(dev, PCIR_COMMAND, command, 4); 483 command = pci_read_config(dev, PCIR_COMMAND, 4); 484 485#ifdef PCN_USEIOSPACE 486 if (!(command & PCIM_CMD_PORTEN)) { 487 printf("pcn%d: failed to enable I/O ports!\n", unit); 488 error = ENXIO;; 489 goto fail; 490 } 491#else 492 if (!(command & PCIM_CMD_MEMEN)) { 493 printf("pcn%d: failed to enable memory mapping!\n", unit); 494 error = ENXIO;; 495 goto fail; 496 } 497#endif 498 499 rid = PCN_RID; 500 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 501 0, ~0, 1, RF_ACTIVE); 502 503 if (sc->pcn_res == NULL) { 504 printf("pcn%d: couldn't map ports/memory\n", unit); 505 error = ENXIO; 506 goto fail; 507 } 508 509 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 510 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 511 512 /* Allocate interrupt */ 513 rid = 0; 514 sc->pcn_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 515 RF_SHAREABLE | RF_ACTIVE); 516 517 if (sc->pcn_irq == NULL) { 518 printf("pcn%d: couldn't map interrupt\n", unit); 519 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 520 error = ENXIO; 521 goto fail; 522 } 523 524 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 525 pcn_intr, sc, &sc->pcn_intrhand); 526 527 if (error) { 528 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_res); 529 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 530 printf("pcn%d: couldn't set up irq\n", unit); 531 goto fail; 532 } 533 534 /* Reset the adapter. */ 535 pcn_reset(sc); 536 537 /* 538 * Get station address from the EEPROM. 539 */ 540 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 541 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 542 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 543 544 /* 545 * An AMD chip was detected. Inform the world. 546 */ 547 printf("pcn%d: Ethernet address: %6D\n", unit, 548 sc->arpcom.ac_enaddr, ":"); 549 550 sc->pcn_unit = unit; 551 callout_handle_init(&sc->pcn_stat_ch); 552 553 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 554 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 555 556 if (sc->pcn_ldata == NULL) { 557 printf("pcn%d: no memory for list buffers!\n", unit); 558 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 559 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 560 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 561 error = ENXIO; 562 goto fail; 563 } 564 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 565 566 ifp = &sc->arpcom.ac_if; 567 ifp->if_softc = sc; 568 ifp->if_unit = unit; 569 ifp->if_name = "pcn"; 570 ifp->if_mtu = ETHERMTU; 571 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 572 ifp->if_ioctl = pcn_ioctl; 573 ifp->if_output = ether_output; 574 ifp->if_start = pcn_start; 575 ifp->if_watchdog = pcn_watchdog; 576 ifp->if_init = pcn_init; 577 ifp->if_baudrate = 10000000; 578 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 579 580 /* 581 * Do MII setup. 582 */ 583 if (mii_phy_probe(dev, &sc->pcn_miibus, 584 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 585 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 586 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 587 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 588 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 589 error = ENXIO; 590 goto fail; 591 } 592 593 /* 594 * Call MI attach routine. 595 */ 596 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 597 callout_handle_init(&sc->pcn_stat_ch); 598 599fail: 600 splx(s); 601 return(error); 602} 603 604static int pcn_detach(dev) 605 device_t dev; 606{ 607 struct pcn_softc *sc; 608 struct ifnet *ifp; 609 int s; 610 611 s = splimp(); 612 613 sc = device_get_softc(dev); 614 ifp = &sc->arpcom.ac_if; 615 616 pcn_reset(sc); 617 pcn_stop(sc); 618 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 619 620 if (sc->pcn_miibus != NULL) { 621 bus_generic_detach(dev); 622 device_delete_child(dev, sc->pcn_miibus); 623 } 624 625 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 626 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 627 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 628 629 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), M_DEVBUF); 630 631 splx(s); 632 633 return(0); 634} 635 636/* 637 * Initialize the transmit descriptors. 638 */ 639static int pcn_list_tx_init(sc) 640 struct pcn_softc *sc; 641{ 642 struct pcn_list_data *ld; 643 struct pcn_ring_data *cd; 644 int i; 645 646 cd = &sc->pcn_cdata; 647 ld = sc->pcn_ldata; 648 649 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 650 cd->pcn_tx_chain[i] = NULL; 651 ld->pcn_tx_list[i].pcn_tbaddr = 0; 652 ld->pcn_tx_list[i].pcn_txctl = 0; 653 ld->pcn_tx_list[i].pcn_txstat = 0; 654 } 655 656 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 657 658 return(0); 659} 660 661 662/* 663 * Initialize the RX descriptors and allocate mbufs for them. 664 */ 665static int pcn_list_rx_init(sc) 666 struct pcn_softc *sc; 667{ 668 struct pcn_list_data *ld; 669 struct pcn_ring_data *cd; 670 int i; 671 672 ld = sc->pcn_ldata; 673 cd = &sc->pcn_cdata; 674 675 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 676 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 677 return(ENOBUFS); 678 } 679 680 cd->pcn_rx_prod = 0; 681 682 return(0); 683} 684 685/* 686 * Initialize an RX descriptor and attach an MBUF cluster. 687 */ 688static int pcn_newbuf(sc, idx, m) 689 struct pcn_softc *sc; 690 int idx; 691 struct mbuf *m; 692{ 693 struct mbuf *m_new = NULL; 694 struct pcn_rx_desc *c; 695 696 c = &sc->pcn_ldata->pcn_rx_list[idx]; 697 698 if (m == NULL) { 699 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 700 if (m_new == NULL) { 701 printf("pcn%d: no memory for rx list " 702 "-- packet dropped!\n", sc->pcn_unit); 703 return(ENOBUFS); 704 } 705 706 MCLGET(m_new, M_DONTWAIT); 707 if (!(m_new->m_flags & M_EXT)) { 708 printf("pcn%d: no memory for rx list " 709 "-- packet dropped!\n", sc->pcn_unit); 710 m_freem(m_new); 711 return(ENOBUFS); 712 } 713 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 714 } else { 715 m_new = m; 716 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 717 m_new->m_data = m_new->m_ext.ext_buf; 718 } 719 720 m_adj(m_new, ETHER_ALIGN); 721 722 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 723 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 724 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 725 c->pcn_bufsz |= PCN_RXLEN_MBO; 726 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 727 728 return(0); 729} 730 731/* 732 * A frame has been uploaded: pass the resulting mbuf chain up to 733 * the higher level protocols. 734 */ 735static void pcn_rxeof(sc) 736 struct pcn_softc *sc; 737{ 738 struct ether_header *eh; 739 struct mbuf *m; 740 struct ifnet *ifp; 741 struct pcn_rx_desc *cur_rx; 742 int i; 743 744 ifp = &sc->arpcom.ac_if; 745 i = sc->pcn_cdata.pcn_rx_prod; 746 747 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 748 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 749 m = sc->pcn_cdata.pcn_rx_chain[i]; 750 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 751 752 /* 753 * If an error occurs, update stats, clear the 754 * status word and leave the mbuf cluster in place: 755 * it should simply get re-used next time this descriptor 756 * comes up in the ring. 757 */ 758 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 759 ifp->if_ierrors++; 760 pcn_newbuf(sc, i, m); 761 PCN_INC(i, PCN_RX_LIST_CNT); 762 continue; 763 } 764 765 if (pcn_newbuf(sc, i, NULL)) { 766 /* Ran out of mbufs; recycle this one. */ 767 pcn_newbuf(sc, i, m); 768 ifp->if_ierrors++; 769 PCN_INC(i, PCN_RX_LIST_CNT); 770 continue; 771 } 772 773 PCN_INC(i, PCN_RX_LIST_CNT); 774 775 /* No errors; receive the packet. */ 776 ifp->if_ipackets++; 777 eh = mtod(m, struct ether_header *); 778 m->m_len = m->m_pkthdr.len = 779 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 780 m->m_pkthdr.rcvif = ifp; 781 782 /* Remove header from mbuf and pass it on. */ 783 m_adj(m, sizeof(struct ether_header)); 784 ether_input(ifp, eh, m); 785 } 786 787 sc->pcn_cdata.pcn_rx_prod = i; 788 789 return; 790} 791 792/* 793 * A frame was downloaded to the chip. It's safe for us to clean up 794 * the list buffers. 795 */ 796 797static void pcn_txeof(sc) 798 struct pcn_softc *sc; 799{ 800 struct pcn_tx_desc *cur_tx = NULL; 801 struct ifnet *ifp; 802 u_int32_t idx; 803 804 ifp = &sc->arpcom.ac_if; 805 806 /* Clear the timeout timer. */ 807 ifp->if_timer = 0; 808 809 /* 810 * Go through our tx list and free mbufs for those 811 * frames that have been transmitted. 812 */ 813 idx = sc->pcn_cdata.pcn_tx_cons; 814 while (idx != sc->pcn_cdata.pcn_tx_prod) { 815 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 816 817 if (!PCN_OWN_TXDESC(cur_tx)) 818 break; 819 820 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 821 sc->pcn_cdata.pcn_tx_cnt--; 822 PCN_INC(idx, PCN_TX_LIST_CNT); 823 continue; 824 } 825 826 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 827 ifp->if_oerrors++; 828 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 829 ifp->if_collisions++; 830 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 831 ifp->if_collisions++; 832 } 833 834 ifp->if_collisions += 835 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 836 837 ifp->if_opackets++; 838 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 839 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 840 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 841 } 842 843 sc->pcn_cdata.pcn_tx_cnt--; 844 PCN_INC(idx, PCN_TX_LIST_CNT); 845 ifp->if_timer = 0; 846 } 847 848 sc->pcn_cdata.pcn_tx_cons = idx; 849 850 if (cur_tx != NULL) 851 ifp->if_flags &= ~IFF_OACTIVE; 852 853 return; 854} 855 856static void pcn_tick(xsc) 857 void *xsc; 858{ 859 struct pcn_softc *sc; 860 struct mii_data *mii; 861 struct ifnet *ifp; 862 int s; 863 864 s = splimp(); 865 866 sc = xsc; 867 ifp = &sc->arpcom.ac_if; 868 869 mii = device_get_softc(sc->pcn_miibus); 870 mii_tick(mii); 871 872 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 873 sc->pcn_link = 0; 874 875 if (!sc->pcn_link) { 876 mii_pollstat(mii); 877 if (mii->mii_media_status & IFM_ACTIVE && 878 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 879 sc->pcn_link++; 880 if (ifp->if_snd.ifq_head != NULL) 881 pcn_start(ifp); 882 } 883 884 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 885 886 splx(s); 887 888 return; 889} 890 891static void pcn_intr(arg) 892 void *arg; 893{ 894 struct pcn_softc *sc; 895 struct ifnet *ifp; 896 u_int32_t status; 897 898 sc = arg; 899 ifp = &sc->arpcom.ac_if; 900 901 /* Supress unwanted interrupts */ 902 if (!(ifp->if_flags & IFF_UP)) { 903 pcn_stop(sc); 904 return; 905 } 906 907 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 908 909 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 910 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 911 912 if (status & PCN_CSR_RINT) 913 pcn_rxeof(sc); 914 915 if (status & PCN_CSR_TINT) 916 pcn_txeof(sc); 917 918 if (status & PCN_CSR_ERR) { 919 pcn_init(sc); 920 break; 921 } 922 } 923 924 if (ifp->if_snd.ifq_head != NULL) 925 pcn_start(ifp); 926 927 return; 928} 929 930/* 931 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 932 * pointers to the fragment pointers. 933 */ 934static int pcn_encap(sc, m_head, txidx) 935 struct pcn_softc *sc; 936 struct mbuf *m_head; 937 u_int32_t *txidx; 938{ 939 struct pcn_tx_desc *f = NULL; 940 struct mbuf *m; 941 int frag, cur, cnt = 0; 942 943 /* 944 * Start packing the mbufs in this chain into 945 * the fragment pointers. Stop when we run out 946 * of fragments or hit the end of the mbuf chain. 947 */ 948 m = m_head; 949 cur = frag = *txidx; 950 951 for (m = m_head; m != NULL; m = m->m_next) { 952 if (m->m_len != 0) { 953 if ((PCN_TX_LIST_CNT - 954 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 955 return(ENOBUFS); 956 f = &sc->pcn_ldata->pcn_tx_list[frag]; 957 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 958 f->pcn_txctl |= PCN_TXCTL_MBO; 959 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 960 if (cnt == 0) 961 f->pcn_txctl |= PCN_TXCTL_STP; 962 else 963 f->pcn_txctl |= PCN_TXCTL_OWN; 964 cur = frag; 965 PCN_INC(frag, PCN_TX_LIST_CNT); 966 cnt++; 967 } 968 } 969 970 if (m != NULL) 971 return(ENOBUFS); 972 973 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 974 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 975 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 976 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 977 sc->pcn_cdata.pcn_tx_cnt += cnt; 978 *txidx = frag; 979 980 return(0); 981} 982 983/* 984 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 985 * to the mbuf data regions directly in the transmit lists. We also save a 986 * copy of the pointers since the transmit list fragment pointers are 987 * physical addresses. 988 */ 989static void pcn_start(ifp) 990 struct ifnet *ifp; 991{ 992 struct pcn_softc *sc; 993 struct mbuf *m_head = NULL; 994 u_int32_t idx; 995 996 sc = ifp->if_softc; 997 998 if (!sc->pcn_link) 999 return; 1000 1001 idx = sc->pcn_cdata.pcn_tx_prod; 1002 1003 if (ifp->if_flags & IFF_OACTIVE) 1004 return; 1005 1006 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1007 IF_DEQUEUE(&ifp->if_snd, m_head); 1008 if (m_head == NULL) 1009 break; 1010 1011 if (pcn_encap(sc, m_head, &idx)) { 1012 IF_PREPEND(&ifp->if_snd, m_head); 1013 ifp->if_flags |= IFF_OACTIVE; 1014 break; 1015 } 1016 1017 /* 1018 * If there's a BPF listener, bounce a copy of this frame 1019 * to him. 1020 */ 1021 if (ifp->if_bpf) 1022 bpf_mtap(ifp, m_head); 1023 1024 } 1025 1026 /* Transmit */ 1027 sc->pcn_cdata.pcn_tx_prod = idx; 1028 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1029 1030 /* 1031 * Set a timeout in case the chip goes out to lunch. 1032 */ 1033 ifp->if_timer = 5; 1034 1035 return; 1036} 1037 1038static void pcn_init(xsc) 1039 void *xsc; 1040{ 1041 struct pcn_softc *sc = xsc; 1042 struct ifnet *ifp = &sc->arpcom.ac_if; 1043 struct mii_data *mii = NULL; 1044 int s; 1045 1046 s = splimp(); 1047 1048 /* 1049 * Cancel pending I/O and free all RX/TX buffers. 1050 */ 1051 pcn_stop(sc); 1052 pcn_reset(sc); 1053 1054 mii = device_get_softc(sc->pcn_miibus); 1055 1056 /* Set MAC address */ 1057 pcn_csr_write(sc, PCN_CSR_PAR0, 1058 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1059 pcn_csr_write(sc, PCN_CSR_PAR1, 1060 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1061 pcn_csr_write(sc, PCN_CSR_PAR2, 1062 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1063 1064 /* Init circular RX list. */ 1065 if (pcn_list_rx_init(sc) == ENOBUFS) { 1066 printf("pcn%d: initialization failed: no " 1067 "memory for rx buffers\n", sc->pcn_unit); 1068 pcn_stop(sc); 1069 (void)splx(s); 1070 return; 1071 } 1072 1073 /* 1074 * Init tx descriptors. 1075 */ 1076 pcn_list_tx_init(sc); 1077 1078 /* Set up the mode register. */ 1079 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1080 1081 /* If we want promiscuous mode, set the allframes bit. */ 1082 if (ifp->if_flags & IFF_PROMISC) { 1083 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1084 } else { 1085 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1086 } 1087 1088 /* Set the capture broadcast bit to capture broadcast frames. */ 1089 if (ifp->if_flags & IFF_BROADCAST) { 1090 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1091 } else { 1092 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1093 } 1094 1095 /* 1096 * Load the multicast filter. 1097 */ 1098 pcn_setmulti(sc); 1099 1100 /* 1101 * Load the addresses of the RX and TX lists. 1102 */ 1103 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1104 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1105 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1106 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1107 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1108 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1109 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1110 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1111 1112 /* Set the RX and TX ring sizes. */ 1113 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1114 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1115 1116 /* We're not using the initialization block. */ 1117 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1118 1119 /* Enable fast suspend mode. */ 1120 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1121 1122 /* 1123 * Enable burst read and write. Also set the no underflow 1124 * bit. This will avoid transmit underruns in certain 1125 * conditions while still providing decent performance. 1126 */ 1127 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1128 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1129 1130 /* Enable graceful recovery from underflow. */ 1131 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1132 1133 /* Enable auto-padding of short TX frames. */ 1134 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1135 1136 /* Disable MII autoneg (we handle this ourselves). */ 1137 PCN_BCR_CLRBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1138 1139 if (sc->pcn_type == Am79C978) 1140 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1141 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1142 1143 /* Enable interrupts and start the controller running. */ 1144 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1145 1146 mii_mediachg(mii); 1147 1148 ifp->if_flags |= IFF_RUNNING; 1149 ifp->if_flags &= ~IFF_OACTIVE; 1150 1151 (void)splx(s); 1152 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 1153 1154 return; 1155} 1156 1157/* 1158 * Set media options. 1159 */ 1160static int pcn_ifmedia_upd(ifp) 1161 struct ifnet *ifp; 1162{ 1163 struct pcn_softc *sc; 1164 struct mii_data *mii; 1165 1166 sc = ifp->if_softc; 1167 mii = device_get_softc(sc->pcn_miibus); 1168 1169 sc->pcn_link = 0; 1170 if (mii->mii_instance) { 1171 struct mii_softc *miisc; 1172 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1173 miisc = LIST_NEXT(miisc, mii_list)) 1174 mii_phy_reset(miisc); 1175 } 1176 mii_mediachg(mii); 1177 1178 return(0); 1179} 1180 1181/* 1182 * Report current media status. 1183 */ 1184static void pcn_ifmedia_sts(ifp, ifmr) 1185 struct ifnet *ifp; 1186 struct ifmediareq *ifmr; 1187{ 1188 struct pcn_softc *sc; 1189 struct mii_data *mii; 1190 1191 sc = ifp->if_softc; 1192 1193 mii = device_get_softc(sc->pcn_miibus); 1194 mii_pollstat(mii); 1195 ifmr->ifm_active = mii->mii_media_active; 1196 ifmr->ifm_status = mii->mii_media_status; 1197 1198 return; 1199} 1200 1201static int pcn_ioctl(ifp, command, data) 1202 struct ifnet *ifp; 1203 u_long command; 1204 caddr_t data; 1205{ 1206 struct pcn_softc *sc = ifp->if_softc; 1207 struct ifreq *ifr = (struct ifreq *) data; 1208 struct mii_data *mii = NULL; 1209 int s, error = 0; 1210 1211 s = splimp(); 1212 1213 switch(command) { 1214 case SIOCSIFADDR: 1215 case SIOCGIFADDR: 1216 case SIOCSIFMTU: 1217 error = ether_ioctl(ifp, command, data); 1218 break; 1219 case SIOCSIFFLAGS: 1220 if (ifp->if_flags & IFF_UP) { 1221 if (ifp->if_flags & IFF_RUNNING && 1222 ifp->if_flags & IFF_PROMISC && 1223 !(sc->pcn_if_flags & IFF_PROMISC)) { 1224 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1225 PCN_EXTCTL1_SPND); 1226 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, 1227 PCN_MODE_PROMISC); 1228 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1229 PCN_EXTCTL1_SPND); 1230 } else if (ifp->if_flags & IFF_RUNNING && 1231 !(ifp->if_flags & IFF_PROMISC) && 1232 sc->pcn_if_flags & IFF_PROMISC) { 1233 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1234 PCN_EXTCTL1_SPND); 1235 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, 1236 PCN_MODE_PROMISC); 1237 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1238 PCN_EXTCTL1_SPND); 1239 } else if (!(ifp->if_flags & IFF_RUNNING)) 1240 pcn_init(sc); 1241 } else { 1242 if (ifp->if_flags & IFF_RUNNING) 1243 pcn_stop(sc); 1244 } 1245 sc->pcn_if_flags = ifp->if_flags; 1246 error = 0; 1247 break; 1248 case SIOCADDMULTI: 1249 case SIOCDELMULTI: 1250 pcn_setmulti(sc); 1251 error = 0; 1252 break; 1253 case SIOCGIFMEDIA: 1254 case SIOCSIFMEDIA: 1255 mii = device_get_softc(sc->pcn_miibus); 1256 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1257 break; 1258 default: 1259 error = EINVAL; 1260 break; 1261 } 1262 1263 (void)splx(s); 1264 1265 return(error); 1266} 1267 1268static void pcn_watchdog(ifp) 1269 struct ifnet *ifp; 1270{ 1271 struct pcn_softc *sc; 1272 1273 sc = ifp->if_softc; 1274 1275 ifp->if_oerrors++; 1276 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1277 1278 pcn_stop(sc); 1279 pcn_reset(sc); 1280 pcn_init(sc); 1281 1282 if (ifp->if_snd.ifq_head != NULL) 1283 pcn_start(ifp); 1284 1285 return; 1286} 1287 1288/* 1289 * Stop the adapter and free any mbufs allocated to the 1290 * RX and TX lists. 1291 */ 1292static void pcn_stop(sc) 1293 struct pcn_softc *sc; 1294{ 1295 register int i; 1296 struct ifnet *ifp; 1297 1298 ifp = &sc->arpcom.ac_if; 1299 ifp->if_timer = 0; 1300 1301 untimeout(pcn_tick, sc, sc->pcn_stat_ch); 1302 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1303 sc->pcn_link = 0; 1304 1305 /* 1306 * Free data in the RX lists. 1307 */ 1308 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1309 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1310 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1311 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1312 } 1313 } 1314 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1315 sizeof(sc->pcn_ldata->pcn_rx_list)); 1316 1317 /* 1318 * Free the TX list buffers. 1319 */ 1320 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1321 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1322 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1323 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1324 } 1325 } 1326 1327 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1328 sizeof(sc->pcn_ldata->pcn_tx_list)); 1329 1330 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1331 1332 return; 1333} 1334 1335/* 1336 * Stop all chip I/O so that the kernel's probe routines don't 1337 * get confused by errant DMAs when rebooting. 1338 */ 1339static void pcn_shutdown(dev) 1340 device_t dev; 1341{ 1342 struct pcn_softc *sc; 1343 1344 sc = device_get_softc(dev); 1345 1346 pcn_reset(sc); 1347 pcn_stop(sc); 1348 1349 return; 1350} 1351