if_pcn.c revision 66210
1/* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/pci/if_pcn.c 66210 2000-09-22 04:03:10Z wpaul $ 34 */ 35 36/* 37 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 38 * from http://www.amd.com. 39 * 40 * Written by Bill Paul <wpaul@osd.bsdi.com> 41 */ 42 43/* 44 * The AMD PCnet/PCI controllers are more advanced and functional 45 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 46 * backwards compatibility with the LANCE and thus can be made 47 * to work with older LANCE drivers. This is in fact how the 48 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 49 * is that the PCnet/PCI devices offer several performance enhancements 50 * which can't be exploited in LANCE compatibility mode. Chief among 51 * these enhancements is the ability to perform PCI DMA operations 52 * using 32-bit addressing (which eliminates the need for ISA 53 * bounce-buffering), and special receive buffer alignment (which 54 * allows the receive handler to pass packets to the upper protocol 55 * layers without copying on both the x86 and alpha platforms). 56 */ 57 58#include <sys/param.h> 59#include <sys/systm.h> 60#include <sys/sockio.h> 61#include <sys/mbuf.h> 62#include <sys/malloc.h> 63#include <sys/kernel.h> 64#include <sys/socket.h> 65 66#include <net/if.h> 67#include <net/if_arp.h> 68#include <net/ethernet.h> 69#include <net/if_dl.h> 70#include <net/if_media.h> 71 72#include <net/bpf.h> 73 74#include <vm/vm.h> /* for vtophys */ 75#include <vm/pmap.h> /* for vtophys */ 76#include <machine/clock.h> /* for DELAY */ 77#include <machine/bus_pio.h> 78#include <machine/bus_memio.h> 79#include <machine/bus.h> 80#include <machine/resource.h> 81#include <sys/bus.h> 82#include <sys/rman.h> 83 84#include <dev/mii/mii.h> 85#include <dev/mii/miivar.h> 86 87#include <pci/pcireg.h> 88#include <pci/pcivar.h> 89 90#define PCN_USEIOSPACE 91 92#include <pci/if_pcnreg.h> 93 94MODULE_DEPEND(pcn, miibus, 1, 1, 1); 95 96/* "controller miibus0" required. See GENERIC if you get errors here. */ 97#include "miibus_if.h" 98 99#ifndef lint 100static const char rcsid[] = 101 "$FreeBSD: head/sys/pci/if_pcn.c 66210 2000-09-22 04:03:10Z wpaul $"; 102#endif 103 104/* 105 * Various supported device vendors/types and their names. 106 */ 107static struct pcn_type pcn_devs[] = { 108 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 109 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 110 { 0, 0, NULL } 111}; 112 113static u_int32_t pcn_csr_read __P((struct pcn_softc *, int)); 114static void pcn_csr_write __P((struct pcn_softc *, int, int)); 115static u_int32_t pcn_bcr_read __P((struct pcn_softc *, int)); 116static void pcn_bcr_write __P((struct pcn_softc *, int, int)); 117 118static int pcn_probe __P((device_t)); 119static int pcn_attach __P((device_t)); 120static int pcn_detach __P((device_t)); 121 122static int pcn_newbuf __P((struct pcn_softc *, int, struct mbuf *)); 123static int pcn_encap __P((struct pcn_softc *, 124 struct mbuf *, u_int32_t *)); 125static void pcn_rxeof __P((struct pcn_softc *)); 126static void pcn_txeof __P((struct pcn_softc *)); 127static void pcn_intr __P((void *)); 128static void pcn_tick __P((void *)); 129static void pcn_start __P((struct ifnet *)); 130static int pcn_ioctl __P((struct ifnet *, u_long, caddr_t)); 131static void pcn_init __P((void *)); 132static void pcn_stop __P((struct pcn_softc *)); 133static void pcn_watchdog __P((struct ifnet *)); 134static void pcn_shutdown __P((device_t)); 135static int pcn_ifmedia_upd __P((struct ifnet *)); 136static void pcn_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 137 138static int pcn_miibus_readreg __P((device_t, int, int)); 139static int pcn_miibus_writereg __P((device_t, int, int, int)); 140static void pcn_miibus_statchg __P((device_t)); 141 142static void pcn_setmulti __P((struct pcn_softc *)); 143static u_int32_t pcn_crc __P((caddr_t)); 144static void pcn_reset __P((struct pcn_softc *)); 145static int pcn_list_rx_init __P((struct pcn_softc *)); 146static int pcn_list_tx_init __P((struct pcn_softc *)); 147 148#ifdef PCN_USEIOSPACE 149#define PCN_RES SYS_RES_IOPORT 150#define PCN_RID PCN_PCI_LOIO 151#else 152#define PCN_RES SYS_RES_MEMORY 153#define PCN_RID PCN_PCI_LOMEM 154#endif 155 156static device_method_t pcn_methods[] = { 157 /* Device interface */ 158 DEVMETHOD(device_probe, pcn_probe), 159 DEVMETHOD(device_attach, pcn_attach), 160 DEVMETHOD(device_detach, pcn_detach), 161 DEVMETHOD(device_shutdown, pcn_shutdown), 162 163 /* bus interface */ 164 DEVMETHOD(bus_print_child, bus_generic_print_child), 165 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 166 167 /* MII interface */ 168 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 169 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 170 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 171 172 { 0, 0 } 173}; 174 175static driver_t pcn_driver = { 176 "pcn", 177 pcn_methods, 178 sizeof(struct pcn_softc) 179}; 180 181static devclass_t pcn_devclass; 182 183DRIVER_MODULE(if_pcn, pci, pcn_driver, pcn_devclass, 0, 0); 184DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 185 186#define PCN_CSR_SETBIT(sc, reg, x) \ 187 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 188 189#define PCN_CSR_CLRBIT(sc, reg, x) \ 190 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 191 192#define PCN_BCR_SETBIT(sc, reg, x) \ 193 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 194 195#define PCN_BCR_CLRBIT(sc, reg, x) \ 196 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 197 198static u_int32_t pcn_csr_read(sc, reg) 199 struct pcn_softc *sc; 200 int reg; 201{ 202 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 203 return(CSR_READ_4(sc, PCN_IO32_RDP)); 204} 205 206static void pcn_csr_write(sc, reg, val) 207 struct pcn_softc *sc; 208 int reg; 209{ 210 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 211 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 212 return; 213} 214 215static u_int32_t pcn_bcr_read(sc, reg) 216 struct pcn_softc *sc; 217 int reg; 218{ 219 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 220 return(CSR_READ_4(sc, PCN_IO32_BDP)); 221} 222 223static void pcn_bcr_write(sc, reg, val) 224 struct pcn_softc *sc; 225 int reg; 226{ 227 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 228 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 229 return; 230} 231 232static int pcn_miibus_readreg(dev, phy, reg) 233 device_t dev; 234 int phy, reg; 235{ 236 struct pcn_softc *sc; 237 int val; 238 239 sc = device_get_softc(dev); 240 241 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 242 return(0); 243 244 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 245 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 246 if (val == 0xFFFF) 247 return(0); 248 249 sc->pcn_phyaddr = phy; 250 251 return(val); 252} 253 254static int pcn_miibus_writereg(dev, phy, reg, data) 255 device_t dev; 256 int phy, reg, data; 257{ 258 struct pcn_softc *sc; 259 260 sc = device_get_softc(dev); 261 262 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 263 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 264 265 return(0); 266} 267 268static void pcn_miibus_statchg(dev) 269 device_t dev; 270{ 271 struct pcn_softc *sc; 272 struct mii_data *mii; 273 274 sc = device_get_softc(dev); 275 mii = device_get_softc(sc->pcn_miibus); 276 277 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 278 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 279 } else { 280 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 281 } 282 283 return; 284} 285 286#define DC_POLY 0xEDB88320 287 288static u_int32_t pcn_crc(addr) 289 caddr_t addr; 290{ 291 u_int32_t idx, bit, data, crc; 292 293 /* Compute CRC for the address value. */ 294 crc = 0xFFFFFFFF; /* initial value */ 295 296 for (idx = 0; idx < 6; idx++) { 297 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 298 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 299 } 300 301 return ((crc >> 26) & 0x3F); 302} 303 304static void pcn_setmulti(sc) 305 struct pcn_softc *sc; 306{ 307 struct ifnet *ifp; 308 struct ifmultiaddr *ifma; 309 u_int32_t h, i; 310 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 311 312 ifp = &sc->arpcom.ac_if; 313 314 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 315 316 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 317 for (i = 0; i < 4; i++) 318 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 319 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 320 return; 321 } 322 323 /* first, zot all the existing hash bits */ 324 for (i = 0; i < 4; i++) 325 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 326 327 /* now program new ones */ 328 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 329 ifma = ifma->ifma_link.le_next) { 330 if (ifma->ifma_addr->sa_family != AF_LINK) 331 continue; 332 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 333 hashes[h >> 4] |= 1 << (h & 0xF); 334 } 335 336 for (i = 0; i < 4; i++) 337 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 338 339 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 340 341 return; 342} 343 344static void pcn_reset(sc) 345 struct pcn_softc *sc; 346{ 347 /* 348 * Issue a reset by reading from the RESET register. 349 * Note that we don't know if the chip is operating in 350 * 16-bit or 32-bit mode at this point, so we attempt 351 * to reset the chip both ways. If one fails, the other 352 * will succeed. 353 */ 354 CSR_READ_2(sc, PCN_IO16_RESET); 355 CSR_READ_4(sc, PCN_IO32_RESET); 356 357 /* Wait a little while for the chip to get its brains in order. */ 358 DELAY(1000); 359 360 /* Select 32-bit (DWIO) mode */ 361 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 362 363 /* Select software style 3. */ 364 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 365 366 return; 367} 368 369/* 370 * Probe for an AMD chip. Check the PCI vendor and device 371 * IDs against our list and return a device name if we find a match. 372 */ 373static int pcn_probe(dev) 374 device_t dev; 375{ 376 struct pcn_type *t; 377 struct pcn_softc *sc; 378 int rid; 379 u_int32_t chip_id; 380 381 t = pcn_devs; 382 sc = device_get_softc(dev); 383 384 while(t->pcn_name != NULL) { 385 if ((pci_get_vendor(dev) == t->pcn_vid) && 386 (pci_get_device(dev) == t->pcn_did)) { 387 /* 388 * Temporarily map the I/O space 389 * so we can read the chip ID register. 390 */ 391 rid = PCN_RID; 392 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 393 0, ~0, 1, RF_ACTIVE); 394 if (sc->pcn_res == NULL) { 395 device_printf(dev, 396 "couldn't map ports/memory\n"); 397 return(ENXIO); 398 } 399 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 400 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 401 pcn_reset(sc); 402 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 403 chip_id <<= 16; 404 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 405 bus_release_resource(dev, PCN_RES, 406 PCN_RID, sc->pcn_res); 407 chip_id >>= 12; 408 sc->pcn_type = chip_id & PART_MASK; 409 switch(sc->pcn_type) { 410 case Am79C971: 411 case Am79C972: 412 case Am79C973: 413 case Am79C978: 414 break; 415 default: 416 return(ENXIO); 417 break; 418 } 419 device_set_desc(dev, t->pcn_name); 420 return(0); 421 } 422 t++; 423 } 424 425 return(ENXIO); 426} 427 428/* 429 * Attach the interface. Allocate softc structures, do ifmedia 430 * setup and ethernet/BPF attach. 431 */ 432static int pcn_attach(dev) 433 device_t dev; 434{ 435 int s; 436 u_int32_t eaddr[2]; 437 u_int32_t command; 438 struct pcn_softc *sc; 439 struct ifnet *ifp; 440 int unit, error = 0, rid; 441 442 s = splimp(); 443 444 sc = device_get_softc(dev); 445 unit = device_get_unit(dev); 446 447 /* 448 * Handle power management nonsense. 449 */ 450 451 command = pci_read_config(dev, PCN_PCI_CAPID, 4) & 0x000000FF; 452 if (command == 0x01) { 453 454 command = pci_read_config(dev, PCN_PCI_PWRMGMTCTRL, 4); 455 if (command & PCN_PSTATE_MASK) { 456 u_int32_t iobase, membase, irq; 457 458 /* Save important PCI config data. */ 459 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 460 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 461 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 462 463 /* Reset the power state. */ 464 printf("pcn%d: chip is in D%d power mode " 465 "-- setting to D0\n", unit, command & PCN_PSTATE_MASK); 466 command &= 0xFFFFFFFC; 467 pci_write_config(dev, PCN_PCI_PWRMGMTCTRL, command, 4); 468 469 /* Restore PCI config data. */ 470 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 471 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 472 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 473 } 474 } 475 476 /* 477 * Map control/status registers. 478 */ 479 command = pci_read_config(dev, PCIR_COMMAND, 4); 480 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 481 pci_write_config(dev, PCIR_COMMAND, command, 4); 482 command = pci_read_config(dev, PCIR_COMMAND, 4); 483 484#ifdef PCN_USEIOSPACE 485 if (!(command & PCIM_CMD_PORTEN)) { 486 printf("pcn%d: failed to enable I/O ports!\n", unit); 487 error = ENXIO;; 488 goto fail; 489 } 490#else 491 if (!(command & PCIM_CMD_MEMEN)) { 492 printf("pcn%d: failed to enable memory mapping!\n", unit); 493 error = ENXIO;; 494 goto fail; 495 } 496#endif 497 498 rid = PCN_RID; 499 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 500 0, ~0, 1, RF_ACTIVE); 501 502 if (sc->pcn_res == NULL) { 503 printf("pcn%d: couldn't map ports/memory\n", unit); 504 error = ENXIO; 505 goto fail; 506 } 507 508 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 509 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 510 511 /* Allocate interrupt */ 512 rid = 0; 513 sc->pcn_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 514 RF_SHAREABLE | RF_ACTIVE); 515 516 if (sc->pcn_irq == NULL) { 517 printf("pcn%d: couldn't map interrupt\n", unit); 518 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 519 error = ENXIO; 520 goto fail; 521 } 522 523 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 524 pcn_intr, sc, &sc->pcn_intrhand); 525 526 if (error) { 527 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_res); 528 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 529 printf("pcn%d: couldn't set up irq\n", unit); 530 goto fail; 531 } 532 533 /* Reset the adapter. */ 534 pcn_reset(sc); 535 536 /* 537 * Get station address from the EEPROM. 538 */ 539 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 540 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 541 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 542 543 /* 544 * An AMD chip was detected. Inform the world. 545 */ 546 printf("pcn%d: Ethernet address: %6D\n", unit, 547 sc->arpcom.ac_enaddr, ":"); 548 549 sc->pcn_unit = unit; 550 callout_handle_init(&sc->pcn_stat_ch); 551 552 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 553 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 554 555 if (sc->pcn_ldata == NULL) { 556 printf("pcn%d: no memory for list buffers!\n", unit); 557 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 558 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 559 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 560 error = ENXIO; 561 goto fail; 562 } 563 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 564 565 ifp = &sc->arpcom.ac_if; 566 ifp->if_softc = sc; 567 ifp->if_unit = unit; 568 ifp->if_name = "pcn"; 569 ifp->if_mtu = ETHERMTU; 570 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 571 ifp->if_ioctl = pcn_ioctl; 572 ifp->if_output = ether_output; 573 ifp->if_start = pcn_start; 574 ifp->if_watchdog = pcn_watchdog; 575 ifp->if_init = pcn_init; 576 ifp->if_baudrate = 10000000; 577 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 578 579 /* 580 * Do MII setup. 581 */ 582 if (mii_phy_probe(dev, &sc->pcn_miibus, 583 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 584 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 585 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 586 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 587 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 588 error = ENXIO; 589 goto fail; 590 } 591 592 /* 593 * Call MI attach routine. 594 */ 595 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 596 callout_handle_init(&sc->pcn_stat_ch); 597 598fail: 599 splx(s); 600 return(error); 601} 602 603static int pcn_detach(dev) 604 device_t dev; 605{ 606 struct pcn_softc *sc; 607 struct ifnet *ifp; 608 int s; 609 610 s = splimp(); 611 612 sc = device_get_softc(dev); 613 ifp = &sc->arpcom.ac_if; 614 615 pcn_reset(sc); 616 pcn_stop(sc); 617 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 618 619 if (sc->pcn_miibus != NULL) { 620 bus_generic_detach(dev); 621 device_delete_child(dev, sc->pcn_miibus); 622 } 623 624 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 625 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 626 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 627 628 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), M_DEVBUF); 629 630 splx(s); 631 632 return(0); 633} 634 635/* 636 * Initialize the transmit descriptors. 637 */ 638static int pcn_list_tx_init(sc) 639 struct pcn_softc *sc; 640{ 641 struct pcn_list_data *ld; 642 struct pcn_ring_data *cd; 643 int i; 644 645 cd = &sc->pcn_cdata; 646 ld = sc->pcn_ldata; 647 648 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 649 cd->pcn_tx_chain[i] = NULL; 650 ld->pcn_tx_list[i].pcn_tbaddr = 0; 651 ld->pcn_tx_list[i].pcn_txctl = 0; 652 ld->pcn_tx_list[i].pcn_txstat = 0; 653 } 654 655 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 656 657 return(0); 658} 659 660 661/* 662 * Initialize the RX descriptors and allocate mbufs for them. 663 */ 664static int pcn_list_rx_init(sc) 665 struct pcn_softc *sc; 666{ 667 struct pcn_list_data *ld; 668 struct pcn_ring_data *cd; 669 int i; 670 671 ld = sc->pcn_ldata; 672 cd = &sc->pcn_cdata; 673 674 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 675 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 676 return(ENOBUFS); 677 } 678 679 cd->pcn_rx_prod = 0; 680 681 return(0); 682} 683 684/* 685 * Initialize an RX descriptor and attach an MBUF cluster. 686 */ 687static int pcn_newbuf(sc, idx, m) 688 struct pcn_softc *sc; 689 int idx; 690 struct mbuf *m; 691{ 692 struct mbuf *m_new = NULL; 693 struct pcn_rx_desc *c; 694 695 c = &sc->pcn_ldata->pcn_rx_list[idx]; 696 697 if (m == NULL) { 698 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 699 if (m_new == NULL) { 700 printf("pcn%d: no memory for rx list " 701 "-- packet dropped!\n", sc->pcn_unit); 702 return(ENOBUFS); 703 } 704 705 MCLGET(m_new, M_DONTWAIT); 706 if (!(m_new->m_flags & M_EXT)) { 707 printf("pcn%d: no memory for rx list " 708 "-- packet dropped!\n", sc->pcn_unit); 709 m_freem(m_new); 710 return(ENOBUFS); 711 } 712 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 713 } else { 714 m_new = m; 715 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 716 m_new->m_data = m_new->m_ext.ext_buf; 717 } 718 719 m_adj(m_new, ETHER_ALIGN); 720 721 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 722 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 723 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 724 c->pcn_bufsz |= PCN_RXLEN_MBO; 725 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 726 727 return(0); 728} 729 730/* 731 * A frame has been uploaded: pass the resulting mbuf chain up to 732 * the higher level protocols. 733 */ 734static void pcn_rxeof(sc) 735 struct pcn_softc *sc; 736{ 737 struct ether_header *eh; 738 struct mbuf *m; 739 struct ifnet *ifp; 740 struct pcn_rx_desc *cur_rx; 741 int i; 742 743 ifp = &sc->arpcom.ac_if; 744 i = sc->pcn_cdata.pcn_rx_prod; 745 746 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 747 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 748 m = sc->pcn_cdata.pcn_rx_chain[i]; 749 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 750 751 /* 752 * If an error occurs, update stats, clear the 753 * status word and leave the mbuf cluster in place: 754 * it should simply get re-used next time this descriptor 755 * comes up in the ring. 756 */ 757 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 758 ifp->if_ierrors++; 759 pcn_newbuf(sc, i, m); 760 PCN_INC(i, PCN_RX_LIST_CNT); 761 continue; 762 } 763 764 pcn_newbuf(sc, i, NULL); 765 PCN_INC(i, PCN_RX_LIST_CNT); 766 767 /* No errors; receive the packet. */ 768 ifp->if_ipackets++; 769 eh = mtod(m, struct ether_header *); 770 m->m_len = m->m_pkthdr.len = 771 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 772 m->m_pkthdr.rcvif = ifp; 773 774 /* Remove header from mbuf and pass it on. */ 775 m_adj(m, sizeof(struct ether_header)); 776 ether_input(ifp, eh, m); 777 } 778 779 sc->pcn_cdata.pcn_rx_prod = i; 780 781 return; 782} 783 784/* 785 * A frame was downloaded to the chip. It's safe for us to clean up 786 * the list buffers. 787 */ 788 789static void pcn_txeof(sc) 790 struct pcn_softc *sc; 791{ 792 struct pcn_tx_desc *cur_tx = NULL; 793 struct ifnet *ifp; 794 u_int32_t idx; 795 796 ifp = &sc->arpcom.ac_if; 797 798 /* Clear the timeout timer. */ 799 ifp->if_timer = 0; 800 801 /* 802 * Go through our tx list and free mbufs for those 803 * frames that have been transmitted. 804 */ 805 idx = sc->pcn_cdata.pcn_tx_cons; 806 while (idx != sc->pcn_cdata.pcn_tx_prod) { 807 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 808 809 if (!PCN_OWN_TXDESC(cur_tx)) 810 break; 811 812 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 813 sc->pcn_cdata.pcn_tx_cnt--; 814 PCN_INC(idx, PCN_TX_LIST_CNT); 815 continue; 816 } 817 818 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 819 ifp->if_oerrors++; 820 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 821 ifp->if_collisions++; 822 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 823 ifp->if_collisions++; 824 } 825 826 ifp->if_collisions += 827 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 828 829 ifp->if_opackets++; 830 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 831 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 832 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 833 } 834 835 sc->pcn_cdata.pcn_tx_cnt--; 836 PCN_INC(idx, PCN_TX_LIST_CNT); 837 ifp->if_timer = 0; 838 } 839 840 sc->pcn_cdata.pcn_tx_cons = idx; 841 842 if (cur_tx != NULL) 843 ifp->if_flags &= ~IFF_OACTIVE; 844 845 return; 846} 847 848static void pcn_tick(xsc) 849 void *xsc; 850{ 851 struct pcn_softc *sc; 852 struct mii_data *mii; 853 struct ifnet *ifp; 854 int s; 855 856 s = splimp(); 857 858 sc = xsc; 859 ifp = &sc->arpcom.ac_if; 860 861 mii = device_get_softc(sc->pcn_miibus); 862 mii_tick(mii); 863 864 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 865 sc->pcn_link = 0; 866 867 if (!sc->pcn_link) { 868 mii_pollstat(mii); 869 if (mii->mii_media_status & IFM_ACTIVE && 870 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 871 sc->pcn_link++; 872 if (ifp->if_snd.ifq_head != NULL) 873 pcn_start(ifp); 874 } 875 876 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 877 878 splx(s); 879 880 return; 881} 882 883static void pcn_intr(arg) 884 void *arg; 885{ 886 struct pcn_softc *sc; 887 struct ifnet *ifp; 888 u_int32_t status; 889 890 sc = arg; 891 ifp = &sc->arpcom.ac_if; 892 893 /* Supress unwanted interrupts */ 894 if (!(ifp->if_flags & IFF_UP)) { 895 pcn_stop(sc); 896 return; 897 } 898 899 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 900 901 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 902 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 903 904 if (status & PCN_CSR_RINT) 905 pcn_rxeof(sc); 906 907 if (status & PCN_CSR_TINT) 908 pcn_txeof(sc); 909 910 if (status & PCN_CSR_ERR) { 911 pcn_init(sc); 912 break; 913 } 914 } 915 916 if (ifp->if_snd.ifq_head != NULL) 917 pcn_start(ifp); 918 919 return; 920} 921 922/* 923 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 924 * pointers to the fragment pointers. 925 */ 926static int pcn_encap(sc, m_head, txidx) 927 struct pcn_softc *sc; 928 struct mbuf *m_head; 929 u_int32_t *txidx; 930{ 931 struct pcn_tx_desc *f = NULL; 932 struct mbuf *m; 933 int frag, cur, cnt = 0; 934 935 /* 936 * Start packing the mbufs in this chain into 937 * the fragment pointers. Stop when we run out 938 * of fragments or hit the end of the mbuf chain. 939 */ 940 m = m_head; 941 cur = frag = *txidx; 942 943 for (m = m_head; m != NULL; m = m->m_next) { 944 if (m->m_len != 0) { 945 if ((PCN_TX_LIST_CNT - 946 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 947 return(ENOBUFS); 948 f = &sc->pcn_ldata->pcn_tx_list[frag]; 949 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 950 f->pcn_txctl |= PCN_TXCTL_MBO; 951 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 952 if (cnt == 0) 953 f->pcn_txctl |= PCN_TXCTL_STP; 954 else 955 f->pcn_txctl |= PCN_TXCTL_OWN; 956 cur = frag; 957 PCN_INC(frag, PCN_TX_LIST_CNT); 958 cnt++; 959 } 960 } 961 962 if (m != NULL) 963 return(ENOBUFS); 964 965 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 966 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 967 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 968 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 969 sc->pcn_cdata.pcn_tx_cnt += cnt; 970 *txidx = frag; 971 972 return(0); 973} 974 975/* 976 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 977 * to the mbuf data regions directly in the transmit lists. We also save a 978 * copy of the pointers since the transmit list fragment pointers are 979 * physical addresses. 980 */ 981static void pcn_start(ifp) 982 struct ifnet *ifp; 983{ 984 struct pcn_softc *sc; 985 struct mbuf *m_head = NULL; 986 u_int32_t idx; 987 988 sc = ifp->if_softc; 989 990 if (!sc->pcn_link) 991 return; 992 993 idx = sc->pcn_cdata.pcn_tx_prod; 994 995 if (ifp->if_flags & IFF_OACTIVE) 996 return; 997 998 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 999 IF_DEQUEUE(&ifp->if_snd, m_head); 1000 if (m_head == NULL) 1001 break; 1002 1003 if (pcn_encap(sc, m_head, &idx)) { 1004 IF_PREPEND(&ifp->if_snd, m_head); 1005 ifp->if_flags |= IFF_OACTIVE; 1006 break; 1007 } 1008 1009 /* 1010 * If there's a BPF listener, bounce a copy of this frame 1011 * to him. 1012 */ 1013 if (ifp->if_bpf) 1014 bpf_mtap(ifp, m_head); 1015 1016 } 1017 1018 /* Transmit */ 1019 sc->pcn_cdata.pcn_tx_prod = idx; 1020 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1021 1022 /* 1023 * Set a timeout in case the chip goes out to lunch. 1024 */ 1025 ifp->if_timer = 5; 1026 1027 return; 1028} 1029 1030static void pcn_init(xsc) 1031 void *xsc; 1032{ 1033 struct pcn_softc *sc = xsc; 1034 struct ifnet *ifp = &sc->arpcom.ac_if; 1035 struct mii_data *mii = NULL; 1036 int s; 1037 1038 s = splimp(); 1039 1040 /* 1041 * Cancel pending I/O and free all RX/TX buffers. 1042 */ 1043 pcn_stop(sc); 1044 pcn_reset(sc); 1045 1046 mii = device_get_softc(sc->pcn_miibus); 1047 1048 /* Set MAC address */ 1049 pcn_csr_write(sc, PCN_CSR_PAR0, 1050 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1051 pcn_csr_write(sc, PCN_CSR_PAR1, 1052 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1053 pcn_csr_write(sc, PCN_CSR_PAR2, 1054 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1055 1056 /* Init circular RX list. */ 1057 if (pcn_list_rx_init(sc) == ENOBUFS) { 1058 printf("pcn%d: initialization failed: no " 1059 "memory for rx buffers\n", sc->pcn_unit); 1060 pcn_stop(sc); 1061 (void)splx(s); 1062 return; 1063 } 1064 1065 /* 1066 * Init tx descriptors. 1067 */ 1068 pcn_list_tx_init(sc); 1069 1070 /* Set up the mode register. */ 1071 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1072 1073 /* If we want promiscuous mode, set the allframes bit. */ 1074 if (ifp->if_flags & IFF_PROMISC) { 1075 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1076 } else { 1077 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1078 } 1079 1080 /* Set the capture broadcast bit to capture broadcast frames. */ 1081 if (ifp->if_flags & IFF_BROADCAST) { 1082 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1083 } else { 1084 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1085 } 1086 1087 /* 1088 * Load the multicast filter. 1089 */ 1090 pcn_setmulti(sc); 1091 1092 /* 1093 * Load the addresses of the RX and TX lists. 1094 */ 1095 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1096 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1097 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1098 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1099 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1100 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1101 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1102 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1103 1104 /* Set the RX and TX ring sizes. */ 1105 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1106 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1107 1108 /* We're not using the initialization block. */ 1109 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1110 1111 /* Enable fast suspend mode. */ 1112 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1113 1114 /* 1115 * Enable burst read and write. Also set the no underflow 1116 * bit. This will avoid transmit underruns in certain 1117 * conditions while still providing decent performance. 1118 */ 1119 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1120 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1121 1122 /* Enable graceful recovery from underflow. */ 1123 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1124 1125 /* Enable auto-padding of short TX frames. */ 1126 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1127 1128 /* Disable MII autoneg (we handle this ourselves). */ 1129 PCN_BCR_CLRBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1130 1131 if (sc->pcn_type == Am79C978) 1132 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1133 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1134 1135 /* Enable interrupts and start the controller running. */ 1136 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1137 1138 mii_mediachg(mii); 1139 1140 ifp->if_flags |= IFF_RUNNING; 1141 ifp->if_flags &= ~IFF_OACTIVE; 1142 1143 (void)splx(s); 1144 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 1145 1146 return; 1147} 1148 1149/* 1150 * Set media options. 1151 */ 1152static int pcn_ifmedia_upd(ifp) 1153 struct ifnet *ifp; 1154{ 1155 struct pcn_softc *sc; 1156 struct mii_data *mii; 1157 1158 sc = ifp->if_softc; 1159 mii = device_get_softc(sc->pcn_miibus); 1160 1161 sc->pcn_link = 0; 1162 if (mii->mii_instance) { 1163 struct mii_softc *miisc; 1164 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1165 miisc = LIST_NEXT(miisc, mii_list)) 1166 mii_phy_reset(miisc); 1167 } 1168 mii_mediachg(mii); 1169 1170 return(0); 1171} 1172 1173/* 1174 * Report current media status. 1175 */ 1176static void pcn_ifmedia_sts(ifp, ifmr) 1177 struct ifnet *ifp; 1178 struct ifmediareq *ifmr; 1179{ 1180 struct pcn_softc *sc; 1181 struct mii_data *mii; 1182 1183 sc = ifp->if_softc; 1184 1185 mii = device_get_softc(sc->pcn_miibus); 1186 mii_pollstat(mii); 1187 ifmr->ifm_active = mii->mii_media_active; 1188 ifmr->ifm_status = mii->mii_media_status; 1189 1190 return; 1191} 1192 1193static int pcn_ioctl(ifp, command, data) 1194 struct ifnet *ifp; 1195 u_long command; 1196 caddr_t data; 1197{ 1198 struct pcn_softc *sc = ifp->if_softc; 1199 struct ifreq *ifr = (struct ifreq *) data; 1200 struct mii_data *mii = NULL; 1201 int s, error = 0; 1202 1203 s = splimp(); 1204 1205 switch(command) { 1206 case SIOCSIFADDR: 1207 case SIOCGIFADDR: 1208 case SIOCSIFMTU: 1209 error = ether_ioctl(ifp, command, data); 1210 break; 1211 case SIOCSIFFLAGS: 1212 if (ifp->if_flags & IFF_UP) { 1213 if (ifp->if_flags & IFF_RUNNING && 1214 ifp->if_flags & IFF_PROMISC && 1215 !(sc->pcn_if_flags & IFF_PROMISC)) { 1216 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1217 PCN_EXTCTL1_SPND); 1218 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, 1219 PCN_MODE_PROMISC); 1220 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1221 PCN_EXTCTL1_SPND); 1222 } else if (ifp->if_flags & IFF_RUNNING && 1223 !(ifp->if_flags & IFF_PROMISC) && 1224 sc->pcn_if_flags & IFF_PROMISC) { 1225 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1226 PCN_EXTCTL1_SPND); 1227 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, 1228 PCN_MODE_PROMISC); 1229 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1230 PCN_EXTCTL1_SPND); 1231 } else if (!(ifp->if_flags & IFF_RUNNING)) 1232 pcn_init(sc); 1233 } else { 1234 if (ifp->if_flags & IFF_RUNNING) 1235 pcn_stop(sc); 1236 } 1237 sc->pcn_if_flags = ifp->if_flags; 1238 error = 0; 1239 break; 1240 case SIOCADDMULTI: 1241 case SIOCDELMULTI: 1242 pcn_setmulti(sc); 1243 error = 0; 1244 break; 1245 case SIOCGIFMEDIA: 1246 case SIOCSIFMEDIA: 1247 mii = device_get_softc(sc->pcn_miibus); 1248 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1249 break; 1250 default: 1251 error = EINVAL; 1252 break; 1253 } 1254 1255 (void)splx(s); 1256 1257 return(error); 1258} 1259 1260static void pcn_watchdog(ifp) 1261 struct ifnet *ifp; 1262{ 1263 struct pcn_softc *sc; 1264 1265 sc = ifp->if_softc; 1266 1267 ifp->if_oerrors++; 1268 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1269 1270 pcn_stop(sc); 1271 pcn_reset(sc); 1272 pcn_init(sc); 1273 1274 if (ifp->if_snd.ifq_head != NULL) 1275 pcn_start(ifp); 1276 1277 return; 1278} 1279 1280/* 1281 * Stop the adapter and free any mbufs allocated to the 1282 * RX and TX lists. 1283 */ 1284static void pcn_stop(sc) 1285 struct pcn_softc *sc; 1286{ 1287 register int i; 1288 struct ifnet *ifp; 1289 1290 ifp = &sc->arpcom.ac_if; 1291 ifp->if_timer = 0; 1292 1293 untimeout(pcn_tick, sc, sc->pcn_stat_ch); 1294 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1295 sc->pcn_link = 0; 1296 1297 /* 1298 * Free data in the RX lists. 1299 */ 1300 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1301 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1302 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1303 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1304 } 1305 } 1306 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1307 sizeof(sc->pcn_ldata->pcn_rx_list)); 1308 1309 /* 1310 * Free the TX list buffers. 1311 */ 1312 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1313 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1314 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1315 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1316 } 1317 } 1318 1319 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1320 sizeof(sc->pcn_ldata->pcn_tx_list)); 1321 1322 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1323 1324 return; 1325} 1326 1327/* 1328 * Stop all chip I/O so that the kernel's probe routines don't 1329 * get confused by errant DMAs when rebooting. 1330 */ 1331static void pcn_shutdown(dev) 1332 device_t dev; 1333{ 1334 struct pcn_softc *sc; 1335 1336 sc = device_get_softc(dev); 1337 1338 pcn_reset(sc); 1339 pcn_stop(sc); 1340 1341 return; 1342} 1343