if_pcn.c revision 271813
1/*- 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/dev/pcn/if_pcn.c 271813 2014-09-18 20:24:47Z glebius $"); 36 37/* 38 * AMD Am79c972 fast ethernet PCI NIC driver. Datasheets are available 39 * from http://www.amd.com. 40 * 41 * The AMD PCnet/PCI controllers are more advanced and functional 42 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 43 * backwards compatibility with the LANCE and thus can be made 44 * to work with older LANCE drivers. This is in fact how the 45 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 46 * is that the PCnet/PCI devices offer several performance enhancements 47 * which can't be exploited in LANCE compatibility mode. Chief among 48 * these enhancements is the ability to perform PCI DMA operations 49 * using 32-bit addressing (which eliminates the need for ISA 50 * bounce-buffering), and special receive buffer alignment (which 51 * allows the receive handler to pass packets to the upper protocol 52 * layers without copying on both the x86 and alpha platforms). 53 */ 54 55#include <sys/param.h> 56#include <sys/systm.h> 57#include <sys/sockio.h> 58#include <sys/mbuf.h> 59#include <sys/malloc.h> 60#include <sys/kernel.h> 61#include <sys/module.h> 62#include <sys/socket.h> 63 64#include <net/if.h> 65#include <net/if_var.h> 66#include <net/if_arp.h> 67#include <net/ethernet.h> 68#include <net/if_dl.h> 69#include <net/if_media.h> 70#include <net/if_types.h> 71 72#include <net/bpf.h> 73 74#include <vm/vm.h> /* for vtophys */ 75#include <vm/pmap.h> /* for vtophys */ 76#include <machine/bus.h> 77#include <machine/resource.h> 78#include <sys/bus.h> 79#include <sys/rman.h> 80 81#include <dev/mii/mii.h> 82#include <dev/mii/miivar.h> 83 84#include <dev/pci/pcireg.h> 85#include <dev/pci/pcivar.h> 86 87#define PCN_USEIOSPACE 88 89#include <dev/pcn/if_pcnreg.h> 90 91MODULE_DEPEND(pcn, pci, 1, 1, 1); 92MODULE_DEPEND(pcn, ether, 1, 1, 1); 93MODULE_DEPEND(pcn, miibus, 1, 1, 1); 94 95/* "device miibus" required. See GENERIC if you get errors here. */ 96#include "miibus_if.h" 97 98/* 99 * Various supported device vendors/types and their names. 100 */ 101static const struct pcn_type pcn_devs[] = { 102 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 103 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 104 { 0, 0, NULL } 105}; 106 107static const struct pcn_chipid { 108 u_int32_t id; 109 const char *name; 110} pcn_chipid[] = { 111 { Am79C971, "Am79C971" }, 112 { Am79C972, "Am79C972" }, 113 { Am79C973, "Am79C973" }, 114 { Am79C978, "Am79C978" }, 115 { Am79C975, "Am79C975" }, 116 { Am79C976, "Am79C976" }, 117 { 0, NULL }, 118}; 119 120static const char *pcn_chipid_name(u_int32_t); 121static u_int32_t pcn_chip_id(device_t); 122static const struct pcn_type *pcn_match(u_int16_t, u_int16_t); 123 124static u_int32_t pcn_csr_read(struct pcn_softc *, int); 125static u_int16_t pcn_csr_read16(struct pcn_softc *, int); 126static u_int16_t pcn_bcr_read16(struct pcn_softc *, int); 127static void pcn_csr_write(struct pcn_softc *, int, int); 128static u_int32_t pcn_bcr_read(struct pcn_softc *, int); 129static void pcn_bcr_write(struct pcn_softc *, int, int); 130 131static int pcn_probe(device_t); 132static int pcn_attach(device_t); 133static int pcn_detach(device_t); 134 135static int pcn_newbuf(struct pcn_softc *, int, struct mbuf *); 136static int pcn_encap(struct pcn_softc *, struct mbuf *, u_int32_t *); 137static void pcn_rxeof(struct pcn_softc *); 138static void pcn_txeof(struct pcn_softc *); 139static void pcn_intr(void *); 140static void pcn_tick(void *); 141static void pcn_start(struct ifnet *); 142static void pcn_start_locked(struct ifnet *); 143static int pcn_ioctl(struct ifnet *, u_long, caddr_t); 144static void pcn_init(void *); 145static void pcn_init_locked(struct pcn_softc *); 146static void pcn_stop(struct pcn_softc *); 147static void pcn_watchdog(struct pcn_softc *); 148static int pcn_shutdown(device_t); 149static int pcn_ifmedia_upd(struct ifnet *); 150static void pcn_ifmedia_sts(struct ifnet *, struct ifmediareq *); 151 152static int pcn_miibus_readreg(device_t, int, int); 153static int pcn_miibus_writereg(device_t, int, int, int); 154static void pcn_miibus_statchg(device_t); 155 156static void pcn_setfilt(struct ifnet *); 157static void pcn_setmulti(struct pcn_softc *); 158static void pcn_reset(struct pcn_softc *); 159static int pcn_list_rx_init(struct pcn_softc *); 160static int pcn_list_tx_init(struct pcn_softc *); 161 162#ifdef PCN_USEIOSPACE 163#define PCN_RES SYS_RES_IOPORT 164#define PCN_RID PCN_PCI_LOIO 165#else 166#define PCN_RES SYS_RES_MEMORY 167#define PCN_RID PCN_PCI_LOMEM 168#endif 169 170static device_method_t pcn_methods[] = { 171 /* Device interface */ 172 DEVMETHOD(device_probe, pcn_probe), 173 DEVMETHOD(device_attach, pcn_attach), 174 DEVMETHOD(device_detach, pcn_detach), 175 DEVMETHOD(device_shutdown, pcn_shutdown), 176 177 /* MII interface */ 178 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 179 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 180 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 181 182 DEVMETHOD_END 183}; 184 185static driver_t pcn_driver = { 186 "pcn", 187 pcn_methods, 188 sizeof(struct pcn_softc) 189}; 190 191static devclass_t pcn_devclass; 192 193DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0); 194DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 195 196#define PCN_CSR_SETBIT(sc, reg, x) \ 197 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 198 199#define PCN_CSR_CLRBIT(sc, reg, x) \ 200 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 201 202#define PCN_BCR_SETBIT(sc, reg, x) \ 203 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 204 205#define PCN_BCR_CLRBIT(sc, reg, x) \ 206 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 207 208static u_int32_t 209pcn_csr_read(sc, reg) 210 struct pcn_softc *sc; 211 int reg; 212{ 213 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 214 return(CSR_READ_4(sc, PCN_IO32_RDP)); 215} 216 217static u_int16_t 218pcn_csr_read16(sc, reg) 219 struct pcn_softc *sc; 220 int reg; 221{ 222 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 223 return(CSR_READ_2(sc, PCN_IO16_RDP)); 224} 225 226static void 227pcn_csr_write(sc, reg, val) 228 struct pcn_softc *sc; 229 int reg; 230 int val; 231{ 232 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 233 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 234 return; 235} 236 237static u_int32_t 238pcn_bcr_read(sc, reg) 239 struct pcn_softc *sc; 240 int reg; 241{ 242 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 243 return(CSR_READ_4(sc, PCN_IO32_BDP)); 244} 245 246static u_int16_t 247pcn_bcr_read16(sc, reg) 248 struct pcn_softc *sc; 249 int reg; 250{ 251 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 252 return(CSR_READ_2(sc, PCN_IO16_BDP)); 253} 254 255static void 256pcn_bcr_write(sc, reg, val) 257 struct pcn_softc *sc; 258 int reg; 259 int val; 260{ 261 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 262 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 263 return; 264} 265 266static int 267pcn_miibus_readreg(dev, phy, reg) 268 device_t dev; 269 int phy, reg; 270{ 271 struct pcn_softc *sc; 272 int val; 273 274 sc = device_get_softc(dev); 275 276 /* 277 * At least Am79C971 with DP83840A wedge when isolating the 278 * external PHY so we can't allow multiple external PHYs. 279 * There are cards that use Am79C971 with both the internal 280 * and an external PHY though. 281 * For internal PHYs it doesn't really matter whether we can 282 * isolate the remaining internal and the external ones in 283 * the PHY drivers as the internal PHYs have to be enabled 284 * individually in PCN_BCR_PHYSEL, PCN_CSR_MODE, etc. 285 * With Am79C97{3,5,8} we don't support switching beetween 286 * the internal and external PHYs, yet, so we can't allow 287 * multiple PHYs with these either. 288 * Am79C97{2,6} actually only support external PHYs (not 289 * connectable internal ones respond at the usual addresses, 290 * which don't hurt if we let them show up on the bus) and 291 * isolating them works. 292 */ 293 if (((sc->pcn_type == Am79C971 && phy != PCN_PHYAD_10BT) || 294 sc->pcn_type == Am79C973 || sc->pcn_type == Am79C975 || 295 sc->pcn_type == Am79C978) && sc->pcn_extphyaddr != -1 && 296 phy != sc->pcn_extphyaddr) 297 return(0); 298 299 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 300 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 301 if (val == 0xFFFF) 302 return(0); 303 304 if (((sc->pcn_type == Am79C971 && phy != PCN_PHYAD_10BT) || 305 sc->pcn_type == Am79C973 || sc->pcn_type == Am79C975 || 306 sc->pcn_type == Am79C978) && sc->pcn_extphyaddr == -1) 307 sc->pcn_extphyaddr = phy; 308 309 return(val); 310} 311 312static int 313pcn_miibus_writereg(dev, phy, reg, data) 314 device_t dev; 315 int phy, reg, data; 316{ 317 struct pcn_softc *sc; 318 319 sc = device_get_softc(dev); 320 321 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 322 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 323 324 return(0); 325} 326 327static void 328pcn_miibus_statchg(dev) 329 device_t dev; 330{ 331 struct pcn_softc *sc; 332 struct mii_data *mii; 333 334 sc = device_get_softc(dev); 335 mii = device_get_softc(sc->pcn_miibus); 336 337 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 338 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 339 } else { 340 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 341 } 342 343 return; 344} 345 346static void 347pcn_setmulti(sc) 348 struct pcn_softc *sc; 349{ 350 struct ifnet *ifp; 351 struct ifmultiaddr *ifma; 352 u_int32_t h, i; 353 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 354 355 ifp = sc->pcn_ifp; 356 357 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 358 359 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 360 for (i = 0; i < 4; i++) 361 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 362 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 363 return; 364 } 365 366 /* first, zot all the existing hash bits */ 367 for (i = 0; i < 4; i++) 368 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 369 370 /* now program new ones */ 371 if_maddr_rlock(ifp); 372 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 373 if (ifma->ifma_addr->sa_family != AF_LINK) 374 continue; 375 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 376 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 377 hashes[h >> 4] |= 1 << (h & 0xF); 378 } 379 if_maddr_runlock(ifp); 380 381 for (i = 0; i < 4; i++) 382 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 383 384 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 385 386 return; 387} 388 389static void 390pcn_reset(sc) 391 struct pcn_softc *sc; 392{ 393 /* 394 * Issue a reset by reading from the RESET register. 395 * Note that we don't know if the chip is operating in 396 * 16-bit or 32-bit mode at this point, so we attempt 397 * to reset the chip both ways. If one fails, the other 398 * will succeed. 399 */ 400 CSR_READ_2(sc, PCN_IO16_RESET); 401 CSR_READ_4(sc, PCN_IO32_RESET); 402 403 /* Wait a little while for the chip to get its brains in order. */ 404 DELAY(1000); 405 406 /* Select 32-bit (DWIO) mode */ 407 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 408 409 /* Select software style 3. */ 410 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 411 412 return; 413} 414 415static const char * 416pcn_chipid_name(u_int32_t id) 417{ 418 const struct pcn_chipid *p; 419 420 p = pcn_chipid; 421 while (p->name) { 422 if (id == p->id) 423 return (p->name); 424 p++; 425 } 426 return ("Unknown"); 427} 428 429static u_int32_t 430pcn_chip_id(device_t dev) 431{ 432 struct pcn_softc *sc; 433 u_int32_t chip_id; 434 435 sc = device_get_softc(dev); 436 /* 437 * Note: we can *NOT* put the chip into 438 * 32-bit mode yet. The le(4) driver will only 439 * work in 16-bit mode, and once the chip 440 * goes into 32-bit mode, the only way to 441 * get it out again is with a hardware reset. 442 * So if pcn_probe() is called before the 443 * le(4) driver's probe routine, the chip will 444 * be locked into 32-bit operation and the 445 * le(4) driver will be unable to attach to it. 446 * Note II: if the chip happens to already 447 * be in 32-bit mode, we still need to check 448 * the chip ID, but first we have to detect 449 * 32-bit mode using only 16-bit operations. 450 * The safest way to do this is to read the 451 * PCI subsystem ID from BCR23/24 and compare 452 * that with the value read from PCI config 453 * space. 454 */ 455 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 456 chip_id <<= 16; 457 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 458 /* 459 * Note III: the test for 0x10001000 is a hack to 460 * pacify VMware, who's pseudo-PCnet interface is 461 * broken. Reading the subsystem register from PCI 462 * config space yields 0x00000000 while reading the 463 * same value from I/O space yields 0x10001000. It's 464 * not supposed to be that way. 465 */ 466 if (chip_id == pci_read_config(dev, 467 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 468 /* We're in 16-bit mode. */ 469 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 470 chip_id <<= 16; 471 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 472 } else { 473 /* We're in 32-bit mode. */ 474 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 475 chip_id <<= 16; 476 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 477 } 478 479 return (chip_id); 480} 481 482static const struct pcn_type * 483pcn_match(u_int16_t vid, u_int16_t did) 484{ 485 const struct pcn_type *t; 486 487 t = pcn_devs; 488 while (t->pcn_name != NULL) { 489 if ((vid == t->pcn_vid) && (did == t->pcn_did)) 490 return (t); 491 t++; 492 } 493 return (NULL); 494} 495 496/* 497 * Probe for an AMD chip. Check the PCI vendor and device 498 * IDs against our list and return a device name if we find a match. 499 */ 500static int 501pcn_probe(dev) 502 device_t dev; 503{ 504 const struct pcn_type *t; 505 struct pcn_softc *sc; 506 int rid; 507 u_int32_t chip_id; 508 509 t = pcn_match(pci_get_vendor(dev), pci_get_device(dev)); 510 if (t == NULL) 511 return (ENXIO); 512 sc = device_get_softc(dev); 513 514 /* 515 * Temporarily map the I/O space so we can read the chip ID register. 516 */ 517 rid = PCN_RID; 518 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE); 519 if (sc->pcn_res == NULL) { 520 device_printf(dev, "couldn't map ports/memory\n"); 521 return(ENXIO); 522 } 523 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 524 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 525 526 chip_id = pcn_chip_id(dev); 527 528 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 529 530 switch((chip_id >> 12) & PART_MASK) { 531 case Am79C971: 532 case Am79C972: 533 case Am79C973: 534 case Am79C975: 535 case Am79C976: 536 case Am79C978: 537 break; 538 default: 539 return(ENXIO); 540 } 541 device_set_desc(dev, t->pcn_name); 542 return(BUS_PROBE_DEFAULT); 543} 544 545/* 546 * Attach the interface. Allocate softc structures, do ifmedia 547 * setup and ethernet/BPF attach. 548 */ 549static int 550pcn_attach(dev) 551 device_t dev; 552{ 553 u_int32_t eaddr[2]; 554 struct pcn_softc *sc; 555 struct mii_data *mii; 556 struct mii_softc *miisc; 557 struct ifnet *ifp; 558 int error = 0, rid; 559 560 sc = device_get_softc(dev); 561 562 /* Initialize our mutex. */ 563 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 564 MTX_DEF); 565 /* 566 * Map control/status registers. 567 */ 568 pci_enable_busmaster(dev); 569 570 /* Retrieve the chip ID */ 571 sc->pcn_type = (pcn_chip_id(dev) >> 12) & PART_MASK; 572 device_printf(dev, "Chip ID %04x (%s)\n", 573 sc->pcn_type, pcn_chipid_name(sc->pcn_type)); 574 575 rid = PCN_RID; 576 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE); 577 578 if (sc->pcn_res == NULL) { 579 device_printf(dev, "couldn't map ports/memory\n"); 580 error = ENXIO; 581 goto fail; 582 } 583 584 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 585 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 586 587 /* Allocate interrupt */ 588 rid = 0; 589 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 590 RF_SHAREABLE | RF_ACTIVE); 591 592 if (sc->pcn_irq == NULL) { 593 device_printf(dev, "couldn't map interrupt\n"); 594 error = ENXIO; 595 goto fail; 596 } 597 598 /* Reset the adapter. */ 599 pcn_reset(sc); 600 601 /* 602 * Get station address from the EEPROM. 603 */ 604 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 605 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 606 607 callout_init_mtx(&sc->pcn_stat_callout, &sc->pcn_mtx, 0); 608 609 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 610 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 611 612 if (sc->pcn_ldata == NULL) { 613 device_printf(dev, "no memory for list buffers!\n"); 614 error = ENXIO; 615 goto fail; 616 } 617 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 618 619 ifp = sc->pcn_ifp = if_alloc(IFT_ETHER); 620 if (ifp == NULL) { 621 device_printf(dev, "can not if_alloc()\n"); 622 error = ENOSPC; 623 goto fail; 624 } 625 ifp->if_softc = sc; 626 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 627 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 628 ifp->if_ioctl = pcn_ioctl; 629 ifp->if_start = pcn_start; 630 ifp->if_init = pcn_init; 631 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 632 633 /* 634 * Do MII setup. 635 * See the comment in pcn_miibus_readreg() for why we can't 636 * universally pass MIIF_NOISOLATE here. 637 */ 638 sc->pcn_extphyaddr = -1; 639 error = mii_attach(dev, &sc->pcn_miibus, ifp, pcn_ifmedia_upd, 640 pcn_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 641 if (error != 0) { 642 device_printf(dev, "attaching PHYs failed\n"); 643 goto fail; 644 } 645 /* 646 * Record the media instances of internal PHYs, which map the 647 * built-in interfaces to the MII, so we can set the active 648 * PHY/port based on the currently selected media. 649 */ 650 sc->pcn_inst_10bt = -1; 651 mii = device_get_softc(sc->pcn_miibus); 652 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 653 switch (miisc->mii_phy) { 654 case PCN_PHYAD_10BT: 655 sc->pcn_inst_10bt = miisc->mii_inst; 656 break; 657 /* 658 * XXX deal with the Am79C97{3,5} internal 100baseT 659 * and the Am79C978 internal HomePNA PHYs. 660 */ 661 } 662 } 663 664 /* 665 * Call MI attach routine. 666 */ 667 ether_ifattach(ifp, (u_int8_t *) eaddr); 668 669 /* Hook interrupt last to avoid having to lock softc */ 670 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET | INTR_MPSAFE, 671 NULL, pcn_intr, sc, &sc->pcn_intrhand); 672 673 if (error) { 674 device_printf(dev, "couldn't set up irq\n"); 675 ether_ifdetach(ifp); 676 goto fail; 677 } 678 679fail: 680 if (error) 681 pcn_detach(dev); 682 683 return(error); 684} 685 686/* 687 * Shutdown hardware and free up resources. This can be called any 688 * time after the mutex has been initialized. It is called in both 689 * the error case in attach and the normal detach case so it needs 690 * to be careful about only freeing resources that have actually been 691 * allocated. 692 */ 693static int 694pcn_detach(dev) 695 device_t dev; 696{ 697 struct pcn_softc *sc; 698 struct ifnet *ifp; 699 700 sc = device_get_softc(dev); 701 ifp = sc->pcn_ifp; 702 703 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized")); 704 705 /* These should only be active if attach succeeded */ 706 if (device_is_attached(dev)) { 707 PCN_LOCK(sc); 708 pcn_reset(sc); 709 pcn_stop(sc); 710 PCN_UNLOCK(sc); 711 callout_drain(&sc->pcn_stat_callout); 712 ether_ifdetach(ifp); 713 } 714 if (sc->pcn_miibus) 715 device_delete_child(dev, sc->pcn_miibus); 716 bus_generic_detach(dev); 717 718 if (sc->pcn_intrhand) 719 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 720 if (sc->pcn_irq) 721 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 722 if (sc->pcn_res) 723 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 724 725 if (ifp) 726 if_free(ifp); 727 728 if (sc->pcn_ldata) { 729 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 730 M_DEVBUF); 731 } 732 733 mtx_destroy(&sc->pcn_mtx); 734 735 return(0); 736} 737 738/* 739 * Initialize the transmit descriptors. 740 */ 741static int 742pcn_list_tx_init(sc) 743 struct pcn_softc *sc; 744{ 745 struct pcn_list_data *ld; 746 struct pcn_ring_data *cd; 747 int i; 748 749 cd = &sc->pcn_cdata; 750 ld = sc->pcn_ldata; 751 752 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 753 cd->pcn_tx_chain[i] = NULL; 754 ld->pcn_tx_list[i].pcn_tbaddr = 0; 755 ld->pcn_tx_list[i].pcn_txctl = 0; 756 ld->pcn_tx_list[i].pcn_txstat = 0; 757 } 758 759 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 760 761 return(0); 762} 763 764 765/* 766 * Initialize the RX descriptors and allocate mbufs for them. 767 */ 768static int 769pcn_list_rx_init(sc) 770 struct pcn_softc *sc; 771{ 772 struct pcn_ring_data *cd; 773 int i; 774 775 cd = &sc->pcn_cdata; 776 777 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 778 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 779 return(ENOBUFS); 780 } 781 782 cd->pcn_rx_prod = 0; 783 784 return(0); 785} 786 787/* 788 * Initialize an RX descriptor and attach an MBUF cluster. 789 */ 790static int 791pcn_newbuf(sc, idx, m) 792 struct pcn_softc *sc; 793 int idx; 794 struct mbuf *m; 795{ 796 struct mbuf *m_new = NULL; 797 struct pcn_rx_desc *c; 798 799 c = &sc->pcn_ldata->pcn_rx_list[idx]; 800 801 if (m == NULL) { 802 MGETHDR(m_new, M_NOWAIT, MT_DATA); 803 if (m_new == NULL) 804 return(ENOBUFS); 805 806 MCLGET(m_new, M_NOWAIT); 807 if (!(m_new->m_flags & M_EXT)) { 808 m_freem(m_new); 809 return(ENOBUFS); 810 } 811 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 812 } else { 813 m_new = m; 814 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 815 m_new->m_data = m_new->m_ext.ext_buf; 816 } 817 818 m_adj(m_new, ETHER_ALIGN); 819 820 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 821 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 822 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 823 c->pcn_bufsz |= PCN_RXLEN_MBO; 824 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 825 826 return(0); 827} 828 829/* 830 * A frame has been uploaded: pass the resulting mbuf chain up to 831 * the higher level protocols. 832 */ 833static void 834pcn_rxeof(sc) 835 struct pcn_softc *sc; 836{ 837 struct mbuf *m; 838 struct ifnet *ifp; 839 struct pcn_rx_desc *cur_rx; 840 int i; 841 842 PCN_LOCK_ASSERT(sc); 843 844 ifp = sc->pcn_ifp; 845 i = sc->pcn_cdata.pcn_rx_prod; 846 847 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 848 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 849 m = sc->pcn_cdata.pcn_rx_chain[i]; 850 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 851 852 /* 853 * If an error occurs, update stats, clear the 854 * status word and leave the mbuf cluster in place: 855 * it should simply get re-used next time this descriptor 856 * comes up in the ring. 857 */ 858 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 859 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 860 pcn_newbuf(sc, i, m); 861 PCN_INC(i, PCN_RX_LIST_CNT); 862 continue; 863 } 864 865 if (pcn_newbuf(sc, i, NULL)) { 866 /* Ran out of mbufs; recycle this one. */ 867 pcn_newbuf(sc, i, m); 868 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 869 PCN_INC(i, PCN_RX_LIST_CNT); 870 continue; 871 } 872 873 PCN_INC(i, PCN_RX_LIST_CNT); 874 875 /* No errors; receive the packet. */ 876 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 877 m->m_len = m->m_pkthdr.len = 878 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 879 m->m_pkthdr.rcvif = ifp; 880 881 PCN_UNLOCK(sc); 882 (*ifp->if_input)(ifp, m); 883 PCN_LOCK(sc); 884 } 885 886 sc->pcn_cdata.pcn_rx_prod = i; 887 888 return; 889} 890 891/* 892 * A frame was downloaded to the chip. It's safe for us to clean up 893 * the list buffers. 894 */ 895 896static void 897pcn_txeof(sc) 898 struct pcn_softc *sc; 899{ 900 struct pcn_tx_desc *cur_tx = NULL; 901 struct ifnet *ifp; 902 u_int32_t idx; 903 904 ifp = sc->pcn_ifp; 905 906 /* 907 * Go through our tx list and free mbufs for those 908 * frames that have been transmitted. 909 */ 910 idx = sc->pcn_cdata.pcn_tx_cons; 911 while (idx != sc->pcn_cdata.pcn_tx_prod) { 912 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 913 914 if (!PCN_OWN_TXDESC(cur_tx)) 915 break; 916 917 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 918 sc->pcn_cdata.pcn_tx_cnt--; 919 PCN_INC(idx, PCN_TX_LIST_CNT); 920 continue; 921 } 922 923 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 924 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 925 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 926 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 927 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 928 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 929 } 930 931 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 932 cur_tx->pcn_txstat & PCN_TXSTAT_TRC); 933 934 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 935 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 936 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 937 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 938 } 939 940 sc->pcn_cdata.pcn_tx_cnt--; 941 PCN_INC(idx, PCN_TX_LIST_CNT); 942 } 943 944 if (idx != sc->pcn_cdata.pcn_tx_cons) { 945 /* Some buffers have been freed. */ 946 sc->pcn_cdata.pcn_tx_cons = idx; 947 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 948 } 949 sc->pcn_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 950 951 return; 952} 953 954static void 955pcn_tick(xsc) 956 void *xsc; 957{ 958 struct pcn_softc *sc; 959 struct mii_data *mii; 960 struct ifnet *ifp; 961 962 sc = xsc; 963 ifp = sc->pcn_ifp; 964 PCN_LOCK_ASSERT(sc); 965 966 mii = device_get_softc(sc->pcn_miibus); 967 mii_tick(mii); 968 969 /* link just died */ 970 if (sc->pcn_link && !(mii->mii_media_status & IFM_ACTIVE)) 971 sc->pcn_link = 0; 972 973 /* link just came up, restart */ 974 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE && 975 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 976 sc->pcn_link++; 977 if (ifp->if_snd.ifq_head != NULL) 978 pcn_start_locked(ifp); 979 } 980 981 if (sc->pcn_timer > 0 && --sc->pcn_timer == 0) 982 pcn_watchdog(sc); 983 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc); 984 985 return; 986} 987 988static void 989pcn_intr(arg) 990 void *arg; 991{ 992 struct pcn_softc *sc; 993 struct ifnet *ifp; 994 u_int32_t status; 995 996 sc = arg; 997 ifp = sc->pcn_ifp; 998 999 PCN_LOCK(sc); 1000 1001 /* Suppress unwanted interrupts */ 1002 if (!(ifp->if_flags & IFF_UP)) { 1003 pcn_stop(sc); 1004 PCN_UNLOCK(sc); 1005 return; 1006 } 1007 1008 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 1009 1010 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 1011 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 1012 1013 if (status & PCN_CSR_RINT) 1014 pcn_rxeof(sc); 1015 1016 if (status & PCN_CSR_TINT) 1017 pcn_txeof(sc); 1018 1019 if (status & PCN_CSR_ERR) { 1020 pcn_init_locked(sc); 1021 break; 1022 } 1023 } 1024 1025 if (ifp->if_snd.ifq_head != NULL) 1026 pcn_start_locked(ifp); 1027 1028 PCN_UNLOCK(sc); 1029 return; 1030} 1031 1032/* 1033 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1034 * pointers to the fragment pointers. 1035 */ 1036static int 1037pcn_encap(sc, m_head, txidx) 1038 struct pcn_softc *sc; 1039 struct mbuf *m_head; 1040 u_int32_t *txidx; 1041{ 1042 struct pcn_tx_desc *f = NULL; 1043 struct mbuf *m; 1044 int frag, cur, cnt = 0; 1045 1046 /* 1047 * Start packing the mbufs in this chain into 1048 * the fragment pointers. Stop when we run out 1049 * of fragments or hit the end of the mbuf chain. 1050 */ 1051 m = m_head; 1052 cur = frag = *txidx; 1053 1054 for (m = m_head; m != NULL; m = m->m_next) { 1055 if (m->m_len == 0) 1056 continue; 1057 1058 if ((PCN_TX_LIST_CNT - (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 1059 return(ENOBUFS); 1060 f = &sc->pcn_ldata->pcn_tx_list[frag]; 1061 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 1062 f->pcn_txctl |= PCN_TXCTL_MBO; 1063 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 1064 if (cnt == 0) 1065 f->pcn_txctl |= PCN_TXCTL_STP; 1066 else 1067 f->pcn_txctl |= PCN_TXCTL_OWN; 1068 cur = frag; 1069 PCN_INC(frag, PCN_TX_LIST_CNT); 1070 cnt++; 1071 } 1072 1073 if (m != NULL) 1074 return(ENOBUFS); 1075 1076 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1077 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1078 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1079 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1080 sc->pcn_cdata.pcn_tx_cnt += cnt; 1081 *txidx = frag; 1082 1083 return(0); 1084} 1085 1086/* 1087 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1088 * to the mbuf data regions directly in the transmit lists. We also save a 1089 * copy of the pointers since the transmit list fragment pointers are 1090 * physical addresses. 1091 */ 1092static void 1093pcn_start(ifp) 1094 struct ifnet *ifp; 1095{ 1096 struct pcn_softc *sc; 1097 1098 sc = ifp->if_softc; 1099 PCN_LOCK(sc); 1100 pcn_start_locked(ifp); 1101 PCN_UNLOCK(sc); 1102} 1103 1104static void 1105pcn_start_locked(ifp) 1106 struct ifnet *ifp; 1107{ 1108 struct pcn_softc *sc; 1109 struct mbuf *m_head = NULL; 1110 u_int32_t idx; 1111 1112 sc = ifp->if_softc; 1113 1114 PCN_LOCK_ASSERT(sc); 1115 1116 if (!sc->pcn_link) 1117 return; 1118 1119 idx = sc->pcn_cdata.pcn_tx_prod; 1120 1121 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1122 return; 1123 1124 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1125 IF_DEQUEUE(&ifp->if_snd, m_head); 1126 if (m_head == NULL) 1127 break; 1128 1129 if (pcn_encap(sc, m_head, &idx)) { 1130 IF_PREPEND(&ifp->if_snd, m_head); 1131 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1132 break; 1133 } 1134 1135 /* 1136 * If there's a BPF listener, bounce a copy of this frame 1137 * to him. 1138 */ 1139 BPF_MTAP(ifp, m_head); 1140 1141 } 1142 1143 /* Transmit */ 1144 sc->pcn_cdata.pcn_tx_prod = idx; 1145 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1146 1147 /* 1148 * Set a timeout in case the chip goes out to lunch. 1149 */ 1150 sc->pcn_timer = 5; 1151 1152 return; 1153} 1154 1155static void 1156pcn_setfilt(ifp) 1157 struct ifnet *ifp; 1158{ 1159 struct pcn_softc *sc; 1160 1161 sc = ifp->if_softc; 1162 1163 /* If we want promiscuous mode, set the allframes bit. */ 1164 if (ifp->if_flags & IFF_PROMISC) { 1165 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1166 } else { 1167 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1168 } 1169 1170 /* Set the capture broadcast bit to capture broadcast frames. */ 1171 if (ifp->if_flags & IFF_BROADCAST) { 1172 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1173 } else { 1174 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1175 } 1176 1177 return; 1178} 1179 1180static void 1181pcn_init(xsc) 1182 void *xsc; 1183{ 1184 struct pcn_softc *sc = xsc; 1185 1186 PCN_LOCK(sc); 1187 pcn_init_locked(sc); 1188 PCN_UNLOCK(sc); 1189} 1190 1191static void 1192pcn_init_locked(sc) 1193 struct pcn_softc *sc; 1194{ 1195 struct ifnet *ifp = sc->pcn_ifp; 1196 struct mii_data *mii = NULL; 1197 struct ifmedia_entry *ife; 1198 1199 PCN_LOCK_ASSERT(sc); 1200 1201 /* 1202 * Cancel pending I/O and free all RX/TX buffers. 1203 */ 1204 pcn_stop(sc); 1205 pcn_reset(sc); 1206 1207 mii = device_get_softc(sc->pcn_miibus); 1208 ife = mii->mii_media.ifm_cur; 1209 1210 /* Set MAC address */ 1211 pcn_csr_write(sc, PCN_CSR_PAR0, 1212 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[0]); 1213 pcn_csr_write(sc, PCN_CSR_PAR1, 1214 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[1]); 1215 pcn_csr_write(sc, PCN_CSR_PAR2, 1216 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[2]); 1217 1218 /* Init circular RX list. */ 1219 if (pcn_list_rx_init(sc) == ENOBUFS) { 1220 if_printf(ifp, "initialization failed: no " 1221 "memory for rx buffers\n"); 1222 pcn_stop(sc); 1223 return; 1224 } 1225 1226 /* 1227 * Init tx descriptors. 1228 */ 1229 pcn_list_tx_init(sc); 1230 1231 /* Clear PCN_MISC_ASEL so we can set the port via PCN_CSR_MODE. */ 1232 PCN_BCR_CLRBIT(sc, PCN_BCR_MISCCFG, PCN_MISC_ASEL); 1233 1234 /* 1235 * Set up the port based on the currently selected media. 1236 * For Am79C978 we've to unconditionally set PCN_PORT_MII and 1237 * set the PHY in PCN_BCR_PHYSEL instead. 1238 */ 1239 if (sc->pcn_type != Am79C978 && 1240 IFM_INST(ife->ifm_media) == sc->pcn_inst_10bt) 1241 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_10BASET); 1242 else 1243 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1244 1245 /* Set up RX filter. */ 1246 pcn_setfilt(ifp); 1247 1248 /* 1249 * Load the multicast filter. 1250 */ 1251 pcn_setmulti(sc); 1252 1253 /* 1254 * Load the addresses of the RX and TX lists. 1255 */ 1256 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1257 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1258 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1259 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1260 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1261 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1262 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1263 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1264 1265 /* Set the RX and TX ring sizes. */ 1266 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1267 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1268 1269 /* We're not using the initialization block. */ 1270 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1271 1272 /* Enable fast suspend mode. */ 1273 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1274 1275 /* 1276 * Enable burst read and write. Also set the no underflow 1277 * bit. This will avoid transmit underruns in certain 1278 * conditions while still providing decent performance. 1279 */ 1280 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1281 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1282 1283 /* Enable graceful recovery from underflow. */ 1284 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1285 1286 /* Enable auto-padding of short TX frames. */ 1287 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1288 1289 /* Disable MII autoneg (we handle this ourselves). */ 1290 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1291 1292 if (sc->pcn_type == Am79C978) 1293 /* XXX support other PHYs? */ 1294 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1295 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1296 1297 /* Enable interrupts and start the controller running. */ 1298 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1299 1300 mii_mediachg(mii); 1301 1302 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1303 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1304 1305 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc); 1306 1307 return; 1308} 1309 1310/* 1311 * Set media options. 1312 */ 1313static int 1314pcn_ifmedia_upd(ifp) 1315 struct ifnet *ifp; 1316{ 1317 struct pcn_softc *sc; 1318 1319 sc = ifp->if_softc; 1320 1321 PCN_LOCK(sc); 1322 1323 /* 1324 * At least Am79C971 with DP83840A can wedge when switching 1325 * from the internal 10baseT PHY to the external PHY without 1326 * issuing pcn_reset(). For setting the port in PCN_CSR_MODE 1327 * the PCnet chip has to be powered down or stopped anyway 1328 * and although documented otherwise it doesn't take effect 1329 * until the next initialization. 1330 */ 1331 sc->pcn_link = 0; 1332 pcn_stop(sc); 1333 pcn_reset(sc); 1334 pcn_init_locked(sc); 1335 if (ifp->if_snd.ifq_head != NULL) 1336 pcn_start_locked(ifp); 1337 1338 PCN_UNLOCK(sc); 1339 1340 return(0); 1341} 1342 1343/* 1344 * Report current media status. 1345 */ 1346static void 1347pcn_ifmedia_sts(ifp, ifmr) 1348 struct ifnet *ifp; 1349 struct ifmediareq *ifmr; 1350{ 1351 struct pcn_softc *sc; 1352 struct mii_data *mii; 1353 1354 sc = ifp->if_softc; 1355 1356 mii = device_get_softc(sc->pcn_miibus); 1357 PCN_LOCK(sc); 1358 mii_pollstat(mii); 1359 ifmr->ifm_active = mii->mii_media_active; 1360 ifmr->ifm_status = mii->mii_media_status; 1361 PCN_UNLOCK(sc); 1362 1363 return; 1364} 1365 1366static int 1367pcn_ioctl(ifp, command, data) 1368 struct ifnet *ifp; 1369 u_long command; 1370 caddr_t data; 1371{ 1372 struct pcn_softc *sc = ifp->if_softc; 1373 struct ifreq *ifr = (struct ifreq *) data; 1374 struct mii_data *mii = NULL; 1375 int error = 0; 1376 1377 switch(command) { 1378 case SIOCSIFFLAGS: 1379 PCN_LOCK(sc); 1380 if (ifp->if_flags & IFF_UP) { 1381 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1382 ifp->if_flags & IFF_PROMISC && 1383 !(sc->pcn_if_flags & IFF_PROMISC)) { 1384 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1385 PCN_EXTCTL1_SPND); 1386 pcn_setfilt(ifp); 1387 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1388 PCN_EXTCTL1_SPND); 1389 pcn_csr_write(sc, PCN_CSR_CSR, 1390 PCN_CSR_INTEN|PCN_CSR_START); 1391 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1392 !(ifp->if_flags & IFF_PROMISC) && 1393 sc->pcn_if_flags & IFF_PROMISC) { 1394 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1395 PCN_EXTCTL1_SPND); 1396 pcn_setfilt(ifp); 1397 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1398 PCN_EXTCTL1_SPND); 1399 pcn_csr_write(sc, PCN_CSR_CSR, 1400 PCN_CSR_INTEN|PCN_CSR_START); 1401 } else if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1402 pcn_init_locked(sc); 1403 } else { 1404 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1405 pcn_stop(sc); 1406 } 1407 sc->pcn_if_flags = ifp->if_flags; 1408 PCN_UNLOCK(sc); 1409 error = 0; 1410 break; 1411 case SIOCADDMULTI: 1412 case SIOCDELMULTI: 1413 PCN_LOCK(sc); 1414 pcn_setmulti(sc); 1415 PCN_UNLOCK(sc); 1416 error = 0; 1417 break; 1418 case SIOCGIFMEDIA: 1419 case SIOCSIFMEDIA: 1420 mii = device_get_softc(sc->pcn_miibus); 1421 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1422 break; 1423 default: 1424 error = ether_ioctl(ifp, command, data); 1425 break; 1426 } 1427 1428 return(error); 1429} 1430 1431static void 1432pcn_watchdog(struct pcn_softc *sc) 1433{ 1434 struct ifnet *ifp; 1435 1436 PCN_LOCK_ASSERT(sc); 1437 ifp = sc->pcn_ifp; 1438 1439 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1440 if_printf(ifp, "watchdog timeout\n"); 1441 1442 pcn_stop(sc); 1443 pcn_reset(sc); 1444 pcn_init_locked(sc); 1445 1446 if (ifp->if_snd.ifq_head != NULL) 1447 pcn_start_locked(ifp); 1448} 1449 1450/* 1451 * Stop the adapter and free any mbufs allocated to the 1452 * RX and TX lists. 1453 */ 1454static void 1455pcn_stop(struct pcn_softc *sc) 1456{ 1457 register int i; 1458 struct ifnet *ifp; 1459 1460 PCN_LOCK_ASSERT(sc); 1461 ifp = sc->pcn_ifp; 1462 sc->pcn_timer = 0; 1463 1464 callout_stop(&sc->pcn_stat_callout); 1465 1466 /* Turn off interrupts */ 1467 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN); 1468 /* Stop adapter */ 1469 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1470 sc->pcn_link = 0; 1471 1472 /* 1473 * Free data in the RX lists. 1474 */ 1475 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1476 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1477 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1478 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1479 } 1480 } 1481 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1482 sizeof(sc->pcn_ldata->pcn_rx_list)); 1483 1484 /* 1485 * Free the TX list buffers. 1486 */ 1487 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1488 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1489 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1490 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1491 } 1492 } 1493 1494 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1495 sizeof(sc->pcn_ldata->pcn_tx_list)); 1496 1497 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1498 1499 return; 1500} 1501 1502/* 1503 * Stop all chip I/O so that the kernel's probe routines don't 1504 * get confused by errant DMAs when rebooting. 1505 */ 1506static int 1507pcn_shutdown(device_t dev) 1508{ 1509 struct pcn_softc *sc; 1510 1511 sc = device_get_softc(dev); 1512 1513 PCN_LOCK(sc); 1514 pcn_reset(sc); 1515 pcn_stop(sc); 1516 PCN_UNLOCK(sc); 1517 1518 return 0; 1519} 1520