if_pcn.c revision 131253
1/* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/pci/if_pcn.c 131253 2004-06-28 20:07:03Z imp $"); 36 37/* 38 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 39 * from http://www.amd.com. 40 * 41 * The AMD PCnet/PCI controllers are more advanced and functional 42 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 43 * backwards compatibility with the LANCE and thus can be made 44 * to work with older LANCE drivers. This is in fact how the 45 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 46 * is that the PCnet/PCI devices offer several performance enhancements 47 * which can't be exploited in LANCE compatibility mode. Chief among 48 * these enhancements is the ability to perform PCI DMA operations 49 * using 32-bit addressing (which eliminates the need for ISA 50 * bounce-buffering), and special receive buffer alignment (which 51 * allows the receive handler to pass packets to the upper protocol 52 * layers without copying on both the x86 and alpha platforms). 53 */ 54 55#include <sys/param.h> 56#include <sys/systm.h> 57#include <sys/sockio.h> 58#include <sys/mbuf.h> 59#include <sys/malloc.h> 60#include <sys/kernel.h> 61#include <sys/module.h> 62#include <sys/socket.h> 63 64#include <net/if.h> 65#include <net/if_arp.h> 66#include <net/ethernet.h> 67#include <net/if_dl.h> 68#include <net/if_media.h> 69 70#include <net/bpf.h> 71 72#include <vm/vm.h> /* for vtophys */ 73#include <vm/pmap.h> /* for vtophys */ 74#include <machine/bus_pio.h> 75#include <machine/bus_memio.h> 76#include <machine/bus.h> 77#include <machine/resource.h> 78#include <sys/bus.h> 79#include <sys/rman.h> 80 81#include <dev/mii/mii.h> 82#include <dev/mii/miivar.h> 83 84#include <dev/pci/pcireg.h> 85#include <dev/pci/pcivar.h> 86 87#define PCN_USEIOSPACE 88 89#include <pci/if_pcnreg.h> 90 91MODULE_DEPEND(pcn, pci, 1, 1, 1); 92MODULE_DEPEND(pcn, ether, 1, 1, 1); 93MODULE_DEPEND(pcn, miibus, 1, 1, 1); 94 95/* "controller miibus0" required. See GENERIC if you get errors here. */ 96#include "miibus_if.h" 97 98/* 99 * Various supported device vendors/types and their names. 100 */ 101static struct pcn_type pcn_devs[] = { 102 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 103 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 104 { 0, 0, NULL } 105}; 106 107static u_int32_t pcn_csr_read (struct pcn_softc *, int); 108static u_int16_t pcn_csr_read16 (struct pcn_softc *, int); 109static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int); 110static void pcn_csr_write (struct pcn_softc *, int, int); 111static u_int32_t pcn_bcr_read (struct pcn_softc *, int); 112static void pcn_bcr_write (struct pcn_softc *, int, int); 113 114static int pcn_probe (device_t); 115static int pcn_attach (device_t); 116static int pcn_detach (device_t); 117 118static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *); 119static int pcn_encap (struct pcn_softc *, 120 struct mbuf *, u_int32_t *); 121static void pcn_rxeof (struct pcn_softc *); 122static void pcn_txeof (struct pcn_softc *); 123static void pcn_intr (void *); 124static void pcn_tick (void *); 125static void pcn_start (struct ifnet *); 126static int pcn_ioctl (struct ifnet *, u_long, caddr_t); 127static void pcn_init (void *); 128static void pcn_stop (struct pcn_softc *); 129static void pcn_watchdog (struct ifnet *); 130static void pcn_shutdown (device_t); 131static int pcn_ifmedia_upd (struct ifnet *); 132static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *); 133 134static int pcn_miibus_readreg (device_t, int, int); 135static int pcn_miibus_writereg (device_t, int, int, int); 136static void pcn_miibus_statchg (device_t); 137 138static void pcn_setfilt (struct ifnet *); 139static void pcn_setmulti (struct pcn_softc *); 140static void pcn_reset (struct pcn_softc *); 141static int pcn_list_rx_init (struct pcn_softc *); 142static int pcn_list_tx_init (struct pcn_softc *); 143 144#ifdef PCN_USEIOSPACE 145#define PCN_RES SYS_RES_IOPORT 146#define PCN_RID PCN_PCI_LOIO 147#else 148#define PCN_RES SYS_RES_MEMORY 149#define PCN_RID PCN_PCI_LOMEM 150#endif 151 152static device_method_t pcn_methods[] = { 153 /* Device interface */ 154 DEVMETHOD(device_probe, pcn_probe), 155 DEVMETHOD(device_attach, pcn_attach), 156 DEVMETHOD(device_detach, pcn_detach), 157 DEVMETHOD(device_shutdown, pcn_shutdown), 158 159 /* bus interface */ 160 DEVMETHOD(bus_print_child, bus_generic_print_child), 161 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 162 163 /* MII interface */ 164 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 165 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 166 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 167 168 { 0, 0 } 169}; 170 171static driver_t pcn_driver = { 172 "pcn", 173 pcn_methods, 174 sizeof(struct pcn_softc) 175}; 176 177static devclass_t pcn_devclass; 178 179DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0); 180DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 181 182#define PCN_CSR_SETBIT(sc, reg, x) \ 183 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 184 185#define PCN_CSR_CLRBIT(sc, reg, x) \ 186 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 187 188#define PCN_BCR_SETBIT(sc, reg, x) \ 189 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 190 191#define PCN_BCR_CLRBIT(sc, reg, x) \ 192 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 193 194static u_int32_t 195pcn_csr_read(sc, reg) 196 struct pcn_softc *sc; 197 int reg; 198{ 199 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 200 return(CSR_READ_4(sc, PCN_IO32_RDP)); 201} 202 203static u_int16_t 204pcn_csr_read16(sc, reg) 205 struct pcn_softc *sc; 206 int reg; 207{ 208 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 209 return(CSR_READ_2(sc, PCN_IO16_RDP)); 210} 211 212static void 213pcn_csr_write(sc, reg, val) 214 struct pcn_softc *sc; 215 int reg; 216 int val; 217{ 218 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 219 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 220 return; 221} 222 223static u_int32_t 224pcn_bcr_read(sc, reg) 225 struct pcn_softc *sc; 226 int reg; 227{ 228 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 229 return(CSR_READ_4(sc, PCN_IO32_BDP)); 230} 231 232static u_int16_t 233pcn_bcr_read16(sc, reg) 234 struct pcn_softc *sc; 235 int reg; 236{ 237 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 238 return(CSR_READ_2(sc, PCN_IO16_BDP)); 239} 240 241static void 242pcn_bcr_write(sc, reg, val) 243 struct pcn_softc *sc; 244 int reg; 245 int val; 246{ 247 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 248 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 249 return; 250} 251 252static int 253pcn_miibus_readreg(dev, phy, reg) 254 device_t dev; 255 int phy, reg; 256{ 257 struct pcn_softc *sc; 258 int val; 259 260 sc = device_get_softc(dev); 261 262 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 263 return(0); 264 265 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 266 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 267 if (val == 0xFFFF) 268 return(0); 269 270 sc->pcn_phyaddr = phy; 271 272 return(val); 273} 274 275static int 276pcn_miibus_writereg(dev, phy, reg, data) 277 device_t dev; 278 int phy, reg, data; 279{ 280 struct pcn_softc *sc; 281 282 sc = device_get_softc(dev); 283 284 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 285 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 286 287 return(0); 288} 289 290static void 291pcn_miibus_statchg(dev) 292 device_t dev; 293{ 294 struct pcn_softc *sc; 295 struct mii_data *mii; 296 297 sc = device_get_softc(dev); 298 mii = device_get_softc(sc->pcn_miibus); 299 300 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 301 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 302 } else { 303 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 304 } 305 306 return; 307} 308 309static void 310pcn_setmulti(sc) 311 struct pcn_softc *sc; 312{ 313 struct ifnet *ifp; 314 struct ifmultiaddr *ifma; 315 u_int32_t h, i; 316 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 317 318 ifp = &sc->arpcom.ac_if; 319 320 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 321 322 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 323 for (i = 0; i < 4; i++) 324 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 325 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 326 return; 327 } 328 329 /* first, zot all the existing hash bits */ 330 for (i = 0; i < 4; i++) 331 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 332 333 /* now program new ones */ 334 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 335 if (ifma->ifma_addr->sa_family != AF_LINK) 336 continue; 337 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 338 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 339 hashes[h >> 4] |= 1 << (h & 0xF); 340 } 341 342 for (i = 0; i < 4; i++) 343 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 344 345 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 346 347 return; 348} 349 350static void 351pcn_reset(sc) 352 struct pcn_softc *sc; 353{ 354 /* 355 * Issue a reset by reading from the RESET register. 356 * Note that we don't know if the chip is operating in 357 * 16-bit or 32-bit mode at this point, so we attempt 358 * to reset the chip both ways. If one fails, the other 359 * will succeed. 360 */ 361 CSR_READ_2(sc, PCN_IO16_RESET); 362 CSR_READ_4(sc, PCN_IO32_RESET); 363 364 /* Wait a little while for the chip to get its brains in order. */ 365 DELAY(1000); 366 367 /* Select 32-bit (DWIO) mode */ 368 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 369 370 /* Select software style 3. */ 371 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 372 373 return; 374} 375 376/* 377 * Probe for an AMD chip. Check the PCI vendor and device 378 * IDs against our list and return a device name if we find a match. 379 */ 380static int 381pcn_probe(dev) 382 device_t dev; 383{ 384 struct pcn_type *t; 385 struct pcn_softc *sc; 386 int rid; 387 u_int32_t chip_id; 388 389 t = pcn_devs; 390 sc = device_get_softc(dev); 391 392 while(t->pcn_name != NULL) { 393 if ((pci_get_vendor(dev) == t->pcn_vid) && 394 (pci_get_device(dev) == t->pcn_did)) { 395 /* 396 * Temporarily map the I/O space 397 * so we can read the chip ID register. 398 */ 399 rid = PCN_RID; 400 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, 401 RF_ACTIVE); 402 if (sc->pcn_res == NULL) { 403 device_printf(dev, 404 "couldn't map ports/memory\n"); 405 return(ENXIO); 406 } 407 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 408 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 409 mtx_init(&sc->pcn_mtx, 410 device_get_nameunit(dev), MTX_NETWORK_LOCK, 411 MTX_DEF); 412 PCN_LOCK(sc); 413 /* 414 * Note: we can *NOT* put the chip into 415 * 32-bit mode yet. The lnc driver will only 416 * work in 16-bit mode, and once the chip 417 * goes into 32-bit mode, the only way to 418 * get it out again is with a hardware reset. 419 * So if pcn_probe() is called before the 420 * lnc driver's probe routine, the chip will 421 * be locked into 32-bit operation and the lnc 422 * driver will be unable to attach to it. 423 * Note II: if the chip happens to already 424 * be in 32-bit mode, we still need to check 425 * the chip ID, but first we have to detect 426 * 32-bit mode using only 16-bit operations. 427 * The safest way to do this is to read the 428 * PCI subsystem ID from BCR23/24 and compare 429 * that with the value read from PCI config 430 * space. 431 */ 432 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 433 chip_id <<= 16; 434 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 435 /* 436 * Note III: the test for 0x10001000 is a hack to 437 * pacify VMware, who's pseudo-PCnet interface is 438 * broken. Reading the subsystem register from PCI 439 * config space yeilds 0x00000000 while reading the 440 * same value from I/O space yeilds 0x10001000. It's 441 * not supposed to be that way. 442 */ 443 if (chip_id == pci_read_config(dev, 444 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 445 /* We're in 16-bit mode. */ 446 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 447 chip_id <<= 16; 448 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 449 } else { 450 /* We're in 32-bit mode. */ 451 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 452 chip_id <<= 16; 453 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 454 } 455 bus_release_resource(dev, PCN_RES, 456 PCN_RID, sc->pcn_res); 457 PCN_UNLOCK(sc); 458 mtx_destroy(&sc->pcn_mtx); 459 chip_id >>= 12; 460 sc->pcn_type = chip_id & PART_MASK; 461 switch(sc->pcn_type) { 462 case Am79C971: 463 case Am79C972: 464 case Am79C973: 465 case Am79C975: 466 case Am79C976: 467 case Am79C978: 468 break; 469 default: 470 return(ENXIO); 471 } 472 device_set_desc(dev, t->pcn_name); 473 return(0); 474 } 475 t++; 476 } 477 478 return(ENXIO); 479} 480 481/* 482 * Attach the interface. Allocate softc structures, do ifmedia 483 * setup and ethernet/BPF attach. 484 */ 485static int 486pcn_attach(dev) 487 device_t dev; 488{ 489 u_int32_t eaddr[2]; 490 struct pcn_softc *sc; 491 struct ifnet *ifp; 492 int unit, error = 0, rid; 493 494 sc = device_get_softc(dev); 495 unit = device_get_unit(dev); 496 497 /* Initialize our mutex. */ 498 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 499 MTX_DEF | MTX_RECURSE); 500 /* 501 * Map control/status registers. 502 */ 503 pci_enable_busmaster(dev); 504 505 rid = PCN_RID; 506 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE); 507 508 if (sc->pcn_res == NULL) { 509 printf("pcn%d: couldn't map ports/memory\n", unit); 510 error = ENXIO; 511 goto fail; 512 } 513 514 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 515 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 516 517 /* Allocate interrupt */ 518 rid = 0; 519 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 520 RF_SHAREABLE | RF_ACTIVE); 521 522 if (sc->pcn_irq == NULL) { 523 printf("pcn%d: couldn't map interrupt\n", unit); 524 error = ENXIO; 525 goto fail; 526 } 527 528 /* Reset the adapter. */ 529 pcn_reset(sc); 530 531 /* 532 * Get station address from the EEPROM. 533 */ 534 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 535 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 536 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 537 538 sc->pcn_unit = unit; 539 callout_handle_init(&sc->pcn_stat_ch); 540 541 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 542 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 543 544 if (sc->pcn_ldata == NULL) { 545 printf("pcn%d: no memory for list buffers!\n", unit); 546 error = ENXIO; 547 goto fail; 548 } 549 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 550 551 ifp = &sc->arpcom.ac_if; 552 ifp->if_softc = sc; 553 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 554 ifp->if_mtu = ETHERMTU; 555 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 556 ifp->if_ioctl = pcn_ioctl; 557 ifp->if_start = pcn_start; 558 ifp->if_watchdog = pcn_watchdog; 559 ifp->if_init = pcn_init; 560 ifp->if_baudrate = 10000000; 561 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 562 563 /* 564 * Do MII setup. 565 */ 566 if (mii_phy_probe(dev, &sc->pcn_miibus, 567 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 568 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 569 error = ENXIO; 570 goto fail; 571 } 572 573 /* 574 * Call MI attach routine. 575 */ 576 ether_ifattach(ifp, (u_int8_t *) eaddr); 577 578 /* Hook interrupt last to avoid having to lock softc */ 579 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 580 pcn_intr, sc, &sc->pcn_intrhand); 581 582 if (error) { 583 printf("pcn%d: couldn't set up irq\n", unit); 584 ether_ifdetach(ifp); 585 goto fail; 586 } 587 588fail: 589 if (error) 590 pcn_detach(dev); 591 592 return(error); 593} 594 595/* 596 * Shutdown hardware and free up resources. This can be called any 597 * time after the mutex has been initialized. It is called in both 598 * the error case in attach and the normal detach case so it needs 599 * to be careful about only freeing resources that have actually been 600 * allocated. 601 */ 602static int 603pcn_detach(dev) 604 device_t dev; 605{ 606 struct pcn_softc *sc; 607 struct ifnet *ifp; 608 609 sc = device_get_softc(dev); 610 ifp = &sc->arpcom.ac_if; 611 612 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized")); 613 PCN_LOCK(sc); 614 615 /* These should only be active if attach succeeded */ 616 if (device_is_attached(dev)) { 617 pcn_reset(sc); 618 pcn_stop(sc); 619 ether_ifdetach(ifp); 620 } 621 if (sc->pcn_miibus) 622 device_delete_child(dev, sc->pcn_miibus); 623 bus_generic_detach(dev); 624 625 if (sc->pcn_intrhand) 626 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 627 if (sc->pcn_irq) 628 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 629 if (sc->pcn_res) 630 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 631 632 if (sc->pcn_ldata) { 633 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 634 M_DEVBUF); 635 } 636 PCN_UNLOCK(sc); 637 638 mtx_destroy(&sc->pcn_mtx); 639 640 return(0); 641} 642 643/* 644 * Initialize the transmit descriptors. 645 */ 646static int 647pcn_list_tx_init(sc) 648 struct pcn_softc *sc; 649{ 650 struct pcn_list_data *ld; 651 struct pcn_ring_data *cd; 652 int i; 653 654 cd = &sc->pcn_cdata; 655 ld = sc->pcn_ldata; 656 657 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 658 cd->pcn_tx_chain[i] = NULL; 659 ld->pcn_tx_list[i].pcn_tbaddr = 0; 660 ld->pcn_tx_list[i].pcn_txctl = 0; 661 ld->pcn_tx_list[i].pcn_txstat = 0; 662 } 663 664 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 665 666 return(0); 667} 668 669 670/* 671 * Initialize the RX descriptors and allocate mbufs for them. 672 */ 673static int 674pcn_list_rx_init(sc) 675 struct pcn_softc *sc; 676{ 677 struct pcn_ring_data *cd; 678 int i; 679 680 cd = &sc->pcn_cdata; 681 682 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 683 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 684 return(ENOBUFS); 685 } 686 687 cd->pcn_rx_prod = 0; 688 689 return(0); 690} 691 692/* 693 * Initialize an RX descriptor and attach an MBUF cluster. 694 */ 695static int 696pcn_newbuf(sc, idx, m) 697 struct pcn_softc *sc; 698 int idx; 699 struct mbuf *m; 700{ 701 struct mbuf *m_new = NULL; 702 struct pcn_rx_desc *c; 703 704 c = &sc->pcn_ldata->pcn_rx_list[idx]; 705 706 if (m == NULL) { 707 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 708 if (m_new == NULL) 709 return(ENOBUFS); 710 711 MCLGET(m_new, M_DONTWAIT); 712 if (!(m_new->m_flags & M_EXT)) { 713 m_freem(m_new); 714 return(ENOBUFS); 715 } 716 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 717 } else { 718 m_new = m; 719 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 720 m_new->m_data = m_new->m_ext.ext_buf; 721 } 722 723 m_adj(m_new, ETHER_ALIGN); 724 725 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 726 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 727 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 728 c->pcn_bufsz |= PCN_RXLEN_MBO; 729 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 730 731 return(0); 732} 733 734/* 735 * A frame has been uploaded: pass the resulting mbuf chain up to 736 * the higher level protocols. 737 */ 738static void 739pcn_rxeof(sc) 740 struct pcn_softc *sc; 741{ 742 struct mbuf *m; 743 struct ifnet *ifp; 744 struct pcn_rx_desc *cur_rx; 745 int i; 746 747 PCN_LOCK_ASSERT(sc); 748 749 ifp = &sc->arpcom.ac_if; 750 i = sc->pcn_cdata.pcn_rx_prod; 751 752 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 753 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 754 m = sc->pcn_cdata.pcn_rx_chain[i]; 755 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 756 757 /* 758 * If an error occurs, update stats, clear the 759 * status word and leave the mbuf cluster in place: 760 * it should simply get re-used next time this descriptor 761 * comes up in the ring. 762 */ 763 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 764 ifp->if_ierrors++; 765 pcn_newbuf(sc, i, m); 766 PCN_INC(i, PCN_RX_LIST_CNT); 767 continue; 768 } 769 770 if (pcn_newbuf(sc, i, NULL)) { 771 /* Ran out of mbufs; recycle this one. */ 772 pcn_newbuf(sc, i, m); 773 ifp->if_ierrors++; 774 PCN_INC(i, PCN_RX_LIST_CNT); 775 continue; 776 } 777 778 PCN_INC(i, PCN_RX_LIST_CNT); 779 780 /* No errors; receive the packet. */ 781 ifp->if_ipackets++; 782 m->m_len = m->m_pkthdr.len = 783 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 784 m->m_pkthdr.rcvif = ifp; 785 786 PCN_UNLOCK(sc); 787 (*ifp->if_input)(ifp, m); 788 PCN_LOCK(sc); 789 } 790 791 sc->pcn_cdata.pcn_rx_prod = i; 792 793 return; 794} 795 796/* 797 * A frame was downloaded to the chip. It's safe for us to clean up 798 * the list buffers. 799 */ 800 801static void 802pcn_txeof(sc) 803 struct pcn_softc *sc; 804{ 805 struct pcn_tx_desc *cur_tx = NULL; 806 struct ifnet *ifp; 807 u_int32_t idx; 808 809 ifp = &sc->arpcom.ac_if; 810 811 /* 812 * Go through our tx list and free mbufs for those 813 * frames that have been transmitted. 814 */ 815 idx = sc->pcn_cdata.pcn_tx_cons; 816 while (idx != sc->pcn_cdata.pcn_tx_prod) { 817 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 818 819 if (!PCN_OWN_TXDESC(cur_tx)) 820 break; 821 822 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 823 sc->pcn_cdata.pcn_tx_cnt--; 824 PCN_INC(idx, PCN_TX_LIST_CNT); 825 continue; 826 } 827 828 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 829 ifp->if_oerrors++; 830 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 831 ifp->if_collisions++; 832 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 833 ifp->if_collisions++; 834 } 835 836 ifp->if_collisions += 837 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 838 839 ifp->if_opackets++; 840 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 841 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 842 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 843 } 844 845 sc->pcn_cdata.pcn_tx_cnt--; 846 PCN_INC(idx, PCN_TX_LIST_CNT); 847 } 848 849 if (idx != sc->pcn_cdata.pcn_tx_cons) { 850 /* Some buffers have been freed. */ 851 sc->pcn_cdata.pcn_tx_cons = idx; 852 ifp->if_flags &= ~IFF_OACTIVE; 853 } 854 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 855 856 return; 857} 858 859static void 860pcn_tick(xsc) 861 void *xsc; 862{ 863 struct pcn_softc *sc; 864 struct mii_data *mii; 865 struct ifnet *ifp; 866 867 sc = xsc; 868 ifp = &sc->arpcom.ac_if; 869 PCN_LOCK(sc); 870 871 mii = device_get_softc(sc->pcn_miibus); 872 mii_tick(mii); 873 874 /* link just died */ 875 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 876 sc->pcn_link = 0; 877 878 /* link just came up, restart */ 879 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE && 880 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 881 sc->pcn_link++; 882 if (ifp->if_snd.ifq_head != NULL) 883 pcn_start(ifp); 884 } 885 886 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 887 888 PCN_UNLOCK(sc); 889 890 return; 891} 892 893static void 894pcn_intr(arg) 895 void *arg; 896{ 897 struct pcn_softc *sc; 898 struct ifnet *ifp; 899 u_int32_t status; 900 901 sc = arg; 902 ifp = &sc->arpcom.ac_if; 903 904 /* Supress unwanted interrupts */ 905 if (!(ifp->if_flags & IFF_UP)) { 906 pcn_stop(sc); 907 return; 908 } 909 910 PCN_LOCK(sc); 911 912 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 913 914 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 915 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 916 917 if (status & PCN_CSR_RINT) 918 pcn_rxeof(sc); 919 920 if (status & PCN_CSR_TINT) 921 pcn_txeof(sc); 922 923 if (status & PCN_CSR_ERR) { 924 pcn_init(sc); 925 break; 926 } 927 } 928 929 if (ifp->if_snd.ifq_head != NULL) 930 pcn_start(ifp); 931 932 PCN_UNLOCK(sc); 933 return; 934} 935 936/* 937 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 938 * pointers to the fragment pointers. 939 */ 940static int 941pcn_encap(sc, m_head, txidx) 942 struct pcn_softc *sc; 943 struct mbuf *m_head; 944 u_int32_t *txidx; 945{ 946 struct pcn_tx_desc *f = NULL; 947 struct mbuf *m; 948 int frag, cur, cnt = 0; 949 950 /* 951 * Start packing the mbufs in this chain into 952 * the fragment pointers. Stop when we run out 953 * of fragments or hit the end of the mbuf chain. 954 */ 955 m = m_head; 956 cur = frag = *txidx; 957 958 for (m = m_head; m != NULL; m = m->m_next) { 959 if (m->m_len != 0) { 960 if ((PCN_TX_LIST_CNT - 961 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 962 return(ENOBUFS); 963 f = &sc->pcn_ldata->pcn_tx_list[frag]; 964 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 965 f->pcn_txctl |= PCN_TXCTL_MBO; 966 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 967 if (cnt == 0) 968 f->pcn_txctl |= PCN_TXCTL_STP; 969 else 970 f->pcn_txctl |= PCN_TXCTL_OWN; 971 cur = frag; 972 PCN_INC(frag, PCN_TX_LIST_CNT); 973 cnt++; 974 } 975 } 976 977 if (m != NULL) 978 return(ENOBUFS); 979 980 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 981 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 982 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 983 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 984 sc->pcn_cdata.pcn_tx_cnt += cnt; 985 *txidx = frag; 986 987 return(0); 988} 989 990/* 991 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 992 * to the mbuf data regions directly in the transmit lists. We also save a 993 * copy of the pointers since the transmit list fragment pointers are 994 * physical addresses. 995 */ 996static void 997pcn_start(ifp) 998 struct ifnet *ifp; 999{ 1000 struct pcn_softc *sc; 1001 struct mbuf *m_head = NULL; 1002 u_int32_t idx; 1003 1004 sc = ifp->if_softc; 1005 1006 PCN_LOCK(sc); 1007 1008 if (!sc->pcn_link) { 1009 PCN_UNLOCK(sc); 1010 return; 1011 } 1012 1013 idx = sc->pcn_cdata.pcn_tx_prod; 1014 1015 if (ifp->if_flags & IFF_OACTIVE) { 1016 PCN_UNLOCK(sc); 1017 return; 1018 } 1019 1020 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1021 IF_DEQUEUE(&ifp->if_snd, m_head); 1022 if (m_head == NULL) 1023 break; 1024 1025 if (pcn_encap(sc, m_head, &idx)) { 1026 IF_PREPEND(&ifp->if_snd, m_head); 1027 ifp->if_flags |= IFF_OACTIVE; 1028 break; 1029 } 1030 1031 /* 1032 * If there's a BPF listener, bounce a copy of this frame 1033 * to him. 1034 */ 1035 BPF_MTAP(ifp, m_head); 1036 1037 } 1038 1039 /* Transmit */ 1040 sc->pcn_cdata.pcn_tx_prod = idx; 1041 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1042 1043 /* 1044 * Set a timeout in case the chip goes out to lunch. 1045 */ 1046 ifp->if_timer = 5; 1047 1048 PCN_UNLOCK(sc); 1049 1050 return; 1051} 1052 1053static void 1054pcn_setfilt(ifp) 1055 struct ifnet *ifp; 1056{ 1057 struct pcn_softc *sc; 1058 1059 sc = ifp->if_softc; 1060 1061 /* If we want promiscuous mode, set the allframes bit. */ 1062 if (ifp->if_flags & IFF_PROMISC) { 1063 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1064 } else { 1065 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1066 } 1067 1068 /* Set the capture broadcast bit to capture broadcast frames. */ 1069 if (ifp->if_flags & IFF_BROADCAST) { 1070 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1071 } else { 1072 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1073 } 1074 1075 return; 1076} 1077 1078static void 1079pcn_init(xsc) 1080 void *xsc; 1081{ 1082 struct pcn_softc *sc = xsc; 1083 struct ifnet *ifp = &sc->arpcom.ac_if; 1084 struct mii_data *mii = NULL; 1085 1086 PCN_LOCK(sc); 1087 1088 /* 1089 * Cancel pending I/O and free all RX/TX buffers. 1090 */ 1091 pcn_stop(sc); 1092 pcn_reset(sc); 1093 1094 mii = device_get_softc(sc->pcn_miibus); 1095 1096 /* Set MAC address */ 1097 pcn_csr_write(sc, PCN_CSR_PAR0, 1098 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1099 pcn_csr_write(sc, PCN_CSR_PAR1, 1100 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1101 pcn_csr_write(sc, PCN_CSR_PAR2, 1102 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1103 1104 /* Init circular RX list. */ 1105 if (pcn_list_rx_init(sc) == ENOBUFS) { 1106 printf("pcn%d: initialization failed: no " 1107 "memory for rx buffers\n", sc->pcn_unit); 1108 pcn_stop(sc); 1109 PCN_UNLOCK(sc); 1110 return; 1111 } 1112 1113 /* 1114 * Init tx descriptors. 1115 */ 1116 pcn_list_tx_init(sc); 1117 1118 /* Set up the mode register. */ 1119 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1120 1121 /* Set up RX filter. */ 1122 pcn_setfilt(ifp); 1123 1124 /* 1125 * Load the multicast filter. 1126 */ 1127 pcn_setmulti(sc); 1128 1129 /* 1130 * Load the addresses of the RX and TX lists. 1131 */ 1132 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1133 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1134 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1135 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1136 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1137 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1138 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1139 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1140 1141 /* Set the RX and TX ring sizes. */ 1142 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1143 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1144 1145 /* We're not using the initialization block. */ 1146 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1147 1148 /* Enable fast suspend mode. */ 1149 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1150 1151 /* 1152 * Enable burst read and write. Also set the no underflow 1153 * bit. This will avoid transmit underruns in certain 1154 * conditions while still providing decent performance. 1155 */ 1156 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1157 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1158 1159 /* Enable graceful recovery from underflow. */ 1160 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1161 1162 /* Enable auto-padding of short TX frames. */ 1163 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1164 1165 /* Disable MII autoneg (we handle this ourselves). */ 1166 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1167 1168 if (sc->pcn_type == Am79C978) 1169 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1170 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1171 1172 /* Enable interrupts and start the controller running. */ 1173 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1174 1175 mii_mediachg(mii); 1176 1177 ifp->if_flags |= IFF_RUNNING; 1178 ifp->if_flags &= ~IFF_OACTIVE; 1179 1180 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 1181 PCN_UNLOCK(sc); 1182 1183 return; 1184} 1185 1186/* 1187 * Set media options. 1188 */ 1189static int 1190pcn_ifmedia_upd(ifp) 1191 struct ifnet *ifp; 1192{ 1193 struct pcn_softc *sc; 1194 struct mii_data *mii; 1195 1196 sc = ifp->if_softc; 1197 mii = device_get_softc(sc->pcn_miibus); 1198 1199 sc->pcn_link = 0; 1200 if (mii->mii_instance) { 1201 struct mii_softc *miisc; 1202 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1203 mii_phy_reset(miisc); 1204 } 1205 mii_mediachg(mii); 1206 1207 return(0); 1208} 1209 1210/* 1211 * Report current media status. 1212 */ 1213static void 1214pcn_ifmedia_sts(ifp, ifmr) 1215 struct ifnet *ifp; 1216 struct ifmediareq *ifmr; 1217{ 1218 struct pcn_softc *sc; 1219 struct mii_data *mii; 1220 1221 sc = ifp->if_softc; 1222 1223 mii = device_get_softc(sc->pcn_miibus); 1224 mii_pollstat(mii); 1225 ifmr->ifm_active = mii->mii_media_active; 1226 ifmr->ifm_status = mii->mii_media_status; 1227 1228 return; 1229} 1230 1231static int 1232pcn_ioctl(ifp, command, data) 1233 struct ifnet *ifp; 1234 u_long command; 1235 caddr_t data; 1236{ 1237 struct pcn_softc *sc = ifp->if_softc; 1238 struct ifreq *ifr = (struct ifreq *) data; 1239 struct mii_data *mii = NULL; 1240 int error = 0; 1241 1242 PCN_LOCK(sc); 1243 1244 switch(command) { 1245 case SIOCSIFFLAGS: 1246 if (ifp->if_flags & IFF_UP) { 1247 if (ifp->if_flags & IFF_RUNNING && 1248 ifp->if_flags & IFF_PROMISC && 1249 !(sc->pcn_if_flags & IFF_PROMISC)) { 1250 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1251 PCN_EXTCTL1_SPND); 1252 pcn_setfilt(ifp); 1253 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1254 PCN_EXTCTL1_SPND); 1255 pcn_csr_write(sc, PCN_CSR_CSR, 1256 PCN_CSR_INTEN|PCN_CSR_START); 1257 } else if (ifp->if_flags & IFF_RUNNING && 1258 !(ifp->if_flags & IFF_PROMISC) && 1259 sc->pcn_if_flags & IFF_PROMISC) { 1260 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1261 PCN_EXTCTL1_SPND); 1262 pcn_setfilt(ifp); 1263 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1264 PCN_EXTCTL1_SPND); 1265 pcn_csr_write(sc, PCN_CSR_CSR, 1266 PCN_CSR_INTEN|PCN_CSR_START); 1267 } else if (!(ifp->if_flags & IFF_RUNNING)) 1268 pcn_init(sc); 1269 } else { 1270 if (ifp->if_flags & IFF_RUNNING) 1271 pcn_stop(sc); 1272 } 1273 sc->pcn_if_flags = ifp->if_flags; 1274 error = 0; 1275 break; 1276 case SIOCADDMULTI: 1277 case SIOCDELMULTI: 1278 pcn_setmulti(sc); 1279 error = 0; 1280 break; 1281 case SIOCGIFMEDIA: 1282 case SIOCSIFMEDIA: 1283 mii = device_get_softc(sc->pcn_miibus); 1284 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1285 break; 1286 default: 1287 error = ether_ioctl(ifp, command, data); 1288 break; 1289 } 1290 1291 PCN_UNLOCK(sc); 1292 1293 return(error); 1294} 1295 1296static void 1297pcn_watchdog(ifp) 1298 struct ifnet *ifp; 1299{ 1300 struct pcn_softc *sc; 1301 1302 sc = ifp->if_softc; 1303 1304 PCN_LOCK(sc); 1305 1306 ifp->if_oerrors++; 1307 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1308 1309 pcn_stop(sc); 1310 pcn_reset(sc); 1311 pcn_init(sc); 1312 1313 if (ifp->if_snd.ifq_head != NULL) 1314 pcn_start(ifp); 1315 1316 PCN_UNLOCK(sc); 1317 1318 return; 1319} 1320 1321/* 1322 * Stop the adapter and free any mbufs allocated to the 1323 * RX and TX lists. 1324 */ 1325static void 1326pcn_stop(sc) 1327 struct pcn_softc *sc; 1328{ 1329 register int i; 1330 struct ifnet *ifp; 1331 1332 ifp = &sc->arpcom.ac_if; 1333 PCN_LOCK(sc); 1334 ifp->if_timer = 0; 1335 1336 untimeout(pcn_tick, sc, sc->pcn_stat_ch); 1337 1338 /* Turn off interrupts */ 1339 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN); 1340 /* Stop adapter */ 1341 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1342 sc->pcn_link = 0; 1343 1344 /* 1345 * Free data in the RX lists. 1346 */ 1347 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1348 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1349 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1350 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1351 } 1352 } 1353 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1354 sizeof(sc->pcn_ldata->pcn_rx_list)); 1355 1356 /* 1357 * Free the TX list buffers. 1358 */ 1359 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1360 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1361 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1362 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1363 } 1364 } 1365 1366 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1367 sizeof(sc->pcn_ldata->pcn_tx_list)); 1368 1369 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1370 PCN_UNLOCK(sc); 1371 1372 return; 1373} 1374 1375/* 1376 * Stop all chip I/O so that the kernel's probe routines don't 1377 * get confused by errant DMAs when rebooting. 1378 */ 1379static void 1380pcn_shutdown(dev) 1381 device_t dev; 1382{ 1383 struct pcn_softc *sc; 1384 1385 sc = device_get_softc(dev); 1386 1387 PCN_LOCK(sc); 1388 pcn_reset(sc); 1389 pcn_stop(sc); 1390 PCN_UNLOCK(sc); 1391 1392 return; 1393} 1394