if_pcn.c revision 130270
1/* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/pci/if_pcn.c 130270 2004-06-09 14:34:04Z naddy $"); 36 37/* 38 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 39 * from http://www.amd.com. 40 * 41 * The AMD PCnet/PCI controllers are more advanced and functional 42 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 43 * backwards compatibility with the LANCE and thus can be made 44 * to work with older LANCE drivers. This is in fact how the 45 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 46 * is that the PCnet/PCI devices offer several performance enhancements 47 * which can't be exploited in LANCE compatibility mode. Chief among 48 * these enhancements is the ability to perform PCI DMA operations 49 * using 32-bit addressing (which eliminates the need for ISA 50 * bounce-buffering), and special receive buffer alignment (which 51 * allows the receive handler to pass packets to the upper protocol 52 * layers without copying on both the x86 and alpha platforms). 53 */ 54 55#include <sys/param.h> 56#include <sys/systm.h> 57#include <sys/sockio.h> 58#include <sys/mbuf.h> 59#include <sys/malloc.h> 60#include <sys/kernel.h> 61#include <sys/module.h> 62#include <sys/socket.h> 63 64#include <net/if.h> 65#include <net/if_arp.h> 66#include <net/ethernet.h> 67#include <net/if_dl.h> 68#include <net/if_media.h> 69 70#include <net/bpf.h> 71 72#include <vm/vm.h> /* for vtophys */ 73#include <vm/pmap.h> /* for vtophys */ 74#include <machine/bus_pio.h> 75#include <machine/bus_memio.h> 76#include <machine/bus.h> 77#include <machine/resource.h> 78#include <sys/bus.h> 79#include <sys/rman.h> 80 81#include <dev/mii/mii.h> 82#include <dev/mii/miivar.h> 83 84#include <dev/pci/pcireg.h> 85#include <dev/pci/pcivar.h> 86 87#define PCN_USEIOSPACE 88 89#include <pci/if_pcnreg.h> 90 91MODULE_DEPEND(pcn, pci, 1, 1, 1); 92MODULE_DEPEND(pcn, ether, 1, 1, 1); 93MODULE_DEPEND(pcn, miibus, 1, 1, 1); 94 95/* "controller miibus0" required. See GENERIC if you get errors here. */ 96#include "miibus_if.h" 97 98/* 99 * Various supported device vendors/types and their names. 100 */ 101static struct pcn_type pcn_devs[] = { 102 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 103 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 104 { 0, 0, NULL } 105}; 106 107static u_int32_t pcn_csr_read (struct pcn_softc *, int); 108static u_int16_t pcn_csr_read16 (struct pcn_softc *, int); 109static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int); 110static void pcn_csr_write (struct pcn_softc *, int, int); 111static u_int32_t pcn_bcr_read (struct pcn_softc *, int); 112static void pcn_bcr_write (struct pcn_softc *, int, int); 113 114static int pcn_probe (device_t); 115static int pcn_attach (device_t); 116static int pcn_detach (device_t); 117 118static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *); 119static int pcn_encap (struct pcn_softc *, 120 struct mbuf *, u_int32_t *); 121static void pcn_rxeof (struct pcn_softc *); 122static void pcn_txeof (struct pcn_softc *); 123static void pcn_intr (void *); 124static void pcn_tick (void *); 125static void pcn_start (struct ifnet *); 126static int pcn_ioctl (struct ifnet *, u_long, caddr_t); 127static void pcn_init (void *); 128static void pcn_stop (struct pcn_softc *); 129static void pcn_watchdog (struct ifnet *); 130static void pcn_shutdown (device_t); 131static int pcn_ifmedia_upd (struct ifnet *); 132static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *); 133 134static int pcn_miibus_readreg (device_t, int, int); 135static int pcn_miibus_writereg (device_t, int, int, int); 136static void pcn_miibus_statchg (device_t); 137 138static void pcn_setfilt (struct ifnet *); 139static void pcn_setmulti (struct pcn_softc *); 140static void pcn_reset (struct pcn_softc *); 141static int pcn_list_rx_init (struct pcn_softc *); 142static int pcn_list_tx_init (struct pcn_softc *); 143 144#ifdef PCN_USEIOSPACE 145#define PCN_RES SYS_RES_IOPORT 146#define PCN_RID PCN_PCI_LOIO 147#else 148#define PCN_RES SYS_RES_MEMORY 149#define PCN_RID PCN_PCI_LOMEM 150#endif 151 152static device_method_t pcn_methods[] = { 153 /* Device interface */ 154 DEVMETHOD(device_probe, pcn_probe), 155 DEVMETHOD(device_attach, pcn_attach), 156 DEVMETHOD(device_detach, pcn_detach), 157 DEVMETHOD(device_shutdown, pcn_shutdown), 158 159 /* bus interface */ 160 DEVMETHOD(bus_print_child, bus_generic_print_child), 161 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 162 163 /* MII interface */ 164 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 165 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 166 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 167 168 { 0, 0 } 169}; 170 171static driver_t pcn_driver = { 172 "pcn", 173 pcn_methods, 174 sizeof(struct pcn_softc) 175}; 176 177static devclass_t pcn_devclass; 178 179DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0); 180DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 181 182#define PCN_CSR_SETBIT(sc, reg, x) \ 183 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 184 185#define PCN_CSR_CLRBIT(sc, reg, x) \ 186 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 187 188#define PCN_BCR_SETBIT(sc, reg, x) \ 189 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 190 191#define PCN_BCR_CLRBIT(sc, reg, x) \ 192 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 193 194static u_int32_t 195pcn_csr_read(sc, reg) 196 struct pcn_softc *sc; 197 int reg; 198{ 199 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 200 return(CSR_READ_4(sc, PCN_IO32_RDP)); 201} 202 203static u_int16_t 204pcn_csr_read16(sc, reg) 205 struct pcn_softc *sc; 206 int reg; 207{ 208 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 209 return(CSR_READ_2(sc, PCN_IO16_RDP)); 210} 211 212static void 213pcn_csr_write(sc, reg, val) 214 struct pcn_softc *sc; 215 int reg; 216 int val; 217{ 218 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 219 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 220 return; 221} 222 223static u_int32_t 224pcn_bcr_read(sc, reg) 225 struct pcn_softc *sc; 226 int reg; 227{ 228 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 229 return(CSR_READ_4(sc, PCN_IO32_BDP)); 230} 231 232static u_int16_t 233pcn_bcr_read16(sc, reg) 234 struct pcn_softc *sc; 235 int reg; 236{ 237 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 238 return(CSR_READ_2(sc, PCN_IO16_BDP)); 239} 240 241static void 242pcn_bcr_write(sc, reg, val) 243 struct pcn_softc *sc; 244 int reg; 245 int val; 246{ 247 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 248 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 249 return; 250} 251 252static int 253pcn_miibus_readreg(dev, phy, reg) 254 device_t dev; 255 int phy, reg; 256{ 257 struct pcn_softc *sc; 258 int val; 259 260 sc = device_get_softc(dev); 261 262 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 263 return(0); 264 265 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 266 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 267 if (val == 0xFFFF) 268 return(0); 269 270 sc->pcn_phyaddr = phy; 271 272 return(val); 273} 274 275static int 276pcn_miibus_writereg(dev, phy, reg, data) 277 device_t dev; 278 int phy, reg, data; 279{ 280 struct pcn_softc *sc; 281 282 sc = device_get_softc(dev); 283 284 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 285 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 286 287 return(0); 288} 289 290static void 291pcn_miibus_statchg(dev) 292 device_t dev; 293{ 294 struct pcn_softc *sc; 295 struct mii_data *mii; 296 297 sc = device_get_softc(dev); 298 mii = device_get_softc(sc->pcn_miibus); 299 300 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 301 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 302 } else { 303 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 304 } 305 306 return; 307} 308 309static void 310pcn_setmulti(sc) 311 struct pcn_softc *sc; 312{ 313 struct ifnet *ifp; 314 struct ifmultiaddr *ifma; 315 u_int32_t h, i; 316 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 317 318 ifp = &sc->arpcom.ac_if; 319 320 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 321 322 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 323 for (i = 0; i < 4; i++) 324 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 325 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 326 return; 327 } 328 329 /* first, zot all the existing hash bits */ 330 for (i = 0; i < 4; i++) 331 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 332 333 /* now program new ones */ 334 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 335 if (ifma->ifma_addr->sa_family != AF_LINK) 336 continue; 337 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 338 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 339 hashes[h >> 4] |= 1 << (h & 0xF); 340 } 341 342 for (i = 0; i < 4; i++) 343 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 344 345 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 346 347 return; 348} 349 350static void 351pcn_reset(sc) 352 struct pcn_softc *sc; 353{ 354 /* 355 * Issue a reset by reading from the RESET register. 356 * Note that we don't know if the chip is operating in 357 * 16-bit or 32-bit mode at this point, so we attempt 358 * to reset the chip both ways. If one fails, the other 359 * will succeed. 360 */ 361 CSR_READ_2(sc, PCN_IO16_RESET); 362 CSR_READ_4(sc, PCN_IO32_RESET); 363 364 /* Wait a little while for the chip to get its brains in order. */ 365 DELAY(1000); 366 367 /* Select 32-bit (DWIO) mode */ 368 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 369 370 /* Select software style 3. */ 371 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 372 373 return; 374} 375 376/* 377 * Probe for an AMD chip. Check the PCI vendor and device 378 * IDs against our list and return a device name if we find a match. 379 */ 380static int 381pcn_probe(dev) 382 device_t dev; 383{ 384 struct pcn_type *t; 385 struct pcn_softc *sc; 386 int rid; 387 u_int32_t chip_id; 388 389 t = pcn_devs; 390 sc = device_get_softc(dev); 391 392 while(t->pcn_name != NULL) { 393 if ((pci_get_vendor(dev) == t->pcn_vid) && 394 (pci_get_device(dev) == t->pcn_did)) { 395 /* 396 * Temporarily map the I/O space 397 * so we can read the chip ID register. 398 */ 399 rid = PCN_RID; 400 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, 401 RF_ACTIVE); 402 if (sc->pcn_res == NULL) { 403 device_printf(dev, 404 "couldn't map ports/memory\n"); 405 return(ENXIO); 406 } 407 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 408 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 409 mtx_init(&sc->pcn_mtx, 410 device_get_nameunit(dev), MTX_NETWORK_LOCK, 411 MTX_DEF); 412 PCN_LOCK(sc); 413 /* 414 * Note: we can *NOT* put the chip into 415 * 32-bit mode yet. The lnc driver will only 416 * work in 16-bit mode, and once the chip 417 * goes into 32-bit mode, the only way to 418 * get it out again is with a hardware reset. 419 * So if pcn_probe() is called before the 420 * lnc driver's probe routine, the chip will 421 * be locked into 32-bit operation and the lnc 422 * driver will be unable to attach to it. 423 * Note II: if the chip happens to already 424 * be in 32-bit mode, we still need to check 425 * the chip ID, but first we have to detect 426 * 32-bit mode using only 16-bit operations. 427 * The safest way to do this is to read the 428 * PCI subsystem ID from BCR23/24 and compare 429 * that with the value read from PCI config 430 * space. 431 */ 432 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 433 chip_id <<= 16; 434 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 435 /* 436 * Note III: the test for 0x10001000 is a hack to 437 * pacify VMware, who's pseudo-PCnet interface is 438 * broken. Reading the subsystem register from PCI 439 * config space yeilds 0x00000000 while reading the 440 * same value from I/O space yeilds 0x10001000. It's 441 * not supposed to be that way. 442 */ 443 if (chip_id == pci_read_config(dev, 444 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 445 /* We're in 16-bit mode. */ 446 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 447 chip_id <<= 16; 448 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 449 } else { 450 /* We're in 32-bit mode. */ 451 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 452 chip_id <<= 16; 453 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 454 } 455 bus_release_resource(dev, PCN_RES, 456 PCN_RID, sc->pcn_res); 457 PCN_UNLOCK(sc); 458 mtx_destroy(&sc->pcn_mtx); 459 chip_id >>= 12; 460 sc->pcn_type = chip_id & PART_MASK; 461 switch(sc->pcn_type) { 462 case Am79C971: 463 case Am79C972: 464 case Am79C973: 465 case Am79C975: 466 case Am79C976: 467 case Am79C978: 468 break; 469 default: 470 return(ENXIO); 471 } 472 device_set_desc(dev, t->pcn_name); 473 return(0); 474 } 475 t++; 476 } 477 478 return(ENXIO); 479} 480 481/* 482 * Attach the interface. Allocate softc structures, do ifmedia 483 * setup and ethernet/BPF attach. 484 */ 485static int 486pcn_attach(dev) 487 device_t dev; 488{ 489 u_int32_t eaddr[2]; 490 struct pcn_softc *sc; 491 struct ifnet *ifp; 492 int unit, error = 0, rid; 493 494 sc = device_get_softc(dev); 495 unit = device_get_unit(dev); 496 497 /* Initialize our mutex. */ 498 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 499 MTX_DEF | MTX_RECURSE); 500#ifndef BURN_BRIDGES 501 /* 502 * Handle power management nonsense. 503 */ 504 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 505 u_int32_t iobase, membase, irq; 506 507 /* Save important PCI config data. */ 508 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 509 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 510 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 511 512 /* Reset the power state. */ 513 printf("pcn%d: chip is in D%d power mode " 514 "-- setting to D0\n", unit, 515 pci_get_powerstate(dev)); 516 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 517 518 /* Restore PCI config data. */ 519 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 520 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 521 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 522 } 523#endif 524 /* 525 * Map control/status registers. 526 */ 527 pci_enable_busmaster(dev); 528 529 rid = PCN_RID; 530 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE); 531 532 if (sc->pcn_res == NULL) { 533 printf("pcn%d: couldn't map ports/memory\n", unit); 534 error = ENXIO; 535 goto fail; 536 } 537 538 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 539 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 540 541 /* Allocate interrupt */ 542 rid = 0; 543 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 544 RF_SHAREABLE | RF_ACTIVE); 545 546 if (sc->pcn_irq == NULL) { 547 printf("pcn%d: couldn't map interrupt\n", unit); 548 error = ENXIO; 549 goto fail; 550 } 551 552 /* Reset the adapter. */ 553 pcn_reset(sc); 554 555 /* 556 * Get station address from the EEPROM. 557 */ 558 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 559 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 560 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 561 562 sc->pcn_unit = unit; 563 callout_handle_init(&sc->pcn_stat_ch); 564 565 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 566 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 567 568 if (sc->pcn_ldata == NULL) { 569 printf("pcn%d: no memory for list buffers!\n", unit); 570 error = ENXIO; 571 goto fail; 572 } 573 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 574 575 ifp = &sc->arpcom.ac_if; 576 ifp->if_softc = sc; 577 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 578 ifp->if_mtu = ETHERMTU; 579 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 580 ifp->if_ioctl = pcn_ioctl; 581 ifp->if_start = pcn_start; 582 ifp->if_watchdog = pcn_watchdog; 583 ifp->if_init = pcn_init; 584 ifp->if_baudrate = 10000000; 585 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 586 587 /* 588 * Do MII setup. 589 */ 590 if (mii_phy_probe(dev, &sc->pcn_miibus, 591 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 592 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 593 error = ENXIO; 594 goto fail; 595 } 596 597 /* 598 * Call MI attach routine. 599 */ 600 ether_ifattach(ifp, (u_int8_t *) eaddr); 601 602 /* Hook interrupt last to avoid having to lock softc */ 603 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 604 pcn_intr, sc, &sc->pcn_intrhand); 605 606 if (error) { 607 printf("pcn%d: couldn't set up irq\n", unit); 608 ether_ifdetach(ifp); 609 goto fail; 610 } 611 612fail: 613 if (error) 614 pcn_detach(dev); 615 616 return(error); 617} 618 619/* 620 * Shutdown hardware and free up resources. This can be called any 621 * time after the mutex has been initialized. It is called in both 622 * the error case in attach and the normal detach case so it needs 623 * to be careful about only freeing resources that have actually been 624 * allocated. 625 */ 626static int 627pcn_detach(dev) 628 device_t dev; 629{ 630 struct pcn_softc *sc; 631 struct ifnet *ifp; 632 633 sc = device_get_softc(dev); 634 ifp = &sc->arpcom.ac_if; 635 636 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized")); 637 PCN_LOCK(sc); 638 639 /* These should only be active if attach succeeded */ 640 if (device_is_attached(dev)) { 641 pcn_reset(sc); 642 pcn_stop(sc); 643 ether_ifdetach(ifp); 644 } 645 if (sc->pcn_miibus) 646 device_delete_child(dev, sc->pcn_miibus); 647 bus_generic_detach(dev); 648 649 if (sc->pcn_intrhand) 650 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 651 if (sc->pcn_irq) 652 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 653 if (sc->pcn_res) 654 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 655 656 if (sc->pcn_ldata) { 657 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 658 M_DEVBUF); 659 } 660 PCN_UNLOCK(sc); 661 662 mtx_destroy(&sc->pcn_mtx); 663 664 return(0); 665} 666 667/* 668 * Initialize the transmit descriptors. 669 */ 670static int 671pcn_list_tx_init(sc) 672 struct pcn_softc *sc; 673{ 674 struct pcn_list_data *ld; 675 struct pcn_ring_data *cd; 676 int i; 677 678 cd = &sc->pcn_cdata; 679 ld = sc->pcn_ldata; 680 681 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 682 cd->pcn_tx_chain[i] = NULL; 683 ld->pcn_tx_list[i].pcn_tbaddr = 0; 684 ld->pcn_tx_list[i].pcn_txctl = 0; 685 ld->pcn_tx_list[i].pcn_txstat = 0; 686 } 687 688 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 689 690 return(0); 691} 692 693 694/* 695 * Initialize the RX descriptors and allocate mbufs for them. 696 */ 697static int 698pcn_list_rx_init(sc) 699 struct pcn_softc *sc; 700{ 701 struct pcn_ring_data *cd; 702 int i; 703 704 cd = &sc->pcn_cdata; 705 706 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 707 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 708 return(ENOBUFS); 709 } 710 711 cd->pcn_rx_prod = 0; 712 713 return(0); 714} 715 716/* 717 * Initialize an RX descriptor and attach an MBUF cluster. 718 */ 719static int 720pcn_newbuf(sc, idx, m) 721 struct pcn_softc *sc; 722 int idx; 723 struct mbuf *m; 724{ 725 struct mbuf *m_new = NULL; 726 struct pcn_rx_desc *c; 727 728 c = &sc->pcn_ldata->pcn_rx_list[idx]; 729 730 if (m == NULL) { 731 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 732 if (m_new == NULL) 733 return(ENOBUFS); 734 735 MCLGET(m_new, M_DONTWAIT); 736 if (!(m_new->m_flags & M_EXT)) { 737 m_freem(m_new); 738 return(ENOBUFS); 739 } 740 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 741 } else { 742 m_new = m; 743 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 744 m_new->m_data = m_new->m_ext.ext_buf; 745 } 746 747 m_adj(m_new, ETHER_ALIGN); 748 749 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 750 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 751 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 752 c->pcn_bufsz |= PCN_RXLEN_MBO; 753 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 754 755 return(0); 756} 757 758/* 759 * A frame has been uploaded: pass the resulting mbuf chain up to 760 * the higher level protocols. 761 */ 762static void 763pcn_rxeof(sc) 764 struct pcn_softc *sc; 765{ 766 struct mbuf *m; 767 struct ifnet *ifp; 768 struct pcn_rx_desc *cur_rx; 769 int i; 770 771 PCN_LOCK_ASSERT(sc); 772 773 ifp = &sc->arpcom.ac_if; 774 i = sc->pcn_cdata.pcn_rx_prod; 775 776 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 777 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 778 m = sc->pcn_cdata.pcn_rx_chain[i]; 779 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 780 781 /* 782 * If an error occurs, update stats, clear the 783 * status word and leave the mbuf cluster in place: 784 * it should simply get re-used next time this descriptor 785 * comes up in the ring. 786 */ 787 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 788 ifp->if_ierrors++; 789 pcn_newbuf(sc, i, m); 790 PCN_INC(i, PCN_RX_LIST_CNT); 791 continue; 792 } 793 794 if (pcn_newbuf(sc, i, NULL)) { 795 /* Ran out of mbufs; recycle this one. */ 796 pcn_newbuf(sc, i, m); 797 ifp->if_ierrors++; 798 PCN_INC(i, PCN_RX_LIST_CNT); 799 continue; 800 } 801 802 PCN_INC(i, PCN_RX_LIST_CNT); 803 804 /* No errors; receive the packet. */ 805 ifp->if_ipackets++; 806 m->m_len = m->m_pkthdr.len = 807 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 808 m->m_pkthdr.rcvif = ifp; 809 810 PCN_UNLOCK(sc); 811 (*ifp->if_input)(ifp, m); 812 PCN_LOCK(sc); 813 } 814 815 sc->pcn_cdata.pcn_rx_prod = i; 816 817 return; 818} 819 820/* 821 * A frame was downloaded to the chip. It's safe for us to clean up 822 * the list buffers. 823 */ 824 825static void 826pcn_txeof(sc) 827 struct pcn_softc *sc; 828{ 829 struct pcn_tx_desc *cur_tx = NULL; 830 struct ifnet *ifp; 831 u_int32_t idx; 832 833 ifp = &sc->arpcom.ac_if; 834 835 /* 836 * Go through our tx list and free mbufs for those 837 * frames that have been transmitted. 838 */ 839 idx = sc->pcn_cdata.pcn_tx_cons; 840 while (idx != sc->pcn_cdata.pcn_tx_prod) { 841 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 842 843 if (!PCN_OWN_TXDESC(cur_tx)) 844 break; 845 846 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 847 sc->pcn_cdata.pcn_tx_cnt--; 848 PCN_INC(idx, PCN_TX_LIST_CNT); 849 continue; 850 } 851 852 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 853 ifp->if_oerrors++; 854 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 855 ifp->if_collisions++; 856 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 857 ifp->if_collisions++; 858 } 859 860 ifp->if_collisions += 861 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 862 863 ifp->if_opackets++; 864 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 865 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 866 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 867 } 868 869 sc->pcn_cdata.pcn_tx_cnt--; 870 PCN_INC(idx, PCN_TX_LIST_CNT); 871 } 872 873 if (idx != sc->pcn_cdata.pcn_tx_cons) { 874 /* Some buffers have been freed. */ 875 sc->pcn_cdata.pcn_tx_cons = idx; 876 ifp->if_flags &= ~IFF_OACTIVE; 877 } 878 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 879 880 return; 881} 882 883static void 884pcn_tick(xsc) 885 void *xsc; 886{ 887 struct pcn_softc *sc; 888 struct mii_data *mii; 889 struct ifnet *ifp; 890 891 sc = xsc; 892 ifp = &sc->arpcom.ac_if; 893 PCN_LOCK(sc); 894 895 mii = device_get_softc(sc->pcn_miibus); 896 mii_tick(mii); 897 898 /* link just died */ 899 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 900 sc->pcn_link = 0; 901 902 /* link just came up, restart */ 903 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE && 904 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 905 sc->pcn_link++; 906 if (ifp->if_snd.ifq_head != NULL) 907 pcn_start(ifp); 908 } 909 910 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 911 912 PCN_UNLOCK(sc); 913 914 return; 915} 916 917static void 918pcn_intr(arg) 919 void *arg; 920{ 921 struct pcn_softc *sc; 922 struct ifnet *ifp; 923 u_int32_t status; 924 925 sc = arg; 926 ifp = &sc->arpcom.ac_if; 927 928 /* Supress unwanted interrupts */ 929 if (!(ifp->if_flags & IFF_UP)) { 930 pcn_stop(sc); 931 return; 932 } 933 934 PCN_LOCK(sc); 935 936 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 937 938 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 939 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 940 941 if (status & PCN_CSR_RINT) 942 pcn_rxeof(sc); 943 944 if (status & PCN_CSR_TINT) 945 pcn_txeof(sc); 946 947 if (status & PCN_CSR_ERR) { 948 pcn_init(sc); 949 break; 950 } 951 } 952 953 if (ifp->if_snd.ifq_head != NULL) 954 pcn_start(ifp); 955 956 PCN_UNLOCK(sc); 957 return; 958} 959 960/* 961 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 962 * pointers to the fragment pointers. 963 */ 964static int 965pcn_encap(sc, m_head, txidx) 966 struct pcn_softc *sc; 967 struct mbuf *m_head; 968 u_int32_t *txidx; 969{ 970 struct pcn_tx_desc *f = NULL; 971 struct mbuf *m; 972 int frag, cur, cnt = 0; 973 974 /* 975 * Start packing the mbufs in this chain into 976 * the fragment pointers. Stop when we run out 977 * of fragments or hit the end of the mbuf chain. 978 */ 979 m = m_head; 980 cur = frag = *txidx; 981 982 for (m = m_head; m != NULL; m = m->m_next) { 983 if (m->m_len != 0) { 984 if ((PCN_TX_LIST_CNT - 985 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 986 return(ENOBUFS); 987 f = &sc->pcn_ldata->pcn_tx_list[frag]; 988 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 989 f->pcn_txctl |= PCN_TXCTL_MBO; 990 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 991 if (cnt == 0) 992 f->pcn_txctl |= PCN_TXCTL_STP; 993 else 994 f->pcn_txctl |= PCN_TXCTL_OWN; 995 cur = frag; 996 PCN_INC(frag, PCN_TX_LIST_CNT); 997 cnt++; 998 } 999 } 1000 1001 if (m != NULL) 1002 return(ENOBUFS); 1003 1004 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1005 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1006 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1007 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1008 sc->pcn_cdata.pcn_tx_cnt += cnt; 1009 *txidx = frag; 1010 1011 return(0); 1012} 1013 1014/* 1015 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1016 * to the mbuf data regions directly in the transmit lists. We also save a 1017 * copy of the pointers since the transmit list fragment pointers are 1018 * physical addresses. 1019 */ 1020static void 1021pcn_start(ifp) 1022 struct ifnet *ifp; 1023{ 1024 struct pcn_softc *sc; 1025 struct mbuf *m_head = NULL; 1026 u_int32_t idx; 1027 1028 sc = ifp->if_softc; 1029 1030 PCN_LOCK(sc); 1031 1032 if (!sc->pcn_link) { 1033 PCN_UNLOCK(sc); 1034 return; 1035 } 1036 1037 idx = sc->pcn_cdata.pcn_tx_prod; 1038 1039 if (ifp->if_flags & IFF_OACTIVE) { 1040 PCN_UNLOCK(sc); 1041 return; 1042 } 1043 1044 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1045 IF_DEQUEUE(&ifp->if_snd, m_head); 1046 if (m_head == NULL) 1047 break; 1048 1049 if (pcn_encap(sc, m_head, &idx)) { 1050 IF_PREPEND(&ifp->if_snd, m_head); 1051 ifp->if_flags |= IFF_OACTIVE; 1052 break; 1053 } 1054 1055 /* 1056 * If there's a BPF listener, bounce a copy of this frame 1057 * to him. 1058 */ 1059 BPF_MTAP(ifp, m_head); 1060 1061 } 1062 1063 /* Transmit */ 1064 sc->pcn_cdata.pcn_tx_prod = idx; 1065 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1066 1067 /* 1068 * Set a timeout in case the chip goes out to lunch. 1069 */ 1070 ifp->if_timer = 5; 1071 1072 PCN_UNLOCK(sc); 1073 1074 return; 1075} 1076 1077static void 1078pcn_setfilt(ifp) 1079 struct ifnet *ifp; 1080{ 1081 struct pcn_softc *sc; 1082 1083 sc = ifp->if_softc; 1084 1085 /* If we want promiscuous mode, set the allframes bit. */ 1086 if (ifp->if_flags & IFF_PROMISC) { 1087 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1088 } else { 1089 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1090 } 1091 1092 /* Set the capture broadcast bit to capture broadcast frames. */ 1093 if (ifp->if_flags & IFF_BROADCAST) { 1094 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1095 } else { 1096 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1097 } 1098 1099 return; 1100} 1101 1102static void 1103pcn_init(xsc) 1104 void *xsc; 1105{ 1106 struct pcn_softc *sc = xsc; 1107 struct ifnet *ifp = &sc->arpcom.ac_if; 1108 struct mii_data *mii = NULL; 1109 1110 PCN_LOCK(sc); 1111 1112 /* 1113 * Cancel pending I/O and free all RX/TX buffers. 1114 */ 1115 pcn_stop(sc); 1116 pcn_reset(sc); 1117 1118 mii = device_get_softc(sc->pcn_miibus); 1119 1120 /* Set MAC address */ 1121 pcn_csr_write(sc, PCN_CSR_PAR0, 1122 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1123 pcn_csr_write(sc, PCN_CSR_PAR1, 1124 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1125 pcn_csr_write(sc, PCN_CSR_PAR2, 1126 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1127 1128 /* Init circular RX list. */ 1129 if (pcn_list_rx_init(sc) == ENOBUFS) { 1130 printf("pcn%d: initialization failed: no " 1131 "memory for rx buffers\n", sc->pcn_unit); 1132 pcn_stop(sc); 1133 PCN_UNLOCK(sc); 1134 return; 1135 } 1136 1137 /* 1138 * Init tx descriptors. 1139 */ 1140 pcn_list_tx_init(sc); 1141 1142 /* Set up the mode register. */ 1143 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1144 1145 /* Set up RX filter. */ 1146 pcn_setfilt(ifp); 1147 1148 /* 1149 * Load the multicast filter. 1150 */ 1151 pcn_setmulti(sc); 1152 1153 /* 1154 * Load the addresses of the RX and TX lists. 1155 */ 1156 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1157 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1158 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1159 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1160 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1161 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1162 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1163 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1164 1165 /* Set the RX and TX ring sizes. */ 1166 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1167 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1168 1169 /* We're not using the initialization block. */ 1170 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1171 1172 /* Enable fast suspend mode. */ 1173 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1174 1175 /* 1176 * Enable burst read and write. Also set the no underflow 1177 * bit. This will avoid transmit underruns in certain 1178 * conditions while still providing decent performance. 1179 */ 1180 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1181 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1182 1183 /* Enable graceful recovery from underflow. */ 1184 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1185 1186 /* Enable auto-padding of short TX frames. */ 1187 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1188 1189 /* Disable MII autoneg (we handle this ourselves). */ 1190 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1191 1192 if (sc->pcn_type == Am79C978) 1193 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1194 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1195 1196 /* Enable interrupts and start the controller running. */ 1197 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1198 1199 mii_mediachg(mii); 1200 1201 ifp->if_flags |= IFF_RUNNING; 1202 ifp->if_flags &= ~IFF_OACTIVE; 1203 1204 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 1205 PCN_UNLOCK(sc); 1206 1207 return; 1208} 1209 1210/* 1211 * Set media options. 1212 */ 1213static int 1214pcn_ifmedia_upd(ifp) 1215 struct ifnet *ifp; 1216{ 1217 struct pcn_softc *sc; 1218 struct mii_data *mii; 1219 1220 sc = ifp->if_softc; 1221 mii = device_get_softc(sc->pcn_miibus); 1222 1223 sc->pcn_link = 0; 1224 if (mii->mii_instance) { 1225 struct mii_softc *miisc; 1226 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1227 mii_phy_reset(miisc); 1228 } 1229 mii_mediachg(mii); 1230 1231 return(0); 1232} 1233 1234/* 1235 * Report current media status. 1236 */ 1237static void 1238pcn_ifmedia_sts(ifp, ifmr) 1239 struct ifnet *ifp; 1240 struct ifmediareq *ifmr; 1241{ 1242 struct pcn_softc *sc; 1243 struct mii_data *mii; 1244 1245 sc = ifp->if_softc; 1246 1247 mii = device_get_softc(sc->pcn_miibus); 1248 mii_pollstat(mii); 1249 ifmr->ifm_active = mii->mii_media_active; 1250 ifmr->ifm_status = mii->mii_media_status; 1251 1252 return; 1253} 1254 1255static int 1256pcn_ioctl(ifp, command, data) 1257 struct ifnet *ifp; 1258 u_long command; 1259 caddr_t data; 1260{ 1261 struct pcn_softc *sc = ifp->if_softc; 1262 struct ifreq *ifr = (struct ifreq *) data; 1263 struct mii_data *mii = NULL; 1264 int error = 0; 1265 1266 PCN_LOCK(sc); 1267 1268 switch(command) { 1269 case SIOCSIFFLAGS: 1270 if (ifp->if_flags & IFF_UP) { 1271 if (ifp->if_flags & IFF_RUNNING && 1272 ifp->if_flags & IFF_PROMISC && 1273 !(sc->pcn_if_flags & IFF_PROMISC)) { 1274 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1275 PCN_EXTCTL1_SPND); 1276 pcn_setfilt(ifp); 1277 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1278 PCN_EXTCTL1_SPND); 1279 pcn_csr_write(sc, PCN_CSR_CSR, 1280 PCN_CSR_INTEN|PCN_CSR_START); 1281 } else if (ifp->if_flags & IFF_RUNNING && 1282 !(ifp->if_flags & IFF_PROMISC) && 1283 sc->pcn_if_flags & IFF_PROMISC) { 1284 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1285 PCN_EXTCTL1_SPND); 1286 pcn_setfilt(ifp); 1287 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1288 PCN_EXTCTL1_SPND); 1289 pcn_csr_write(sc, PCN_CSR_CSR, 1290 PCN_CSR_INTEN|PCN_CSR_START); 1291 } else if (!(ifp->if_flags & IFF_RUNNING)) 1292 pcn_init(sc); 1293 } else { 1294 if (ifp->if_flags & IFF_RUNNING) 1295 pcn_stop(sc); 1296 } 1297 sc->pcn_if_flags = ifp->if_flags; 1298 error = 0; 1299 break; 1300 case SIOCADDMULTI: 1301 case SIOCDELMULTI: 1302 pcn_setmulti(sc); 1303 error = 0; 1304 break; 1305 case SIOCGIFMEDIA: 1306 case SIOCSIFMEDIA: 1307 mii = device_get_softc(sc->pcn_miibus); 1308 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1309 break; 1310 default: 1311 error = ether_ioctl(ifp, command, data); 1312 break; 1313 } 1314 1315 PCN_UNLOCK(sc); 1316 1317 return(error); 1318} 1319 1320static void 1321pcn_watchdog(ifp) 1322 struct ifnet *ifp; 1323{ 1324 struct pcn_softc *sc; 1325 1326 sc = ifp->if_softc; 1327 1328 PCN_LOCK(sc); 1329 1330 ifp->if_oerrors++; 1331 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1332 1333 pcn_stop(sc); 1334 pcn_reset(sc); 1335 pcn_init(sc); 1336 1337 if (ifp->if_snd.ifq_head != NULL) 1338 pcn_start(ifp); 1339 1340 PCN_UNLOCK(sc); 1341 1342 return; 1343} 1344 1345/* 1346 * Stop the adapter and free any mbufs allocated to the 1347 * RX and TX lists. 1348 */ 1349static void 1350pcn_stop(sc) 1351 struct pcn_softc *sc; 1352{ 1353 register int i; 1354 struct ifnet *ifp; 1355 1356 ifp = &sc->arpcom.ac_if; 1357 PCN_LOCK(sc); 1358 ifp->if_timer = 0; 1359 1360 untimeout(pcn_tick, sc, sc->pcn_stat_ch); 1361 1362 /* Turn off interrupts */ 1363 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN); 1364 /* Stop adapter */ 1365 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1366 sc->pcn_link = 0; 1367 1368 /* 1369 * Free data in the RX lists. 1370 */ 1371 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1372 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1373 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1374 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1375 } 1376 } 1377 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1378 sizeof(sc->pcn_ldata->pcn_rx_list)); 1379 1380 /* 1381 * Free the TX list buffers. 1382 */ 1383 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1384 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1385 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1386 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1387 } 1388 } 1389 1390 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1391 sizeof(sc->pcn_ldata->pcn_tx_list)); 1392 1393 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1394 PCN_UNLOCK(sc); 1395 1396 return; 1397} 1398 1399/* 1400 * Stop all chip I/O so that the kernel's probe routines don't 1401 * get confused by errant DMAs when rebooting. 1402 */ 1403static void 1404pcn_shutdown(dev) 1405 device_t dev; 1406{ 1407 struct pcn_softc *sc; 1408 1409 sc = device_get_softc(dev); 1410 1411 PCN_LOCK(sc); 1412 pcn_reset(sc); 1413 pcn_stop(sc); 1414 PCN_UNLOCK(sc); 1415 1416 return; 1417} 1418