if_pcn.c revision 121816
1/* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34/* 35 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 36 * from http://www.amd.com. 37 * 38 * The AMD PCnet/PCI controllers are more advanced and functional 39 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 40 * backwards compatibility with the LANCE and thus can be made 41 * to work with older LANCE drivers. This is in fact how the 42 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 43 * is that the PCnet/PCI devices offer several performance enhancements 44 * which can't be exploited in LANCE compatibility mode. Chief among 45 * these enhancements is the ability to perform PCI DMA operations 46 * using 32-bit addressing (which eliminates the need for ISA 47 * bounce-buffering), and special receive buffer alignment (which 48 * allows the receive handler to pass packets to the upper protocol 49 * layers without copying on both the x86 and alpha platforms). 50 */ 51 52#include <sys/cdefs.h> 53__FBSDID("$FreeBSD: head/sys/pci/if_pcn.c 121816 2003-10-31 18:32:15Z brooks $"); 54 55#include <sys/param.h> 56#include <sys/systm.h> 57#include <sys/sockio.h> 58#include <sys/mbuf.h> 59#include <sys/malloc.h> 60#include <sys/kernel.h> 61#include <sys/socket.h> 62 63#include <net/if.h> 64#include <net/if_arp.h> 65#include <net/ethernet.h> 66#include <net/if_dl.h> 67#include <net/if_media.h> 68 69#include <net/bpf.h> 70 71#include <vm/vm.h> /* for vtophys */ 72#include <vm/pmap.h> /* for vtophys */ 73#include <machine/bus_pio.h> 74#include <machine/bus_memio.h> 75#include <machine/bus.h> 76#include <machine/resource.h> 77#include <sys/bus.h> 78#include <sys/rman.h> 79 80#include <dev/mii/mii.h> 81#include <dev/mii/miivar.h> 82 83#include <dev/pci/pcireg.h> 84#include <dev/pci/pcivar.h> 85 86#define PCN_USEIOSPACE 87 88#include <pci/if_pcnreg.h> 89 90MODULE_DEPEND(pcn, pci, 1, 1, 1); 91MODULE_DEPEND(pcn, ether, 1, 1, 1); 92MODULE_DEPEND(pcn, miibus, 1, 1, 1); 93 94/* "controller miibus0" required. See GENERIC if you get errors here. */ 95#include "miibus_if.h" 96 97/* 98 * Various supported device vendors/types and their names. 99 */ 100static struct pcn_type pcn_devs[] = { 101 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 102 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 103 { 0, 0, NULL } 104}; 105 106static u_int32_t pcn_csr_read (struct pcn_softc *, int); 107static u_int16_t pcn_csr_read16 (struct pcn_softc *, int); 108static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int); 109static void pcn_csr_write (struct pcn_softc *, int, int); 110static u_int32_t pcn_bcr_read (struct pcn_softc *, int); 111static void pcn_bcr_write (struct pcn_softc *, int, int); 112 113static int pcn_probe (device_t); 114static int pcn_attach (device_t); 115static int pcn_detach (device_t); 116 117static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *); 118static int pcn_encap (struct pcn_softc *, 119 struct mbuf *, u_int32_t *); 120static void pcn_rxeof (struct pcn_softc *); 121static void pcn_txeof (struct pcn_softc *); 122static void pcn_intr (void *); 123static void pcn_tick (void *); 124static void pcn_start (struct ifnet *); 125static int pcn_ioctl (struct ifnet *, u_long, caddr_t); 126static void pcn_init (void *); 127static void pcn_stop (struct pcn_softc *); 128static void pcn_watchdog (struct ifnet *); 129static void pcn_shutdown (device_t); 130static int pcn_ifmedia_upd (struct ifnet *); 131static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *); 132 133static int pcn_miibus_readreg (device_t, int, int); 134static int pcn_miibus_writereg (device_t, int, int, int); 135static void pcn_miibus_statchg (device_t); 136 137static void pcn_setfilt (struct ifnet *); 138static void pcn_setmulti (struct pcn_softc *); 139static u_int32_t pcn_crc (caddr_t); 140static void pcn_reset (struct pcn_softc *); 141static int pcn_list_rx_init (struct pcn_softc *); 142static int pcn_list_tx_init (struct pcn_softc *); 143 144#ifdef PCN_USEIOSPACE 145#define PCN_RES SYS_RES_IOPORT 146#define PCN_RID PCN_PCI_LOIO 147#else 148#define PCN_RES SYS_RES_MEMORY 149#define PCN_RID PCN_PCI_LOMEM 150#endif 151 152static device_method_t pcn_methods[] = { 153 /* Device interface */ 154 DEVMETHOD(device_probe, pcn_probe), 155 DEVMETHOD(device_attach, pcn_attach), 156 DEVMETHOD(device_detach, pcn_detach), 157 DEVMETHOD(device_shutdown, pcn_shutdown), 158 159 /* bus interface */ 160 DEVMETHOD(bus_print_child, bus_generic_print_child), 161 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 162 163 /* MII interface */ 164 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 165 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 166 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 167 168 { 0, 0 } 169}; 170 171static driver_t pcn_driver = { 172 "pcn", 173 pcn_methods, 174 sizeof(struct pcn_softc) 175}; 176 177static devclass_t pcn_devclass; 178 179DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0); 180DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 181 182#define PCN_CSR_SETBIT(sc, reg, x) \ 183 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 184 185#define PCN_CSR_CLRBIT(sc, reg, x) \ 186 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 187 188#define PCN_BCR_SETBIT(sc, reg, x) \ 189 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 190 191#define PCN_BCR_CLRBIT(sc, reg, x) \ 192 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 193 194static u_int32_t 195pcn_csr_read(sc, reg) 196 struct pcn_softc *sc; 197 int reg; 198{ 199 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 200 return(CSR_READ_4(sc, PCN_IO32_RDP)); 201} 202 203static u_int16_t 204pcn_csr_read16(sc, reg) 205 struct pcn_softc *sc; 206 int reg; 207{ 208 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 209 return(CSR_READ_2(sc, PCN_IO16_RDP)); 210} 211 212static void 213pcn_csr_write(sc, reg, val) 214 struct pcn_softc *sc; 215 int reg; 216 int val; 217{ 218 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 219 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 220 return; 221} 222 223static u_int32_t 224pcn_bcr_read(sc, reg) 225 struct pcn_softc *sc; 226 int reg; 227{ 228 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 229 return(CSR_READ_4(sc, PCN_IO32_BDP)); 230} 231 232static u_int16_t 233pcn_bcr_read16(sc, reg) 234 struct pcn_softc *sc; 235 int reg; 236{ 237 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 238 return(CSR_READ_2(sc, PCN_IO16_BDP)); 239} 240 241static void 242pcn_bcr_write(sc, reg, val) 243 struct pcn_softc *sc; 244 int reg; 245 int val; 246{ 247 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 248 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 249 return; 250} 251 252static int 253pcn_miibus_readreg(dev, phy, reg) 254 device_t dev; 255 int phy, reg; 256{ 257 struct pcn_softc *sc; 258 int val; 259 260 sc = device_get_softc(dev); 261 262 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 263 return(0); 264 265 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 266 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 267 if (val == 0xFFFF) 268 return(0); 269 270 sc->pcn_phyaddr = phy; 271 272 return(val); 273} 274 275static int 276pcn_miibus_writereg(dev, phy, reg, data) 277 device_t dev; 278 int phy, reg, data; 279{ 280 struct pcn_softc *sc; 281 282 sc = device_get_softc(dev); 283 284 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 285 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 286 287 return(0); 288} 289 290static void 291pcn_miibus_statchg(dev) 292 device_t dev; 293{ 294 struct pcn_softc *sc; 295 struct mii_data *mii; 296 297 sc = device_get_softc(dev); 298 mii = device_get_softc(sc->pcn_miibus); 299 300 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 301 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 302 } else { 303 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 304 } 305 306 return; 307} 308 309#define DC_POLY 0xEDB88320 310 311static u_int32_t 312pcn_crc(addr) 313 caddr_t addr; 314{ 315 u_int32_t idx, bit, data, crc; 316 317 /* Compute CRC for the address value. */ 318 crc = 0xFFFFFFFF; /* initial value */ 319 320 for (idx = 0; idx < 6; idx++) { 321 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 322 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 323 } 324 325 return ((crc >> 26) & 0x3F); 326} 327 328static void 329pcn_setmulti(sc) 330 struct pcn_softc *sc; 331{ 332 struct ifnet *ifp; 333 struct ifmultiaddr *ifma; 334 u_int32_t h, i; 335 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 336 337 ifp = &sc->arpcom.ac_if; 338 339 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 340 341 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 342 for (i = 0; i < 4; i++) 343 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 344 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 345 return; 346 } 347 348 /* first, zot all the existing hash bits */ 349 for (i = 0; i < 4; i++) 350 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 351 352 /* now program new ones */ 353 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 354 if (ifma->ifma_addr->sa_family != AF_LINK) 355 continue; 356 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 357 hashes[h >> 4] |= 1 << (h & 0xF); 358 } 359 360 for (i = 0; i < 4; i++) 361 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 362 363 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 364 365 return; 366} 367 368static void 369pcn_reset(sc) 370 struct pcn_softc *sc; 371{ 372 /* 373 * Issue a reset by reading from the RESET register. 374 * Note that we don't know if the chip is operating in 375 * 16-bit or 32-bit mode at this point, so we attempt 376 * to reset the chip both ways. If one fails, the other 377 * will succeed. 378 */ 379 CSR_READ_2(sc, PCN_IO16_RESET); 380 CSR_READ_4(sc, PCN_IO32_RESET); 381 382 /* Wait a little while for the chip to get its brains in order. */ 383 DELAY(1000); 384 385 /* Select 32-bit (DWIO) mode */ 386 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 387 388 /* Select software style 3. */ 389 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 390 391 return; 392} 393 394/* 395 * Probe for an AMD chip. Check the PCI vendor and device 396 * IDs against our list and return a device name if we find a match. 397 */ 398static int 399pcn_probe(dev) 400 device_t dev; 401{ 402 struct pcn_type *t; 403 struct pcn_softc *sc; 404 int rid; 405 u_int32_t chip_id; 406 407 t = pcn_devs; 408 sc = device_get_softc(dev); 409 410 while(t->pcn_name != NULL) { 411 if ((pci_get_vendor(dev) == t->pcn_vid) && 412 (pci_get_device(dev) == t->pcn_did)) { 413 /* 414 * Temporarily map the I/O space 415 * so we can read the chip ID register. 416 */ 417 rid = PCN_RID; 418 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 419 0, ~0, 1, RF_ACTIVE); 420 if (sc->pcn_res == NULL) { 421 device_printf(dev, 422 "couldn't map ports/memory\n"); 423 return(ENXIO); 424 } 425 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 426 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 427 mtx_init(&sc->pcn_mtx, 428 device_get_nameunit(dev), MTX_NETWORK_LOCK, 429 MTX_DEF); 430 PCN_LOCK(sc); 431 /* 432 * Note: we can *NOT* put the chip into 433 * 32-bit mode yet. The lnc driver will only 434 * work in 16-bit mode, and once the chip 435 * goes into 32-bit mode, the only way to 436 * get it out again is with a hardware reset. 437 * So if pcn_probe() is called before the 438 * lnc driver's probe routine, the chip will 439 * be locked into 32-bit operation and the lnc 440 * driver will be unable to attach to it. 441 * Note II: if the chip happens to already 442 * be in 32-bit mode, we still need to check 443 * the chip ID, but first we have to detect 444 * 32-bit mode using only 16-bit operations. 445 * The safest way to do this is to read the 446 * PCI subsystem ID from BCR23/24 and compare 447 * that with the value read from PCI config 448 * space. 449 */ 450 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 451 chip_id <<= 16; 452 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 453 /* 454 * Note III: the test for 0x10001000 is a hack to 455 * pacify VMware, who's pseudo-PCnet interface is 456 * broken. Reading the subsystem register from PCI 457 * config space yeilds 0x00000000 while reading the 458 * same value from I/O space yeilds 0x10001000. It's 459 * not supposed to be that way. 460 */ 461 if (chip_id == pci_read_config(dev, 462 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 463 /* We're in 16-bit mode. */ 464 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 465 chip_id <<= 16; 466 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 467 } else { 468 /* We're in 32-bit mode. */ 469 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 470 chip_id <<= 16; 471 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 472 } 473 bus_release_resource(dev, PCN_RES, 474 PCN_RID, sc->pcn_res); 475 PCN_UNLOCK(sc); 476 mtx_destroy(&sc->pcn_mtx); 477 chip_id >>= 12; 478 sc->pcn_type = chip_id & PART_MASK; 479 switch(sc->pcn_type) { 480 case Am79C971: 481 case Am79C972: 482 case Am79C973: 483 case Am79C975: 484 case Am79C976: 485 case Am79C978: 486 break; 487 default: 488 return(ENXIO); 489 } 490 device_set_desc(dev, t->pcn_name); 491 return(0); 492 } 493 t++; 494 } 495 496 return(ENXIO); 497} 498 499/* 500 * Attach the interface. Allocate softc structures, do ifmedia 501 * setup and ethernet/BPF attach. 502 */ 503static int 504pcn_attach(dev) 505 device_t dev; 506{ 507 u_int32_t eaddr[2]; 508 struct pcn_softc *sc; 509 struct ifnet *ifp; 510 int unit, error = 0, rid; 511 512 sc = device_get_softc(dev); 513 unit = device_get_unit(dev); 514 515 /* Initialize our mutex. */ 516 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 517 MTX_DEF | MTX_RECURSE); 518#ifndef BURN_BRIDGES 519 /* 520 * Handle power management nonsense. 521 */ 522 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 523 u_int32_t iobase, membase, irq; 524 525 /* Save important PCI config data. */ 526 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 527 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 528 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 529 530 /* Reset the power state. */ 531 printf("pcn%d: chip is in D%d power mode " 532 "-- setting to D0\n", unit, 533 pci_get_powerstate(dev)); 534 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 535 536 /* Restore PCI config data. */ 537 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 538 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 539 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 540 } 541#endif 542 /* 543 * Map control/status registers. 544 */ 545 pci_enable_busmaster(dev); 546 547 rid = PCN_RID; 548 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 549 0, ~0, 1, RF_ACTIVE); 550 551 if (sc->pcn_res == NULL) { 552 printf("pcn%d: couldn't map ports/memory\n", unit); 553 error = ENXIO; 554 goto fail; 555 } 556 557 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 558 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 559 560 /* Allocate interrupt */ 561 rid = 0; 562 sc->pcn_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 563 RF_SHAREABLE | RF_ACTIVE); 564 565 if (sc->pcn_irq == NULL) { 566 printf("pcn%d: couldn't map interrupt\n", unit); 567 error = ENXIO; 568 goto fail; 569 } 570 571 /* Reset the adapter. */ 572 pcn_reset(sc); 573 574 /* 575 * Get station address from the EEPROM. 576 */ 577 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 578 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 579 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 580 581 /* 582 * An AMD chip was detected. Inform the world. 583 */ 584 printf("pcn%d: Ethernet address: %6D\n", unit, 585 sc->arpcom.ac_enaddr, ":"); 586 587 sc->pcn_unit = unit; 588 callout_handle_init(&sc->pcn_stat_ch); 589 590 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 591 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 592 593 if (sc->pcn_ldata == NULL) { 594 printf("pcn%d: no memory for list buffers!\n", unit); 595 error = ENXIO; 596 goto fail; 597 } 598 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 599 600 ifp = &sc->arpcom.ac_if; 601 ifp->if_softc = sc; 602 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 603 ifp->if_mtu = ETHERMTU; 604 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 605 ifp->if_ioctl = pcn_ioctl; 606 ifp->if_output = ether_output; 607 ifp->if_start = pcn_start; 608 ifp->if_watchdog = pcn_watchdog; 609 ifp->if_init = pcn_init; 610 ifp->if_baudrate = 10000000; 611 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 612 613 /* 614 * Do MII setup. 615 */ 616 if (mii_phy_probe(dev, &sc->pcn_miibus, 617 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 618 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 619 error = ENXIO; 620 goto fail; 621 } 622 623 /* 624 * Call MI attach routine. 625 */ 626 ether_ifattach(ifp, (u_int8_t *) eaddr); 627 628 /* Hook interrupt last to avoid having to lock softc */ 629 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 630 pcn_intr, sc, &sc->pcn_intrhand); 631 632 if (error) { 633 printf("pcn%d: couldn't set up irq\n", unit); 634 ether_ifdetach(ifp); 635 goto fail; 636 } 637 638fail: 639 if (error) 640 pcn_detach(dev); 641 642 return(error); 643} 644 645/* 646 * Shutdown hardware and free up resources. This can be called any 647 * time after the mutex has been initialized. It is called in both 648 * the error case in attach and the normal detach case so it needs 649 * to be careful about only freeing resources that have actually been 650 * allocated. 651 */ 652static int 653pcn_detach(dev) 654 device_t dev; 655{ 656 struct pcn_softc *sc; 657 struct ifnet *ifp; 658 659 sc = device_get_softc(dev); 660 ifp = &sc->arpcom.ac_if; 661 662 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized")); 663 PCN_LOCK(sc); 664 665 /* These should only be active if attach succeeded */ 666 if (device_is_attached(dev)) { 667 pcn_reset(sc); 668 pcn_stop(sc); 669 ether_ifdetach(ifp); 670 } 671 if (sc->pcn_miibus) 672 device_delete_child(dev, sc->pcn_miibus); 673 bus_generic_detach(dev); 674 675 if (sc->pcn_intrhand) 676 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 677 if (sc->pcn_irq) 678 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 679 if (sc->pcn_res) 680 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 681 682 if (sc->pcn_ldata) { 683 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 684 M_DEVBUF); 685 } 686 PCN_UNLOCK(sc); 687 688 mtx_destroy(&sc->pcn_mtx); 689 690 return(0); 691} 692 693/* 694 * Initialize the transmit descriptors. 695 */ 696static int 697pcn_list_tx_init(sc) 698 struct pcn_softc *sc; 699{ 700 struct pcn_list_data *ld; 701 struct pcn_ring_data *cd; 702 int i; 703 704 cd = &sc->pcn_cdata; 705 ld = sc->pcn_ldata; 706 707 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 708 cd->pcn_tx_chain[i] = NULL; 709 ld->pcn_tx_list[i].pcn_tbaddr = 0; 710 ld->pcn_tx_list[i].pcn_txctl = 0; 711 ld->pcn_tx_list[i].pcn_txstat = 0; 712 } 713 714 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 715 716 return(0); 717} 718 719 720/* 721 * Initialize the RX descriptors and allocate mbufs for them. 722 */ 723static int 724pcn_list_rx_init(sc) 725 struct pcn_softc *sc; 726{ 727 struct pcn_ring_data *cd; 728 int i; 729 730 cd = &sc->pcn_cdata; 731 732 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 733 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 734 return(ENOBUFS); 735 } 736 737 cd->pcn_rx_prod = 0; 738 739 return(0); 740} 741 742/* 743 * Initialize an RX descriptor and attach an MBUF cluster. 744 */ 745static int 746pcn_newbuf(sc, idx, m) 747 struct pcn_softc *sc; 748 int idx; 749 struct mbuf *m; 750{ 751 struct mbuf *m_new = NULL; 752 struct pcn_rx_desc *c; 753 754 c = &sc->pcn_ldata->pcn_rx_list[idx]; 755 756 if (m == NULL) { 757 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 758 if (m_new == NULL) 759 return(ENOBUFS); 760 761 MCLGET(m_new, M_DONTWAIT); 762 if (!(m_new->m_flags & M_EXT)) { 763 m_freem(m_new); 764 return(ENOBUFS); 765 } 766 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 767 } else { 768 m_new = m; 769 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 770 m_new->m_data = m_new->m_ext.ext_buf; 771 } 772 773 m_adj(m_new, ETHER_ALIGN); 774 775 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 776 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 777 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 778 c->pcn_bufsz |= PCN_RXLEN_MBO; 779 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 780 781 return(0); 782} 783 784/* 785 * A frame has been uploaded: pass the resulting mbuf chain up to 786 * the higher level protocols. 787 */ 788static void 789pcn_rxeof(sc) 790 struct pcn_softc *sc; 791{ 792 struct mbuf *m; 793 struct ifnet *ifp; 794 struct pcn_rx_desc *cur_rx; 795 int i; 796 797 ifp = &sc->arpcom.ac_if; 798 i = sc->pcn_cdata.pcn_rx_prod; 799 800 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 801 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 802 m = sc->pcn_cdata.pcn_rx_chain[i]; 803 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 804 805 /* 806 * If an error occurs, update stats, clear the 807 * status word and leave the mbuf cluster in place: 808 * it should simply get re-used next time this descriptor 809 * comes up in the ring. 810 */ 811 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 812 ifp->if_ierrors++; 813 pcn_newbuf(sc, i, m); 814 PCN_INC(i, PCN_RX_LIST_CNT); 815 continue; 816 } 817 818 if (pcn_newbuf(sc, i, NULL)) { 819 /* Ran out of mbufs; recycle this one. */ 820 pcn_newbuf(sc, i, m); 821 ifp->if_ierrors++; 822 PCN_INC(i, PCN_RX_LIST_CNT); 823 continue; 824 } 825 826 PCN_INC(i, PCN_RX_LIST_CNT); 827 828 /* No errors; receive the packet. */ 829 ifp->if_ipackets++; 830 m->m_len = m->m_pkthdr.len = 831 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 832 m->m_pkthdr.rcvif = ifp; 833 834 (*ifp->if_input)(ifp, m); 835 } 836 837 sc->pcn_cdata.pcn_rx_prod = i; 838 839 return; 840} 841 842/* 843 * A frame was downloaded to the chip. It's safe for us to clean up 844 * the list buffers. 845 */ 846 847static void 848pcn_txeof(sc) 849 struct pcn_softc *sc; 850{ 851 struct pcn_tx_desc *cur_tx = NULL; 852 struct ifnet *ifp; 853 u_int32_t idx; 854 855 ifp = &sc->arpcom.ac_if; 856 857 /* 858 * Go through our tx list and free mbufs for those 859 * frames that have been transmitted. 860 */ 861 idx = sc->pcn_cdata.pcn_tx_cons; 862 while (idx != sc->pcn_cdata.pcn_tx_prod) { 863 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 864 865 if (!PCN_OWN_TXDESC(cur_tx)) 866 break; 867 868 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 869 sc->pcn_cdata.pcn_tx_cnt--; 870 PCN_INC(idx, PCN_TX_LIST_CNT); 871 continue; 872 } 873 874 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 875 ifp->if_oerrors++; 876 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 877 ifp->if_collisions++; 878 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 879 ifp->if_collisions++; 880 } 881 882 ifp->if_collisions += 883 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 884 885 ifp->if_opackets++; 886 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 887 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 888 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 889 } 890 891 sc->pcn_cdata.pcn_tx_cnt--; 892 PCN_INC(idx, PCN_TX_LIST_CNT); 893 } 894 895 if (idx != sc->pcn_cdata.pcn_tx_cons) { 896 /* Some buffers have been freed. */ 897 sc->pcn_cdata.pcn_tx_cons = idx; 898 ifp->if_flags &= ~IFF_OACTIVE; 899 } 900 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 901 902 return; 903} 904 905static void 906pcn_tick(xsc) 907 void *xsc; 908{ 909 struct pcn_softc *sc; 910 struct mii_data *mii; 911 struct ifnet *ifp; 912 913 sc = xsc; 914 ifp = &sc->arpcom.ac_if; 915 PCN_LOCK(sc); 916 917 mii = device_get_softc(sc->pcn_miibus); 918 mii_tick(mii); 919 920 /* link just died */ 921 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 922 sc->pcn_link = 0; 923 924 /* link just came up, restart */ 925 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE && 926 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 927 sc->pcn_link++; 928 if (ifp->if_snd.ifq_head != NULL) 929 pcn_start(ifp); 930 } 931 932 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 933 934 PCN_UNLOCK(sc); 935 936 return; 937} 938 939static void 940pcn_intr(arg) 941 void *arg; 942{ 943 struct pcn_softc *sc; 944 struct ifnet *ifp; 945 u_int32_t status; 946 947 sc = arg; 948 ifp = &sc->arpcom.ac_if; 949 950 /* Supress unwanted interrupts */ 951 if (!(ifp->if_flags & IFF_UP)) { 952 pcn_stop(sc); 953 return; 954 } 955 956 PCN_LOCK(sc); 957 958 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 959 960 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 961 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 962 963 if (status & PCN_CSR_RINT) 964 pcn_rxeof(sc); 965 966 if (status & PCN_CSR_TINT) 967 pcn_txeof(sc); 968 969 if (status & PCN_CSR_ERR) { 970 pcn_init(sc); 971 break; 972 } 973 } 974 975 if (ifp->if_snd.ifq_head != NULL) 976 pcn_start(ifp); 977 978 PCN_UNLOCK(sc); 979 return; 980} 981 982/* 983 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 984 * pointers to the fragment pointers. 985 */ 986static int 987pcn_encap(sc, m_head, txidx) 988 struct pcn_softc *sc; 989 struct mbuf *m_head; 990 u_int32_t *txidx; 991{ 992 struct pcn_tx_desc *f = NULL; 993 struct mbuf *m; 994 int frag, cur, cnt = 0; 995 996 /* 997 * Start packing the mbufs in this chain into 998 * the fragment pointers. Stop when we run out 999 * of fragments or hit the end of the mbuf chain. 1000 */ 1001 m = m_head; 1002 cur = frag = *txidx; 1003 1004 for (m = m_head; m != NULL; m = m->m_next) { 1005 if (m->m_len != 0) { 1006 if ((PCN_TX_LIST_CNT - 1007 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 1008 return(ENOBUFS); 1009 f = &sc->pcn_ldata->pcn_tx_list[frag]; 1010 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 1011 f->pcn_txctl |= PCN_TXCTL_MBO; 1012 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 1013 if (cnt == 0) 1014 f->pcn_txctl |= PCN_TXCTL_STP; 1015 else 1016 f->pcn_txctl |= PCN_TXCTL_OWN; 1017 cur = frag; 1018 PCN_INC(frag, PCN_TX_LIST_CNT); 1019 cnt++; 1020 } 1021 } 1022 1023 if (m != NULL) 1024 return(ENOBUFS); 1025 1026 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1027 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1028 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1029 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1030 sc->pcn_cdata.pcn_tx_cnt += cnt; 1031 *txidx = frag; 1032 1033 return(0); 1034} 1035 1036/* 1037 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1038 * to the mbuf data regions directly in the transmit lists. We also save a 1039 * copy of the pointers since the transmit list fragment pointers are 1040 * physical addresses. 1041 */ 1042static void 1043pcn_start(ifp) 1044 struct ifnet *ifp; 1045{ 1046 struct pcn_softc *sc; 1047 struct mbuf *m_head = NULL; 1048 u_int32_t idx; 1049 1050 sc = ifp->if_softc; 1051 1052 PCN_LOCK(sc); 1053 1054 if (!sc->pcn_link) { 1055 PCN_UNLOCK(sc); 1056 return; 1057 } 1058 1059 idx = sc->pcn_cdata.pcn_tx_prod; 1060 1061 if (ifp->if_flags & IFF_OACTIVE) { 1062 PCN_UNLOCK(sc); 1063 return; 1064 } 1065 1066 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1067 IF_DEQUEUE(&ifp->if_snd, m_head); 1068 if (m_head == NULL) 1069 break; 1070 1071 if (pcn_encap(sc, m_head, &idx)) { 1072 IF_PREPEND(&ifp->if_snd, m_head); 1073 ifp->if_flags |= IFF_OACTIVE; 1074 break; 1075 } 1076 1077 /* 1078 * If there's a BPF listener, bounce a copy of this frame 1079 * to him. 1080 */ 1081 BPF_MTAP(ifp, m_head); 1082 1083 } 1084 1085 /* Transmit */ 1086 sc->pcn_cdata.pcn_tx_prod = idx; 1087 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1088 1089 /* 1090 * Set a timeout in case the chip goes out to lunch. 1091 */ 1092 ifp->if_timer = 5; 1093 1094 PCN_UNLOCK(sc); 1095 1096 return; 1097} 1098 1099static void 1100pcn_setfilt(ifp) 1101 struct ifnet *ifp; 1102{ 1103 struct pcn_softc *sc; 1104 1105 sc = ifp->if_softc; 1106 1107 /* If we want promiscuous mode, set the allframes bit. */ 1108 if (ifp->if_flags & IFF_PROMISC) { 1109 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1110 } else { 1111 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1112 } 1113 1114 /* Set the capture broadcast bit to capture broadcast frames. */ 1115 if (ifp->if_flags & IFF_BROADCAST) { 1116 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1117 } else { 1118 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1119 } 1120 1121 return; 1122} 1123 1124static void 1125pcn_init(xsc) 1126 void *xsc; 1127{ 1128 struct pcn_softc *sc = xsc; 1129 struct ifnet *ifp = &sc->arpcom.ac_if; 1130 struct mii_data *mii = NULL; 1131 1132 PCN_LOCK(sc); 1133 1134 /* 1135 * Cancel pending I/O and free all RX/TX buffers. 1136 */ 1137 pcn_stop(sc); 1138 pcn_reset(sc); 1139 1140 mii = device_get_softc(sc->pcn_miibus); 1141 1142 /* Set MAC address */ 1143 pcn_csr_write(sc, PCN_CSR_PAR0, 1144 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1145 pcn_csr_write(sc, PCN_CSR_PAR1, 1146 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1147 pcn_csr_write(sc, PCN_CSR_PAR2, 1148 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1149 1150 /* Init circular RX list. */ 1151 if (pcn_list_rx_init(sc) == ENOBUFS) { 1152 printf("pcn%d: initialization failed: no " 1153 "memory for rx buffers\n", sc->pcn_unit); 1154 pcn_stop(sc); 1155 PCN_UNLOCK(sc); 1156 return; 1157 } 1158 1159 /* 1160 * Init tx descriptors. 1161 */ 1162 pcn_list_tx_init(sc); 1163 1164 /* Set up the mode register. */ 1165 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1166 1167 /* Set up RX filter. */ 1168 pcn_setfilt(ifp); 1169 1170 /* 1171 * Load the multicast filter. 1172 */ 1173 pcn_setmulti(sc); 1174 1175 /* 1176 * Load the addresses of the RX and TX lists. 1177 */ 1178 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1179 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1180 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1181 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1182 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1183 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1184 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1185 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1186 1187 /* Set the RX and TX ring sizes. */ 1188 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1189 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1190 1191 /* We're not using the initialization block. */ 1192 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1193 1194 /* Enable fast suspend mode. */ 1195 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1196 1197 /* 1198 * Enable burst read and write. Also set the no underflow 1199 * bit. This will avoid transmit underruns in certain 1200 * conditions while still providing decent performance. 1201 */ 1202 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1203 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1204 1205 /* Enable graceful recovery from underflow. */ 1206 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1207 1208 /* Enable auto-padding of short TX frames. */ 1209 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1210 1211 /* Disable MII autoneg (we handle this ourselves). */ 1212 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1213 1214 if (sc->pcn_type == Am79C978) 1215 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1216 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1217 1218 /* Enable interrupts and start the controller running. */ 1219 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1220 1221 mii_mediachg(mii); 1222 1223 ifp->if_flags |= IFF_RUNNING; 1224 ifp->if_flags &= ~IFF_OACTIVE; 1225 1226 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 1227 PCN_UNLOCK(sc); 1228 1229 return; 1230} 1231 1232/* 1233 * Set media options. 1234 */ 1235static int 1236pcn_ifmedia_upd(ifp) 1237 struct ifnet *ifp; 1238{ 1239 struct pcn_softc *sc; 1240 struct mii_data *mii; 1241 1242 sc = ifp->if_softc; 1243 mii = device_get_softc(sc->pcn_miibus); 1244 1245 sc->pcn_link = 0; 1246 if (mii->mii_instance) { 1247 struct mii_softc *miisc; 1248 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1249 mii_phy_reset(miisc); 1250 } 1251 mii_mediachg(mii); 1252 1253 return(0); 1254} 1255 1256/* 1257 * Report current media status. 1258 */ 1259static void 1260pcn_ifmedia_sts(ifp, ifmr) 1261 struct ifnet *ifp; 1262 struct ifmediareq *ifmr; 1263{ 1264 struct pcn_softc *sc; 1265 struct mii_data *mii; 1266 1267 sc = ifp->if_softc; 1268 1269 mii = device_get_softc(sc->pcn_miibus); 1270 mii_pollstat(mii); 1271 ifmr->ifm_active = mii->mii_media_active; 1272 ifmr->ifm_status = mii->mii_media_status; 1273 1274 return; 1275} 1276 1277static int 1278pcn_ioctl(ifp, command, data) 1279 struct ifnet *ifp; 1280 u_long command; 1281 caddr_t data; 1282{ 1283 struct pcn_softc *sc = ifp->if_softc; 1284 struct ifreq *ifr = (struct ifreq *) data; 1285 struct mii_data *mii = NULL; 1286 int error = 0; 1287 1288 PCN_LOCK(sc); 1289 1290 switch(command) { 1291 case SIOCSIFFLAGS: 1292 if (ifp->if_flags & IFF_UP) { 1293 if (ifp->if_flags & IFF_RUNNING && 1294 ifp->if_flags & IFF_PROMISC && 1295 !(sc->pcn_if_flags & IFF_PROMISC)) { 1296 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1297 PCN_EXTCTL1_SPND); 1298 pcn_setfilt(ifp); 1299 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1300 PCN_EXTCTL1_SPND); 1301 pcn_csr_write(sc, PCN_CSR_CSR, 1302 PCN_CSR_INTEN|PCN_CSR_START); 1303 } else if (ifp->if_flags & IFF_RUNNING && 1304 !(ifp->if_flags & IFF_PROMISC) && 1305 sc->pcn_if_flags & IFF_PROMISC) { 1306 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1307 PCN_EXTCTL1_SPND); 1308 pcn_setfilt(ifp); 1309 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1310 PCN_EXTCTL1_SPND); 1311 pcn_csr_write(sc, PCN_CSR_CSR, 1312 PCN_CSR_INTEN|PCN_CSR_START); 1313 } else if (!(ifp->if_flags & IFF_RUNNING)) 1314 pcn_init(sc); 1315 } else { 1316 if (ifp->if_flags & IFF_RUNNING) 1317 pcn_stop(sc); 1318 } 1319 sc->pcn_if_flags = ifp->if_flags; 1320 error = 0; 1321 break; 1322 case SIOCADDMULTI: 1323 case SIOCDELMULTI: 1324 pcn_setmulti(sc); 1325 error = 0; 1326 break; 1327 case SIOCGIFMEDIA: 1328 case SIOCSIFMEDIA: 1329 mii = device_get_softc(sc->pcn_miibus); 1330 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1331 break; 1332 default: 1333 error = ether_ioctl(ifp, command, data); 1334 break; 1335 } 1336 1337 PCN_UNLOCK(sc); 1338 1339 return(error); 1340} 1341 1342static void 1343pcn_watchdog(ifp) 1344 struct ifnet *ifp; 1345{ 1346 struct pcn_softc *sc; 1347 1348 sc = ifp->if_softc; 1349 1350 PCN_LOCK(sc); 1351 1352 ifp->if_oerrors++; 1353 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1354 1355 pcn_stop(sc); 1356 pcn_reset(sc); 1357 pcn_init(sc); 1358 1359 if (ifp->if_snd.ifq_head != NULL) 1360 pcn_start(ifp); 1361 1362 PCN_UNLOCK(sc); 1363 1364 return; 1365} 1366 1367/* 1368 * Stop the adapter and free any mbufs allocated to the 1369 * RX and TX lists. 1370 */ 1371static void 1372pcn_stop(sc) 1373 struct pcn_softc *sc; 1374{ 1375 register int i; 1376 struct ifnet *ifp; 1377 1378 ifp = &sc->arpcom.ac_if; 1379 PCN_LOCK(sc); 1380 ifp->if_timer = 0; 1381 1382 untimeout(pcn_tick, sc, sc->pcn_stat_ch); 1383 1384 /* Turn off interrupts */ 1385 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN); 1386 /* Stop adapter */ 1387 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1388 sc->pcn_link = 0; 1389 1390 /* 1391 * Free data in the RX lists. 1392 */ 1393 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1394 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1395 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1396 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1397 } 1398 } 1399 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1400 sizeof(sc->pcn_ldata->pcn_rx_list)); 1401 1402 /* 1403 * Free the TX list buffers. 1404 */ 1405 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1406 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1407 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1408 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1409 } 1410 } 1411 1412 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1413 sizeof(sc->pcn_ldata->pcn_tx_list)); 1414 1415 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1416 PCN_UNLOCK(sc); 1417 1418 return; 1419} 1420 1421/* 1422 * Stop all chip I/O so that the kernel's probe routines don't 1423 * get confused by errant DMAs when rebooting. 1424 */ 1425static void 1426pcn_shutdown(dev) 1427 device_t dev; 1428{ 1429 struct pcn_softc *sc; 1430 1431 sc = device_get_softc(dev); 1432 1433 PCN_LOCK(sc); 1434 pcn_reset(sc); 1435 pcn_stop(sc); 1436 PCN_UNLOCK(sc); 1437 1438 return; 1439} 1440