if_pcn.c revision 113609
1/* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34/* 35 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 36 * from http://www.amd.com. 37 * 38 * The AMD PCnet/PCI controllers are more advanced and functional 39 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 40 * backwards compatibility with the LANCE and thus can be made 41 * to work with older LANCE drivers. This is in fact how the 42 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 43 * is that the PCnet/PCI devices offer several performance enhancements 44 * which can't be exploited in LANCE compatibility mode. Chief among 45 * these enhancements is the ability to perform PCI DMA operations 46 * using 32-bit addressing (which eliminates the need for ISA 47 * bounce-buffering), and special receive buffer alignment (which 48 * allows the receive handler to pass packets to the upper protocol 49 * layers without copying on both the x86 and alpha platforms). 50 */ 51 52#include <sys/cdefs.h> 53__FBSDID("$FreeBSD: head/sys/pci/if_pcn.c 113609 2003-04-17 20:32:06Z njl $"); 54 55#include <sys/param.h> 56#include <sys/systm.h> 57#include <sys/sockio.h> 58#include <sys/mbuf.h> 59#include <sys/malloc.h> 60#include <sys/kernel.h> 61#include <sys/socket.h> 62 63#include <net/if.h> 64#include <net/if_arp.h> 65#include <net/ethernet.h> 66#include <net/if_dl.h> 67#include <net/if_media.h> 68 69#include <net/bpf.h> 70 71#include <vm/vm.h> /* for vtophys */ 72#include <vm/pmap.h> /* for vtophys */ 73#include <machine/bus_pio.h> 74#include <machine/bus_memio.h> 75#include <machine/bus.h> 76#include <machine/resource.h> 77#include <sys/bus.h> 78#include <sys/rman.h> 79 80#include <dev/mii/mii.h> 81#include <dev/mii/miivar.h> 82 83#include <pci/pcireg.h> 84#include <pci/pcivar.h> 85 86#define PCN_USEIOSPACE 87 88#include <pci/if_pcnreg.h> 89 90MODULE_DEPEND(pcn, pci, 1, 1, 1); 91MODULE_DEPEND(pcn, ether, 1, 1, 1); 92MODULE_DEPEND(pcn, miibus, 1, 1, 1); 93 94/* "controller miibus0" required. See GENERIC if you get errors here. */ 95#include "miibus_if.h" 96 97/* 98 * Various supported device vendors/types and their names. 99 */ 100static struct pcn_type pcn_devs[] = { 101 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 102 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 103 { 0, 0, NULL } 104}; 105 106static u_int32_t pcn_csr_read (struct pcn_softc *, int); 107static u_int16_t pcn_csr_read16 (struct pcn_softc *, int); 108static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int); 109static void pcn_csr_write (struct pcn_softc *, int, int); 110static u_int32_t pcn_bcr_read (struct pcn_softc *, int); 111static void pcn_bcr_write (struct pcn_softc *, int, int); 112 113static int pcn_probe (device_t); 114static int pcn_attach (device_t); 115static int pcn_detach (device_t); 116 117static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *); 118static int pcn_encap (struct pcn_softc *, 119 struct mbuf *, u_int32_t *); 120static void pcn_rxeof (struct pcn_softc *); 121static void pcn_txeof (struct pcn_softc *); 122static void pcn_intr (void *); 123static void pcn_tick (void *); 124static void pcn_start (struct ifnet *); 125static int pcn_ioctl (struct ifnet *, u_long, caddr_t); 126static void pcn_init (void *); 127static void pcn_stop (struct pcn_softc *); 128static void pcn_watchdog (struct ifnet *); 129static void pcn_shutdown (device_t); 130static int pcn_ifmedia_upd (struct ifnet *); 131static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *); 132 133static int pcn_miibus_readreg (device_t, int, int); 134static int pcn_miibus_writereg (device_t, int, int, int); 135static void pcn_miibus_statchg (device_t); 136 137static void pcn_setfilt (struct ifnet *); 138static void pcn_setmulti (struct pcn_softc *); 139static u_int32_t pcn_crc (caddr_t); 140static void pcn_reset (struct pcn_softc *); 141static int pcn_list_rx_init (struct pcn_softc *); 142static int pcn_list_tx_init (struct pcn_softc *); 143 144#ifdef PCN_USEIOSPACE 145#define PCN_RES SYS_RES_IOPORT 146#define PCN_RID PCN_PCI_LOIO 147#else 148#define PCN_RES SYS_RES_MEMORY 149#define PCN_RID PCN_PCI_LOMEM 150#endif 151 152static device_method_t pcn_methods[] = { 153 /* Device interface */ 154 DEVMETHOD(device_probe, pcn_probe), 155 DEVMETHOD(device_attach, pcn_attach), 156 DEVMETHOD(device_detach, pcn_detach), 157 DEVMETHOD(device_shutdown, pcn_shutdown), 158 159 /* bus interface */ 160 DEVMETHOD(bus_print_child, bus_generic_print_child), 161 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 162 163 /* MII interface */ 164 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 165 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 166 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 167 168 { 0, 0 } 169}; 170 171static driver_t pcn_driver = { 172 "pcn", 173 pcn_methods, 174 sizeof(struct pcn_softc) 175}; 176 177static devclass_t pcn_devclass; 178 179DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0); 180DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 181 182#define PCN_CSR_SETBIT(sc, reg, x) \ 183 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 184 185#define PCN_CSR_CLRBIT(sc, reg, x) \ 186 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 187 188#define PCN_BCR_SETBIT(sc, reg, x) \ 189 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 190 191#define PCN_BCR_CLRBIT(sc, reg, x) \ 192 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 193 194static u_int32_t 195pcn_csr_read(sc, reg) 196 struct pcn_softc *sc; 197 int reg; 198{ 199 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 200 return(CSR_READ_4(sc, PCN_IO32_RDP)); 201} 202 203static u_int16_t 204pcn_csr_read16(sc, reg) 205 struct pcn_softc *sc; 206 int reg; 207{ 208 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 209 return(CSR_READ_2(sc, PCN_IO16_RDP)); 210} 211 212static void 213pcn_csr_write(sc, reg, val) 214 struct pcn_softc *sc; 215 int reg; 216{ 217 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 218 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 219 return; 220} 221 222static u_int32_t 223pcn_bcr_read(sc, reg) 224 struct pcn_softc *sc; 225 int reg; 226{ 227 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 228 return(CSR_READ_4(sc, PCN_IO32_BDP)); 229} 230 231static u_int16_t 232pcn_bcr_read16(sc, reg) 233 struct pcn_softc *sc; 234 int reg; 235{ 236 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 237 return(CSR_READ_2(sc, PCN_IO16_BDP)); 238} 239 240static void 241pcn_bcr_write(sc, reg, val) 242 struct pcn_softc *sc; 243 int reg; 244{ 245 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 246 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 247 return; 248} 249 250static int 251pcn_miibus_readreg(dev, phy, reg) 252 device_t dev; 253 int phy, reg; 254{ 255 struct pcn_softc *sc; 256 int val; 257 258 sc = device_get_softc(dev); 259 260 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 261 return(0); 262 263 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 264 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 265 if (val == 0xFFFF) 266 return(0); 267 268 sc->pcn_phyaddr = phy; 269 270 return(val); 271} 272 273static int 274pcn_miibus_writereg(dev, phy, reg, data) 275 device_t dev; 276 int phy, reg, data; 277{ 278 struct pcn_softc *sc; 279 280 sc = device_get_softc(dev); 281 282 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 283 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 284 285 return(0); 286} 287 288static void 289pcn_miibus_statchg(dev) 290 device_t dev; 291{ 292 struct pcn_softc *sc; 293 struct mii_data *mii; 294 295 sc = device_get_softc(dev); 296 mii = device_get_softc(sc->pcn_miibus); 297 298 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 299 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 300 } else { 301 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 302 } 303 304 return; 305} 306 307#define DC_POLY 0xEDB88320 308 309static u_int32_t 310pcn_crc(addr) 311 caddr_t addr; 312{ 313 u_int32_t idx, bit, data, crc; 314 315 /* Compute CRC for the address value. */ 316 crc = 0xFFFFFFFF; /* initial value */ 317 318 for (idx = 0; idx < 6; idx++) { 319 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 320 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 321 } 322 323 return ((crc >> 26) & 0x3F); 324} 325 326static void 327pcn_setmulti(sc) 328 struct pcn_softc *sc; 329{ 330 struct ifnet *ifp; 331 struct ifmultiaddr *ifma; 332 u_int32_t h, i; 333 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 334 335 ifp = &sc->arpcom.ac_if; 336 337 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 338 339 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 340 for (i = 0; i < 4; i++) 341 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 342 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 343 return; 344 } 345 346 /* first, zot all the existing hash bits */ 347 for (i = 0; i < 4; i++) 348 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 349 350 /* now program new ones */ 351 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 352 if (ifma->ifma_addr->sa_family != AF_LINK) 353 continue; 354 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 355 hashes[h >> 4] |= 1 << (h & 0xF); 356 } 357 358 for (i = 0; i < 4; i++) 359 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 360 361 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 362 363 return; 364} 365 366static void 367pcn_reset(sc) 368 struct pcn_softc *sc; 369{ 370 /* 371 * Issue a reset by reading from the RESET register. 372 * Note that we don't know if the chip is operating in 373 * 16-bit or 32-bit mode at this point, so we attempt 374 * to reset the chip both ways. If one fails, the other 375 * will succeed. 376 */ 377 CSR_READ_2(sc, PCN_IO16_RESET); 378 CSR_READ_4(sc, PCN_IO32_RESET); 379 380 /* Wait a little while for the chip to get its brains in order. */ 381 DELAY(1000); 382 383 /* Select 32-bit (DWIO) mode */ 384 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 385 386 /* Select software style 3. */ 387 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 388 389 return; 390} 391 392/* 393 * Probe for an AMD chip. Check the PCI vendor and device 394 * IDs against our list and return a device name if we find a match. 395 */ 396static int 397pcn_probe(dev) 398 device_t dev; 399{ 400 struct pcn_type *t; 401 struct pcn_softc *sc; 402 int rid; 403 u_int32_t chip_id; 404 405 t = pcn_devs; 406 sc = device_get_softc(dev); 407 408 while(t->pcn_name != NULL) { 409 if ((pci_get_vendor(dev) == t->pcn_vid) && 410 (pci_get_device(dev) == t->pcn_did)) { 411 /* 412 * Temporarily map the I/O space 413 * so we can read the chip ID register. 414 */ 415 rid = PCN_RID; 416 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 417 0, ~0, 1, RF_ACTIVE); 418 if (sc->pcn_res == NULL) { 419 device_printf(dev, 420 "couldn't map ports/memory\n"); 421 return(ENXIO); 422 } 423 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 424 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 425 mtx_init(&sc->pcn_mtx, 426 device_get_nameunit(dev), MTX_NETWORK_LOCK, 427 MTX_DEF); 428 PCN_LOCK(sc); 429 /* 430 * Note: we can *NOT* put the chip into 431 * 32-bit mode yet. The lnc driver will only 432 * work in 16-bit mode, and once the chip 433 * goes into 32-bit mode, the only way to 434 * get it out again is with a hardware reset. 435 * So if pcn_probe() is called before the 436 * lnc driver's probe routine, the chip will 437 * be locked into 32-bit operation and the lnc 438 * driver will be unable to attach to it. 439 * Note II: if the chip happens to already 440 * be in 32-bit mode, we still need to check 441 * the chip ID, but first we have to detect 442 * 32-bit mode using only 16-bit operations. 443 * The safest way to do this is to read the 444 * PCI subsystem ID from BCR23/24 and compare 445 * that with the value read from PCI config 446 * space. 447 */ 448 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 449 chip_id <<= 16; 450 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 451 /* 452 * Note III: the test for 0x10001000 is a hack to 453 * pacify VMware, who's pseudo-PCnet interface is 454 * broken. Reading the subsystem register from PCI 455 * config space yeilds 0x00000000 while reading the 456 * same value from I/O space yeilds 0x10001000. It's 457 * not supposed to be that way. 458 */ 459 if (chip_id == pci_read_config(dev, 460 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 461 /* We're in 16-bit mode. */ 462 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 463 chip_id <<= 16; 464 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 465 } else { 466 /* We're in 32-bit mode. */ 467 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 468 chip_id <<= 16; 469 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 470 } 471 bus_release_resource(dev, PCN_RES, 472 PCN_RID, sc->pcn_res); 473 PCN_UNLOCK(sc); 474 mtx_destroy(&sc->pcn_mtx); 475 chip_id >>= 12; 476 sc->pcn_type = chip_id & PART_MASK; 477 switch(sc->pcn_type) { 478 case Am79C971: 479 case Am79C972: 480 case Am79C973: 481 case Am79C975: 482 case Am79C976: 483 case Am79C978: 484 break; 485 default: 486 return(ENXIO); 487 break; 488 } 489 device_set_desc(dev, t->pcn_name); 490 return(0); 491 } 492 t++; 493 } 494 495 return(ENXIO); 496} 497 498/* 499 * Attach the interface. Allocate softc structures, do ifmedia 500 * setup and ethernet/BPF attach. 501 */ 502static int 503pcn_attach(dev) 504 device_t dev; 505{ 506 u_int32_t eaddr[2]; 507 struct pcn_softc *sc; 508 struct ifnet *ifp; 509 int unit, error = 0, rid; 510 511 sc = device_get_softc(dev); 512 unit = device_get_unit(dev); 513 514 /* Initialize our mutex. */ 515 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 516 MTX_DEF | MTX_RECURSE); 517 518 /* 519 * Handle power management nonsense. 520 */ 521 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 522 u_int32_t iobase, membase, irq; 523 524 /* Save important PCI config data. */ 525 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 526 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 527 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 528 529 /* Reset the power state. */ 530 printf("pcn%d: chip is in D%d power mode " 531 "-- setting to D0\n", unit, 532 pci_get_powerstate(dev)); 533 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 534 535 /* Restore PCI config data. */ 536 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 537 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 538 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 539 } 540 541 /* 542 * Map control/status registers. 543 */ 544 pci_enable_busmaster(dev); 545 546 rid = PCN_RID; 547 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 548 0, ~0, 1, RF_ACTIVE); 549 550 if (sc->pcn_res == NULL) { 551 printf("pcn%d: couldn't map ports/memory\n", unit); 552 error = ENXIO; 553 goto fail; 554 } 555 556 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 557 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 558 559 /* Allocate interrupt */ 560 rid = 0; 561 sc->pcn_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 562 RF_SHAREABLE | RF_ACTIVE); 563 564 if (sc->pcn_irq == NULL) { 565 printf("pcn%d: couldn't map interrupt\n", unit); 566 error = ENXIO; 567 goto fail; 568 } 569 570 /* Reset the adapter. */ 571 pcn_reset(sc); 572 573 /* 574 * Get station address from the EEPROM. 575 */ 576 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 577 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 578 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 579 580 /* 581 * An AMD chip was detected. Inform the world. 582 */ 583 printf("pcn%d: Ethernet address: %6D\n", unit, 584 sc->arpcom.ac_enaddr, ":"); 585 586 sc->pcn_unit = unit; 587 callout_handle_init(&sc->pcn_stat_ch); 588 589 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 590 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 591 592 if (sc->pcn_ldata == NULL) { 593 printf("pcn%d: no memory for list buffers!\n", unit); 594 error = ENXIO; 595 goto fail; 596 } 597 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 598 599 ifp = &sc->arpcom.ac_if; 600 ifp->if_softc = sc; 601 ifp->if_unit = unit; 602 ifp->if_name = "pcn"; 603 ifp->if_mtu = ETHERMTU; 604 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 605 ifp->if_ioctl = pcn_ioctl; 606 ifp->if_output = ether_output; 607 ifp->if_start = pcn_start; 608 ifp->if_watchdog = pcn_watchdog; 609 ifp->if_init = pcn_init; 610 ifp->if_baudrate = 10000000; 611 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 612 613 /* 614 * Do MII setup. 615 */ 616 if (mii_phy_probe(dev, &sc->pcn_miibus, 617 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 618 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 619 error = ENXIO; 620 goto fail; 621 } 622 623 /* 624 * Call MI attach routine. 625 */ 626 ether_ifattach(ifp, (u_int8_t *) eaddr); 627 628 /* Hook interrupt last to avoid having to lock softc */ 629 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 630 pcn_intr, sc, &sc->pcn_intrhand); 631 632 if (error) { 633 printf("pcn%d: couldn't set up irq\n", unit); 634 ether_ifdetach(ifp); 635 goto fail; 636 } 637 638fail: 639 if (error) 640 pcn_detach(dev); 641 642 return(error); 643} 644 645/* 646 * Shutdown hardware and free up resources. This can be called any 647 * time after the mutex has been initialized. It is called in both 648 * the error case in attach and the normal detach case so it needs 649 * to be careful about only freeing resources that have actually been 650 * allocated. 651 */ 652static int 653pcn_detach(dev) 654 device_t dev; 655{ 656 struct pcn_softc *sc; 657 struct ifnet *ifp; 658 659 sc = device_get_softc(dev); 660 ifp = &sc->arpcom.ac_if; 661 662 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized")); 663 PCN_LOCK(sc); 664 665 /* These should only be active if attach succeeded */ 666 if (device_is_alive(dev)) { 667 pcn_reset(sc); 668 pcn_stop(sc); 669 ether_ifdetach(ifp); 670 } 671 if (sc->pcn_miibus) 672 device_delete_child(dev, sc->pcn_miibus); 673 bus_generic_detach(dev); 674 675 if (sc->pcn_intrhand) 676 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 677 if (sc->pcn_irq) 678 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 679 if (sc->pcn_res) 680 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 681 682 if (sc->pcn_ldata) { 683 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 684 M_DEVBUF); 685 } 686 PCN_UNLOCK(sc); 687 688 mtx_destroy(&sc->pcn_mtx); 689 690 return(0); 691} 692 693/* 694 * Initialize the transmit descriptors. 695 */ 696static int 697pcn_list_tx_init(sc) 698 struct pcn_softc *sc; 699{ 700 struct pcn_list_data *ld; 701 struct pcn_ring_data *cd; 702 int i; 703 704 cd = &sc->pcn_cdata; 705 ld = sc->pcn_ldata; 706 707 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 708 cd->pcn_tx_chain[i] = NULL; 709 ld->pcn_tx_list[i].pcn_tbaddr = 0; 710 ld->pcn_tx_list[i].pcn_txctl = 0; 711 ld->pcn_tx_list[i].pcn_txstat = 0; 712 } 713 714 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 715 716 return(0); 717} 718 719 720/* 721 * Initialize the RX descriptors and allocate mbufs for them. 722 */ 723static int 724pcn_list_rx_init(sc) 725 struct pcn_softc *sc; 726{ 727 struct pcn_list_data *ld; 728 struct pcn_ring_data *cd; 729 int i; 730 731 ld = sc->pcn_ldata; 732 cd = &sc->pcn_cdata; 733 734 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 735 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 736 return(ENOBUFS); 737 } 738 739 cd->pcn_rx_prod = 0; 740 741 return(0); 742} 743 744/* 745 * Initialize an RX descriptor and attach an MBUF cluster. 746 */ 747static int 748pcn_newbuf(sc, idx, m) 749 struct pcn_softc *sc; 750 int idx; 751 struct mbuf *m; 752{ 753 struct mbuf *m_new = NULL; 754 struct pcn_rx_desc *c; 755 756 c = &sc->pcn_ldata->pcn_rx_list[idx]; 757 758 if (m == NULL) { 759 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 760 if (m_new == NULL) 761 return(ENOBUFS); 762 763 MCLGET(m_new, M_DONTWAIT); 764 if (!(m_new->m_flags & M_EXT)) { 765 m_freem(m_new); 766 return(ENOBUFS); 767 } 768 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 769 } else { 770 m_new = m; 771 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 772 m_new->m_data = m_new->m_ext.ext_buf; 773 } 774 775 m_adj(m_new, ETHER_ALIGN); 776 777 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 778 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 779 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 780 c->pcn_bufsz |= PCN_RXLEN_MBO; 781 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 782 783 return(0); 784} 785 786/* 787 * A frame has been uploaded: pass the resulting mbuf chain up to 788 * the higher level protocols. 789 */ 790static void 791pcn_rxeof(sc) 792 struct pcn_softc *sc; 793{ 794 struct ether_header *eh; 795 struct mbuf *m; 796 struct ifnet *ifp; 797 struct pcn_rx_desc *cur_rx; 798 int i; 799 800 ifp = &sc->arpcom.ac_if; 801 i = sc->pcn_cdata.pcn_rx_prod; 802 803 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 804 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 805 m = sc->pcn_cdata.pcn_rx_chain[i]; 806 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 807 808 /* 809 * If an error occurs, update stats, clear the 810 * status word and leave the mbuf cluster in place: 811 * it should simply get re-used next time this descriptor 812 * comes up in the ring. 813 */ 814 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 815 ifp->if_ierrors++; 816 pcn_newbuf(sc, i, m); 817 PCN_INC(i, PCN_RX_LIST_CNT); 818 continue; 819 } 820 821 if (pcn_newbuf(sc, i, NULL)) { 822 /* Ran out of mbufs; recycle this one. */ 823 pcn_newbuf(sc, i, m); 824 ifp->if_ierrors++; 825 PCN_INC(i, PCN_RX_LIST_CNT); 826 continue; 827 } 828 829 PCN_INC(i, PCN_RX_LIST_CNT); 830 831 /* No errors; receive the packet. */ 832 ifp->if_ipackets++; 833 eh = mtod(m, struct ether_header *); 834 m->m_len = m->m_pkthdr.len = 835 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 836 m->m_pkthdr.rcvif = ifp; 837 838 (*ifp->if_input)(ifp, m); 839 } 840 841 sc->pcn_cdata.pcn_rx_prod = i; 842 843 return; 844} 845 846/* 847 * A frame was downloaded to the chip. It's safe for us to clean up 848 * the list buffers. 849 */ 850 851static void 852pcn_txeof(sc) 853 struct pcn_softc *sc; 854{ 855 struct pcn_tx_desc *cur_tx = NULL; 856 struct ifnet *ifp; 857 u_int32_t idx; 858 859 ifp = &sc->arpcom.ac_if; 860 861 /* 862 * Go through our tx list and free mbufs for those 863 * frames that have been transmitted. 864 */ 865 idx = sc->pcn_cdata.pcn_tx_cons; 866 while (idx != sc->pcn_cdata.pcn_tx_prod) { 867 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 868 869 if (!PCN_OWN_TXDESC(cur_tx)) 870 break; 871 872 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 873 sc->pcn_cdata.pcn_tx_cnt--; 874 PCN_INC(idx, PCN_TX_LIST_CNT); 875 continue; 876 } 877 878 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 879 ifp->if_oerrors++; 880 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 881 ifp->if_collisions++; 882 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 883 ifp->if_collisions++; 884 } 885 886 ifp->if_collisions += 887 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 888 889 ifp->if_opackets++; 890 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 891 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 892 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 893 } 894 895 sc->pcn_cdata.pcn_tx_cnt--; 896 PCN_INC(idx, PCN_TX_LIST_CNT); 897 } 898 899 if (idx != sc->pcn_cdata.pcn_tx_cons) { 900 /* Some buffers have been freed. */ 901 sc->pcn_cdata.pcn_tx_cons = idx; 902 ifp->if_flags &= ~IFF_OACTIVE; 903 } 904 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 905 906 return; 907} 908 909static void 910pcn_tick(xsc) 911 void *xsc; 912{ 913 struct pcn_softc *sc; 914 struct mii_data *mii; 915 struct ifnet *ifp; 916 917 sc = xsc; 918 ifp = &sc->arpcom.ac_if; 919 PCN_LOCK(sc); 920 921 mii = device_get_softc(sc->pcn_miibus); 922 mii_tick(mii); 923 924 /* link just died */ 925 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 926 sc->pcn_link = 0; 927 928 /* link just came up, restart */ 929 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE && 930 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 931 sc->pcn_link++; 932 if (ifp->if_snd.ifq_head != NULL) 933 pcn_start(ifp); 934 } 935 936 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 937 938 PCN_UNLOCK(sc); 939 940 return; 941} 942 943static void 944pcn_intr(arg) 945 void *arg; 946{ 947 struct pcn_softc *sc; 948 struct ifnet *ifp; 949 u_int32_t status; 950 951 sc = arg; 952 ifp = &sc->arpcom.ac_if; 953 954 /* Supress unwanted interrupts */ 955 if (!(ifp->if_flags & IFF_UP)) { 956 pcn_stop(sc); 957 return; 958 } 959 960 PCN_LOCK(sc); 961 962 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 963 964 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 965 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 966 967 if (status & PCN_CSR_RINT) 968 pcn_rxeof(sc); 969 970 if (status & PCN_CSR_TINT) 971 pcn_txeof(sc); 972 973 if (status & PCN_CSR_ERR) { 974 pcn_init(sc); 975 break; 976 } 977 } 978 979 if (ifp->if_snd.ifq_head != NULL) 980 pcn_start(ifp); 981 982 PCN_UNLOCK(sc); 983 return; 984} 985 986/* 987 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 988 * pointers to the fragment pointers. 989 */ 990static int 991pcn_encap(sc, m_head, txidx) 992 struct pcn_softc *sc; 993 struct mbuf *m_head; 994 u_int32_t *txidx; 995{ 996 struct pcn_tx_desc *f = NULL; 997 struct mbuf *m; 998 int frag, cur, cnt = 0; 999 1000 /* 1001 * Start packing the mbufs in this chain into 1002 * the fragment pointers. Stop when we run out 1003 * of fragments or hit the end of the mbuf chain. 1004 */ 1005 m = m_head; 1006 cur = frag = *txidx; 1007 1008 for (m = m_head; m != NULL; m = m->m_next) { 1009 if (m->m_len != 0) { 1010 if ((PCN_TX_LIST_CNT - 1011 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 1012 return(ENOBUFS); 1013 f = &sc->pcn_ldata->pcn_tx_list[frag]; 1014 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 1015 f->pcn_txctl |= PCN_TXCTL_MBO; 1016 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 1017 if (cnt == 0) 1018 f->pcn_txctl |= PCN_TXCTL_STP; 1019 else 1020 f->pcn_txctl |= PCN_TXCTL_OWN; 1021 cur = frag; 1022 PCN_INC(frag, PCN_TX_LIST_CNT); 1023 cnt++; 1024 } 1025 } 1026 1027 if (m != NULL) 1028 return(ENOBUFS); 1029 1030 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1031 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1032 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1033 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1034 sc->pcn_cdata.pcn_tx_cnt += cnt; 1035 *txidx = frag; 1036 1037 return(0); 1038} 1039 1040/* 1041 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1042 * to the mbuf data regions directly in the transmit lists. We also save a 1043 * copy of the pointers since the transmit list fragment pointers are 1044 * physical addresses. 1045 */ 1046static void 1047pcn_start(ifp) 1048 struct ifnet *ifp; 1049{ 1050 struct pcn_softc *sc; 1051 struct mbuf *m_head = NULL; 1052 u_int32_t idx; 1053 1054 sc = ifp->if_softc; 1055 1056 PCN_LOCK(sc); 1057 1058 if (!sc->pcn_link) { 1059 PCN_UNLOCK(sc); 1060 return; 1061 } 1062 1063 idx = sc->pcn_cdata.pcn_tx_prod; 1064 1065 if (ifp->if_flags & IFF_OACTIVE) { 1066 PCN_UNLOCK(sc); 1067 return; 1068 } 1069 1070 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1071 IF_DEQUEUE(&ifp->if_snd, m_head); 1072 if (m_head == NULL) 1073 break; 1074 1075 if (pcn_encap(sc, m_head, &idx)) { 1076 IF_PREPEND(&ifp->if_snd, m_head); 1077 ifp->if_flags |= IFF_OACTIVE; 1078 break; 1079 } 1080 1081 /* 1082 * If there's a BPF listener, bounce a copy of this frame 1083 * to him. 1084 */ 1085 BPF_MTAP(ifp, m_head); 1086 1087 } 1088 1089 /* Transmit */ 1090 sc->pcn_cdata.pcn_tx_prod = idx; 1091 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1092 1093 /* 1094 * Set a timeout in case the chip goes out to lunch. 1095 */ 1096 ifp->if_timer = 5; 1097 1098 PCN_UNLOCK(sc); 1099 1100 return; 1101} 1102 1103static void 1104pcn_setfilt(ifp) 1105 struct ifnet *ifp; 1106{ 1107 struct pcn_softc *sc; 1108 1109 sc = ifp->if_softc; 1110 1111 /* If we want promiscuous mode, set the allframes bit. */ 1112 if (ifp->if_flags & IFF_PROMISC) { 1113 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1114 } else { 1115 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1116 } 1117 1118 /* Set the capture broadcast bit to capture broadcast frames. */ 1119 if (ifp->if_flags & IFF_BROADCAST) { 1120 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1121 } else { 1122 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1123 } 1124 1125 return; 1126} 1127 1128static void 1129pcn_init(xsc) 1130 void *xsc; 1131{ 1132 struct pcn_softc *sc = xsc; 1133 struct ifnet *ifp = &sc->arpcom.ac_if; 1134 struct mii_data *mii = NULL; 1135 1136 PCN_LOCK(sc); 1137 1138 /* 1139 * Cancel pending I/O and free all RX/TX buffers. 1140 */ 1141 pcn_stop(sc); 1142 pcn_reset(sc); 1143 1144 mii = device_get_softc(sc->pcn_miibus); 1145 1146 /* Set MAC address */ 1147 pcn_csr_write(sc, PCN_CSR_PAR0, 1148 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1149 pcn_csr_write(sc, PCN_CSR_PAR1, 1150 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1151 pcn_csr_write(sc, PCN_CSR_PAR2, 1152 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1153 1154 /* Init circular RX list. */ 1155 if (pcn_list_rx_init(sc) == ENOBUFS) { 1156 printf("pcn%d: initialization failed: no " 1157 "memory for rx buffers\n", sc->pcn_unit); 1158 pcn_stop(sc); 1159 PCN_UNLOCK(sc); 1160 return; 1161 } 1162 1163 /* 1164 * Init tx descriptors. 1165 */ 1166 pcn_list_tx_init(sc); 1167 1168 /* Set up the mode register. */ 1169 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1170 1171 /* Set up RX filter. */ 1172 pcn_setfilt(ifp); 1173 1174 /* 1175 * Load the multicast filter. 1176 */ 1177 pcn_setmulti(sc); 1178 1179 /* 1180 * Load the addresses of the RX and TX lists. 1181 */ 1182 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1183 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1184 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1185 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1186 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1187 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1188 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1189 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1190 1191 /* Set the RX and TX ring sizes. */ 1192 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1193 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1194 1195 /* We're not using the initialization block. */ 1196 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1197 1198 /* Enable fast suspend mode. */ 1199 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1200 1201 /* 1202 * Enable burst read and write. Also set the no underflow 1203 * bit. This will avoid transmit underruns in certain 1204 * conditions while still providing decent performance. 1205 */ 1206 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1207 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1208 1209 /* Enable graceful recovery from underflow. */ 1210 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1211 1212 /* Enable auto-padding of short TX frames. */ 1213 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1214 1215 /* Disable MII autoneg (we handle this ourselves). */ 1216 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1217 1218 if (sc->pcn_type == Am79C978) 1219 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1220 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1221 1222 /* Enable interrupts and start the controller running. */ 1223 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1224 1225 mii_mediachg(mii); 1226 1227 ifp->if_flags |= IFF_RUNNING; 1228 ifp->if_flags &= ~IFF_OACTIVE; 1229 1230 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 1231 PCN_UNLOCK(sc); 1232 1233 return; 1234} 1235 1236/* 1237 * Set media options. 1238 */ 1239static int 1240pcn_ifmedia_upd(ifp) 1241 struct ifnet *ifp; 1242{ 1243 struct pcn_softc *sc; 1244 struct mii_data *mii; 1245 1246 sc = ifp->if_softc; 1247 mii = device_get_softc(sc->pcn_miibus); 1248 1249 sc->pcn_link = 0; 1250 if (mii->mii_instance) { 1251 struct mii_softc *miisc; 1252 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1253 mii_phy_reset(miisc); 1254 } 1255 mii_mediachg(mii); 1256 1257 return(0); 1258} 1259 1260/* 1261 * Report current media status. 1262 */ 1263static void 1264pcn_ifmedia_sts(ifp, ifmr) 1265 struct ifnet *ifp; 1266 struct ifmediareq *ifmr; 1267{ 1268 struct pcn_softc *sc; 1269 struct mii_data *mii; 1270 1271 sc = ifp->if_softc; 1272 1273 mii = device_get_softc(sc->pcn_miibus); 1274 mii_pollstat(mii); 1275 ifmr->ifm_active = mii->mii_media_active; 1276 ifmr->ifm_status = mii->mii_media_status; 1277 1278 return; 1279} 1280 1281static int 1282pcn_ioctl(ifp, command, data) 1283 struct ifnet *ifp; 1284 u_long command; 1285 caddr_t data; 1286{ 1287 struct pcn_softc *sc = ifp->if_softc; 1288 struct ifreq *ifr = (struct ifreq *) data; 1289 struct mii_data *mii = NULL; 1290 int error = 0; 1291 1292 PCN_LOCK(sc); 1293 1294 switch(command) { 1295 case SIOCSIFFLAGS: 1296 if (ifp->if_flags & IFF_UP) { 1297 if (ifp->if_flags & IFF_RUNNING && 1298 ifp->if_flags & IFF_PROMISC && 1299 !(sc->pcn_if_flags & IFF_PROMISC)) { 1300 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1301 PCN_EXTCTL1_SPND); 1302 pcn_setfilt(ifp); 1303 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1304 PCN_EXTCTL1_SPND); 1305 pcn_csr_write(sc, PCN_CSR_CSR, 1306 PCN_CSR_INTEN|PCN_CSR_START); 1307 } else if (ifp->if_flags & IFF_RUNNING && 1308 !(ifp->if_flags & IFF_PROMISC) && 1309 sc->pcn_if_flags & IFF_PROMISC) { 1310 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1311 PCN_EXTCTL1_SPND); 1312 pcn_setfilt(ifp); 1313 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1314 PCN_EXTCTL1_SPND); 1315 pcn_csr_write(sc, PCN_CSR_CSR, 1316 PCN_CSR_INTEN|PCN_CSR_START); 1317 } else if (!(ifp->if_flags & IFF_RUNNING)) 1318 pcn_init(sc); 1319 } else { 1320 if (ifp->if_flags & IFF_RUNNING) 1321 pcn_stop(sc); 1322 } 1323 sc->pcn_if_flags = ifp->if_flags; 1324 error = 0; 1325 break; 1326 case SIOCADDMULTI: 1327 case SIOCDELMULTI: 1328 pcn_setmulti(sc); 1329 error = 0; 1330 break; 1331 case SIOCGIFMEDIA: 1332 case SIOCSIFMEDIA: 1333 mii = device_get_softc(sc->pcn_miibus); 1334 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1335 break; 1336 default: 1337 error = ether_ioctl(ifp, command, data); 1338 break; 1339 } 1340 1341 PCN_UNLOCK(sc); 1342 1343 return(error); 1344} 1345 1346static void 1347pcn_watchdog(ifp) 1348 struct ifnet *ifp; 1349{ 1350 struct pcn_softc *sc; 1351 1352 sc = ifp->if_softc; 1353 1354 PCN_LOCK(sc); 1355 1356 ifp->if_oerrors++; 1357 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1358 1359 pcn_stop(sc); 1360 pcn_reset(sc); 1361 pcn_init(sc); 1362 1363 if (ifp->if_snd.ifq_head != NULL) 1364 pcn_start(ifp); 1365 1366 PCN_UNLOCK(sc); 1367 1368 return; 1369} 1370 1371/* 1372 * Stop the adapter and free any mbufs allocated to the 1373 * RX and TX lists. 1374 */ 1375static void 1376pcn_stop(sc) 1377 struct pcn_softc *sc; 1378{ 1379 register int i; 1380 struct ifnet *ifp; 1381 1382 ifp = &sc->arpcom.ac_if; 1383 PCN_LOCK(sc); 1384 ifp->if_timer = 0; 1385 1386 untimeout(pcn_tick, sc, sc->pcn_stat_ch); 1387 1388 /* Turn off interrupts */ 1389 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN); 1390 /* Stop adapter */ 1391 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1392 sc->pcn_link = 0; 1393 1394 /* 1395 * Free data in the RX lists. 1396 */ 1397 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1398 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1399 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1400 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1401 } 1402 } 1403 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1404 sizeof(sc->pcn_ldata->pcn_rx_list)); 1405 1406 /* 1407 * Free the TX list buffers. 1408 */ 1409 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1410 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1411 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1412 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1413 } 1414 } 1415 1416 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1417 sizeof(sc->pcn_ldata->pcn_tx_list)); 1418 1419 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1420 PCN_UNLOCK(sc); 1421 1422 return; 1423} 1424 1425/* 1426 * Stop all chip I/O so that the kernel's probe routines don't 1427 * get confused by errant DMAs when rebooting. 1428 */ 1429static void 1430pcn_shutdown(dev) 1431 device_t dev; 1432{ 1433 struct pcn_softc *sc; 1434 1435 sc = device_get_softc(dev); 1436 1437 PCN_LOCK(sc); 1438 pcn_reset(sc); 1439 pcn_stop(sc); 1440 PCN_UNLOCK(sc); 1441 1442 return; 1443} 1444