if_pcn.c revision 113545
1/* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34/* 35 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 36 * from http://www.amd.com. 37 * 38 * The AMD PCnet/PCI controllers are more advanced and functional 39 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 40 * backwards compatibility with the LANCE and thus can be made 41 * to work with older LANCE drivers. This is in fact how the 42 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 43 * is that the PCnet/PCI devices offer several performance enhancements 44 * which can't be exploited in LANCE compatibility mode. Chief among 45 * these enhancements is the ability to perform PCI DMA operations 46 * using 32-bit addressing (which eliminates the need for ISA 47 * bounce-buffering), and special receive buffer alignment (which 48 * allows the receive handler to pass packets to the upper protocol 49 * layers without copying on both the x86 and alpha platforms). 50 */ 51 52#include <sys/cdefs.h> 53__FBSDID("$FreeBSD: head/sys/pci/if_pcn.c 113545 2003-04-16 03:16:57Z mdodd $"); 54 55#include <sys/param.h> 56#include <sys/systm.h> 57#include <sys/sockio.h> 58#include <sys/mbuf.h> 59#include <sys/malloc.h> 60#include <sys/kernel.h> 61#include <sys/socket.h> 62 63#include <net/if.h> 64#include <net/if_arp.h> 65#include <net/ethernet.h> 66#include <net/if_dl.h> 67#include <net/if_media.h> 68 69#include <net/bpf.h> 70 71#include <vm/vm.h> /* for vtophys */ 72#include <vm/pmap.h> /* for vtophys */ 73#include <machine/bus_pio.h> 74#include <machine/bus_memio.h> 75#include <machine/bus.h> 76#include <machine/resource.h> 77#include <sys/bus.h> 78#include <sys/rman.h> 79 80#include <dev/mii/mii.h> 81#include <dev/mii/miivar.h> 82 83#include <pci/pcireg.h> 84#include <pci/pcivar.h> 85 86#define PCN_USEIOSPACE 87 88#include <pci/if_pcnreg.h> 89 90MODULE_DEPEND(pcn, pci, 1, 1, 1); 91MODULE_DEPEND(pcn, ether, 1, 1, 1); 92MODULE_DEPEND(pcn, miibus, 1, 1, 1); 93 94/* "controller miibus0" required. See GENERIC if you get errors here. */ 95#include "miibus_if.h" 96 97/* 98 * Various supported device vendors/types and their names. 99 */ 100static struct pcn_type pcn_devs[] = { 101 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 102 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 103 { 0, 0, NULL } 104}; 105 106static u_int32_t pcn_csr_read (struct pcn_softc *, int); 107static u_int16_t pcn_csr_read16 (struct pcn_softc *, int); 108static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int); 109static void pcn_csr_write (struct pcn_softc *, int, int); 110static u_int32_t pcn_bcr_read (struct pcn_softc *, int); 111static void pcn_bcr_write (struct pcn_softc *, int, int); 112 113static int pcn_probe (device_t); 114static int pcn_attach (device_t); 115static int pcn_detach (device_t); 116 117static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *); 118static int pcn_encap (struct pcn_softc *, 119 struct mbuf *, u_int32_t *); 120static void pcn_rxeof (struct pcn_softc *); 121static void pcn_txeof (struct pcn_softc *); 122static void pcn_intr (void *); 123static void pcn_tick (void *); 124static void pcn_start (struct ifnet *); 125static int pcn_ioctl (struct ifnet *, u_long, caddr_t); 126static void pcn_init (void *); 127static void pcn_stop (struct pcn_softc *); 128static void pcn_watchdog (struct ifnet *); 129static void pcn_shutdown (device_t); 130static int pcn_ifmedia_upd (struct ifnet *); 131static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *); 132 133static int pcn_miibus_readreg (device_t, int, int); 134static int pcn_miibus_writereg (device_t, int, int, int); 135static void pcn_miibus_statchg (device_t); 136 137static void pcn_setfilt (struct ifnet *); 138static void pcn_setmulti (struct pcn_softc *); 139static u_int32_t pcn_crc (caddr_t); 140static void pcn_reset (struct pcn_softc *); 141static int pcn_list_rx_init (struct pcn_softc *); 142static int pcn_list_tx_init (struct pcn_softc *); 143 144#ifdef PCN_USEIOSPACE 145#define PCN_RES SYS_RES_IOPORT 146#define PCN_RID PCN_PCI_LOIO 147#else 148#define PCN_RES SYS_RES_MEMORY 149#define PCN_RID PCN_PCI_LOMEM 150#endif 151 152static device_method_t pcn_methods[] = { 153 /* Device interface */ 154 DEVMETHOD(device_probe, pcn_probe), 155 DEVMETHOD(device_attach, pcn_attach), 156 DEVMETHOD(device_detach, pcn_detach), 157 DEVMETHOD(device_shutdown, pcn_shutdown), 158 159 /* bus interface */ 160 DEVMETHOD(bus_print_child, bus_generic_print_child), 161 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 162 163 /* MII interface */ 164 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 165 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 166 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 167 168 { 0, 0 } 169}; 170 171static driver_t pcn_driver = { 172 "pcn", 173 pcn_methods, 174 sizeof(struct pcn_softc) 175}; 176 177static devclass_t pcn_devclass; 178 179DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0); 180DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 181 182#define PCN_CSR_SETBIT(sc, reg, x) \ 183 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 184 185#define PCN_CSR_CLRBIT(sc, reg, x) \ 186 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 187 188#define PCN_BCR_SETBIT(sc, reg, x) \ 189 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 190 191#define PCN_BCR_CLRBIT(sc, reg, x) \ 192 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 193 194static u_int32_t 195pcn_csr_read(sc, reg) 196 struct pcn_softc *sc; 197 int reg; 198{ 199 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 200 return(CSR_READ_4(sc, PCN_IO32_RDP)); 201} 202 203static u_int16_t 204pcn_csr_read16(sc, reg) 205 struct pcn_softc *sc; 206 int reg; 207{ 208 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 209 return(CSR_READ_2(sc, PCN_IO16_RDP)); 210} 211 212static void 213pcn_csr_write(sc, reg, val) 214 struct pcn_softc *sc; 215 int reg; 216{ 217 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 218 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 219 return; 220} 221 222static u_int32_t 223pcn_bcr_read(sc, reg) 224 struct pcn_softc *sc; 225 int reg; 226{ 227 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 228 return(CSR_READ_4(sc, PCN_IO32_BDP)); 229} 230 231static u_int16_t 232pcn_bcr_read16(sc, reg) 233 struct pcn_softc *sc; 234 int reg; 235{ 236 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 237 return(CSR_READ_2(sc, PCN_IO16_BDP)); 238} 239 240static void 241pcn_bcr_write(sc, reg, val) 242 struct pcn_softc *sc; 243 int reg; 244{ 245 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 246 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 247 return; 248} 249 250static int 251pcn_miibus_readreg(dev, phy, reg) 252 device_t dev; 253 int phy, reg; 254{ 255 struct pcn_softc *sc; 256 int val; 257 258 sc = device_get_softc(dev); 259 260 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 261 return(0); 262 263 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 264 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 265 if (val == 0xFFFF) 266 return(0); 267 268 sc->pcn_phyaddr = phy; 269 270 return(val); 271} 272 273static int 274pcn_miibus_writereg(dev, phy, reg, data) 275 device_t dev; 276 int phy, reg, data; 277{ 278 struct pcn_softc *sc; 279 280 sc = device_get_softc(dev); 281 282 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 283 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 284 285 return(0); 286} 287 288static void 289pcn_miibus_statchg(dev) 290 device_t dev; 291{ 292 struct pcn_softc *sc; 293 struct mii_data *mii; 294 295 sc = device_get_softc(dev); 296 mii = device_get_softc(sc->pcn_miibus); 297 298 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 299 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 300 } else { 301 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 302 } 303 304 return; 305} 306 307#define DC_POLY 0xEDB88320 308 309static u_int32_t 310pcn_crc(addr) 311 caddr_t addr; 312{ 313 u_int32_t idx, bit, data, crc; 314 315 /* Compute CRC for the address value. */ 316 crc = 0xFFFFFFFF; /* initial value */ 317 318 for (idx = 0; idx < 6; idx++) { 319 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 320 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 321 } 322 323 return ((crc >> 26) & 0x3F); 324} 325 326static void 327pcn_setmulti(sc) 328 struct pcn_softc *sc; 329{ 330 struct ifnet *ifp; 331 struct ifmultiaddr *ifma; 332 u_int32_t h, i; 333 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 334 335 ifp = &sc->arpcom.ac_if; 336 337 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 338 339 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 340 for (i = 0; i < 4; i++) 341 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 342 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 343 return; 344 } 345 346 /* first, zot all the existing hash bits */ 347 for (i = 0; i < 4; i++) 348 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 349 350 /* now program new ones */ 351 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 352 if (ifma->ifma_addr->sa_family != AF_LINK) 353 continue; 354 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 355 hashes[h >> 4] |= 1 << (h & 0xF); 356 } 357 358 for (i = 0; i < 4; i++) 359 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 360 361 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 362 363 return; 364} 365 366static void 367pcn_reset(sc) 368 struct pcn_softc *sc; 369{ 370 /* 371 * Issue a reset by reading from the RESET register. 372 * Note that we don't know if the chip is operating in 373 * 16-bit or 32-bit mode at this point, so we attempt 374 * to reset the chip both ways. If one fails, the other 375 * will succeed. 376 */ 377 CSR_READ_2(sc, PCN_IO16_RESET); 378 CSR_READ_4(sc, PCN_IO32_RESET); 379 380 /* Wait a little while for the chip to get its brains in order. */ 381 DELAY(1000); 382 383 /* Select 32-bit (DWIO) mode */ 384 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 385 386 /* Select software style 3. */ 387 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 388 389 return; 390} 391 392/* 393 * Probe for an AMD chip. Check the PCI vendor and device 394 * IDs against our list and return a device name if we find a match. 395 */ 396static int 397pcn_probe(dev) 398 device_t dev; 399{ 400 struct pcn_type *t; 401 struct pcn_softc *sc; 402 int rid; 403 u_int32_t chip_id; 404 405 t = pcn_devs; 406 sc = device_get_softc(dev); 407 408 while(t->pcn_name != NULL) { 409 if ((pci_get_vendor(dev) == t->pcn_vid) && 410 (pci_get_device(dev) == t->pcn_did)) { 411 /* 412 * Temporarily map the I/O space 413 * so we can read the chip ID register. 414 */ 415 rid = PCN_RID; 416 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 417 0, ~0, 1, RF_ACTIVE); 418 if (sc->pcn_res == NULL) { 419 device_printf(dev, 420 "couldn't map ports/memory\n"); 421 return(ENXIO); 422 } 423 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 424 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 425 mtx_init(&sc->pcn_mtx, 426 device_get_nameunit(dev), MTX_NETWORK_LOCK, 427 MTX_DEF); 428 PCN_LOCK(sc); 429 /* 430 * Note: we can *NOT* put the chip into 431 * 32-bit mode yet. The lnc driver will only 432 * work in 16-bit mode, and once the chip 433 * goes into 32-bit mode, the only way to 434 * get it out again is with a hardware reset. 435 * So if pcn_probe() is called before the 436 * lnc driver's probe routine, the chip will 437 * be locked into 32-bit operation and the lnc 438 * driver will be unable to attach to it. 439 * Note II: if the chip happens to already 440 * be in 32-bit mode, we still need to check 441 * the chip ID, but first we have to detect 442 * 32-bit mode using only 16-bit operations. 443 * The safest way to do this is to read the 444 * PCI subsystem ID from BCR23/24 and compare 445 * that with the value read from PCI config 446 * space. 447 */ 448 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 449 chip_id <<= 16; 450 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 451 /* 452 * Note III: the test for 0x10001000 is a hack to 453 * pacify VMware, who's pseudo-PCnet interface is 454 * broken. Reading the subsystem register from PCI 455 * config space yeilds 0x00000000 while reading the 456 * same value from I/O space yeilds 0x10001000. It's 457 * not supposed to be that way. 458 */ 459 if (chip_id == pci_read_config(dev, 460 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 461 /* We're in 16-bit mode. */ 462 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 463 chip_id <<= 16; 464 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 465 } else { 466 /* We're in 32-bit mode. */ 467 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 468 chip_id <<= 16; 469 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 470 } 471 bus_release_resource(dev, PCN_RES, 472 PCN_RID, sc->pcn_res); 473 PCN_UNLOCK(sc); 474 mtx_destroy(&sc->pcn_mtx); 475 chip_id >>= 12; 476 sc->pcn_type = chip_id & PART_MASK; 477 switch(sc->pcn_type) { 478 case Am79C971: 479 case Am79C972: 480 case Am79C973: 481 case Am79C975: 482 case Am79C976: 483 case Am79C978: 484 break; 485 default: 486 return(ENXIO); 487 break; 488 } 489 device_set_desc(dev, t->pcn_name); 490 return(0); 491 } 492 t++; 493 } 494 495 return(ENXIO); 496} 497 498/* 499 * Attach the interface. Allocate softc structures, do ifmedia 500 * setup and ethernet/BPF attach. 501 */ 502static int 503pcn_attach(dev) 504 device_t dev; 505{ 506 u_int32_t eaddr[2]; 507 u_int32_t command; 508 struct pcn_softc *sc; 509 struct ifnet *ifp; 510 int unit, error = 0, rid; 511 512 sc = device_get_softc(dev); 513 unit = device_get_unit(dev); 514 515 /* Initialize our mutex. */ 516 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 517 MTX_DEF | MTX_RECURSE); 518 519 /* 520 * Handle power management nonsense. 521 */ 522 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 523 u_int32_t iobase, membase, irq; 524 525 /* Save important PCI config data. */ 526 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 527 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 528 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 529 530 /* Reset the power state. */ 531 printf("pcn%d: chip is in D%d power mode " 532 "-- setting to D0\n", unit, 533 pci_get_powerstate(dev)); 534 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 535 536 /* Restore PCI config data. */ 537 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 538 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 539 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 540 } 541 542 /* 543 * Map control/status registers. 544 */ 545 pci_enable_busmaster(dev); 546 547 /* Retreive the chip ID */ 548 command = pcn_chip_id(dev); 549 sc->pcn_type = (command >>= 12) & PART_MASK; 550 device_printf(dev, "Chip ID %04x (%s)\n", 551 sc->pcn_type, pcn_chipid_name(sc->pcn_type)); 552 553 rid = PCN_RID; 554 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 555 0, ~0, 1, RF_ACTIVE); 556 557 if (sc->pcn_res == NULL) { 558 printf("pcn%d: couldn't map ports/memory\n", unit); 559 error = ENXIO; 560 goto fail; 561 } 562 563 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 564 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 565 566 /* Allocate interrupt */ 567 rid = 0; 568 sc->pcn_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 569 RF_SHAREABLE | RF_ACTIVE); 570 571 if (sc->pcn_irq == NULL) { 572 printf("pcn%d: couldn't map interrupt\n", unit); 573 error = ENXIO; 574 goto fail; 575 } 576 577 /* Reset the adapter. */ 578 pcn_reset(sc); 579 580 /* 581 * Get station address from the EEPROM. 582 */ 583 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 584 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 585 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 586 587 /* 588 * An AMD chip was detected. Inform the world. 589 */ 590 printf("pcn%d: Ethernet address: %6D\n", unit, 591 sc->arpcom.ac_enaddr, ":"); 592 593 sc->pcn_unit = unit; 594 callout_handle_init(&sc->pcn_stat_ch); 595 596 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 597 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 598 599 if (sc->pcn_ldata == NULL) { 600 printf("pcn%d: no memory for list buffers!\n", unit); 601 error = ENXIO; 602 goto fail; 603 } 604 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 605 606 ifp = &sc->arpcom.ac_if; 607 ifp->if_softc = sc; 608 ifp->if_unit = unit; 609 ifp->if_name = "pcn"; 610 ifp->if_mtu = ETHERMTU; 611 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 612 ifp->if_ioctl = pcn_ioctl; 613 ifp->if_output = ether_output; 614 ifp->if_start = pcn_start; 615 ifp->if_watchdog = pcn_watchdog; 616 ifp->if_init = pcn_init; 617 ifp->if_baudrate = 10000000; 618 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 619 620 /* 621 * Do MII setup. 622 */ 623 if (mii_phy_probe(dev, &sc->pcn_miibus, 624 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 625 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 626 error = ENXIO; 627 goto fail; 628 } 629 630 /* 631 * Call MI attach routine. 632 */ 633 ether_ifattach(ifp, (u_int8_t *) eaddr); 634 635 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 636 pcn_intr, sc, &sc->pcn_intrhand); 637 638 if (error) { 639 printf("pcn%d: couldn't set up irq\n", unit); 640 goto fail; 641 } 642 643fail: 644 if (error) 645 pcn_detach(dev); 646 647 return(error); 648} 649 650static int 651pcn_detach(dev) 652 device_t dev; 653{ 654 struct pcn_softc *sc; 655 struct ifnet *ifp; 656 657 sc = device_get_softc(dev); 658 ifp = &sc->arpcom.ac_if; 659 660 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized")); 661 PCN_LOCK(sc); 662 663 if (device_is_alive(dev)) { 664 if (bus_child_present(dev)) { 665 pcn_reset(sc); 666 pcn_stop(sc); 667 } 668 ether_ifdetach(ifp); 669 device_delete_child(dev, sc->pcn_miibus); 670 bus_generic_detach(dev); 671 } 672 673 if (sc->pcn_intrhand) 674 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 675 if (sc->pcn_irq) 676 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 677 if (sc->pcn_res) 678 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 679 680 if (sc->pcn_ldata) { 681 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 682 M_DEVBUF); 683 } 684 PCN_UNLOCK(sc); 685 686 mtx_destroy(&sc->pcn_mtx); 687 688 return(0); 689} 690 691/* 692 * Initialize the transmit descriptors. 693 */ 694static int 695pcn_list_tx_init(sc) 696 struct pcn_softc *sc; 697{ 698 struct pcn_list_data *ld; 699 struct pcn_ring_data *cd; 700 int i; 701 702 cd = &sc->pcn_cdata; 703 ld = sc->pcn_ldata; 704 705 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 706 cd->pcn_tx_chain[i] = NULL; 707 ld->pcn_tx_list[i].pcn_tbaddr = 0; 708 ld->pcn_tx_list[i].pcn_txctl = 0; 709 ld->pcn_tx_list[i].pcn_txstat = 0; 710 } 711 712 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 713 714 return(0); 715} 716 717 718/* 719 * Initialize the RX descriptors and allocate mbufs for them. 720 */ 721static int 722pcn_list_rx_init(sc) 723 struct pcn_softc *sc; 724{ 725 struct pcn_list_data *ld; 726 struct pcn_ring_data *cd; 727 int i; 728 729 ld = sc->pcn_ldata; 730 cd = &sc->pcn_cdata; 731 732 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 733 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 734 return(ENOBUFS); 735 } 736 737 cd->pcn_rx_prod = 0; 738 739 return(0); 740} 741 742/* 743 * Initialize an RX descriptor and attach an MBUF cluster. 744 */ 745static int 746pcn_newbuf(sc, idx, m) 747 struct pcn_softc *sc; 748 int idx; 749 struct mbuf *m; 750{ 751 struct mbuf *m_new = NULL; 752 struct pcn_rx_desc *c; 753 754 c = &sc->pcn_ldata->pcn_rx_list[idx]; 755 756 if (m == NULL) { 757 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 758 if (m_new == NULL) 759 return(ENOBUFS); 760 761 MCLGET(m_new, M_DONTWAIT); 762 if (!(m_new->m_flags & M_EXT)) { 763 m_freem(m_new); 764 return(ENOBUFS); 765 } 766 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 767 } else { 768 m_new = m; 769 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 770 m_new->m_data = m_new->m_ext.ext_buf; 771 } 772 773 m_adj(m_new, ETHER_ALIGN); 774 775 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 776 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 777 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 778 c->pcn_bufsz |= PCN_RXLEN_MBO; 779 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 780 781 return(0); 782} 783 784/* 785 * A frame has been uploaded: pass the resulting mbuf chain up to 786 * the higher level protocols. 787 */ 788static void 789pcn_rxeof(sc) 790 struct pcn_softc *sc; 791{ 792 struct ether_header *eh; 793 struct mbuf *m; 794 struct ifnet *ifp; 795 struct pcn_rx_desc *cur_rx; 796 int i; 797 798 ifp = &sc->arpcom.ac_if; 799 i = sc->pcn_cdata.pcn_rx_prod; 800 801 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 802 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 803 m = sc->pcn_cdata.pcn_rx_chain[i]; 804 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 805 806 /* 807 * If an error occurs, update stats, clear the 808 * status word and leave the mbuf cluster in place: 809 * it should simply get re-used next time this descriptor 810 * comes up in the ring. 811 */ 812 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 813 ifp->if_ierrors++; 814 pcn_newbuf(sc, i, m); 815 PCN_INC(i, PCN_RX_LIST_CNT); 816 continue; 817 } 818 819 if (pcn_newbuf(sc, i, NULL)) { 820 /* Ran out of mbufs; recycle this one. */ 821 pcn_newbuf(sc, i, m); 822 ifp->if_ierrors++; 823 PCN_INC(i, PCN_RX_LIST_CNT); 824 continue; 825 } 826 827 PCN_INC(i, PCN_RX_LIST_CNT); 828 829 /* No errors; receive the packet. */ 830 ifp->if_ipackets++; 831 eh = mtod(m, struct ether_header *); 832 m->m_len = m->m_pkthdr.len = 833 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 834 m->m_pkthdr.rcvif = ifp; 835 836 (*ifp->if_input)(ifp, m); 837 } 838 839 sc->pcn_cdata.pcn_rx_prod = i; 840 841 return; 842} 843 844/* 845 * A frame was downloaded to the chip. It's safe for us to clean up 846 * the list buffers. 847 */ 848 849static void 850pcn_txeof(sc) 851 struct pcn_softc *sc; 852{ 853 struct pcn_tx_desc *cur_tx = NULL; 854 struct ifnet *ifp; 855 u_int32_t idx; 856 857 ifp = &sc->arpcom.ac_if; 858 859 /* 860 * Go through our tx list and free mbufs for those 861 * frames that have been transmitted. 862 */ 863 idx = sc->pcn_cdata.pcn_tx_cons; 864 while (idx != sc->pcn_cdata.pcn_tx_prod) { 865 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 866 867 if (!PCN_OWN_TXDESC(cur_tx)) 868 break; 869 870 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 871 sc->pcn_cdata.pcn_tx_cnt--; 872 PCN_INC(idx, PCN_TX_LIST_CNT); 873 continue; 874 } 875 876 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 877 ifp->if_oerrors++; 878 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 879 ifp->if_collisions++; 880 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 881 ifp->if_collisions++; 882 } 883 884 ifp->if_collisions += 885 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 886 887 ifp->if_opackets++; 888 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 889 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 890 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 891 } 892 893 sc->pcn_cdata.pcn_tx_cnt--; 894 PCN_INC(idx, PCN_TX_LIST_CNT); 895 } 896 897 if (idx != sc->pcn_cdata.pcn_tx_cons) { 898 /* Some buffers have been freed. */ 899 sc->pcn_cdata.pcn_tx_cons = idx; 900 ifp->if_flags &= ~IFF_OACTIVE; 901 } 902 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 903 904 return; 905} 906 907static void 908pcn_tick(xsc) 909 void *xsc; 910{ 911 struct pcn_softc *sc; 912 struct mii_data *mii; 913 struct ifnet *ifp; 914 915 sc = xsc; 916 ifp = &sc->arpcom.ac_if; 917 PCN_LOCK(sc); 918 919 mii = device_get_softc(sc->pcn_miibus); 920 mii_tick(mii); 921 922 /* link just died */ 923 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 924 sc->pcn_link = 0; 925 926 /* link just came up, restart */ 927 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE && 928 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 929 sc->pcn_link++; 930 if (ifp->if_snd.ifq_head != NULL) 931 pcn_start(ifp); 932 } 933 934 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 935 936 PCN_UNLOCK(sc); 937 938 return; 939} 940 941static void 942pcn_intr(arg) 943 void *arg; 944{ 945 struct pcn_softc *sc; 946 struct ifnet *ifp; 947 u_int32_t status; 948 949 sc = arg; 950 ifp = &sc->arpcom.ac_if; 951 952 /* Supress unwanted interrupts */ 953 if (!(ifp->if_flags & IFF_UP)) { 954 pcn_stop(sc); 955 return; 956 } 957 958 PCN_LOCK(sc); 959 960 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 961 962 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 963 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 964 965 if (status & PCN_CSR_RINT) 966 pcn_rxeof(sc); 967 968 if (status & PCN_CSR_TINT) 969 pcn_txeof(sc); 970 971 if (status & PCN_CSR_ERR) { 972 pcn_init(sc); 973 break; 974 } 975 } 976 977 if (ifp->if_snd.ifq_head != NULL) 978 pcn_start(ifp); 979 980 PCN_UNLOCK(sc); 981 return; 982} 983 984/* 985 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 986 * pointers to the fragment pointers. 987 */ 988static int 989pcn_encap(sc, m_head, txidx) 990 struct pcn_softc *sc; 991 struct mbuf *m_head; 992 u_int32_t *txidx; 993{ 994 struct pcn_tx_desc *f = NULL; 995 struct mbuf *m; 996 int frag, cur, cnt = 0; 997 998 /* 999 * Start packing the mbufs in this chain into 1000 * the fragment pointers. Stop when we run out 1001 * of fragments or hit the end of the mbuf chain. 1002 */ 1003 m = m_head; 1004 cur = frag = *txidx; 1005 1006 for (m = m_head; m != NULL; m = m->m_next) { 1007 if (m->m_len != 0) { 1008 if ((PCN_TX_LIST_CNT - 1009 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 1010 return(ENOBUFS); 1011 f = &sc->pcn_ldata->pcn_tx_list[frag]; 1012 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 1013 f->pcn_txctl |= PCN_TXCTL_MBO; 1014 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 1015 if (cnt == 0) 1016 f->pcn_txctl |= PCN_TXCTL_STP; 1017 else 1018 f->pcn_txctl |= PCN_TXCTL_OWN; 1019 cur = frag; 1020 PCN_INC(frag, PCN_TX_LIST_CNT); 1021 cnt++; 1022 } 1023 } 1024 1025 if (m != NULL) 1026 return(ENOBUFS); 1027 1028 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1029 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1030 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1031 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1032 sc->pcn_cdata.pcn_tx_cnt += cnt; 1033 *txidx = frag; 1034 1035 return(0); 1036} 1037 1038/* 1039 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1040 * to the mbuf data regions directly in the transmit lists. We also save a 1041 * copy of the pointers since the transmit list fragment pointers are 1042 * physical addresses. 1043 */ 1044static void 1045pcn_start(ifp) 1046 struct ifnet *ifp; 1047{ 1048 struct pcn_softc *sc; 1049 struct mbuf *m_head = NULL; 1050 u_int32_t idx; 1051 1052 sc = ifp->if_softc; 1053 1054 PCN_LOCK(sc); 1055 1056 if (!sc->pcn_link) { 1057 PCN_UNLOCK(sc); 1058 return; 1059 } 1060 1061 idx = sc->pcn_cdata.pcn_tx_prod; 1062 1063 if (ifp->if_flags & IFF_OACTIVE) { 1064 PCN_UNLOCK(sc); 1065 return; 1066 } 1067 1068 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1069 IF_DEQUEUE(&ifp->if_snd, m_head); 1070 if (m_head == NULL) 1071 break; 1072 1073 if (pcn_encap(sc, m_head, &idx)) { 1074 IF_PREPEND(&ifp->if_snd, m_head); 1075 ifp->if_flags |= IFF_OACTIVE; 1076 break; 1077 } 1078 1079 /* 1080 * If there's a BPF listener, bounce a copy of this frame 1081 * to him. 1082 */ 1083 BPF_MTAP(ifp, m_head); 1084 1085 } 1086 1087 /* Transmit */ 1088 sc->pcn_cdata.pcn_tx_prod = idx; 1089 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1090 1091 /* 1092 * Set a timeout in case the chip goes out to lunch. 1093 */ 1094 ifp->if_timer = 5; 1095 1096 PCN_UNLOCK(sc); 1097 1098 return; 1099} 1100 1101static void 1102pcn_setfilt(ifp) 1103 struct ifnet *ifp; 1104{ 1105 struct pcn_softc *sc; 1106 1107 sc = ifp->if_softc; 1108 1109 /* If we want promiscuous mode, set the allframes bit. */ 1110 if (ifp->if_flags & IFF_PROMISC) { 1111 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1112 } else { 1113 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1114 } 1115 1116 /* Set the capture broadcast bit to capture broadcast frames. */ 1117 if (ifp->if_flags & IFF_BROADCAST) { 1118 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1119 } else { 1120 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1121 } 1122 1123 return; 1124} 1125 1126static void 1127pcn_init(xsc) 1128 void *xsc; 1129{ 1130 struct pcn_softc *sc = xsc; 1131 struct ifnet *ifp = &sc->arpcom.ac_if; 1132 struct mii_data *mii = NULL; 1133 1134 PCN_LOCK(sc); 1135 1136 /* 1137 * Cancel pending I/O and free all RX/TX buffers. 1138 */ 1139 pcn_stop(sc); 1140 pcn_reset(sc); 1141 1142 mii = device_get_softc(sc->pcn_miibus); 1143 1144 /* Set MAC address */ 1145 pcn_csr_write(sc, PCN_CSR_PAR0, 1146 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1147 pcn_csr_write(sc, PCN_CSR_PAR1, 1148 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1149 pcn_csr_write(sc, PCN_CSR_PAR2, 1150 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1151 1152 /* Init circular RX list. */ 1153 if (pcn_list_rx_init(sc) == ENOBUFS) { 1154 printf("pcn%d: initialization failed: no " 1155 "memory for rx buffers\n", sc->pcn_unit); 1156 pcn_stop(sc); 1157 PCN_UNLOCK(sc); 1158 return; 1159 } 1160 1161 /* 1162 * Init tx descriptors. 1163 */ 1164 pcn_list_tx_init(sc); 1165 1166 /* Set up the mode register. */ 1167 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1168 1169 /* Set up RX filter. */ 1170 pcn_setfilt(ifp); 1171 1172 /* 1173 * Load the multicast filter. 1174 */ 1175 pcn_setmulti(sc); 1176 1177 /* 1178 * Load the addresses of the RX and TX lists. 1179 */ 1180 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1181 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1182 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1183 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1184 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1185 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1186 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1187 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1188 1189 /* Set the RX and TX ring sizes. */ 1190 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1191 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1192 1193 /* We're not using the initialization block. */ 1194 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1195 1196 /* Enable fast suspend mode. */ 1197 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1198 1199 /* 1200 * Enable burst read and write. Also set the no underflow 1201 * bit. This will avoid transmit underruns in certain 1202 * conditions while still providing decent performance. 1203 */ 1204 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1205 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1206 1207 /* Enable graceful recovery from underflow. */ 1208 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1209 1210 /* Enable auto-padding of short TX frames. */ 1211 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1212 1213 /* Disable MII autoneg (we handle this ourselves). */ 1214 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1215 1216 if (sc->pcn_type == Am79C978) 1217 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1218 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1219 1220 /* Enable interrupts and start the controller running. */ 1221 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1222 1223 mii_mediachg(mii); 1224 1225 ifp->if_flags |= IFF_RUNNING; 1226 ifp->if_flags &= ~IFF_OACTIVE; 1227 1228 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 1229 PCN_UNLOCK(sc); 1230 1231 return; 1232} 1233 1234/* 1235 * Set media options. 1236 */ 1237static int 1238pcn_ifmedia_upd(ifp) 1239 struct ifnet *ifp; 1240{ 1241 struct pcn_softc *sc; 1242 struct mii_data *mii; 1243 1244 sc = ifp->if_softc; 1245 mii = device_get_softc(sc->pcn_miibus); 1246 1247 sc->pcn_link = 0; 1248 if (mii->mii_instance) { 1249 struct mii_softc *miisc; 1250 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1251 mii_phy_reset(miisc); 1252 } 1253 mii_mediachg(mii); 1254 1255 return(0); 1256} 1257 1258/* 1259 * Report current media status. 1260 */ 1261static void 1262pcn_ifmedia_sts(ifp, ifmr) 1263 struct ifnet *ifp; 1264 struct ifmediareq *ifmr; 1265{ 1266 struct pcn_softc *sc; 1267 struct mii_data *mii; 1268 1269 sc = ifp->if_softc; 1270 1271 mii = device_get_softc(sc->pcn_miibus); 1272 mii_pollstat(mii); 1273 ifmr->ifm_active = mii->mii_media_active; 1274 ifmr->ifm_status = mii->mii_media_status; 1275 1276 return; 1277} 1278 1279static int 1280pcn_ioctl(ifp, command, data) 1281 struct ifnet *ifp; 1282 u_long command; 1283 caddr_t data; 1284{ 1285 struct pcn_softc *sc = ifp->if_softc; 1286 struct ifreq *ifr = (struct ifreq *) data; 1287 struct mii_data *mii = NULL; 1288 int error = 0; 1289 1290 PCN_LOCK(sc); 1291 1292 switch(command) { 1293 case SIOCSIFFLAGS: 1294 if (ifp->if_flags & IFF_UP) { 1295 if (ifp->if_flags & IFF_RUNNING && 1296 ifp->if_flags & IFF_PROMISC && 1297 !(sc->pcn_if_flags & IFF_PROMISC)) { 1298 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1299 PCN_EXTCTL1_SPND); 1300 pcn_setfilt(ifp); 1301 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1302 PCN_EXTCTL1_SPND); 1303 pcn_csr_write(sc, PCN_CSR_CSR, 1304 PCN_CSR_INTEN|PCN_CSR_START); 1305 } else if (ifp->if_flags & IFF_RUNNING && 1306 !(ifp->if_flags & IFF_PROMISC) && 1307 sc->pcn_if_flags & IFF_PROMISC) { 1308 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1309 PCN_EXTCTL1_SPND); 1310 pcn_setfilt(ifp); 1311 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1312 PCN_EXTCTL1_SPND); 1313 pcn_csr_write(sc, PCN_CSR_CSR, 1314 PCN_CSR_INTEN|PCN_CSR_START); 1315 } else if (!(ifp->if_flags & IFF_RUNNING)) 1316 pcn_init(sc); 1317 } else { 1318 if (ifp->if_flags & IFF_RUNNING) 1319 pcn_stop(sc); 1320 } 1321 sc->pcn_if_flags = ifp->if_flags; 1322 error = 0; 1323 break; 1324 case SIOCADDMULTI: 1325 case SIOCDELMULTI: 1326 pcn_setmulti(sc); 1327 error = 0; 1328 break; 1329 case SIOCGIFMEDIA: 1330 case SIOCSIFMEDIA: 1331 mii = device_get_softc(sc->pcn_miibus); 1332 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1333 break; 1334 default: 1335 error = ether_ioctl(ifp, command, data); 1336 break; 1337 } 1338 1339 PCN_UNLOCK(sc); 1340 1341 return(error); 1342} 1343 1344static void 1345pcn_watchdog(ifp) 1346 struct ifnet *ifp; 1347{ 1348 struct pcn_softc *sc; 1349 1350 sc = ifp->if_softc; 1351 1352 PCN_LOCK(sc); 1353 1354 ifp->if_oerrors++; 1355 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1356 1357 pcn_stop(sc); 1358 pcn_reset(sc); 1359 pcn_init(sc); 1360 1361 if (ifp->if_snd.ifq_head != NULL) 1362 pcn_start(ifp); 1363 1364 PCN_UNLOCK(sc); 1365 1366 return; 1367} 1368 1369/* 1370 * Stop the adapter and free any mbufs allocated to the 1371 * RX and TX lists. 1372 */ 1373static void 1374pcn_stop(sc) 1375 struct pcn_softc *sc; 1376{ 1377 register int i; 1378 struct ifnet *ifp; 1379 1380 ifp = &sc->arpcom.ac_if; 1381 PCN_LOCK(sc); 1382 ifp->if_timer = 0; 1383 1384 untimeout(pcn_tick, sc, sc->pcn_stat_ch); 1385 1386 /* Turn off interrupts */ 1387 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN); 1388 /* Stop adapter */ 1389 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1390 sc->pcn_link = 0; 1391 1392 /* 1393 * Free data in the RX lists. 1394 */ 1395 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1396 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1397 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1398 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1399 } 1400 } 1401 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1402 sizeof(sc->pcn_ldata->pcn_rx_list)); 1403 1404 /* 1405 * Free the TX list buffers. 1406 */ 1407 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1408 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1409 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1410 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1411 } 1412 } 1413 1414 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1415 sizeof(sc->pcn_ldata->pcn_tx_list)); 1416 1417 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1418 PCN_UNLOCK(sc); 1419 1420 return; 1421} 1422 1423/* 1424 * Stop all chip I/O so that the kernel's probe routines don't 1425 * get confused by errant DMAs when rebooting. 1426 */ 1427static void 1428pcn_shutdown(dev) 1429 device_t dev; 1430{ 1431 struct pcn_softc *sc; 1432 1433 sc = device_get_softc(dev); 1434 1435 PCN_LOCK(sc); 1436 pcn_reset(sc); 1437 pcn_stop(sc); 1438 PCN_UNLOCK(sc); 1439 1440 return; 1441} 1442