if_pcn.c revision 113038
1/* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34/* 35 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 36 * from http://www.amd.com. 37 * 38 * The AMD PCnet/PCI controllers are more advanced and functional 39 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 40 * backwards compatibility with the LANCE and thus can be made 41 * to work with older LANCE drivers. This is in fact how the 42 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 43 * is that the PCnet/PCI devices offer several performance enhancements 44 * which can't be exploited in LANCE compatibility mode. Chief among 45 * these enhancements is the ability to perform PCI DMA operations 46 * using 32-bit addressing (which eliminates the need for ISA 47 * bounce-buffering), and special receive buffer alignment (which 48 * allows the receive handler to pass packets to the upper protocol 49 * layers without copying on both the x86 and alpha platforms). 50 */ 51 52#include <sys/cdefs.h> 53__FBSDID("$FreeBSD: head/sys/pci/if_pcn.c 113038 2003-04-03 21:36:33Z obrien $"); 54 55#include <sys/param.h> 56#include <sys/systm.h> 57#include <sys/sockio.h> 58#include <sys/mbuf.h> 59#include <sys/malloc.h> 60#include <sys/kernel.h> 61#include <sys/socket.h> 62 63#include <net/if.h> 64#include <net/if_arp.h> 65#include <net/ethernet.h> 66#include <net/if_dl.h> 67#include <net/if_media.h> 68 69#include <net/bpf.h> 70 71#include <vm/vm.h> /* for vtophys */ 72#include <vm/pmap.h> /* for vtophys */ 73#include <machine/bus_pio.h> 74#include <machine/bus_memio.h> 75#include <machine/bus.h> 76#include <machine/resource.h> 77#include <sys/bus.h> 78#include <sys/rman.h> 79 80#include <dev/mii/mii.h> 81#include <dev/mii/miivar.h> 82 83#include <pci/pcireg.h> 84#include <pci/pcivar.h> 85 86#define PCN_USEIOSPACE 87 88#include <pci/if_pcnreg.h> 89 90MODULE_DEPEND(pcn, miibus, 1, 1, 1); 91 92/* "controller miibus0" required. See GENERIC if you get errors here. */ 93#include "miibus_if.h" 94 95/* 96 * Various supported device vendors/types and their names. 97 */ 98static struct pcn_type pcn_devs[] = { 99 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 100 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 101 { 0, 0, NULL } 102}; 103 104static u_int32_t pcn_csr_read (struct pcn_softc *, int); 105static u_int16_t pcn_csr_read16 (struct pcn_softc *, int); 106static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int); 107static void pcn_csr_write (struct pcn_softc *, int, int); 108static u_int32_t pcn_bcr_read (struct pcn_softc *, int); 109static void pcn_bcr_write (struct pcn_softc *, int, int); 110 111static int pcn_probe (device_t); 112static int pcn_attach (device_t); 113static int pcn_detach (device_t); 114 115static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *); 116static int pcn_encap (struct pcn_softc *, 117 struct mbuf *, u_int32_t *); 118static void pcn_rxeof (struct pcn_softc *); 119static void pcn_txeof (struct pcn_softc *); 120static void pcn_intr (void *); 121static void pcn_tick (void *); 122static void pcn_start (struct ifnet *); 123static int pcn_ioctl (struct ifnet *, u_long, caddr_t); 124static void pcn_init (void *); 125static void pcn_stop (struct pcn_softc *); 126static void pcn_watchdog (struct ifnet *); 127static void pcn_shutdown (device_t); 128static int pcn_ifmedia_upd (struct ifnet *); 129static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *); 130 131static int pcn_miibus_readreg (device_t, int, int); 132static int pcn_miibus_writereg (device_t, int, int, int); 133static void pcn_miibus_statchg (device_t); 134 135static void pcn_setfilt (struct ifnet *); 136static void pcn_setmulti (struct pcn_softc *); 137static u_int32_t pcn_crc (caddr_t); 138static void pcn_reset (struct pcn_softc *); 139static int pcn_list_rx_init (struct pcn_softc *); 140static int pcn_list_tx_init (struct pcn_softc *); 141 142#ifdef PCN_USEIOSPACE 143#define PCN_RES SYS_RES_IOPORT 144#define PCN_RID PCN_PCI_LOIO 145#else 146#define PCN_RES SYS_RES_MEMORY 147#define PCN_RID PCN_PCI_LOMEM 148#endif 149 150static device_method_t pcn_methods[] = { 151 /* Device interface */ 152 DEVMETHOD(device_probe, pcn_probe), 153 DEVMETHOD(device_attach, pcn_attach), 154 DEVMETHOD(device_detach, pcn_detach), 155 DEVMETHOD(device_shutdown, pcn_shutdown), 156 157 /* bus interface */ 158 DEVMETHOD(bus_print_child, bus_generic_print_child), 159 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 160 161 /* MII interface */ 162 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 163 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 164 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 165 166 { 0, 0 } 167}; 168 169static driver_t pcn_driver = { 170 "pcn", 171 pcn_methods, 172 sizeof(struct pcn_softc) 173}; 174 175static devclass_t pcn_devclass; 176 177DRIVER_MODULE(if_pcn, pci, pcn_driver, pcn_devclass, 0, 0); 178DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 179 180#define PCN_CSR_SETBIT(sc, reg, x) \ 181 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 182 183#define PCN_CSR_CLRBIT(sc, reg, x) \ 184 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 185 186#define PCN_BCR_SETBIT(sc, reg, x) \ 187 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 188 189#define PCN_BCR_CLRBIT(sc, reg, x) \ 190 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 191 192static u_int32_t 193pcn_csr_read(sc, reg) 194 struct pcn_softc *sc; 195 int reg; 196{ 197 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 198 return(CSR_READ_4(sc, PCN_IO32_RDP)); 199} 200 201static u_int16_t 202pcn_csr_read16(sc, reg) 203 struct pcn_softc *sc; 204 int reg; 205{ 206 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 207 return(CSR_READ_2(sc, PCN_IO16_RDP)); 208} 209 210static void 211pcn_csr_write(sc, reg, val) 212 struct pcn_softc *sc; 213 int reg; 214{ 215 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 216 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 217 return; 218} 219 220static u_int32_t 221pcn_bcr_read(sc, reg) 222 struct pcn_softc *sc; 223 int reg; 224{ 225 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 226 return(CSR_READ_4(sc, PCN_IO32_BDP)); 227} 228 229static u_int16_t 230pcn_bcr_read16(sc, reg) 231 struct pcn_softc *sc; 232 int reg; 233{ 234 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 235 return(CSR_READ_2(sc, PCN_IO16_BDP)); 236} 237 238static void 239pcn_bcr_write(sc, reg, val) 240 struct pcn_softc *sc; 241 int reg; 242{ 243 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 244 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 245 return; 246} 247 248static int 249pcn_miibus_readreg(dev, phy, reg) 250 device_t dev; 251 int phy, reg; 252{ 253 struct pcn_softc *sc; 254 int val; 255 256 sc = device_get_softc(dev); 257 258 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 259 return(0); 260 261 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 262 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 263 if (val == 0xFFFF) 264 return(0); 265 266 sc->pcn_phyaddr = phy; 267 268 return(val); 269} 270 271static int 272pcn_miibus_writereg(dev, phy, reg, data) 273 device_t dev; 274 int phy, reg, data; 275{ 276 struct pcn_softc *sc; 277 278 sc = device_get_softc(dev); 279 280 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 281 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 282 283 return(0); 284} 285 286static void 287pcn_miibus_statchg(dev) 288 device_t dev; 289{ 290 struct pcn_softc *sc; 291 struct mii_data *mii; 292 293 sc = device_get_softc(dev); 294 mii = device_get_softc(sc->pcn_miibus); 295 296 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 297 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 298 } else { 299 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 300 } 301 302 return; 303} 304 305#define DC_POLY 0xEDB88320 306 307static u_int32_t 308pcn_crc(addr) 309 caddr_t addr; 310{ 311 u_int32_t idx, bit, data, crc; 312 313 /* Compute CRC for the address value. */ 314 crc = 0xFFFFFFFF; /* initial value */ 315 316 for (idx = 0; idx < 6; idx++) { 317 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 318 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 319 } 320 321 return ((crc >> 26) & 0x3F); 322} 323 324static void 325pcn_setmulti(sc) 326 struct pcn_softc *sc; 327{ 328 struct ifnet *ifp; 329 struct ifmultiaddr *ifma; 330 u_int32_t h, i; 331 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 332 333 ifp = &sc->arpcom.ac_if; 334 335 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 336 337 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 338 for (i = 0; i < 4; i++) 339 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 340 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 341 return; 342 } 343 344 /* first, zot all the existing hash bits */ 345 for (i = 0; i < 4; i++) 346 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 347 348 /* now program new ones */ 349 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 350 if (ifma->ifma_addr->sa_family != AF_LINK) 351 continue; 352 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 353 hashes[h >> 4] |= 1 << (h & 0xF); 354 } 355 356 for (i = 0; i < 4; i++) 357 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 358 359 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 360 361 return; 362} 363 364static void 365pcn_reset(sc) 366 struct pcn_softc *sc; 367{ 368 /* 369 * Issue a reset by reading from the RESET register. 370 * Note that we don't know if the chip is operating in 371 * 16-bit or 32-bit mode at this point, so we attempt 372 * to reset the chip both ways. If one fails, the other 373 * will succeed. 374 */ 375 CSR_READ_2(sc, PCN_IO16_RESET); 376 CSR_READ_4(sc, PCN_IO32_RESET); 377 378 /* Wait a little while for the chip to get its brains in order. */ 379 DELAY(1000); 380 381 /* Select 32-bit (DWIO) mode */ 382 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 383 384 /* Select software style 3. */ 385 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 386 387 return; 388} 389 390/* 391 * Probe for an AMD chip. Check the PCI vendor and device 392 * IDs against our list and return a device name if we find a match. 393 */ 394static int 395pcn_probe(dev) 396 device_t dev; 397{ 398 struct pcn_type *t; 399 struct pcn_softc *sc; 400 int rid; 401 u_int32_t chip_id; 402 403 t = pcn_devs; 404 sc = device_get_softc(dev); 405 406 while(t->pcn_name != NULL) { 407 if ((pci_get_vendor(dev) == t->pcn_vid) && 408 (pci_get_device(dev) == t->pcn_did)) { 409 /* 410 * Temporarily map the I/O space 411 * so we can read the chip ID register. 412 */ 413 rid = PCN_RID; 414 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 415 0, ~0, 1, RF_ACTIVE); 416 if (sc->pcn_res == NULL) { 417 device_printf(dev, 418 "couldn't map ports/memory\n"); 419 return(ENXIO); 420 } 421 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 422 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 423 mtx_init(&sc->pcn_mtx, 424 device_get_nameunit(dev), MTX_NETWORK_LOCK, 425 MTX_DEF); 426 PCN_LOCK(sc); 427 /* 428 * Note: we can *NOT* put the chip into 429 * 32-bit mode yet. The lnc driver will only 430 * work in 16-bit mode, and once the chip 431 * goes into 32-bit mode, the only way to 432 * get it out again is with a hardware reset. 433 * So if pcn_probe() is called before the 434 * lnc driver's probe routine, the chip will 435 * be locked into 32-bit operation and the lnc 436 * driver will be unable to attach to it. 437 * Note II: if the chip happens to already 438 * be in 32-bit mode, we still need to check 439 * the chip ID, but first we have to detect 440 * 32-bit mode using only 16-bit operations. 441 * The safest way to do this is to read the 442 * PCI subsystem ID from BCR23/24 and compare 443 * that with the value read from PCI config 444 * space. 445 */ 446 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 447 chip_id <<= 16; 448 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 449 /* 450 * Note III: the test for 0x10001000 is a hack to 451 * pacify VMware, who's pseudo-PCnet interface is 452 * broken. Reading the subsystem register from PCI 453 * config space yeilds 0x00000000 while reading the 454 * same value from I/O space yeilds 0x10001000. It's 455 * not supposed to be that way. 456 */ 457 if (chip_id == pci_read_config(dev, 458 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 459 /* We're in 16-bit mode. */ 460 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 461 chip_id <<= 16; 462 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 463 } else { 464 /* We're in 32-bit mode. */ 465 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 466 chip_id <<= 16; 467 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 468 } 469 bus_release_resource(dev, PCN_RES, 470 PCN_RID, sc->pcn_res); 471 PCN_UNLOCK(sc); 472 mtx_destroy(&sc->pcn_mtx); 473 chip_id >>= 12; 474 sc->pcn_type = chip_id & PART_MASK; 475 switch(sc->pcn_type) { 476 case Am79C971: 477 case Am79C972: 478 case Am79C973: 479 case Am79C975: 480 case Am79C976: 481 case Am79C978: 482 break; 483 default: 484 return(ENXIO); 485 break; 486 } 487 device_set_desc(dev, t->pcn_name); 488 return(0); 489 } 490 t++; 491 } 492 493 return(ENXIO); 494} 495 496/* 497 * Attach the interface. Allocate softc structures, do ifmedia 498 * setup and ethernet/BPF attach. 499 */ 500static int 501pcn_attach(dev) 502 device_t dev; 503{ 504 u_int32_t eaddr[2]; 505 u_int32_t command; 506 struct pcn_softc *sc; 507 struct ifnet *ifp; 508 int unit, error = 0, rid; 509 510 sc = device_get_softc(dev); 511 unit = device_get_unit(dev); 512 513 /* Initialize our mutex. */ 514 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 515 MTX_DEF | MTX_RECURSE); 516 517 /* 518 * Handle power management nonsense. 519 */ 520 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 521 u_int32_t iobase, membase, irq; 522 523 /* Save important PCI config data. */ 524 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 525 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 526 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 527 528 /* Reset the power state. */ 529 printf("pcn%d: chip is in D%d power mode " 530 "-- setting to D0\n", unit, 531 pci_get_powerstate(dev)); 532 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 533 534 /* Restore PCI config data. */ 535 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 536 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 537 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 538 } 539 540 /* 541 * Map control/status registers. 542 */ 543 pci_enable_busmaster(dev); 544 pci_enable_io(dev, SYS_RES_IOPORT); 545 pci_enable_io(dev, SYS_RES_MEMORY); 546 command = pci_read_config(dev, PCIR_COMMAND, 4); 547 548#ifdef PCN_USEIOSPACE 549 if (!(command & PCIM_CMD_PORTEN)) { 550 printf("pcn%d: failed to enable I/O ports!\n", unit); 551 error = ENXIO; 552 goto fail; 553 } 554#else 555 if (!(command & PCIM_CMD_MEMEN)) { 556 printf("pcn%d: failed to enable memory mapping!\n", unit); 557 error = ENXIO; 558 goto fail; 559 } 560#endif 561 562 rid = PCN_RID; 563 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 564 0, ~0, 1, RF_ACTIVE); 565 566 if (sc->pcn_res == NULL) { 567 printf("pcn%d: couldn't map ports/memory\n", unit); 568 error = ENXIO; 569 goto fail; 570 } 571 572 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 573 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 574 575 /* Allocate interrupt */ 576 rid = 0; 577 sc->pcn_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 578 RF_SHAREABLE | RF_ACTIVE); 579 580 if (sc->pcn_irq == NULL) { 581 printf("pcn%d: couldn't map interrupt\n", unit); 582 error = ENXIO; 583 goto fail; 584 } 585 586 /* Reset the adapter. */ 587 pcn_reset(sc); 588 589 /* 590 * Get station address from the EEPROM. 591 */ 592 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 593 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 594 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 595 596 /* 597 * An AMD chip was detected. Inform the world. 598 */ 599 printf("pcn%d: Ethernet address: %6D\n", unit, 600 sc->arpcom.ac_enaddr, ":"); 601 602 sc->pcn_unit = unit; 603 callout_handle_init(&sc->pcn_stat_ch); 604 605 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 606 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 607 608 if (sc->pcn_ldata == NULL) { 609 printf("pcn%d: no memory for list buffers!\n", unit); 610 error = ENXIO; 611 goto fail; 612 } 613 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 614 615 ifp = &sc->arpcom.ac_if; 616 ifp->if_softc = sc; 617 ifp->if_unit = unit; 618 ifp->if_name = "pcn"; 619 ifp->if_mtu = ETHERMTU; 620 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 621 ifp->if_ioctl = pcn_ioctl; 622 ifp->if_output = ether_output; 623 ifp->if_start = pcn_start; 624 ifp->if_watchdog = pcn_watchdog; 625 ifp->if_init = pcn_init; 626 ifp->if_baudrate = 10000000; 627 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 628 629 /* 630 * Do MII setup. 631 */ 632 if (mii_phy_probe(dev, &sc->pcn_miibus, 633 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 634 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 635 error = ENXIO; 636 goto fail; 637 } 638 639 /* 640 * Call MI attach routine. 641 */ 642 ether_ifattach(ifp, (u_int8_t *) eaddr); 643 644 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 645 pcn_intr, sc, &sc->pcn_intrhand); 646 647 if (error) { 648 printf("pcn%d: couldn't set up irq\n", unit); 649 goto fail; 650 } 651 652fail: 653 if (error) 654 pcn_detach(dev); 655 656 return(error); 657} 658 659static int 660pcn_detach(dev) 661 device_t dev; 662{ 663 struct pcn_softc *sc; 664 struct ifnet *ifp; 665 666 sc = device_get_softc(dev); 667 ifp = &sc->arpcom.ac_if; 668 669 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized")); 670 PCN_LOCK(sc); 671 672 if (device_is_alive(dev)) { 673 if (bus_child_present(dev)) { 674 pcn_reset(sc); 675 pcn_stop(sc); 676 } 677 ether_ifdetach(ifp); 678 device_delete_child(dev, sc->pcn_miibus); 679 bus_generic_detach(dev); 680 } 681 682 if (sc->pcn_intrhand) 683 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 684 if (sc->pcn_irq) 685 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 686 if (sc->pcn_res) 687 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 688 689 if (sc->pcn_ldata) { 690 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 691 M_DEVBUF); 692 } 693 PCN_UNLOCK(sc); 694 695 mtx_destroy(&sc->pcn_mtx); 696 697 return(0); 698} 699 700/* 701 * Initialize the transmit descriptors. 702 */ 703static int 704pcn_list_tx_init(sc) 705 struct pcn_softc *sc; 706{ 707 struct pcn_list_data *ld; 708 struct pcn_ring_data *cd; 709 int i; 710 711 cd = &sc->pcn_cdata; 712 ld = sc->pcn_ldata; 713 714 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 715 cd->pcn_tx_chain[i] = NULL; 716 ld->pcn_tx_list[i].pcn_tbaddr = 0; 717 ld->pcn_tx_list[i].pcn_txctl = 0; 718 ld->pcn_tx_list[i].pcn_txstat = 0; 719 } 720 721 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 722 723 return(0); 724} 725 726 727/* 728 * Initialize the RX descriptors and allocate mbufs for them. 729 */ 730static int 731pcn_list_rx_init(sc) 732 struct pcn_softc *sc; 733{ 734 struct pcn_list_data *ld; 735 struct pcn_ring_data *cd; 736 int i; 737 738 ld = sc->pcn_ldata; 739 cd = &sc->pcn_cdata; 740 741 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 742 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 743 return(ENOBUFS); 744 } 745 746 cd->pcn_rx_prod = 0; 747 748 return(0); 749} 750 751/* 752 * Initialize an RX descriptor and attach an MBUF cluster. 753 */ 754static int 755pcn_newbuf(sc, idx, m) 756 struct pcn_softc *sc; 757 int idx; 758 struct mbuf *m; 759{ 760 struct mbuf *m_new = NULL; 761 struct pcn_rx_desc *c; 762 763 c = &sc->pcn_ldata->pcn_rx_list[idx]; 764 765 if (m == NULL) { 766 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 767 if (m_new == NULL) 768 return(ENOBUFS); 769 770 MCLGET(m_new, M_DONTWAIT); 771 if (!(m_new->m_flags & M_EXT)) { 772 m_freem(m_new); 773 return(ENOBUFS); 774 } 775 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 776 } else { 777 m_new = m; 778 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 779 m_new->m_data = m_new->m_ext.ext_buf; 780 } 781 782 m_adj(m_new, ETHER_ALIGN); 783 784 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 785 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 786 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 787 c->pcn_bufsz |= PCN_RXLEN_MBO; 788 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 789 790 return(0); 791} 792 793/* 794 * A frame has been uploaded: pass the resulting mbuf chain up to 795 * the higher level protocols. 796 */ 797static void 798pcn_rxeof(sc) 799 struct pcn_softc *sc; 800{ 801 struct ether_header *eh; 802 struct mbuf *m; 803 struct ifnet *ifp; 804 struct pcn_rx_desc *cur_rx; 805 int i; 806 807 ifp = &sc->arpcom.ac_if; 808 i = sc->pcn_cdata.pcn_rx_prod; 809 810 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 811 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 812 m = sc->pcn_cdata.pcn_rx_chain[i]; 813 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 814 815 /* 816 * If an error occurs, update stats, clear the 817 * status word and leave the mbuf cluster in place: 818 * it should simply get re-used next time this descriptor 819 * comes up in the ring. 820 */ 821 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 822 ifp->if_ierrors++; 823 pcn_newbuf(sc, i, m); 824 PCN_INC(i, PCN_RX_LIST_CNT); 825 continue; 826 } 827 828 if (pcn_newbuf(sc, i, NULL)) { 829 /* Ran out of mbufs; recycle this one. */ 830 pcn_newbuf(sc, i, m); 831 ifp->if_ierrors++; 832 PCN_INC(i, PCN_RX_LIST_CNT); 833 continue; 834 } 835 836 PCN_INC(i, PCN_RX_LIST_CNT); 837 838 /* No errors; receive the packet. */ 839 ifp->if_ipackets++; 840 eh = mtod(m, struct ether_header *); 841 m->m_len = m->m_pkthdr.len = 842 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 843 m->m_pkthdr.rcvif = ifp; 844 845 (*ifp->if_input)(ifp, m); 846 } 847 848 sc->pcn_cdata.pcn_rx_prod = i; 849 850 return; 851} 852 853/* 854 * A frame was downloaded to the chip. It's safe for us to clean up 855 * the list buffers. 856 */ 857 858static void 859pcn_txeof(sc) 860 struct pcn_softc *sc; 861{ 862 struct pcn_tx_desc *cur_tx = NULL; 863 struct ifnet *ifp; 864 u_int32_t idx; 865 866 ifp = &sc->arpcom.ac_if; 867 868 /* 869 * Go through our tx list and free mbufs for those 870 * frames that have been transmitted. 871 */ 872 idx = sc->pcn_cdata.pcn_tx_cons; 873 while (idx != sc->pcn_cdata.pcn_tx_prod) { 874 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 875 876 if (!PCN_OWN_TXDESC(cur_tx)) 877 break; 878 879 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 880 sc->pcn_cdata.pcn_tx_cnt--; 881 PCN_INC(idx, PCN_TX_LIST_CNT); 882 continue; 883 } 884 885 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 886 ifp->if_oerrors++; 887 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 888 ifp->if_collisions++; 889 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 890 ifp->if_collisions++; 891 } 892 893 ifp->if_collisions += 894 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 895 896 ifp->if_opackets++; 897 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 898 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 899 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 900 } 901 902 sc->pcn_cdata.pcn_tx_cnt--; 903 PCN_INC(idx, PCN_TX_LIST_CNT); 904 } 905 906 if (idx != sc->pcn_cdata.pcn_tx_cons) { 907 /* Some buffers have been freed. */ 908 sc->pcn_cdata.pcn_tx_cons = idx; 909 ifp->if_flags &= ~IFF_OACTIVE; 910 } 911 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 912 913 return; 914} 915 916static void 917pcn_tick(xsc) 918 void *xsc; 919{ 920 struct pcn_softc *sc; 921 struct mii_data *mii; 922 struct ifnet *ifp; 923 924 sc = xsc; 925 ifp = &sc->arpcom.ac_if; 926 PCN_LOCK(sc); 927 928 mii = device_get_softc(sc->pcn_miibus); 929 mii_tick(mii); 930 931 /* link just died */ 932 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 933 sc->pcn_link = 0; 934 935 /* link just came up, restart */ 936 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE && 937 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 938 sc->pcn_link++; 939 if (ifp->if_snd.ifq_head != NULL) 940 pcn_start(ifp); 941 } 942 943 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 944 945 PCN_UNLOCK(sc); 946 947 return; 948} 949 950static void 951pcn_intr(arg) 952 void *arg; 953{ 954 struct pcn_softc *sc; 955 struct ifnet *ifp; 956 u_int32_t status; 957 958 sc = arg; 959 ifp = &sc->arpcom.ac_if; 960 961 /* Supress unwanted interrupts */ 962 if (!(ifp->if_flags & IFF_UP)) { 963 pcn_stop(sc); 964 return; 965 } 966 967 PCN_LOCK(sc); 968 969 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 970 971 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 972 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 973 974 if (status & PCN_CSR_RINT) 975 pcn_rxeof(sc); 976 977 if (status & PCN_CSR_TINT) 978 pcn_txeof(sc); 979 980 if (status & PCN_CSR_ERR) { 981 pcn_init(sc); 982 break; 983 } 984 } 985 986 if (ifp->if_snd.ifq_head != NULL) 987 pcn_start(ifp); 988 989 PCN_UNLOCK(sc); 990 return; 991} 992 993/* 994 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 995 * pointers to the fragment pointers. 996 */ 997static int 998pcn_encap(sc, m_head, txidx) 999 struct pcn_softc *sc; 1000 struct mbuf *m_head; 1001 u_int32_t *txidx; 1002{ 1003 struct pcn_tx_desc *f = NULL; 1004 struct mbuf *m; 1005 int frag, cur, cnt = 0; 1006 1007 /* 1008 * Start packing the mbufs in this chain into 1009 * the fragment pointers. Stop when we run out 1010 * of fragments or hit the end of the mbuf chain. 1011 */ 1012 m = m_head; 1013 cur = frag = *txidx; 1014 1015 for (m = m_head; m != NULL; m = m->m_next) { 1016 if (m->m_len != 0) { 1017 if ((PCN_TX_LIST_CNT - 1018 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 1019 return(ENOBUFS); 1020 f = &sc->pcn_ldata->pcn_tx_list[frag]; 1021 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 1022 f->pcn_txctl |= PCN_TXCTL_MBO; 1023 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 1024 if (cnt == 0) 1025 f->pcn_txctl |= PCN_TXCTL_STP; 1026 else 1027 f->pcn_txctl |= PCN_TXCTL_OWN; 1028 cur = frag; 1029 PCN_INC(frag, PCN_TX_LIST_CNT); 1030 cnt++; 1031 } 1032 } 1033 1034 if (m != NULL) 1035 return(ENOBUFS); 1036 1037 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1038 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1039 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1040 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1041 sc->pcn_cdata.pcn_tx_cnt += cnt; 1042 *txidx = frag; 1043 1044 return(0); 1045} 1046 1047/* 1048 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1049 * to the mbuf data regions directly in the transmit lists. We also save a 1050 * copy of the pointers since the transmit list fragment pointers are 1051 * physical addresses. 1052 */ 1053static void 1054pcn_start(ifp) 1055 struct ifnet *ifp; 1056{ 1057 struct pcn_softc *sc; 1058 struct mbuf *m_head = NULL; 1059 u_int32_t idx; 1060 1061 sc = ifp->if_softc; 1062 1063 PCN_LOCK(sc); 1064 1065 if (!sc->pcn_link) { 1066 PCN_UNLOCK(sc); 1067 return; 1068 } 1069 1070 idx = sc->pcn_cdata.pcn_tx_prod; 1071 1072 if (ifp->if_flags & IFF_OACTIVE) { 1073 PCN_UNLOCK(sc); 1074 return; 1075 } 1076 1077 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1078 IF_DEQUEUE(&ifp->if_snd, m_head); 1079 if (m_head == NULL) 1080 break; 1081 1082 if (pcn_encap(sc, m_head, &idx)) { 1083 IF_PREPEND(&ifp->if_snd, m_head); 1084 ifp->if_flags |= IFF_OACTIVE; 1085 break; 1086 } 1087 1088 /* 1089 * If there's a BPF listener, bounce a copy of this frame 1090 * to him. 1091 */ 1092 BPF_MTAP(ifp, m_head); 1093 1094 } 1095 1096 /* Transmit */ 1097 sc->pcn_cdata.pcn_tx_prod = idx; 1098 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1099 1100 /* 1101 * Set a timeout in case the chip goes out to lunch. 1102 */ 1103 ifp->if_timer = 5; 1104 1105 PCN_UNLOCK(sc); 1106 1107 return; 1108} 1109 1110static void 1111pcn_setfilt(ifp) 1112 struct ifnet *ifp; 1113{ 1114 struct pcn_softc *sc; 1115 1116 sc = ifp->if_softc; 1117 1118 /* If we want promiscuous mode, set the allframes bit. */ 1119 if (ifp->if_flags & IFF_PROMISC) { 1120 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1121 } else { 1122 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1123 } 1124 1125 /* Set the capture broadcast bit to capture broadcast frames. */ 1126 if (ifp->if_flags & IFF_BROADCAST) { 1127 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1128 } else { 1129 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1130 } 1131 1132 return; 1133} 1134 1135static void 1136pcn_init(xsc) 1137 void *xsc; 1138{ 1139 struct pcn_softc *sc = xsc; 1140 struct ifnet *ifp = &sc->arpcom.ac_if; 1141 struct mii_data *mii = NULL; 1142 1143 PCN_LOCK(sc); 1144 1145 /* 1146 * Cancel pending I/O and free all RX/TX buffers. 1147 */ 1148 pcn_stop(sc); 1149 pcn_reset(sc); 1150 1151 mii = device_get_softc(sc->pcn_miibus); 1152 1153 /* Set MAC address */ 1154 pcn_csr_write(sc, PCN_CSR_PAR0, 1155 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1156 pcn_csr_write(sc, PCN_CSR_PAR1, 1157 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1158 pcn_csr_write(sc, PCN_CSR_PAR2, 1159 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1160 1161 /* Init circular RX list. */ 1162 if (pcn_list_rx_init(sc) == ENOBUFS) { 1163 printf("pcn%d: initialization failed: no " 1164 "memory for rx buffers\n", sc->pcn_unit); 1165 pcn_stop(sc); 1166 PCN_UNLOCK(sc); 1167 return; 1168 } 1169 1170 /* 1171 * Init tx descriptors. 1172 */ 1173 pcn_list_tx_init(sc); 1174 1175 /* Set up the mode register. */ 1176 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1177 1178 /* Set up RX filter. */ 1179 pcn_setfilt(ifp); 1180 1181 /* 1182 * Load the multicast filter. 1183 */ 1184 pcn_setmulti(sc); 1185 1186 /* 1187 * Load the addresses of the RX and TX lists. 1188 */ 1189 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1190 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1191 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1192 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1193 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1194 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1195 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1196 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1197 1198 /* Set the RX and TX ring sizes. */ 1199 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1200 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1201 1202 /* We're not using the initialization block. */ 1203 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1204 1205 /* Enable fast suspend mode. */ 1206 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1207 1208 /* 1209 * Enable burst read and write. Also set the no underflow 1210 * bit. This will avoid transmit underruns in certain 1211 * conditions while still providing decent performance. 1212 */ 1213 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1214 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1215 1216 /* Enable graceful recovery from underflow. */ 1217 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1218 1219 /* Enable auto-padding of short TX frames. */ 1220 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1221 1222 /* Disable MII autoneg (we handle this ourselves). */ 1223 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1224 1225 if (sc->pcn_type == Am79C978) 1226 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1227 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1228 1229 /* Enable interrupts and start the controller running. */ 1230 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1231 1232 mii_mediachg(mii); 1233 1234 ifp->if_flags |= IFF_RUNNING; 1235 ifp->if_flags &= ~IFF_OACTIVE; 1236 1237 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 1238 PCN_UNLOCK(sc); 1239 1240 return; 1241} 1242 1243/* 1244 * Set media options. 1245 */ 1246static int 1247pcn_ifmedia_upd(ifp) 1248 struct ifnet *ifp; 1249{ 1250 struct pcn_softc *sc; 1251 struct mii_data *mii; 1252 1253 sc = ifp->if_softc; 1254 mii = device_get_softc(sc->pcn_miibus); 1255 1256 sc->pcn_link = 0; 1257 if (mii->mii_instance) { 1258 struct mii_softc *miisc; 1259 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1260 mii_phy_reset(miisc); 1261 } 1262 mii_mediachg(mii); 1263 1264 return(0); 1265} 1266 1267/* 1268 * Report current media status. 1269 */ 1270static void 1271pcn_ifmedia_sts(ifp, ifmr) 1272 struct ifnet *ifp; 1273 struct ifmediareq *ifmr; 1274{ 1275 struct pcn_softc *sc; 1276 struct mii_data *mii; 1277 1278 sc = ifp->if_softc; 1279 1280 mii = device_get_softc(sc->pcn_miibus); 1281 mii_pollstat(mii); 1282 ifmr->ifm_active = mii->mii_media_active; 1283 ifmr->ifm_status = mii->mii_media_status; 1284 1285 return; 1286} 1287 1288static int 1289pcn_ioctl(ifp, command, data) 1290 struct ifnet *ifp; 1291 u_long command; 1292 caddr_t data; 1293{ 1294 struct pcn_softc *sc = ifp->if_softc; 1295 struct ifreq *ifr = (struct ifreq *) data; 1296 struct mii_data *mii = NULL; 1297 int error = 0; 1298 1299 PCN_LOCK(sc); 1300 1301 switch(command) { 1302 case SIOCSIFFLAGS: 1303 if (ifp->if_flags & IFF_UP) { 1304 if (ifp->if_flags & IFF_RUNNING && 1305 ifp->if_flags & IFF_PROMISC && 1306 !(sc->pcn_if_flags & IFF_PROMISC)) { 1307 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1308 PCN_EXTCTL1_SPND); 1309 pcn_setfilt(ifp); 1310 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1311 PCN_EXTCTL1_SPND); 1312 pcn_csr_write(sc, PCN_CSR_CSR, 1313 PCN_CSR_INTEN|PCN_CSR_START); 1314 } else if (ifp->if_flags & IFF_RUNNING && 1315 !(ifp->if_flags & IFF_PROMISC) && 1316 sc->pcn_if_flags & IFF_PROMISC) { 1317 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1318 PCN_EXTCTL1_SPND); 1319 pcn_setfilt(ifp); 1320 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1321 PCN_EXTCTL1_SPND); 1322 pcn_csr_write(sc, PCN_CSR_CSR, 1323 PCN_CSR_INTEN|PCN_CSR_START); 1324 } else if (!(ifp->if_flags & IFF_RUNNING)) 1325 pcn_init(sc); 1326 } else { 1327 if (ifp->if_flags & IFF_RUNNING) 1328 pcn_stop(sc); 1329 } 1330 sc->pcn_if_flags = ifp->if_flags; 1331 error = 0; 1332 break; 1333 case SIOCADDMULTI: 1334 case SIOCDELMULTI: 1335 pcn_setmulti(sc); 1336 error = 0; 1337 break; 1338 case SIOCGIFMEDIA: 1339 case SIOCSIFMEDIA: 1340 mii = device_get_softc(sc->pcn_miibus); 1341 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1342 break; 1343 default: 1344 error = ether_ioctl(ifp, command, data); 1345 break; 1346 } 1347 1348 PCN_UNLOCK(sc); 1349 1350 return(error); 1351} 1352 1353static void 1354pcn_watchdog(ifp) 1355 struct ifnet *ifp; 1356{ 1357 struct pcn_softc *sc; 1358 1359 sc = ifp->if_softc; 1360 1361 PCN_LOCK(sc); 1362 1363 ifp->if_oerrors++; 1364 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1365 1366 pcn_stop(sc); 1367 pcn_reset(sc); 1368 pcn_init(sc); 1369 1370 if (ifp->if_snd.ifq_head != NULL) 1371 pcn_start(ifp); 1372 1373 PCN_UNLOCK(sc); 1374 1375 return; 1376} 1377 1378/* 1379 * Stop the adapter and free any mbufs allocated to the 1380 * RX and TX lists. 1381 */ 1382static void 1383pcn_stop(sc) 1384 struct pcn_softc *sc; 1385{ 1386 register int i; 1387 struct ifnet *ifp; 1388 1389 ifp = &sc->arpcom.ac_if; 1390 PCN_LOCK(sc); 1391 ifp->if_timer = 0; 1392 1393 untimeout(pcn_tick, sc, sc->pcn_stat_ch); 1394 1395 /* Turn off interrupts */ 1396 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN); 1397 /* Stop adapter */ 1398 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1399 sc->pcn_link = 0; 1400 1401 /* 1402 * Free data in the RX lists. 1403 */ 1404 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1405 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1406 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1407 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1408 } 1409 } 1410 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1411 sizeof(sc->pcn_ldata->pcn_rx_list)); 1412 1413 /* 1414 * Free the TX list buffers. 1415 */ 1416 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1417 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1418 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1419 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1420 } 1421 } 1422 1423 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1424 sizeof(sc->pcn_ldata->pcn_tx_list)); 1425 1426 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1427 PCN_UNLOCK(sc); 1428 1429 return; 1430} 1431 1432/* 1433 * Stop all chip I/O so that the kernel's probe routines don't 1434 * get confused by errant DMAs when rebooting. 1435 */ 1436static void 1437pcn_shutdown(dev) 1438 device_t dev; 1439{ 1440 struct pcn_softc *sc; 1441 1442 sc = device_get_softc(dev); 1443 1444 PCN_LOCK(sc); 1445 pcn_reset(sc); 1446 pcn_stop(sc); 1447 PCN_UNLOCK(sc); 1448 1449 return; 1450} 1451