if_pcn.c revision 112872
1/* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/pci/if_pcn.c 112872 2003-03-31 17:29:43Z njl $ 34 */ 35 36/* 37 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 38 * from http://www.amd.com. 39 * 40 * Written by Bill Paul <wpaul@osd.bsdi.com> 41 */ 42 43/* 44 * The AMD PCnet/PCI controllers are more advanced and functional 45 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 46 * backwards compatibility with the LANCE and thus can be made 47 * to work with older LANCE drivers. This is in fact how the 48 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 49 * is that the PCnet/PCI devices offer several performance enhancements 50 * which can't be exploited in LANCE compatibility mode. Chief among 51 * these enhancements is the ability to perform PCI DMA operations 52 * using 32-bit addressing (which eliminates the need for ISA 53 * bounce-buffering), and special receive buffer alignment (which 54 * allows the receive handler to pass packets to the upper protocol 55 * layers without copying on both the x86 and alpha platforms). 56 */ 57 58#include <sys/param.h> 59#include <sys/systm.h> 60#include <sys/sockio.h> 61#include <sys/mbuf.h> 62#include <sys/malloc.h> 63#include <sys/kernel.h> 64#include <sys/socket.h> 65 66#include <net/if.h> 67#include <net/if_arp.h> 68#include <net/ethernet.h> 69#include <net/if_dl.h> 70#include <net/if_media.h> 71 72#include <net/bpf.h> 73 74#include <vm/vm.h> /* for vtophys */ 75#include <vm/pmap.h> /* for vtophys */ 76#include <machine/bus_pio.h> 77#include <machine/bus_memio.h> 78#include <machine/bus.h> 79#include <machine/resource.h> 80#include <sys/bus.h> 81#include <sys/rman.h> 82 83#include <dev/mii/mii.h> 84#include <dev/mii/miivar.h> 85 86#include <pci/pcireg.h> 87#include <pci/pcivar.h> 88 89#define PCN_USEIOSPACE 90 91#include <pci/if_pcnreg.h> 92 93MODULE_DEPEND(pcn, miibus, 1, 1, 1); 94 95/* "controller miibus0" required. See GENERIC if you get errors here. */ 96#include "miibus_if.h" 97 98#ifndef lint 99static const char rcsid[] = 100 "$FreeBSD: head/sys/pci/if_pcn.c 112872 2003-03-31 17:29:43Z njl $"; 101#endif 102 103/* 104 * Various supported device vendors/types and their names. 105 */ 106static struct pcn_type pcn_devs[] = { 107 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 108 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 109 { 0, 0, NULL } 110}; 111 112static u_int32_t pcn_csr_read (struct pcn_softc *, int); 113static u_int16_t pcn_csr_read16 (struct pcn_softc *, int); 114static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int); 115static void pcn_csr_write (struct pcn_softc *, int, int); 116static u_int32_t pcn_bcr_read (struct pcn_softc *, int); 117static void pcn_bcr_write (struct pcn_softc *, int, int); 118 119static int pcn_probe (device_t); 120static int pcn_attach (device_t); 121static int pcn_detach (device_t); 122 123static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *); 124static int pcn_encap (struct pcn_softc *, 125 struct mbuf *, u_int32_t *); 126static void pcn_rxeof (struct pcn_softc *); 127static void pcn_txeof (struct pcn_softc *); 128static void pcn_intr (void *); 129static void pcn_tick (void *); 130static void pcn_start (struct ifnet *); 131static int pcn_ioctl (struct ifnet *, u_long, caddr_t); 132static void pcn_init (void *); 133static void pcn_stop (struct pcn_softc *); 134static void pcn_watchdog (struct ifnet *); 135static void pcn_shutdown (device_t); 136static int pcn_ifmedia_upd (struct ifnet *); 137static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *); 138 139static int pcn_miibus_readreg (device_t, int, int); 140static int pcn_miibus_writereg (device_t, int, int, int); 141static void pcn_miibus_statchg (device_t); 142 143static void pcn_setfilt (struct ifnet *); 144static void pcn_setmulti (struct pcn_softc *); 145static u_int32_t pcn_crc (caddr_t); 146static void pcn_reset (struct pcn_softc *); 147static int pcn_list_rx_init (struct pcn_softc *); 148static int pcn_list_tx_init (struct pcn_softc *); 149 150#ifdef PCN_USEIOSPACE 151#define PCN_RES SYS_RES_IOPORT 152#define PCN_RID PCN_PCI_LOIO 153#else 154#define PCN_RES SYS_RES_MEMORY 155#define PCN_RID PCN_PCI_LOMEM 156#endif 157 158static device_method_t pcn_methods[] = { 159 /* Device interface */ 160 DEVMETHOD(device_probe, pcn_probe), 161 DEVMETHOD(device_attach, pcn_attach), 162 DEVMETHOD(device_detach, pcn_detach), 163 DEVMETHOD(device_shutdown, pcn_shutdown), 164 165 /* bus interface */ 166 DEVMETHOD(bus_print_child, bus_generic_print_child), 167 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 168 169 /* MII interface */ 170 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 171 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 172 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 173 174 { 0, 0 } 175}; 176 177static driver_t pcn_driver = { 178 "pcn", 179 pcn_methods, 180 sizeof(struct pcn_softc) 181}; 182 183static devclass_t pcn_devclass; 184 185DRIVER_MODULE(if_pcn, pci, pcn_driver, pcn_devclass, 0, 0); 186DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 187 188#define PCN_CSR_SETBIT(sc, reg, x) \ 189 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 190 191#define PCN_CSR_CLRBIT(sc, reg, x) \ 192 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 193 194#define PCN_BCR_SETBIT(sc, reg, x) \ 195 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 196 197#define PCN_BCR_CLRBIT(sc, reg, x) \ 198 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 199 200static u_int32_t 201pcn_csr_read(sc, reg) 202 struct pcn_softc *sc; 203 int reg; 204{ 205 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 206 return(CSR_READ_4(sc, PCN_IO32_RDP)); 207} 208 209static u_int16_t 210pcn_csr_read16(sc, reg) 211 struct pcn_softc *sc; 212 int reg; 213{ 214 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 215 return(CSR_READ_2(sc, PCN_IO16_RDP)); 216} 217 218static void 219pcn_csr_write(sc, reg, val) 220 struct pcn_softc *sc; 221 int reg; 222{ 223 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 224 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 225 return; 226} 227 228static u_int32_t 229pcn_bcr_read(sc, reg) 230 struct pcn_softc *sc; 231 int reg; 232{ 233 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 234 return(CSR_READ_4(sc, PCN_IO32_BDP)); 235} 236 237static u_int16_t 238pcn_bcr_read16(sc, reg) 239 struct pcn_softc *sc; 240 int reg; 241{ 242 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 243 return(CSR_READ_2(sc, PCN_IO16_BDP)); 244} 245 246static void 247pcn_bcr_write(sc, reg, val) 248 struct pcn_softc *sc; 249 int reg; 250{ 251 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 252 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 253 return; 254} 255 256static int 257pcn_miibus_readreg(dev, phy, reg) 258 device_t dev; 259 int phy, reg; 260{ 261 struct pcn_softc *sc; 262 int val; 263 264 sc = device_get_softc(dev); 265 266 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 267 return(0); 268 269 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 270 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 271 if (val == 0xFFFF) 272 return(0); 273 274 sc->pcn_phyaddr = phy; 275 276 return(val); 277} 278 279static int 280pcn_miibus_writereg(dev, phy, reg, data) 281 device_t dev; 282 int phy, reg, data; 283{ 284 struct pcn_softc *sc; 285 286 sc = device_get_softc(dev); 287 288 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 289 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 290 291 return(0); 292} 293 294static void 295pcn_miibus_statchg(dev) 296 device_t dev; 297{ 298 struct pcn_softc *sc; 299 struct mii_data *mii; 300 301 sc = device_get_softc(dev); 302 mii = device_get_softc(sc->pcn_miibus); 303 304 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 305 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 306 } else { 307 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 308 } 309 310 return; 311} 312 313#define DC_POLY 0xEDB88320 314 315static u_int32_t 316pcn_crc(addr) 317 caddr_t addr; 318{ 319 u_int32_t idx, bit, data, crc; 320 321 /* Compute CRC for the address value. */ 322 crc = 0xFFFFFFFF; /* initial value */ 323 324 for (idx = 0; idx < 6; idx++) { 325 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 326 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 327 } 328 329 return ((crc >> 26) & 0x3F); 330} 331 332static void 333pcn_setmulti(sc) 334 struct pcn_softc *sc; 335{ 336 struct ifnet *ifp; 337 struct ifmultiaddr *ifma; 338 u_int32_t h, i; 339 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 340 341 ifp = &sc->arpcom.ac_if; 342 343 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 344 345 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 346 for (i = 0; i < 4; i++) 347 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 348 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 349 return; 350 } 351 352 /* first, zot all the existing hash bits */ 353 for (i = 0; i < 4; i++) 354 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 355 356 /* now program new ones */ 357 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 358 if (ifma->ifma_addr->sa_family != AF_LINK) 359 continue; 360 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 361 hashes[h >> 4] |= 1 << (h & 0xF); 362 } 363 364 for (i = 0; i < 4; i++) 365 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 366 367 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 368 369 return; 370} 371 372static void 373pcn_reset(sc) 374 struct pcn_softc *sc; 375{ 376 /* 377 * Issue a reset by reading from the RESET register. 378 * Note that we don't know if the chip is operating in 379 * 16-bit or 32-bit mode at this point, so we attempt 380 * to reset the chip both ways. If one fails, the other 381 * will succeed. 382 */ 383 CSR_READ_2(sc, PCN_IO16_RESET); 384 CSR_READ_4(sc, PCN_IO32_RESET); 385 386 /* Wait a little while for the chip to get its brains in order. */ 387 DELAY(1000); 388 389 /* Select 32-bit (DWIO) mode */ 390 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 391 392 /* Select software style 3. */ 393 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 394 395 return; 396} 397 398/* 399 * Probe for an AMD chip. Check the PCI vendor and device 400 * IDs against our list and return a device name if we find a match. 401 */ 402static int 403pcn_probe(dev) 404 device_t dev; 405{ 406 struct pcn_type *t; 407 struct pcn_softc *sc; 408 int rid; 409 u_int32_t chip_id; 410 411 t = pcn_devs; 412 sc = device_get_softc(dev); 413 414 while(t->pcn_name != NULL) { 415 if ((pci_get_vendor(dev) == t->pcn_vid) && 416 (pci_get_device(dev) == t->pcn_did)) { 417 /* 418 * Temporarily map the I/O space 419 * so we can read the chip ID register. 420 */ 421 rid = PCN_RID; 422 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 423 0, ~0, 1, RF_ACTIVE); 424 if (sc->pcn_res == NULL) { 425 device_printf(dev, 426 "couldn't map ports/memory\n"); 427 return(ENXIO); 428 } 429 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 430 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 431 mtx_init(&sc->pcn_mtx, 432 device_get_nameunit(dev), MTX_NETWORK_LOCK, 433 MTX_DEF); 434 PCN_LOCK(sc); 435 /* 436 * Note: we can *NOT* put the chip into 437 * 32-bit mode yet. The lnc driver will only 438 * work in 16-bit mode, and once the chip 439 * goes into 32-bit mode, the only way to 440 * get it out again is with a hardware reset. 441 * So if pcn_probe() is called before the 442 * lnc driver's probe routine, the chip will 443 * be locked into 32-bit operation and the lnc 444 * driver will be unable to attach to it. 445 * Note II: if the chip happens to already 446 * be in 32-bit mode, we still need to check 447 * the chip ID, but first we have to detect 448 * 32-bit mode using only 16-bit operations. 449 * The safest way to do this is to read the 450 * PCI subsystem ID from BCR23/24 and compare 451 * that with the value read from PCI config 452 * space. 453 */ 454 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 455 chip_id <<= 16; 456 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 457 /* 458 * Note III: the test for 0x10001000 is a hack to 459 * pacify VMware, who's pseudo-PCnet interface is 460 * broken. Reading the subsystem register from PCI 461 * config space yeilds 0x00000000 while reading the 462 * same value from I/O space yeilds 0x10001000. It's 463 * not supposed to be that way. 464 */ 465 if (chip_id == pci_read_config(dev, 466 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 467 /* We're in 16-bit mode. */ 468 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 469 chip_id <<= 16; 470 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 471 } else { 472 /* We're in 32-bit mode. */ 473 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 474 chip_id <<= 16; 475 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 476 } 477 bus_release_resource(dev, PCN_RES, 478 PCN_RID, sc->pcn_res); 479 PCN_UNLOCK(sc); 480 mtx_destroy(&sc->pcn_mtx); 481 chip_id >>= 12; 482 sc->pcn_type = chip_id & PART_MASK; 483 switch(sc->pcn_type) { 484 case Am79C971: 485 case Am79C972: 486 case Am79C973: 487 case Am79C975: 488 case Am79C976: 489 case Am79C978: 490 break; 491 default: 492 return(ENXIO); 493 break; 494 } 495 device_set_desc(dev, t->pcn_name); 496 return(0); 497 } 498 t++; 499 } 500 501 return(ENXIO); 502} 503 504/* 505 * Attach the interface. Allocate softc structures, do ifmedia 506 * setup and ethernet/BPF attach. 507 */ 508static int 509pcn_attach(dev) 510 device_t dev; 511{ 512 u_int32_t eaddr[2]; 513 u_int32_t command; 514 struct pcn_softc *sc; 515 struct ifnet *ifp; 516 int unit, error = 0, rid; 517 518 sc = device_get_softc(dev); 519 unit = device_get_unit(dev); 520 521 /* Initialize our mutex. */ 522 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 523 MTX_DEF | MTX_RECURSE); 524 525 /* 526 * Handle power management nonsense. 527 */ 528 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 529 u_int32_t iobase, membase, irq; 530 531 /* Save important PCI config data. */ 532 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 533 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 534 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 535 536 /* Reset the power state. */ 537 printf("pcn%d: chip is in D%d power mode " 538 "-- setting to D0\n", unit, 539 pci_get_powerstate(dev)); 540 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 541 542 /* Restore PCI config data. */ 543 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 544 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 545 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 546 } 547 548 /* 549 * Map control/status registers. 550 */ 551 pci_enable_busmaster(dev); 552 pci_enable_io(dev, SYS_RES_IOPORT); 553 pci_enable_io(dev, SYS_RES_MEMORY); 554 command = pci_read_config(dev, PCIR_COMMAND, 4); 555 556#ifdef PCN_USEIOSPACE 557 if (!(command & PCIM_CMD_PORTEN)) { 558 printf("pcn%d: failed to enable I/O ports!\n", unit); 559 error = ENXIO; 560 goto fail; 561 } 562#else 563 if (!(command & PCIM_CMD_MEMEN)) { 564 printf("pcn%d: failed to enable memory mapping!\n", unit); 565 error = ENXIO; 566 goto fail; 567 } 568#endif 569 570 rid = PCN_RID; 571 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 572 0, ~0, 1, RF_ACTIVE); 573 574 if (sc->pcn_res == NULL) { 575 printf("pcn%d: couldn't map ports/memory\n", unit); 576 error = ENXIO; 577 goto fail; 578 } 579 580 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 581 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 582 583 /* Allocate interrupt */ 584 rid = 0; 585 sc->pcn_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 586 RF_SHAREABLE | RF_ACTIVE); 587 588 if (sc->pcn_irq == NULL) { 589 printf("pcn%d: couldn't map interrupt\n", unit); 590 error = ENXIO; 591 goto fail; 592 } 593 594 /* Reset the adapter. */ 595 pcn_reset(sc); 596 597 /* 598 * Get station address from the EEPROM. 599 */ 600 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 601 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 602 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 603 604 /* 605 * An AMD chip was detected. Inform the world. 606 */ 607 printf("pcn%d: Ethernet address: %6D\n", unit, 608 sc->arpcom.ac_enaddr, ":"); 609 610 sc->pcn_unit = unit; 611 callout_handle_init(&sc->pcn_stat_ch); 612 613 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 614 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 615 616 if (sc->pcn_ldata == NULL) { 617 printf("pcn%d: no memory for list buffers!\n", unit); 618 error = ENXIO; 619 goto fail; 620 } 621 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 622 623 ifp = &sc->arpcom.ac_if; 624 ifp->if_softc = sc; 625 ifp->if_unit = unit; 626 ifp->if_name = "pcn"; 627 ifp->if_mtu = ETHERMTU; 628 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 629 ifp->if_ioctl = pcn_ioctl; 630 ifp->if_output = ether_output; 631 ifp->if_start = pcn_start; 632 ifp->if_watchdog = pcn_watchdog; 633 ifp->if_init = pcn_init; 634 ifp->if_baudrate = 10000000; 635 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 636 637 /* 638 * Do MII setup. 639 */ 640 if (mii_phy_probe(dev, &sc->pcn_miibus, 641 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 642 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 643 error = ENXIO; 644 goto fail; 645 } 646 647 /* 648 * Call MI attach routine. 649 */ 650 ether_ifattach(ifp, (u_int8_t *) eaddr); 651 652 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 653 pcn_intr, sc, &sc->pcn_intrhand); 654 655 if (error) { 656 printf("pcn%d: couldn't set up irq\n", unit); 657 goto fail; 658 } 659 660fail: 661 if (error) 662 pcn_detach(dev); 663 664 return(error); 665} 666 667static int 668pcn_detach(dev) 669 device_t dev; 670{ 671 struct pcn_softc *sc; 672 struct ifnet *ifp; 673 674 sc = device_get_softc(dev); 675 ifp = &sc->arpcom.ac_if; 676 677 KASSERT(mtx_initialized(&sc->pcn_mtx), "pcn mutex not initialized"); 678 PCN_LOCK(sc); 679 680 if (device_is_alive(dev)) { 681 if (bus_child_present(dev)) { 682 pcn_reset(sc); 683 pcn_stop(sc); 684 } 685 ether_ifdetach(ifp); 686 device_delete_child(dev, sc->pcn_miibus); 687 bus_generic_detach(dev); 688 } 689 690 if (sc->pcn_intrhand) 691 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 692 if (sc->pcn_irq) 693 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 694 if (sc->pcn_res) 695 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 696 697 if (sc->pcn_ldata) { 698 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 699 M_DEVBUF); 700 } 701 PCN_UNLOCK(sc); 702 703 mtx_destroy(&sc->pcn_mtx); 704 705 return(0); 706} 707 708/* 709 * Initialize the transmit descriptors. 710 */ 711static int 712pcn_list_tx_init(sc) 713 struct pcn_softc *sc; 714{ 715 struct pcn_list_data *ld; 716 struct pcn_ring_data *cd; 717 int i; 718 719 cd = &sc->pcn_cdata; 720 ld = sc->pcn_ldata; 721 722 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 723 cd->pcn_tx_chain[i] = NULL; 724 ld->pcn_tx_list[i].pcn_tbaddr = 0; 725 ld->pcn_tx_list[i].pcn_txctl = 0; 726 ld->pcn_tx_list[i].pcn_txstat = 0; 727 } 728 729 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 730 731 return(0); 732} 733 734 735/* 736 * Initialize the RX descriptors and allocate mbufs for them. 737 */ 738static int 739pcn_list_rx_init(sc) 740 struct pcn_softc *sc; 741{ 742 struct pcn_list_data *ld; 743 struct pcn_ring_data *cd; 744 int i; 745 746 ld = sc->pcn_ldata; 747 cd = &sc->pcn_cdata; 748 749 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 750 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 751 return(ENOBUFS); 752 } 753 754 cd->pcn_rx_prod = 0; 755 756 return(0); 757} 758 759/* 760 * Initialize an RX descriptor and attach an MBUF cluster. 761 */ 762static int 763pcn_newbuf(sc, idx, m) 764 struct pcn_softc *sc; 765 int idx; 766 struct mbuf *m; 767{ 768 struct mbuf *m_new = NULL; 769 struct pcn_rx_desc *c; 770 771 c = &sc->pcn_ldata->pcn_rx_list[idx]; 772 773 if (m == NULL) { 774 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 775 if (m_new == NULL) 776 return(ENOBUFS); 777 778 MCLGET(m_new, M_DONTWAIT); 779 if (!(m_new->m_flags & M_EXT)) { 780 m_freem(m_new); 781 return(ENOBUFS); 782 } 783 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 784 } else { 785 m_new = m; 786 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 787 m_new->m_data = m_new->m_ext.ext_buf; 788 } 789 790 m_adj(m_new, ETHER_ALIGN); 791 792 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 793 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 794 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 795 c->pcn_bufsz |= PCN_RXLEN_MBO; 796 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 797 798 return(0); 799} 800 801/* 802 * A frame has been uploaded: pass the resulting mbuf chain up to 803 * the higher level protocols. 804 */ 805static void 806pcn_rxeof(sc) 807 struct pcn_softc *sc; 808{ 809 struct ether_header *eh; 810 struct mbuf *m; 811 struct ifnet *ifp; 812 struct pcn_rx_desc *cur_rx; 813 int i; 814 815 ifp = &sc->arpcom.ac_if; 816 i = sc->pcn_cdata.pcn_rx_prod; 817 818 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 819 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 820 m = sc->pcn_cdata.pcn_rx_chain[i]; 821 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 822 823 /* 824 * If an error occurs, update stats, clear the 825 * status word and leave the mbuf cluster in place: 826 * it should simply get re-used next time this descriptor 827 * comes up in the ring. 828 */ 829 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 830 ifp->if_ierrors++; 831 pcn_newbuf(sc, i, m); 832 PCN_INC(i, PCN_RX_LIST_CNT); 833 continue; 834 } 835 836 if (pcn_newbuf(sc, i, NULL)) { 837 /* Ran out of mbufs; recycle this one. */ 838 pcn_newbuf(sc, i, m); 839 ifp->if_ierrors++; 840 PCN_INC(i, PCN_RX_LIST_CNT); 841 continue; 842 } 843 844 PCN_INC(i, PCN_RX_LIST_CNT); 845 846 /* No errors; receive the packet. */ 847 ifp->if_ipackets++; 848 eh = mtod(m, struct ether_header *); 849 m->m_len = m->m_pkthdr.len = 850 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 851 m->m_pkthdr.rcvif = ifp; 852 853 (*ifp->if_input)(ifp, m); 854 } 855 856 sc->pcn_cdata.pcn_rx_prod = i; 857 858 return; 859} 860 861/* 862 * A frame was downloaded to the chip. It's safe for us to clean up 863 * the list buffers. 864 */ 865 866static void 867pcn_txeof(sc) 868 struct pcn_softc *sc; 869{ 870 struct pcn_tx_desc *cur_tx = NULL; 871 struct ifnet *ifp; 872 u_int32_t idx; 873 874 ifp = &sc->arpcom.ac_if; 875 876 /* 877 * Go through our tx list and free mbufs for those 878 * frames that have been transmitted. 879 */ 880 idx = sc->pcn_cdata.pcn_tx_cons; 881 while (idx != sc->pcn_cdata.pcn_tx_prod) { 882 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 883 884 if (!PCN_OWN_TXDESC(cur_tx)) 885 break; 886 887 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 888 sc->pcn_cdata.pcn_tx_cnt--; 889 PCN_INC(idx, PCN_TX_LIST_CNT); 890 continue; 891 } 892 893 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 894 ifp->if_oerrors++; 895 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 896 ifp->if_collisions++; 897 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 898 ifp->if_collisions++; 899 } 900 901 ifp->if_collisions += 902 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 903 904 ifp->if_opackets++; 905 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 906 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 907 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 908 } 909 910 sc->pcn_cdata.pcn_tx_cnt--; 911 PCN_INC(idx, PCN_TX_LIST_CNT); 912 } 913 914 if (idx != sc->pcn_cdata.pcn_tx_cons) { 915 /* Some buffers have been freed. */ 916 sc->pcn_cdata.pcn_tx_cons = idx; 917 ifp->if_flags &= ~IFF_OACTIVE; 918 } 919 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 920 921 return; 922} 923 924static void 925pcn_tick(xsc) 926 void *xsc; 927{ 928 struct pcn_softc *sc; 929 struct mii_data *mii; 930 struct ifnet *ifp; 931 932 sc = xsc; 933 ifp = &sc->arpcom.ac_if; 934 PCN_LOCK(sc); 935 936 mii = device_get_softc(sc->pcn_miibus); 937 mii_tick(mii); 938 939 /* link just died */ 940 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 941 sc->pcn_link = 0; 942 943 /* link just came up, restart */ 944 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE && 945 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 946 sc->pcn_link++; 947 if (ifp->if_snd.ifq_head != NULL) 948 pcn_start(ifp); 949 } 950 951 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 952 953 PCN_UNLOCK(sc); 954 955 return; 956} 957 958static void 959pcn_intr(arg) 960 void *arg; 961{ 962 struct pcn_softc *sc; 963 struct ifnet *ifp; 964 u_int32_t status; 965 966 sc = arg; 967 ifp = &sc->arpcom.ac_if; 968 969 /* Supress unwanted interrupts */ 970 if (!(ifp->if_flags & IFF_UP)) { 971 pcn_stop(sc); 972 return; 973 } 974 975 PCN_LOCK(sc); 976 977 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 978 979 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 980 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 981 982 if (status & PCN_CSR_RINT) 983 pcn_rxeof(sc); 984 985 if (status & PCN_CSR_TINT) 986 pcn_txeof(sc); 987 988 if (status & PCN_CSR_ERR) { 989 pcn_init(sc); 990 break; 991 } 992 } 993 994 if (ifp->if_snd.ifq_head != NULL) 995 pcn_start(ifp); 996 997 PCN_UNLOCK(sc); 998 return; 999} 1000 1001/* 1002 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1003 * pointers to the fragment pointers. 1004 */ 1005static int 1006pcn_encap(sc, m_head, txidx) 1007 struct pcn_softc *sc; 1008 struct mbuf *m_head; 1009 u_int32_t *txidx; 1010{ 1011 struct pcn_tx_desc *f = NULL; 1012 struct mbuf *m; 1013 int frag, cur, cnt = 0; 1014 1015 /* 1016 * Start packing the mbufs in this chain into 1017 * the fragment pointers. Stop when we run out 1018 * of fragments or hit the end of the mbuf chain. 1019 */ 1020 m = m_head; 1021 cur = frag = *txidx; 1022 1023 for (m = m_head; m != NULL; m = m->m_next) { 1024 if (m->m_len != 0) { 1025 if ((PCN_TX_LIST_CNT - 1026 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 1027 return(ENOBUFS); 1028 f = &sc->pcn_ldata->pcn_tx_list[frag]; 1029 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 1030 f->pcn_txctl |= PCN_TXCTL_MBO; 1031 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 1032 if (cnt == 0) 1033 f->pcn_txctl |= PCN_TXCTL_STP; 1034 else 1035 f->pcn_txctl |= PCN_TXCTL_OWN; 1036 cur = frag; 1037 PCN_INC(frag, PCN_TX_LIST_CNT); 1038 cnt++; 1039 } 1040 } 1041 1042 if (m != NULL) 1043 return(ENOBUFS); 1044 1045 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1046 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1047 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1048 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1049 sc->pcn_cdata.pcn_tx_cnt += cnt; 1050 *txidx = frag; 1051 1052 return(0); 1053} 1054 1055/* 1056 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1057 * to the mbuf data regions directly in the transmit lists. We also save a 1058 * copy of the pointers since the transmit list fragment pointers are 1059 * physical addresses. 1060 */ 1061static void 1062pcn_start(ifp) 1063 struct ifnet *ifp; 1064{ 1065 struct pcn_softc *sc; 1066 struct mbuf *m_head = NULL; 1067 u_int32_t idx; 1068 1069 sc = ifp->if_softc; 1070 1071 PCN_LOCK(sc); 1072 1073 if (!sc->pcn_link) { 1074 PCN_UNLOCK(sc); 1075 return; 1076 } 1077 1078 idx = sc->pcn_cdata.pcn_tx_prod; 1079 1080 if (ifp->if_flags & IFF_OACTIVE) { 1081 PCN_UNLOCK(sc); 1082 return; 1083 } 1084 1085 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1086 IF_DEQUEUE(&ifp->if_snd, m_head); 1087 if (m_head == NULL) 1088 break; 1089 1090 if (pcn_encap(sc, m_head, &idx)) { 1091 IF_PREPEND(&ifp->if_snd, m_head); 1092 ifp->if_flags |= IFF_OACTIVE; 1093 break; 1094 } 1095 1096 /* 1097 * If there's a BPF listener, bounce a copy of this frame 1098 * to him. 1099 */ 1100 BPF_MTAP(ifp, m_head); 1101 1102 } 1103 1104 /* Transmit */ 1105 sc->pcn_cdata.pcn_tx_prod = idx; 1106 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1107 1108 /* 1109 * Set a timeout in case the chip goes out to lunch. 1110 */ 1111 ifp->if_timer = 5; 1112 1113 PCN_UNLOCK(sc); 1114 1115 return; 1116} 1117 1118static void 1119pcn_setfilt(ifp) 1120 struct ifnet *ifp; 1121{ 1122 struct pcn_softc *sc; 1123 1124 sc = ifp->if_softc; 1125 1126 /* If we want promiscuous mode, set the allframes bit. */ 1127 if (ifp->if_flags & IFF_PROMISC) { 1128 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1129 } else { 1130 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1131 } 1132 1133 /* Set the capture broadcast bit to capture broadcast frames. */ 1134 if (ifp->if_flags & IFF_BROADCAST) { 1135 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1136 } else { 1137 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1138 } 1139 1140 return; 1141} 1142 1143static void 1144pcn_init(xsc) 1145 void *xsc; 1146{ 1147 struct pcn_softc *sc = xsc; 1148 struct ifnet *ifp = &sc->arpcom.ac_if; 1149 struct mii_data *mii = NULL; 1150 1151 PCN_LOCK(sc); 1152 1153 /* 1154 * Cancel pending I/O and free all RX/TX buffers. 1155 */ 1156 pcn_stop(sc); 1157 pcn_reset(sc); 1158 1159 mii = device_get_softc(sc->pcn_miibus); 1160 1161 /* Set MAC address */ 1162 pcn_csr_write(sc, PCN_CSR_PAR0, 1163 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1164 pcn_csr_write(sc, PCN_CSR_PAR1, 1165 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1166 pcn_csr_write(sc, PCN_CSR_PAR2, 1167 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1168 1169 /* Init circular RX list. */ 1170 if (pcn_list_rx_init(sc) == ENOBUFS) { 1171 printf("pcn%d: initialization failed: no " 1172 "memory for rx buffers\n", sc->pcn_unit); 1173 pcn_stop(sc); 1174 PCN_UNLOCK(sc); 1175 return; 1176 } 1177 1178 /* 1179 * Init tx descriptors. 1180 */ 1181 pcn_list_tx_init(sc); 1182 1183 /* Set up the mode register. */ 1184 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1185 1186 /* Set up RX filter. */ 1187 pcn_setfilt(ifp); 1188 1189 /* 1190 * Load the multicast filter. 1191 */ 1192 pcn_setmulti(sc); 1193 1194 /* 1195 * Load the addresses of the RX and TX lists. 1196 */ 1197 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1198 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1199 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1200 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1201 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1202 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1203 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1204 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1205 1206 /* Set the RX and TX ring sizes. */ 1207 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1208 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1209 1210 /* We're not using the initialization block. */ 1211 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1212 1213 /* Enable fast suspend mode. */ 1214 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1215 1216 /* 1217 * Enable burst read and write. Also set the no underflow 1218 * bit. This will avoid transmit underruns in certain 1219 * conditions while still providing decent performance. 1220 */ 1221 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1222 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1223 1224 /* Enable graceful recovery from underflow. */ 1225 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1226 1227 /* Enable auto-padding of short TX frames. */ 1228 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1229 1230 /* Disable MII autoneg (we handle this ourselves). */ 1231 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1232 1233 if (sc->pcn_type == Am79C978) 1234 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1235 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1236 1237 /* Enable interrupts and start the controller running. */ 1238 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1239 1240 mii_mediachg(mii); 1241 1242 ifp->if_flags |= IFF_RUNNING; 1243 ifp->if_flags &= ~IFF_OACTIVE; 1244 1245 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 1246 PCN_UNLOCK(sc); 1247 1248 return; 1249} 1250 1251/* 1252 * Set media options. 1253 */ 1254static int 1255pcn_ifmedia_upd(ifp) 1256 struct ifnet *ifp; 1257{ 1258 struct pcn_softc *sc; 1259 struct mii_data *mii; 1260 1261 sc = ifp->if_softc; 1262 mii = device_get_softc(sc->pcn_miibus); 1263 1264 sc->pcn_link = 0; 1265 if (mii->mii_instance) { 1266 struct mii_softc *miisc; 1267 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1268 mii_phy_reset(miisc); 1269 } 1270 mii_mediachg(mii); 1271 1272 return(0); 1273} 1274 1275/* 1276 * Report current media status. 1277 */ 1278static void 1279pcn_ifmedia_sts(ifp, ifmr) 1280 struct ifnet *ifp; 1281 struct ifmediareq *ifmr; 1282{ 1283 struct pcn_softc *sc; 1284 struct mii_data *mii; 1285 1286 sc = ifp->if_softc; 1287 1288 mii = device_get_softc(sc->pcn_miibus); 1289 mii_pollstat(mii); 1290 ifmr->ifm_active = mii->mii_media_active; 1291 ifmr->ifm_status = mii->mii_media_status; 1292 1293 return; 1294} 1295 1296static int 1297pcn_ioctl(ifp, command, data) 1298 struct ifnet *ifp; 1299 u_long command; 1300 caddr_t data; 1301{ 1302 struct pcn_softc *sc = ifp->if_softc; 1303 struct ifreq *ifr = (struct ifreq *) data; 1304 struct mii_data *mii = NULL; 1305 int error = 0; 1306 1307 PCN_LOCK(sc); 1308 1309 switch(command) { 1310 case SIOCSIFFLAGS: 1311 if (ifp->if_flags & IFF_UP) { 1312 if (ifp->if_flags & IFF_RUNNING && 1313 ifp->if_flags & IFF_PROMISC && 1314 !(sc->pcn_if_flags & IFF_PROMISC)) { 1315 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1316 PCN_EXTCTL1_SPND); 1317 pcn_setfilt(ifp); 1318 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1319 PCN_EXTCTL1_SPND); 1320 pcn_csr_write(sc, PCN_CSR_CSR, 1321 PCN_CSR_INTEN|PCN_CSR_START); 1322 } else if (ifp->if_flags & IFF_RUNNING && 1323 !(ifp->if_flags & IFF_PROMISC) && 1324 sc->pcn_if_flags & IFF_PROMISC) { 1325 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1326 PCN_EXTCTL1_SPND); 1327 pcn_setfilt(ifp); 1328 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1329 PCN_EXTCTL1_SPND); 1330 pcn_csr_write(sc, PCN_CSR_CSR, 1331 PCN_CSR_INTEN|PCN_CSR_START); 1332 } else if (!(ifp->if_flags & IFF_RUNNING)) 1333 pcn_init(sc); 1334 } else { 1335 if (ifp->if_flags & IFF_RUNNING) 1336 pcn_stop(sc); 1337 } 1338 sc->pcn_if_flags = ifp->if_flags; 1339 error = 0; 1340 break; 1341 case SIOCADDMULTI: 1342 case SIOCDELMULTI: 1343 pcn_setmulti(sc); 1344 error = 0; 1345 break; 1346 case SIOCGIFMEDIA: 1347 case SIOCSIFMEDIA: 1348 mii = device_get_softc(sc->pcn_miibus); 1349 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1350 break; 1351 default: 1352 error = ether_ioctl(ifp, command, data); 1353 break; 1354 } 1355 1356 PCN_UNLOCK(sc); 1357 1358 return(error); 1359} 1360 1361static void 1362pcn_watchdog(ifp) 1363 struct ifnet *ifp; 1364{ 1365 struct pcn_softc *sc; 1366 1367 sc = ifp->if_softc; 1368 1369 PCN_LOCK(sc); 1370 1371 ifp->if_oerrors++; 1372 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1373 1374 pcn_stop(sc); 1375 pcn_reset(sc); 1376 pcn_init(sc); 1377 1378 if (ifp->if_snd.ifq_head != NULL) 1379 pcn_start(ifp); 1380 1381 PCN_UNLOCK(sc); 1382 1383 return; 1384} 1385 1386/* 1387 * Stop the adapter and free any mbufs allocated to the 1388 * RX and TX lists. 1389 */ 1390static void 1391pcn_stop(sc) 1392 struct pcn_softc *sc; 1393{ 1394 register int i; 1395 struct ifnet *ifp; 1396 1397 ifp = &sc->arpcom.ac_if; 1398 PCN_LOCK(sc); 1399 ifp->if_timer = 0; 1400 1401 untimeout(pcn_tick, sc, sc->pcn_stat_ch); 1402 1403 /* Turn off interrupts */ 1404 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN); 1405 /* Stop adapter */ 1406 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1407 sc->pcn_link = 0; 1408 1409 /* 1410 * Free data in the RX lists. 1411 */ 1412 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1413 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1414 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1415 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1416 } 1417 } 1418 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1419 sizeof(sc->pcn_ldata->pcn_rx_list)); 1420 1421 /* 1422 * Free the TX list buffers. 1423 */ 1424 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1425 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1426 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1427 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1428 } 1429 } 1430 1431 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1432 sizeof(sc->pcn_ldata->pcn_tx_list)); 1433 1434 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1435 PCN_UNLOCK(sc); 1436 1437 return; 1438} 1439 1440/* 1441 * Stop all chip I/O so that the kernel's probe routines don't 1442 * get confused by errant DMAs when rebooting. 1443 */ 1444static void 1445pcn_shutdown(dev) 1446 device_t dev; 1447{ 1448 struct pcn_softc *sc; 1449 1450 sc = device_get_softc(dev); 1451 1452 PCN_LOCK(sc); 1453 pcn_reset(sc); 1454 pcn_stop(sc); 1455 PCN_UNLOCK(sc); 1456 1457 return; 1458} 1459